Diff: max17055.cpp

Revision:

19:20590e00feab

Parent:

18:37bca022d144

Child:

20:dcb0e5893677

--- a/max17055.cpp	Wed Oct 10 00:35:12 2018 +0000
+++ b/max17055.cpp	Tue Oct 23 17:30:14 2018 +0000
@@ -166,32 +166,26 @@
  * @retval       0 on success
  * @retval       non-0 for errors
  */
-int MAX17055::write_and_verify_reg(Registers_e reg_addr, uint16_t reg_data)
+int MAX17055::write_and_verify_reg(Registers_e reg_addr, uint16_t reg_data2write)
 {
-    int retries = 8;
+    int retries = 0;
     int ret;
     int statusRead;
     int statusWrite;
     uint16_t read_data;
 
+
     do {
-        statusWrite = writeReg(reg_addr, reg_data);
+        statusWrite = writeReg(reg_addr, reg_data2write);
         if (statusWrite != F_SUCCESS_0)
-            ret = F_ERROR_1;
-        wait_ms(3);
+            return F_ERROR_1;      
+        wait_ms(1);
         statusRead = readReg(reg_addr, read_data);
         if  (statusRead != F_SUCCESS_0)
-            ret = F_ERROR_1;
-        if (read_data != reg_data) {
-            ret = F_ERROR_3;
-            retries--;
-        }
-    } while (retries && read_data != reg_data);
-
-    if (ret!=F_SUCCESS_0)
-        return ret;
-    else
-        return F_SUCCESS_0;
+            return F_ERROR_1;
+    } while (reg_data2write != read_data && retries++<3);
+    
+    return F_SUCCESS_0;
 }
 
 /**
@@ -208,13 +202,15 @@
 
     int ret;
     int time_out = 10;
+    int32_t status;
     uint16_t hibcfg_value;
+    uint16_t read_data;
 
 
-//    status = readReg(VERSION_REG, read_data);
-//    if (status != F_SUCCESS_0)
-//        return status;
-
+    status = readReg(VERSION_REG, read_data);
+    if (status != F_SUCCESS_0)
+        return status;
+    printf("Version REG = %X \r\n", read_data);
     ///STEP 0. Check for POR (Skip load model if POR bit is cleared)
 
     if (check_POR_func() == F_ERROR_5)
@@ -225,28 +221,35 @@
     if (ret < F_SUCCESS_0) {
         return ret;
     }
+     printf("STEP 1\r\n");
 
     ///STEP 1.2. Force exit from hibernate
     hibcfg_value = forcedExitHiberMode();
+    printf("STEP 1.2\r\n");
 
 
     ///STEP 2. Initialize configuration
     ///STEP 2.1. Load EZ Config
     EZconfig(des_data);
+    printf("STEP 2\r\n");
 
     ///STEP 2.2. Poll ModelCFG.ModelRefresh bit for clear
     ret = poll_flag_clear(MODELCFG_REG, MAX17055_MODELCFG_REFRESH, time_out);
     if(ret < F_SUCCESS_0) {
         return ret;
     }
+    printf("STEP 2.2\r\n");
     ///STEP3. Restore original HibCfg
     writeReg(HIBCFG_REG, hibcfg_value);
+    printf("STEP 3\r\n");
 
     /* Clear Status.POR */
     ret = clear_POR_bit();
     if (ret < F_SUCCESS_0)
         return ret; //See errors
+    printf("Clear POR bit\r\n");
     return F_SUCCESS_0;
+    
 }
 
 /**
@@ -264,7 +267,7 @@
     uint16_t read_data;
 
     readReg(STATUS_REG, read_data);
-    printf("STATUS REF = %X \r\n", read_data);
+//    printf("STATUS REF = %X \r\n", read_data);
     if (!(read_data & MAX17055_STATUS_POR ) ) {
         return F_ERROR_5;  //POR not detected.
     } else
@@ -313,15 +316,19 @@
     int ret;
 
     do {
-        wait_ms(1);
+        wait_ms(50);
         ret = readReg(reg_addr, data);
+//        printf("read reg %X\r\n", data);
+//        printf("mask %X\r\n", mask);
         if(ret < F_SUCCESS_0)
             return F_ERROR_1;
+            
 
         if(!(data & mask))
             return F_SUCCESS_0;
 
         timeout -= 1;
+//        printf("end timeout %d \r\n", timeout);
     } while(timeout > 0);
 
     return F_ERROR_4;
@@ -406,19 +413,21 @@
     const int param_EZ_FG1 = 0x8400; // Sets config bit for the charge voltage for the m5
     const int param_EZ_FG2 = 0x8000;
     uint16_t dpacc, ret;
+    const int DIV_32 = 5;//DesignCap divide by 32 for EZ config
+    const int DIV_16 = 4;//DesignCap divide by 16 only for custom ini files
 
     ///STEP 2.1.2 Store the EZ Config values into the appropriate registers.
     ret = writeReg(DESIGNCAP_REG, des_data.designcap);
-    ret = writeReg(DQACC_REG, des_data.designcap >> 5);  //DesignCap divide by 32
+    ret = writeReg(DQACC_REG, des_data.designcap >> DIV_32);  
     ret = writeReg(ICHGTERM_REG, des_data.ichgterm);
     ret = writeReg(VEMPTY_REG, des_data.vempty);
 
     if (des_data.vcharge > charger_th) {
-        dpacc = (des_data.designcap >> 5) * chg_V_high / des_data.designcap;
+        dpacc = (des_data.designcap >> DIV_32) * chg_V_high / des_data.designcap;
         ret = writeReg(DPACC_REG, dpacc);
         ret = writeReg(MODELCFG_REG, param_EZ_FG1); //
     } else {
-        dpacc = (des_data.designcap >> 5) * chg_V_low / des_data.designcap;
+        dpacc = (des_data.designcap >> DIV_32) * chg_V_low / des_data.designcap;
         ret = writeReg(DPACC_REG, dpacc);
         ret = writeReg(MODELCFG_REG, param_EZ_FG2);
     }