Maxim Integrated / MAX11131

Maxim Integrated MAX11131 SPI 12-bit 16-channel ADC with SampleSet

Dependents:   MAX11131BOB_Tester MAX11131BOB_12bit_16ch_SampleSet_SPI_ADC MAX11131BOB_Serial_Tester

MAX11131.cpp@11:eaaf13fe381e, 2021-06-06 (annotated)

Committer:
whismanoid
Date:
Sun Jun 06 03:47:56 2021 -0700
Revision:
11:eaaf13fe381e
Parent:
10:92aedaa14cce 
selftest SPIfrequency SPIgetFrequency

Who changed what in which revision?

UserRevisionLine numberNew contents of line
whismanoid 9:8d47cb713984 1 // /*******************************************************************************
whismanoid 9:8d47cb713984 2 // * Copyright (C) 2021 Maxim Integrated Products, Inc., All Rights Reserved.
whismanoid 1:77f1ee332e4a 3 // *
whismanoid 1:77f1ee332e4a 4 // * Permission is hereby granted, free of charge, to any person obtaining a
whismanoid 1:77f1ee332e4a 5 // * copy of this software and associated documentation files (the "Software"),
whismanoid 1:77f1ee332e4a 6 // * to deal in the Software without restriction, including without limitation
whismanoid 1:77f1ee332e4a 7 // * the rights to use, copy, modify, merge, publish, distribute, sublicense,
whismanoid 1:77f1ee332e4a 8 // * and/or sell copies of the Software, and to permit persons to whom the
whismanoid 1:77f1ee332e4a 9 // * Software is furnished to do so, subject to the following conditions:
whismanoid 1:77f1ee332e4a 10 // *
whismanoid 1:77f1ee332e4a 11 // * The above copyright notice and this permission notice shall be included
whismanoid 1:77f1ee332e4a 12 // * in all copies or substantial portions of the Software.
whismanoid 1:77f1ee332e4a 13 // *
whismanoid 1:77f1ee332e4a 14 // * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
whismanoid 1:77f1ee332e4a 15 // * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
whismanoid 1:77f1ee332e4a 16 // * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
whismanoid 1:77f1ee332e4a 17 // * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
whismanoid 1:77f1ee332e4a 18 // * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
whismanoid 1:77f1ee332e4a 19 // * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
whismanoid 1:77f1ee332e4a 20 // * OTHER DEALINGS IN THE SOFTWARE.
whismanoid 1:77f1ee332e4a 21 // *
whismanoid 1:77f1ee332e4a 22 // * Except as contained in this notice, the name of Maxim Integrated
whismanoid 1:77f1ee332e4a 23 // * Products, Inc. shall not be used except as stated in the Maxim Integrated
whismanoid 1:77f1ee332e4a 24 // * Products, Inc. Branding Policy.
whismanoid 1:77f1ee332e4a 25 // *
whismanoid 1:77f1ee332e4a 26 // * The mere transfer of this software does not imply any licenses
whismanoid 1:77f1ee332e4a 27 // * of trade secrets, proprietary technology, copyrights, patents,
whismanoid 1:77f1ee332e4a 28 // * trademarks, maskwork rights, or any other form of intellectual
whismanoid 1:77f1ee332e4a 29 // * property whatsoever. Maxim Integrated Products, Inc. retains all
whismanoid 1:77f1ee332e4a 30 // * ownership rights.
whismanoid 1:77f1ee332e4a 31 // *******************************************************************************
whismanoid 1:77f1ee332e4a 32 // */
whismanoid 1:77f1ee332e4a 33 // *********************************************************************
whismanoid 1:77f1ee332e4a 34 // @file MAX11131.cpp
whismanoid 1:77f1ee332e4a 35 // *********************************************************************
whismanoid 1:77f1ee332e4a 36 // Device Driver file
whismanoid 1:77f1ee332e4a 37 // DO NOT EDIT; except areas designated "CUSTOMIZE". Automatically generated file.
whismanoid 1:77f1ee332e4a 38 // generated by XMLSystemOfDevicesToMBED.py
whismanoid 1:77f1ee332e4a 39 // System Name = ExampleSystem
whismanoid 1:77f1ee332e4a 40 // System Description = Device driver example
whismanoid 1:77f1ee332e4a 41
whismanoid 1:77f1ee332e4a 42 #include "MAX11131.h"
whismanoid 1:77f1ee332e4a 43
whismanoid 1:77f1ee332e4a 44 // Device Name = MAX11131
whismanoid 1:77f1ee332e4a 45 // Device Description = 3Msps, Low-Power, Serial SPI 12-Bit, 16-Channel, Differential/Single-Ended Input, SAR ADC
whismanoid 6:cb7bdeb185d0 46 // Device DeviceBriefDescription = 12-bit 3Msps 16-ch ADC
whismanoid 1:77f1ee332e4a 47 // Device Manufacturer = Maxim Integrated
whismanoid 1:77f1ee332e4a 48 // Device PartNumber = MAX11131ATI+
whismanoid 1:77f1ee332e4a 49 // Device RegValue_Width = DataWidth16bit_HL
whismanoid 1:77f1ee332e4a 50 //
whismanoid 1:77f1ee332e4a 51 // ADC MaxOutputDataRate = 3Msps
whismanoid 1:77f1ee332e4a 52 // ADC NumChannels = 16
whismanoid 1:77f1ee332e4a 53 // ADC ResolutionBits = 12
whismanoid 1:77f1ee332e4a 54 //
whismanoid 1:77f1ee332e4a 55 // SPI CS = ActiveLow
whismanoid 1:77f1ee332e4a 56 // SPI FrameStart = CS
whismanoid 1:77f1ee332e4a 57 // SPI CPOL = 1
whismanoid 1:77f1ee332e4a 58 // SPI CPHA = 1
whismanoid 1:77f1ee332e4a 59 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 1:77f1ee332e4a 60 // SPI SCLK Idle High
whismanoid 1:77f1ee332e4a 61 // SPI SCLKMaxMHz = 48
whismanoid 1:77f1ee332e4a 62 // SPI SCLKMinMHz = 0.48
whismanoid 1:77f1ee332e4a 63 //
whismanoid 1:77f1ee332e4a 64 // InputPin Name = CNVST
whismanoid 1:77f1ee332e4a 65 // InputPin Description = Active-Low Conversion Start Input/Analog Input 14
whismanoid 1:77f1ee332e4a 66 // InputPin Function = Trigger
whismanoid 1:77f1ee332e4a 67 //
whismanoid 1:77f1ee332e4a 68 // InputPin Name = REF+
whismanoid 1:77f1ee332e4a 69 // InputPin Description = External Positive Reference Input. Apply a reference voltage at REF+. Bypass to GND with a 0.47uF capacitor.
whismanoid 1:77f1ee332e4a 70 // InputPin Function = Reference
whismanoid 1:77f1ee332e4a 71 //
whismanoid 1:77f1ee332e4a 72 // InputPin Name = REF-/AIN15
whismanoid 1:77f1ee332e4a 73 // InputPin Description = External Differential Reference Negative Input/Analog Input 15
whismanoid 1:77f1ee332e4a 74 // InputPin Function = Reference
whismanoid 1:77f1ee332e4a 75 //
whismanoid 1:77f1ee332e4a 76 // OutputPin Name = EOC
whismanoid 1:77f1ee332e4a 77 // OutputPin Description = End of Conversion Output. Data is valid after EOC pulls low (Internal clock mode only).
whismanoid 1:77f1ee332e4a 78 // OutputPin Function = Event
whismanoid 1:77f1ee332e4a 79 //
whismanoid 1:77f1ee332e4a 80 // SupplyPin Name = VDD
whismanoid 1:77f1ee332e4a 81 // SupplyPin Description = Power-Supply Input. Bypass to GND with a 10uF in parallel with a 0.1uF capacitors.
whismanoid 1:77f1ee332e4a 82 // SupplyPin VinMax = 3.6
whismanoid 1:77f1ee332e4a 83 // SupplyPin VinMin = 2.35
whismanoid 1:77f1ee332e4a 84 // SupplyPin Function = Analog
whismanoid 1:77f1ee332e4a 85 //
whismanoid 1:77f1ee332e4a 86 // SupplyPin Name = OVDD
whismanoid 1:77f1ee332e4a 87 // SupplyPin Description = Interface Digital Power-Supply Input. Bypass to GND with a 10uF in parallel with a 0.1uF capacitors.
whismanoid 1:77f1ee332e4a 88 // SupplyPin VinMax = 3.6
whismanoid 1:77f1ee332e4a 89 // SupplyPin VinMin = 1.5
whismanoid 1:77f1ee332e4a 90 // SupplyPin Function = Digital
whismanoid 1:77f1ee332e4a 91 //
whismanoid 1:77f1ee332e4a 92
whismanoid 1:77f1ee332e4a 93 MAX11131::MAX11131(SPI &spi, DigitalOut &cs_pin, // SPI interface
whismanoid 1:77f1ee332e4a 94 DigitalOut &CNVST_pin, // Digital Trigger Input to MAX11131 device
whismanoid 6:cb7bdeb185d0 95 // AnalogOut &REF_plus_pin, // Reference Input to MAX11131 device
whismanoid 6:cb7bdeb185d0 96 // AnalogOut &REF_minus_slash_AIN15_pin, // Reference Input to MAX11131 device
whismanoid 1:77f1ee332e4a 97 DigitalIn &EOC_pin, // Digital Event Output from MAX11131 device
whismanoid 1:77f1ee332e4a 98 MAX11131_ic_t ic_variant)
whismanoid 1:77f1ee332e4a 99 : m_spi(spi), m_cs_pin(cs_pin), // SPI interface
whismanoid 1:77f1ee332e4a 100 m_CNVST_pin(CNVST_pin), // Digital Trigger Input to MAX11131 device
whismanoid 6:cb7bdeb185d0 101 // m_REF_plus_pin(REF_plus_pin), // Reference Input to MAX11131 device
whismanoid 6:cb7bdeb185d0 102 // m_REF_minus_slash_AIN15_pin(REF_minus_slash_AIN15_pin), // Reference Input to MAX11131 device
whismanoid 1:77f1ee332e4a 103 m_EOC_pin(EOC_pin), // Digital Event Output from MAX11131 device
whismanoid 1:77f1ee332e4a 104 m_ic_variant(ic_variant)
whismanoid 1:77f1ee332e4a 105 {
whismanoid 1:77f1ee332e4a 106 // SPI CS = ActiveLow
whismanoid 1:77f1ee332e4a 107 // SPI FrameStart = CS
whismanoid 1:77f1ee332e4a 108 m_SPI_cs_state = 1;
whismanoid 9:8d47cb713984 109 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 9:8d47cb713984 110 m_cs_pin = m_SPI_cs_state;
whismanoid 9:8d47cb713984 111 }
whismanoid 1:77f1ee332e4a 112
whismanoid 1:77f1ee332e4a 113 // SPI CPOL = 1
whismanoid 1:77f1ee332e4a 114 // SPI CPHA = 1
whismanoid 1:77f1ee332e4a 115 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 1:77f1ee332e4a 116 // SPI SCLK Idle High
whismanoid 6:cb7bdeb185d0 117 m_SPI_dataMode = 3; //SPI_MODE3; // CPOL=1,CPHA=1: Rising Edge stable; SCLK idle High
whismanoid 1:77f1ee332e4a 118 m_spi.format(8,m_SPI_dataMode); // int bits_must_be_8, int mode=0_3 CPOL=0,CPHA=0
whismanoid 1:77f1ee332e4a 119
whismanoid 1:77f1ee332e4a 120 // SPI SCLKMaxMHz = 48
whismanoid 1:77f1ee332e4a 121 // SPI SCLKMinMHz = 0.48
whismanoid 1:77f1ee332e4a 122 //#define SPI_SCLK_Hz 48000000 // 48MHz
whismanoid 1:77f1ee332e4a 123 //#define SPI_SCLK_Hz 24000000 // 24MHz
whismanoid 1:77f1ee332e4a 124 //#define SPI_SCLK_Hz 12000000 // 12MHz
whismanoid 3:621191a7e3fd 125 //#define SPI_SCLK_Hz 6000000 // 6MHz
whismanoid 1:77f1ee332e4a 126 //#define SPI_SCLK_Hz 4000000 // 4MHz
whismanoid 1:77f1ee332e4a 127 //#define SPI_SCLK_Hz 2000000 // 2MHz
whismanoid 1:77f1ee332e4a 128 //#define SPI_SCLK_Hz 1000000 // 1MHz
whismanoid 3:621191a7e3fd 129 #if defined(TARGET_MAX32600)
whismanoid 3:621191a7e3fd 130 // MAX11131BOB_Serial_Tester on MAX32600MBED limit SCLK=6MHz
whismanoid 3:621191a7e3fd 131 m_SPI_SCLK_Hz = 6000000; // 6MHz; MAX11131 limit is 48MHz
whismanoid 3:621191a7e3fd 132 #else
whismanoid 3:621191a7e3fd 133 // all other platforms
whismanoid 9:8d47cb713984 134 m_SPI_SCLK_Hz = 24000000; // platform limit 24MHz; MAX11131 limit is 48MHz
whismanoid 3:621191a7e3fd 135 #endif
whismanoid 1:77f1ee332e4a 136 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 1:77f1ee332e4a 137
whismanoid 6:cb7bdeb185d0 138 //
whismanoid 6:cb7bdeb185d0 139 // CNVST Trigger Input to MAX11131 device
whismanoid 6:cb7bdeb185d0 140 m_CNVST_pin = 1; // output logic high -- initial value in constructor
whismanoid 1:77f1ee332e4a 141 //
whismanoid 6:cb7bdeb185d0 142 // REF_plus Reference Input to MAX11131 device
whismanoid 6:cb7bdeb185d0 143 //
whismanoid 6:cb7bdeb185d0 144 // REF_minus_slash_AIN15 Reference Input to MAX11131 device
whismanoid 6:cb7bdeb185d0 145 //
whismanoid 6:cb7bdeb185d0 146 // EOC Event Output from device
whismanoid 1:77f1ee332e4a 147 }
whismanoid 1:77f1ee332e4a 148
whismanoid 1:77f1ee332e4a 149 MAX11131::~MAX11131()
whismanoid 1:77f1ee332e4a 150 {
whismanoid 1:77f1ee332e4a 151 // do nothing
whismanoid 1:77f1ee332e4a 152 }
whismanoid 1:77f1ee332e4a 153
whismanoid 6:cb7bdeb185d0 154 /// set SPI SCLK frequency
whismanoid 1:77f1ee332e4a 155 void MAX11131::spi_frequency(int spi_sclk_Hz)
whismanoid 1:77f1ee332e4a 156 {
whismanoid 1:77f1ee332e4a 157 m_SPI_SCLK_Hz = spi_sclk_Hz;
whismanoid 1:77f1ee332e4a 158 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 1:77f1ee332e4a 159 }
whismanoid 1:77f1ee332e4a 160
whismanoid 10:92aedaa14cce 161 // set SPI SCLK frequency for MAX11131
whismanoid 10:92aedaa14cce 162 //
whismanoid 11:eaaf13fe381e 163 void MAX11131::SPIfrequency(int spi_sclk_Hz)
whismanoid 10:92aedaa14cce 164 {
whismanoid 11:eaaf13fe381e 165 m_SPI_SCLK_Hz = spi_sclk_Hz;
whismanoid 11:eaaf13fe381e 166 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 10:92aedaa14cce 167 }
whismanoid 10:92aedaa14cce 168
whismanoid 10:92aedaa14cce 169 // get SPI SCLK frequency for MAX11131
whismanoid 10:92aedaa14cce 170 //
whismanoid 11:eaaf13fe381e 171 int MAX11131::SPIgetFrequency()
whismanoid 10:92aedaa14cce 172 {
whismanoid 11:eaaf13fe381e 173 return m_SPI_SCLK_Hz;
whismanoid 10:92aedaa14cce 174 }
whismanoid 10:92aedaa14cce 175
whismanoid 1:77f1ee332e4a 176 // Assert SPI Chip Select
whismanoid 1:77f1ee332e4a 177 // SPI chip-select for MAX11131
whismanoid 1:77f1ee332e4a 178 //
whismanoid 9:8d47cb713984 179 inline void MAX11131::SPIoutputCS(int isLogicHigh)
whismanoid 1:77f1ee332e4a 180 {
whismanoid 1:77f1ee332e4a 181 m_SPI_cs_state = isLogicHigh;
whismanoid 9:8d47cb713984 182 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 9:8d47cb713984 183 m_cs_pin = m_SPI_cs_state;
whismanoid 9:8d47cb713984 184 }
whismanoid 1:77f1ee332e4a 185 }
whismanoid 1:77f1ee332e4a 186
whismanoid 1:77f1ee332e4a 187 // SPI write 16 bits
whismanoid 1:77f1ee332e4a 188 // SPI interface to MAX11131 shift 16 bits mosiData16 into MAX11131 DIN
whismanoid 1:77f1ee332e4a 189 // ignoring MAX11131 DOUT
whismanoid 1:77f1ee332e4a 190 //
whismanoid 1:77f1ee332e4a 191 void MAX11131::SPIwrite16bits(int16_t mosiData16)
whismanoid 1:77f1ee332e4a 192 {
whismanoid 1:77f1ee332e4a 193 size_t byteCount = 2;
whismanoid 1:77f1ee332e4a 194 static char mosiData[2];
whismanoid 1:77f1ee332e4a 195 static char misoData[2];
whismanoid 1:77f1ee332e4a 196 mosiData[0] = (char)((mosiData16 >> 8) & 0xFF); // MSByte
whismanoid 1:77f1ee332e4a 197 mosiData[1] = (char)((mosiData16 >> 0) & 0xFF); // LSByte
whismanoid 1:77f1ee332e4a 198 //
whismanoid 1:77f1ee332e4a 199 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 1:77f1ee332e4a 200 //~ noInterrupts();
whismanoid 1:77f1ee332e4a 201 //
whismanoid 1:77f1ee332e4a 202 //~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid 1:77f1ee332e4a 203 //
whismanoid 1:77f1ee332e4a 204 unsigned int numBytesTransferred = m_spi.write(mosiData, byteCount, misoData, byteCount);
whismanoid 1:77f1ee332e4a 205 //~ m_spi.transfer(mosiData8_FF0000);
whismanoid 1:77f1ee332e4a 206 //~ m_spi.transfer(mosiData16_00FF00);
whismanoid 1:77f1ee332e4a 207 //~ m_spi.transfer(mosiData16_0000FF);
whismanoid 1:77f1ee332e4a 208 //
whismanoid 1:77f1ee332e4a 209 //~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid 1:77f1ee332e4a 210 //
whismanoid 1:77f1ee332e4a 211 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 1:77f1ee332e4a 212 //~ interrupts();
whismanoid 6:cb7bdeb185d0 213 // Optional Diagnostic function to print SPI transactions
whismanoid 6:cb7bdeb185d0 214 if (onSPIprint)
whismanoid 6:cb7bdeb185d0 215 {
whismanoid 6:cb7bdeb185d0 216 onSPIprint(byteCount, (uint8_t*)mosiData, (uint8_t*)misoData);
whismanoid 6:cb7bdeb185d0 217 }
whismanoid 1:77f1ee332e4a 218 //
whismanoid 1:77f1ee332e4a 219 // VERIFY: SPIwrite24bits print diagnostic information
whismanoid 1:77f1ee332e4a 220 //cmdLine.serial().printf(" MOSI->"));
whismanoid 1:77f1ee332e4a 221 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 222 //Serial.print( (mosiData8_FF0000 & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 223 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 224 //Serial.print( (mosiData16_00FF00 & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 225 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 226 //Serial.print( (mosiData16_0000FF & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 227 // hex dump mosiData[0..byteCount-1]
whismanoid 1:77f1ee332e4a 228 #if 0 // HAS_MICROUSBSERIAL
whismanoid 1:77f1ee332e4a 229 cmdLine_microUSBserial.serial().printf("\r\nSPI");
whismanoid 1:77f1ee332e4a 230 if (byteCount > 7) {
whismanoid 1:77f1ee332e4a 231 cmdLine_microUSBserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 1:77f1ee332e4a 232 }
whismanoid 1:77f1ee332e4a 233 cmdLine_microUSBserial.serial().printf(" MOSI->");
whismanoid 1:77f1ee332e4a 234 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 1:77f1ee332e4a 235 {
whismanoid 1:77f1ee332e4a 236 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 1:77f1ee332e4a 237 }
whismanoid 1:77f1ee332e4a 238 // hex dump misoData[0..byteCount-1]
whismanoid 9:8d47cb713984 239 cmdLine_microUSBserial.serial().printf(" MISO<-");
whismanoid 1:77f1ee332e4a 240 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 1:77f1ee332e4a 241 {
whismanoid 1:77f1ee332e4a 242 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 1:77f1ee332e4a 243 }
whismanoid 1:77f1ee332e4a 244 cmdLine_microUSBserial.serial().printf(" ");
whismanoid 1:77f1ee332e4a 245 #endif
whismanoid 1:77f1ee332e4a 246 #if 0 // HAS_DAPLINK_SERIAL
whismanoid 1:77f1ee332e4a 247 cmdLine_DAPLINKserial.serial().printf("\r\nSPI");
whismanoid 1:77f1ee332e4a 248 if (byteCount > 7) {
whismanoid 1:77f1ee332e4a 249 cmdLine_DAPLINKserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 1:77f1ee332e4a 250 }
whismanoid 1:77f1ee332e4a 251 cmdLine_DAPLINKserial.serial().printf(" MOSI->");
whismanoid 1:77f1ee332e4a 252 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 1:77f1ee332e4a 253 {
whismanoid 1:77f1ee332e4a 254 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 1:77f1ee332e4a 255 }
whismanoid 1:77f1ee332e4a 256 // hex dump misoData[0..byteCount-1]
whismanoid 9:8d47cb713984 257 cmdLine_DAPLINKserial.serial().printf(" MISO<-");
whismanoid 1:77f1ee332e4a 258 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 1:77f1ee332e4a 259 {
whismanoid 1:77f1ee332e4a 260 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 1:77f1ee332e4a 261 }
whismanoid 1:77f1ee332e4a 262 cmdLine_DAPLINKserial.serial().printf(" ");
whismanoid 1:77f1ee332e4a 263 #endif
whismanoid 1:77f1ee332e4a 264 // VERIFY: DIAGNOSTIC: print MAX5715 device register write
whismanoid 1:77f1ee332e4a 265 // TODO: MAX5715_print_register_verbose(mosiData8_FF0000, mosiData16_00FFFF);
whismanoid 1:77f1ee332e4a 266 // TODO: print_verbose_SPI_diagnostic(mosiData16_FF00, mosiData16_00FF, misoData16_FF00, misoData16_00FF);
whismanoid 1:77f1ee332e4a 267 //
whismanoid 1:77f1ee332e4a 268 // int misoData16 = (misoData16_FF00 << 8) | misoData16_00FF;
whismanoid 1:77f1ee332e4a 269 // return misoData16;
whismanoid 1:77f1ee332e4a 270 }
whismanoid 1:77f1ee332e4a 271
whismanoid 1:77f1ee332e4a 272 // SPI write 17-24 bits
whismanoid 1:77f1ee332e4a 273 // SPI interface to MAX11131 shift 16 bits mosiData16 into MAX11131 DIN
whismanoid 1:77f1ee332e4a 274 // followed by one additional SCLK byte.
whismanoid 1:77f1ee332e4a 275 // ignoring MAX11131 DOUT
whismanoid 1:77f1ee332e4a 276 //
whismanoid 1:77f1ee332e4a 277 void MAX11131::SPIwrite24bits(int16_t mosiData16_FFFF00, int8_t mosiData8_0000FF)
whismanoid 1:77f1ee332e4a 278 {
whismanoid 1:77f1ee332e4a 279 // TODO: implement SPIwrite24bits(int16_t mosiData16_FFFF00, int8_t mosiData8_0000FF)
whismanoid 1:77f1ee332e4a 280 size_t byteCount = 3;
whismanoid 1:77f1ee332e4a 281 static char mosiData[3];
whismanoid 1:77f1ee332e4a 282 static char misoData[3];
whismanoid 1:77f1ee332e4a 283 mosiData[0] = (char)((mosiData16_FFFF00 >> 8) & 0xFF); // MSByte
whismanoid 1:77f1ee332e4a 284 mosiData[1] = (char)((mosiData16_FFFF00 >> 0) & 0xFF); // LSByte
whismanoid 1:77f1ee332e4a 285 mosiData[2] = mosiData8_0000FF;
whismanoid 1:77f1ee332e4a 286 //
whismanoid 1:77f1ee332e4a 287 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 1:77f1ee332e4a 288 //~ noInterrupts();
whismanoid 1:77f1ee332e4a 289 //
whismanoid 1:77f1ee332e4a 290 //~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid 1:77f1ee332e4a 291 //
whismanoid 1:77f1ee332e4a 292 unsigned int numBytesTransferred = m_spi.write(mosiData, byteCount, misoData, byteCount);
whismanoid 1:77f1ee332e4a 293 //~ m_spi.transfer(mosiData8_FF0000);
whismanoid 1:77f1ee332e4a 294 //~ m_spi.transfer(mosiData16_00FF00);
whismanoid 1:77f1ee332e4a 295 //~ m_spi.transfer(mosiData16_0000FF);
whismanoid 1:77f1ee332e4a 296 //
whismanoid 1:77f1ee332e4a 297 //~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid 1:77f1ee332e4a 298 //
whismanoid 1:77f1ee332e4a 299 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 1:77f1ee332e4a 300 //~ interrupts();
whismanoid 6:cb7bdeb185d0 301 // Optional Diagnostic function to print SPI transactions
whismanoid 6:cb7bdeb185d0 302 if (onSPIprint)
whismanoid 6:cb7bdeb185d0 303 {
whismanoid 6:cb7bdeb185d0 304 onSPIprint(byteCount, (uint8_t*)mosiData, (uint8_t*)misoData);
whismanoid 6:cb7bdeb185d0 305 }
whismanoid 1:77f1ee332e4a 306 //
whismanoid 1:77f1ee332e4a 307 // VERIFY: SPIwrite24bits print diagnostic information
whismanoid 1:77f1ee332e4a 308 //cmdLine.serial().printf(" MOSI->"));
whismanoid 1:77f1ee332e4a 309 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 310 //Serial.print( (mosiData8_FF0000 & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 311 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 312 //Serial.print( (mosiData16_00FF00 & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 313 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 314 //Serial.print( (mosiData16_0000FF & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 315 // hex dump mosiData[0..byteCount-1]
whismanoid 1:77f1ee332e4a 316 #if 0 // HAS_MICROUSBSERIAL
whismanoid 1:77f1ee332e4a 317 cmdLine_microUSBserial.serial().printf("\r\nSPI");
whismanoid 1:77f1ee332e4a 318 if (byteCount > 7) {
whismanoid 1:77f1ee332e4a 319 cmdLine_microUSBserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 1:77f1ee332e4a 320 }
whismanoid 1:77f1ee332e4a 321 cmdLine_microUSBserial.serial().printf(" MOSI->");
whismanoid 1:77f1ee332e4a 322 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 1:77f1ee332e4a 323 {
whismanoid 1:77f1ee332e4a 324 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 1:77f1ee332e4a 325 }
whismanoid 1:77f1ee332e4a 326 // hex dump misoData[0..byteCount-1]
whismanoid 9:8d47cb713984 327 cmdLine_microUSBserial.serial().printf(" MISO<-");
whismanoid 1:77f1ee332e4a 328 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 1:77f1ee332e4a 329 {
whismanoid 1:77f1ee332e4a 330 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 1:77f1ee332e4a 331 }
whismanoid 1:77f1ee332e4a 332 cmdLine_microUSBserial.serial().printf(" ");
whismanoid 1:77f1ee332e4a 333 #endif
whismanoid 1:77f1ee332e4a 334 #if 0 // HAS_DAPLINK_SERIAL
whismanoid 1:77f1ee332e4a 335 cmdLine_DAPLINKserial.serial().printf("\r\nSPI");
whismanoid 1:77f1ee332e4a 336 if (byteCount > 7) {
whismanoid 1:77f1ee332e4a 337 cmdLine_DAPLINKserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 1:77f1ee332e4a 338 }
whismanoid 1:77f1ee332e4a 339 cmdLine_DAPLINKserial.serial().printf(" MOSI->");
whismanoid 1:77f1ee332e4a 340 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 1:77f1ee332e4a 341 {
whismanoid 1:77f1ee332e4a 342 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 1:77f1ee332e4a 343 }
whismanoid 1:77f1ee332e4a 344 // hex dump misoData[0..byteCount-1]
whismanoid 9:8d47cb713984 345 cmdLine_DAPLINKserial.serial().printf(" MISO<-");
whismanoid 1:77f1ee332e4a 346 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 1:77f1ee332e4a 347 {
whismanoid 1:77f1ee332e4a 348 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 1:77f1ee332e4a 349 }
whismanoid 1:77f1ee332e4a 350 cmdLine_DAPLINKserial.serial().printf(" ");
whismanoid 1:77f1ee332e4a 351 #endif
whismanoid 1:77f1ee332e4a 352 // VERIFY: DIAGNOSTIC: print MAX5715 device register write
whismanoid 1:77f1ee332e4a 353 // TODO: MAX5715_print_register_verbose(mosiData8_FF0000, mosiData16_00FFFF);
whismanoid 1:77f1ee332e4a 354 //
whismanoid 1:77f1ee332e4a 355 // int misoData16 = (misoData16_FF00 << 8) | misoData16_00FF;
whismanoid 1:77f1ee332e4a 356 // return misoData16;
whismanoid 1:77f1ee332e4a 357 }
whismanoid 1:77f1ee332e4a 358
whismanoid 1:77f1ee332e4a 359 // SPI read 16 bits while MOSI (MAX11131 DIN) is 0
whismanoid 1:77f1ee332e4a 360 // SPI interface to capture 16 bits miso data from MAX11131 DOUT
whismanoid 1:77f1ee332e4a 361 //
whismanoid 1:77f1ee332e4a 362 int16_t MAX11131::SPIread16bits()
whismanoid 1:77f1ee332e4a 363 {
whismanoid 1:77f1ee332e4a 364 int mosiData16 = 0;
whismanoid 1:77f1ee332e4a 365 size_t byteCount = 2;
whismanoid 1:77f1ee332e4a 366 static char mosiData[2];
whismanoid 1:77f1ee332e4a 367 static char misoData[2];
whismanoid 1:77f1ee332e4a 368 mosiData[0] = (char)((mosiData16 >> 8) & 0xFF); // MSByte
whismanoid 1:77f1ee332e4a 369 mosiData[1] = (char)((mosiData16 >> 0) & 0xFF); // LSByte
whismanoid 1:77f1ee332e4a 370 //
whismanoid 1:77f1ee332e4a 371 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 1:77f1ee332e4a 372 //~ noInterrupts();
whismanoid 1:77f1ee332e4a 373 //
whismanoid 1:77f1ee332e4a 374 //~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid 1:77f1ee332e4a 375 //
whismanoid 1:77f1ee332e4a 376 unsigned int numBytesTransferred = m_spi.write(mosiData, byteCount, misoData, byteCount);
whismanoid 1:77f1ee332e4a 377 //~ m_spi.transfer(mosiData8_FF0000);
whismanoid 1:77f1ee332e4a 378 //~ m_spi.transfer(mosiData16_00FF00);
whismanoid 1:77f1ee332e4a 379 //~ m_spi.transfer(mosiData16_0000FF);
whismanoid 1:77f1ee332e4a 380 //
whismanoid 1:77f1ee332e4a 381 //~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid 1:77f1ee332e4a 382 //
whismanoid 1:77f1ee332e4a 383 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 1:77f1ee332e4a 384 //~ interrupts();
whismanoid 6:cb7bdeb185d0 385 // Optional Diagnostic function to print SPI transactions
whismanoid 6:cb7bdeb185d0 386 if (onSPIprint)
whismanoid 6:cb7bdeb185d0 387 {
whismanoid 6:cb7bdeb185d0 388 onSPIprint(byteCount, (uint8_t*)mosiData, (uint8_t*)misoData);
whismanoid 6:cb7bdeb185d0 389 }
whismanoid 1:77f1ee332e4a 390 //
whismanoid 1:77f1ee332e4a 391 // VERIFY: SPIwrite24bits print diagnostic information
whismanoid 1:77f1ee332e4a 392 //cmdLine.serial().printf(" MOSI->"));
whismanoid 1:77f1ee332e4a 393 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 394 //Serial.print( (mosiData8_FF0000 & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 395 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 396 //Serial.print( (mosiData16_00FF00 & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 397 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 398 //Serial.print( (mosiData16_0000FF & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 399 // hex dump mosiData[0..byteCount-1]
whismanoid 1:77f1ee332e4a 400 #if 0 // HAS_MICROUSBSERIAL
whismanoid 1:77f1ee332e4a 401 cmdLine_microUSBserial.serial().printf("\r\nSPI");
whismanoid 1:77f1ee332e4a 402 if (byteCount > 7) {
whismanoid 1:77f1ee332e4a 403 cmdLine_microUSBserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 1:77f1ee332e4a 404 }
whismanoid 1:77f1ee332e4a 405 cmdLine_microUSBserial.serial().printf(" MOSI->");
whismanoid 1:77f1ee332e4a 406 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 1:77f1ee332e4a 407 {
whismanoid 1:77f1ee332e4a 408 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 1:77f1ee332e4a 409 }
whismanoid 1:77f1ee332e4a 410 // hex dump misoData[0..byteCount-1]
whismanoid 9:8d47cb713984 411 cmdLine_microUSBserial.serial().printf(" MISO<-");
whismanoid 1:77f1ee332e4a 412 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 1:77f1ee332e4a 413 {
whismanoid 1:77f1ee332e4a 414 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 1:77f1ee332e4a 415 }
whismanoid 1:77f1ee332e4a 416 cmdLine_microUSBserial.serial().printf(" ");
whismanoid 1:77f1ee332e4a 417 #endif
whismanoid 1:77f1ee332e4a 418 #if 0 // HAS_DAPLINK_SERIAL
whismanoid 1:77f1ee332e4a 419 cmdLine_DAPLINKserial.serial().printf("\r\nSPI");
whismanoid 1:77f1ee332e4a 420 if (byteCount > 7) {
whismanoid 1:77f1ee332e4a 421 cmdLine_DAPLINKserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 1:77f1ee332e4a 422 }
whismanoid 1:77f1ee332e4a 423 cmdLine_DAPLINKserial.serial().printf(" MOSI->");
whismanoid 1:77f1ee332e4a 424 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 1:77f1ee332e4a 425 {
whismanoid 1:77f1ee332e4a 426 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 1:77f1ee332e4a 427 }
whismanoid 1:77f1ee332e4a 428 // hex dump misoData[0..byteCount-1]
whismanoid 9:8d47cb713984 429 cmdLine_DAPLINKserial.serial().printf(" MISO<-");
whismanoid 1:77f1ee332e4a 430 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 1:77f1ee332e4a 431 {
whismanoid 1:77f1ee332e4a 432 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 1:77f1ee332e4a 433 }
whismanoid 1:77f1ee332e4a 434 cmdLine_DAPLINKserial.serial().printf(" ");
whismanoid 1:77f1ee332e4a 435 #endif
whismanoid 1:77f1ee332e4a 436 // VERIFY: DIAGNOSTIC: print MAX5715 device register write
whismanoid 1:77f1ee332e4a 437 // TODO: MAX5715_print_register_verbose(mosiData8_FF0000, mosiData16_00FFFF);
whismanoid 1:77f1ee332e4a 438 // TODO: print_verbose_SPI_diagnostic(mosiData16_FF00, mosiData16_00FF, misoData16_FF00, misoData16_00FF);
whismanoid 1:77f1ee332e4a 439 //
whismanoid 1:77f1ee332e4a 440 int misoData16 = (misoData[0] << 8) | misoData[1];
whismanoid 1:77f1ee332e4a 441 return misoData16;
whismanoid 1:77f1ee332e4a 442 }
whismanoid 1:77f1ee332e4a 443
whismanoid 1:77f1ee332e4a 444 // Assert MAX11131 CNVST convert start.
whismanoid 1:77f1ee332e4a 445 // Required when using any of the InternalClock modes with SWCNV 0.
whismanoid 1:77f1ee332e4a 446 // Trigger measurement by driving CNVST/AIN14 pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 447 //
whismanoid 1:77f1ee332e4a 448 void MAX11131::CNVSToutputPulseLow()
whismanoid 1:77f1ee332e4a 449 {
whismanoid 1:77f1ee332e4a 450 // m_CNVST_pin.output(); // only applicable to DigitalInOut
whismanoid 1:77f1ee332e4a 451 m_CNVST_pin = 0; // output logic low
whismanoid 1:77f1ee332e4a 452 wait(0.01); // pulse low delay time
whismanoid 1:77f1ee332e4a 453 m_CNVST_pin = 1; // output logic high
whismanoid 1:77f1ee332e4a 454 }
whismanoid 1:77f1ee332e4a 455
whismanoid 1:77f1ee332e4a 456 // Wait for MAX11131 EOC pin low, indicating end of conversion.
whismanoid 1:77f1ee332e4a 457 // Required when using any of the InternalClock modes.
whismanoid 1:77f1ee332e4a 458 //
whismanoid 1:77f1ee332e4a 459 void MAX11131::EOCinputWaitUntilLow()
whismanoid 1:77f1ee332e4a 460 {
whismanoid 1:77f1ee332e4a 461 // m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid 1:77f1ee332e4a 462 while (m_EOC_pin != 0)
whismanoid 1:77f1ee332e4a 463 {
whismanoid 1:77f1ee332e4a 464 // spinlock waiting for logic low pin state
whismanoid 1:77f1ee332e4a 465 }
whismanoid 1:77f1ee332e4a 466 }
whismanoid 1:77f1ee332e4a 467
whismanoid 1:77f1ee332e4a 468 // Return the status of the MAX11131 EOC pin.
whismanoid 1:77f1ee332e4a 469 //
whismanoid 1:77f1ee332e4a 470 int MAX11131::EOCinputValue()
whismanoid 1:77f1ee332e4a 471 {
whismanoid 1:77f1ee332e4a 472 // m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid 1:77f1ee332e4a 473 return m_EOC_pin.read();
whismanoid 1:77f1ee332e4a 474 }
whismanoid 1:77f1ee332e4a 475
whismanoid 1:77f1ee332e4a 476 //----------------------------------------
whismanoid 6:cb7bdeb185d0 477 // Menu item '!'
whismanoid 1:77f1ee332e4a 478 // Initialize device
whismanoid 9:8d47cb713984 479 //
whismanoid 9:8d47cb713984 480 // TODO1: #170 MAX11131 Self Test for Test Fixture Firmware
whismanoid 9:8d47cb713984 481 // @future test group ____ // Verify function ____ (enabled by default)
whismanoid 9:8d47cb713984 482 //
whismanoid 9:8d47cb713984 483 // @future test group DACCodeOfVoltage // Verify function DACCodeOfVoltage (enabled by default)
whismanoid 9:8d47cb713984 484 // @future test group DACCodeOfVoltage tinyTester.blink_time_msec = 20 // quickly speed through the software verification
whismanoid 9:8d47cb713984 485 // @future test group DACCodeOfVoltage tinyTester.print("VRef = 2.500 MAX5171 14-bit LSB = 0.00015V")
whismanoid 9:8d47cb713984 486 // @future test group DACCodeOfVoltage VRef = 2.500
whismanoid 9:8d47cb713984 487 // @future test group DACCodeOfVoltage tinyTester.err_threshold = 0.00015259720441921504 // 14-bit LSB (2.500/16383)
whismanoid 9:8d47cb713984 488 // //
whismanoid 9:8d47cb713984 489 // @future test group DACCodeOfVoltage DACCodeOfVoltage(2.499847412109375) expect 0x3FFF
whismanoid 9:8d47cb713984 490 // //
whismanoid 9:8d47cb713984 491 // //
whismanoid 9:8d47cb713984 492 // @future test group CODE_LOAD // Verify function CODE_LOAD (enabled by default)
whismanoid 9:8d47cb713984 493 // @future test group CODE_LOAD tinyTester.blink_time_msec = 75 // default 75 resume hardware self test
whismanoid 9:8d47cb713984 494 // @future test group CODE_LOAD tinyTester.settle_time_msec = 250
whismanoid 9:8d47cb713984 495 // @future test Init()
whismanoid 9:8d47cb713984 496 // @future test VRef expect 2.500 // Nominal Full-Scale Voltage Reference
whismanoid 9:8d47cb713984 497 // //
whismanoid 9:8d47cb713984 498 // tinyTester.err_threshold = 0.030; // 30mV
whismanoid 9:8d47cb713984 499 // @future test group CODE_LOAD tinyTester.err_threshold = 0.030
whismanoid 9:8d47cb713984 500 // @future test group CODE_LOAD tinyTester.DigitalIn_Read_Expect_WarnOnly(UPO_pin, "UPO", 1, "UPO_pin is high after MAX5171 UPO_HIGH command")
whismanoid 9:8d47cb713984 501 // @future test group CODE_LOAD tinyTester.AnalogIn0_Read_Expect_voltageV(1.2500)
whismanoid 9:8d47cb713984 502 //
whismanoid 9:8d47cb713984 503 //
whismanoid 9:8d47cb713984 504 //
whismanoid 9:8d47cb713984 505 // TODO1: #170 MAX11131 Self Test for Test Fixture Firmware
whismanoid 9:8d47cb713984 506 // @future test group ____ // Verify function ____ (enabled by default)
whismanoid 10:92aedaa14cce 507 // @future test group ____ // Verify function ____ (enabled by default)
whismanoid 9:8d47cb713984 508 // // MAX11131BOB self-test functions
whismanoid 9:8d47cb713984 509 // //~ SelfTest_FAIL(cmdLine);
whismanoid 9:8d47cb713984 510 // //~ cmdLine.serial().printf("test program not implemented yet");
whismanoid 9:8d47cb713984 511 // int16_t value_u12;
whismanoid 9:8d47cb713984 512 // int channelId;
whismanoid 9:8d47cb713984 513 // double voltageV = 0.5;
whismanoid 9:8d47cb713984 514 // //
whismanoid 9:8d47cb713984 515 // //cmdLine.serial().printf("
whismanoid 9:8d47cb713984 516 // 0.0: MAX11131.Init()");
whismanoid 9:8d47cb713984 517 // //Init();
whismanoid 9:8d47cb713984 518 // //
whismanoid 9:8d47cb713984 519 // // Device Testing: ADC commands, verify with on-board ADC and SPI framing
whismanoid 9:8d47cb713984 520 // //
whismanoid 10:92aedaa14cce 521 // @test group SPI48_3MSps // support 3MSps parts SCLK<=48MHz (enabled by default)
whismanoid 10:92aedaa14cce 522 // @test group SPI48_3MSps tinyTester.print("SPI 48MHz")
whismanoid 11:eaaf13fe381e 523 // @test group SPI48_3MSps SPIfrequency(48000000); // support 3MSps parts SCLK<=48MHz
whismanoid 11:eaaf13fe381e 524 // @test group SPI48_3MSps SPIgetFrequency() expect 48000000
whismanoid 11:eaaf13fe381e 525 // @test group SPI48_3MSps tinyTester.settle_time_msec = 250 // default 250
whismanoid 11:eaaf13fe381e 526 // @test group SPI48_3MSps tinyTester.Wait_Output_Settling()
whismanoid 11:eaaf13fe381e 527 // @test group SPI48_3MSps SPIoutputCS(0)
whismanoid 11:eaaf13fe381e 528 // @test group SPI48_3MSps SPIread16bits()
whismanoid 11:eaaf13fe381e 529 // @test group SPI48_3MSps SPIoutputCS(1)
whismanoid 10:92aedaa14cce 530 // //
whismanoid 10:92aedaa14cce 531 // @test group SPI16MHz_1MSps // support 1MSps parts SCLK<=16MHz (enabled by default)
whismanoid 10:92aedaa14cce 532 // @test group SPI16MHz_1MSps tinyTester.print("SPI 16MHz")
whismanoid 11:eaaf13fe381e 533 // @test group SPI16MHz_1MSps SPIfrequency(16000000); // support 1MSps parts SCLK<=16MHz
whismanoid 11:eaaf13fe381e 534 // @test group SPI16MHz_1MSps SPIgetFrequency() expect 16000000
whismanoid 11:eaaf13fe381e 535 // @test group SPI16MHz_1MSps tinyTester.settle_time_msec = 250 // default 250
whismanoid 11:eaaf13fe381e 536 // @test group SPI16MHz_1MSps tinyTester.Wait_Output_Settling()
whismanoid 11:eaaf13fe381e 537 // @test group SPI16MHz_1MSps SPIoutputCS(0)
whismanoid 11:eaaf13fe381e 538 // @test group SPI16MHz_1MSps SPIread16bits()
whismanoid 11:eaaf13fe381e 539 // @test group SPI16MHz_1MSps SPIoutputCS(1)
whismanoid 10:92aedaa14cce 540 // //
whismanoid 10:92aedaa14cce 541 // @test group SPI8MHz_500kSps // support 500kSps parts SCLK<=8MHz (enabled by default)
whismanoid 10:92aedaa14cce 542 // @test group SPI8MHz_500kSps tinyTester.print("SPI 8MHz")
whismanoid 11:eaaf13fe381e 543 // @test group SPI8MHz_500kSps SPIfrequency(8000000); // support 500kSps parts SCLK<=8MHz
whismanoid 11:eaaf13fe381e 544 // @test group SPI8MHz_500kSps SPIgetFrequency() expect 8000000
whismanoid 11:eaaf13fe381e 545 // @test group SPI8MHz_500kSps tinyTester.settle_time_msec = 250 // default 250
whismanoid 11:eaaf13fe381e 546 // @test group SPI8MHz_500kSps tinyTester.Wait_Output_Settling()
whismanoid 11:eaaf13fe381e 547 // @test group SPI8MHz_500kSps SPIoutputCS(0)
whismanoid 11:eaaf13fe381e 548 // @test group SPI8MHz_500kSps SPIread16bits()
whismanoid 11:eaaf13fe381e 549 // @test group SPI8MHz_500kSps SPIoutputCS(1)
whismanoid 10:92aedaa14cce 550 // //
whismanoid 10:92aedaa14cce 551 // @test group SPI12MHz_1MSps // support 1MSps parts SCLK<=16MHz (enabled by default)
whismanoid 10:92aedaa14cce 552 // @test group SPI12MHz_1MSps tinyTester.print("SPI 12MHz")
whismanoid 11:eaaf13fe381e 553 // @test group SPI12MHz_1MSps SPIfrequency(12000000); // support 1MSps parts SCLK<=16MHz
whismanoid 11:eaaf13fe381e 554 // @test group SPI12MHz_1MSps SPIgetFrequency() expect 12000000
whismanoid 11:eaaf13fe381e 555 // @test group SPI12MHz_1MSps tinyTester.settle_time_msec = 250 // default 250
whismanoid 11:eaaf13fe381e 556 // @test group SPI12MHz_1MSps tinyTester.Wait_Output_Settling()
whismanoid 11:eaaf13fe381e 557 // @test group SPI12MHz_1MSps SPIoutputCS(0)
whismanoid 11:eaaf13fe381e 558 // @test group SPI12MHz_1MSps SPIread16bits()
whismanoid 11:eaaf13fe381e 559 // @test group SPI12MHz_1MSps SPIoutputCS(1)
whismanoid 10:92aedaa14cce 560 // //
whismanoid 9:8d47cb713984 561 // @test tinyTester.blink_time_msec = 75 // default 75 resume hardware self test
whismanoid 9:8d47cb713984 562 // tinyTester.blink_time_msec = 75;
whismanoid 9:8d47cb713984 563 // // MAX11131 SelfTest: MAX11131 SPI connections (Power Supply and GND, SCLK, MOSI, MISO, CS)
whismanoid 9:8d47cb713984 564 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 565 // ");
whismanoid 9:8d47cb713984 566 // cmdLine.serial().printf(
whismanoid 9:8d47cb713984 567 // "
whismanoid 9:8d47cb713984 568 // 1.0: Test Scan_0100_StandardExt -- verify SPI (VDD, GND, SCLK, MOSI, MISO, CS)");
whismanoid 10:92aedaa14cce 569 // @test tinyTester.print("0.0: MAX11131.Init()")
whismanoid 9:8d47cb713984 570 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 571 // MAX11131.Init()");
whismanoid 9:8d47cb713984 572 // Init();
whismanoid 10:92aedaa14cce 573 // @test Init()
whismanoid 10:92aedaa14cce 574 // @test VRef expect 2.500 // Nominal Full-Scale Voltage Reference
whismanoid 10:92aedaa14cce 575 // //
whismanoid 10:92aedaa14cce 576 // @test group TEST10_SCAN_0100 // Test SCAN_0100_StandardExt -- verify VDD,GND,SCLK,MOSI,MISO,CS (enabled by default)
whismanoid 10:92aedaa14cce 577 // @test group TEST10_SCAN_0100 tinyTester.print("1.0: Test SCAN_0100_StandardExt -- verify VDD,GND,SCLK,MOSI,MISO,CS")
whismanoid 10:92aedaa14cce 578 // @test group TEST10_SCAN_0100 SPIoutputCS(0)
whismanoid 10:92aedaa14cce 579 // @test group TEST10_SCAN_0100 tinyTester.print("0000_0000_0100_0010 ADC_MODE_CONTROL SCAN_0000")
whismanoid 10:92aedaa14cce 580 // @test group TEST10_SCAN_0100 tinyTester.print(" CHSEL=0 RESET=2 CHANID=1")
whismanoid 10:92aedaa14cce 581 // @test group TEST10_SCAN_0100 SPIwrite16bits(0x0040)
whismanoid 10:92aedaa14cce 582 // @test group TEST10_SCAN_0100 SPIoutputCS(1)
whismanoid 10:92aedaa14cce 583 // @test group TEST10_SCAN_0100 SPIoutputCS(0)
whismanoid 10:92aedaa14cce 584 // @test group TEST10_SCAN_0100 SPIread16bits()
whismanoid 10:92aedaa14cce 585 // @test group TEST10_SCAN_0100 SPIoutputCS(1)
whismanoid 10:92aedaa14cce 586 // @test group TEST10_SCAN_0100 SPIoutputCS(0)
whismanoid 10:92aedaa14cce 587 // @test group TEST10_SCAN_0100 SPIread16bits()
whismanoid 10:92aedaa14cce 588 // @test group TEST10_SCAN_0100 SPIoutputCS(1)
whismanoid 10:92aedaa14cce 589 // @test group TEST10_SCAN_0100 SPIoutputCS(0)
whismanoid 10:92aedaa14cce 590 // @test group TEST10_SCAN_0100 SPIread16bits()
whismanoid 10:92aedaa14cce 591 // @test group TEST10_SCAN_0100 SPIoutputCS(1)
whismanoid 10:92aedaa14cce 592 // @test group TEST10_SCAN_0100 tinyTester.print("1000_0000_0000_0000 ADC_CONFIGURATION REFSEL=0 SPM[1:0]=0 ECHO=0")
whismanoid 10:92aedaa14cce 593 // @test group TEST10_SCAN_0100 SPIoutputCS(0)
whismanoid 10:92aedaa14cce 594 // @test group TEST10_SCAN_0100 SPIwrite16bits(0x8000)
whismanoid 10:92aedaa14cce 595 // @test group TEST10_SCAN_0100 SPIoutputCS(1)
whismanoid 10:92aedaa14cce 596 // @test group TEST10_SCAN_0100 tinyTester.print("0010_0111_1010_0100 ADC_MODE_CONTROL SCAN_0100_StandardExt")
whismanoid 10:92aedaa14cce 597 // @test group TEST10_SCAN_0100 tinyTester.print(" CHSEL=15 RESET=1 CHANID=1")
whismanoid 10:92aedaa14cce 598 // @test group TEST10_SCAN_0100 SPIoutputCS(0)
whismanoid 10:92aedaa14cce 599 // @test group TEST10_SCAN_0100 SPIwrite16bits(0x27a4)
whismanoid 10:92aedaa14cce 600 // @test group TEST10_SCAN_0100 SPIoutputCS(1)
whismanoid 10:92aedaa14cce 601 // @test group TEST10_SCAN_0100 tinyTester.print("MISO --> expect 0x0xxx (channel ID 0)")
whismanoid 10:92aedaa14cce 602 // @test group TEST10_SCAN_0100 SPIoutputCS(0)
whismanoid 10:92aedaa14cce 603 // @test group TEST10_SCAN_0100 SPIread16bits() expect 0x0000 mask 0xF000 // expect 0x0xxx (channel ID 0)
whismanoid 10:92aedaa14cce 604 // @test group TEST10_SCAN_0100 SPIoutputCS(1)
whismanoid 10:92aedaa14cce 605 // @test group TEST10_SCAN_0100 tinyTester.print("MISO --> expect 0x1xxx (channel ID 1)")
whismanoid 10:92aedaa14cce 606 // @test group TEST10_SCAN_0100 SPIoutputCS(0)
whismanoid 10:92aedaa14cce 607 // @test group TEST10_SCAN_0100 SPIread16bits() expect 0x1000 mask 0xF000 // expect 0x1xxx (channel ID 1)
whismanoid 10:92aedaa14cce 608 // @test group TEST10_SCAN_0100 SPIoutputCS(1)
whismanoid 10:92aedaa14cce 609 // @test group TEST10_SCAN_0100 tinyTester.print("MISO --> expect 0x2xxx (channel ID 2)")
whismanoid 10:92aedaa14cce 610 // @test group TEST10_SCAN_0100 SPIoutputCS(0)
whismanoid 10:92aedaa14cce 611 // @test group TEST10_SCAN_0100 SPIread16bits() expect 0x2000 mask 0xF000 // expect 0x2xxx (channel ID 2)
whismanoid 10:92aedaa14cce 612 // @test group TEST10_SCAN_0100 SPIoutputCS(1)
whismanoid 10:92aedaa14cce 613 // @test group TEST10_SCAN_0100 tinyTester.print("MISO --> expect 0x3xxx (channel ID 3)")
whismanoid 10:92aedaa14cce 614 // @test group TEST10_SCAN_0100 SPIoutputCS(0)
whismanoid 10:92aedaa14cce 615 // @test group TEST10_SCAN_0100 SPIread16bits() expect 0x3000 mask 0xF000 // expect 0x3xxx (channel ID 3)
whismanoid 10:92aedaa14cce 616 // @test group TEST10_SCAN_0100 SPIoutputCS(1)
whismanoid 10:92aedaa14cce 617 // @test group TEST10_SCAN_0100 tinyTester.print("MISO --> expect 0x4xxx (channel ID 4)")
whismanoid 10:92aedaa14cce 618 // @test group TEST10_SCAN_0100 SPIoutputCS(0)
whismanoid 10:92aedaa14cce 619 // @test group TEST10_SCAN_0100 SPIread16bits() expect 0x4000 mask 0xF000 // expect 0x4xxx (channel ID 4)
whismanoid 10:92aedaa14cce 620 // @test group TEST10_SCAN_0100 SPIoutputCS(1)
whismanoid 10:92aedaa14cce 621 // @test group TEST10_SCAN_0100 tinyTester.print("MISO --> expect 0x5xxx (channel ID 5)")
whismanoid 10:92aedaa14cce 622 // @test group TEST10_SCAN_0100 SPIoutputCS(0)
whismanoid 10:92aedaa14cce 623 // @test group TEST10_SCAN_0100 SPIread16bits() expect 0x5000 mask 0xF000 // expect 0x5xxx (channel ID 5)
whismanoid 10:92aedaa14cce 624 // @test group TEST10_SCAN_0100 SPIoutputCS(1)
whismanoid 10:92aedaa14cce 625 // @test group TEST10_SCAN_0100 tinyTester.print("MISO --> expect 0x6xxx (channel ID 6)")
whismanoid 10:92aedaa14cce 626 // @test group TEST10_SCAN_0100 SPIoutputCS(0)
whismanoid 10:92aedaa14cce 627 // @test group TEST10_SCAN_0100 SPIread16bits() expect 0x6000 mask 0xF000 // expect 0x6xxx (channel ID 6)
whismanoid 10:92aedaa14cce 628 // @test group TEST10_SCAN_0100 SPIoutputCS(1)
whismanoid 10:92aedaa14cce 629 // @test group TEST10_SCAN_0100 tinyTester.print("MISO --> expect 0x7xxx (channel ID 7)")
whismanoid 10:92aedaa14cce 630 // @test group TEST10_SCAN_0100 SPIoutputCS(0)
whismanoid 10:92aedaa14cce 631 // @test group TEST10_SCAN_0100 SPIread16bits() expect 0x7000 mask 0xF000 // expect 0x7xxx (channel ID 7)
whismanoid 10:92aedaa14cce 632 // @test group TEST10_SCAN_0100 SPIoutputCS(1)
whismanoid 10:92aedaa14cce 633 // @test group TEST10_SCAN_0100 tinyTester.print("MISO --> expect 0x8xxx (channel ID 8)")
whismanoid 10:92aedaa14cce 634 // @test group TEST10_SCAN_0100 SPIoutputCS(0)
whismanoid 10:92aedaa14cce 635 // @test group TEST10_SCAN_0100 SPIread16bits() expect 0x8000 mask 0xF000 // expect 0x8xxx (channel ID 8)
whismanoid 10:92aedaa14cce 636 // @test group TEST10_SCAN_0100 SPIoutputCS(1)
whismanoid 10:92aedaa14cce 637 // @test group TEST10_SCAN_0100 tinyTester.print("MISO --> expect 0x9xxx (channel ID 9)")
whismanoid 10:92aedaa14cce 638 // @test group TEST10_SCAN_0100 SPIoutputCS(0)
whismanoid 10:92aedaa14cce 639 // @test group TEST10_SCAN_0100 SPIread16bits() expect 0x9000 mask 0xF000 // expect 0x9xxx (channel ID 9)
whismanoid 10:92aedaa14cce 640 // @test group TEST10_SCAN_0100 SPIoutputCS(1)
whismanoid 10:92aedaa14cce 641 // @test group TEST10_SCAN_0100 tinyTester.print("MISO --> expect 0xaxxx (channel ID 10)")
whismanoid 10:92aedaa14cce 642 // @test group TEST10_SCAN_0100 SPIoutputCS(0)
whismanoid 10:92aedaa14cce 643 // @test group TEST10_SCAN_0100 SPIread16bits() expect 0xA000 mask 0xF000 // expect 0xaxxx (channel ID 10)
whismanoid 10:92aedaa14cce 644 // @test group TEST10_SCAN_0100 SPIoutputCS(1)
whismanoid 10:92aedaa14cce 645 // @test group TEST10_SCAN_0100 tinyTester.print("MISO --> expect 0xbxxx (channel ID 11)")
whismanoid 10:92aedaa14cce 646 // @test group TEST10_SCAN_0100 SPIoutputCS(0)
whismanoid 10:92aedaa14cce 647 // @test group TEST10_SCAN_0100 SPIread16bits() expect 0xB000 mask 0xF000 // expect 0xbxxx (channel ID 11)
whismanoid 10:92aedaa14cce 648 // @test group TEST10_SCAN_0100 SPIoutputCS(1)
whismanoid 10:92aedaa14cce 649 // @test group TEST10_SCAN_0100 tinyTester.print("MISO --> expect 0xcxxx (channel ID 12)")
whismanoid 10:92aedaa14cce 650 // @test group TEST10_SCAN_0100 SPIoutputCS(0)
whismanoid 10:92aedaa14cce 651 // @test group TEST10_SCAN_0100 SPIread16bits() expect 0xC000 mask 0xF000 // expect 0xcxxx (channel ID 12)
whismanoid 10:92aedaa14cce 652 // @test group TEST10_SCAN_0100 SPIoutputCS(1)
whismanoid 10:92aedaa14cce 653 // @test group TEST10_SCAN_0100 tinyTester.print("MISO --> expect 0xdxxx (channel ID 13)")
whismanoid 10:92aedaa14cce 654 // @test group TEST10_SCAN_0100 SPIoutputCS(0)
whismanoid 10:92aedaa14cce 655 // @test group TEST10_SCAN_0100 SPIread16bits() expect 0xD000 mask 0xF000 // expect 0xdxxx (channel ID 13)
whismanoid 10:92aedaa14cce 656 // @test group TEST10_SCAN_0100 SPIoutputCS(1)
whismanoid 10:92aedaa14cce 657 // @test group TEST10_SCAN_0100 tinyTester.print("MISO --> expect 0xexxx (channel ID 14)")
whismanoid 10:92aedaa14cce 658 // @test group TEST10_SCAN_0100 SPIoutputCS(0)
whismanoid 10:92aedaa14cce 659 // @test group TEST10_SCAN_0100 SPIread16bits() expect 0xE000 mask 0xF000 // expect 0xexxx (channel ID 14)
whismanoid 10:92aedaa14cce 660 // @test group TEST10_SCAN_0100 SPIoutputCS(1)
whismanoid 10:92aedaa14cce 661 // @test group TEST10_SCAN_0100 tinyTester.print("MISO --> expect 0xfxxx (channel ID 15)")
whismanoid 10:92aedaa14cce 662 // @test group TEST10_SCAN_0100 SPIoutputCS(0)
whismanoid 10:92aedaa14cce 663 // @test group TEST10_SCAN_0100 SPIread16bits() expect 0xF000 mask 0xF000 // expect 0xfxxx (channel ID 15)
whismanoid 10:92aedaa14cce 664 // @test group TEST10_SCAN_0100 SPIoutputCS(1)
whismanoid 10:92aedaa14cce 665 // //
whismanoid 10:92aedaa14cce 666 // @test group TEST4_SCAN_0100 // 4 ch=15 pm=0 id=1 -- ScanStandardExternalCloc (enabled by default)
whismanoid 10:92aedaa14cce 667 // @test group TEST4_SCAN_0100 tinyTester.print("4 ch=15 pm=0 id=1 -- ScanStandardExternalClock")
whismanoid 10:92aedaa14cce 668 // @test group TEST4_SCAN_0100 tinyTester.print("channelNumber_0_15 = 15")
whismanoid 10:92aedaa14cce 669 // @test group TEST4_SCAN_0100 channelNumber_0_15 = 15
whismanoid 10:92aedaa14cce 670 // @test group TEST4_SCAN_0100 tinyTester.print("PowerManagement_0_2 = 0")
whismanoid 10:92aedaa14cce 671 // @test group TEST4_SCAN_0100 PowerManagement_0_2 = 0 // 0=Normal
whismanoid 10:92aedaa14cce 672 // @test group TEST4_SCAN_0100 tinyTester.print("chan_id_0_1 = 1")
whismanoid 10:92aedaa14cce 673 // @test group TEST4_SCAN_0100 chan_id_0_1 = 1 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 10:92aedaa14cce 674 // @test group TEST4_SCAN_0100 tinyTester.print("ScanStandardExternalClock() expect 16")
whismanoid 10:92aedaa14cce 675 // @test group TEST4_SCAN_0100 ScanStandardExternalClock() expect 16 // Scan_0100_StandardExt
whismanoid 10:92aedaa14cce 676 // @test group TEST4_SCAN_0100 tinyTester.print("NumWords expect 16")
whismanoid 10:92aedaa14cce 677 // @test group TEST4_SCAN_0100 NumWords expect 16
whismanoid 10:92aedaa14cce 678 // @test group TEST4_SCAN_0100 ReadAINcode()
whismanoid 10:92aedaa14cce 679 // @test group TEST4_SCAN_0100 tinyTester.print("Verify RAW_misoData16[0..15]>>12&0x000F == 0..15 channelId")
whismanoid 10:92aedaa14cce 680 // @test group TEST4_SCAN_0100 RAW_misoData16[0] expect 0x0000 mask 0xF000 // expect 0x0xxx (channel ID 0)
whismanoid 10:92aedaa14cce 681 // @test group TEST4_SCAN_0100 RAW_misoData16[1] expect 0x1000 mask 0xF000 // expect 0x1xxx (channel ID 1)
whismanoid 10:92aedaa14cce 682 // @test group TEST4_SCAN_0100 RAW_misoData16[2] expect 0x2000 mask 0xF000 // expect 0x2xxx (channel ID 2)
whismanoid 10:92aedaa14cce 683 // @test group TEST4_SCAN_0100 RAW_misoData16[3] expect 0x3000 mask 0xF000 // expect 0x3xxx (channel ID 3)
whismanoid 10:92aedaa14cce 684 // @test group TEST4_SCAN_0100 RAW_misoData16[4] expect 0x4000 mask 0xF000 // expect 0x4xxx (channel ID 4)
whismanoid 10:92aedaa14cce 685 // @test group TEST4_SCAN_0100 RAW_misoData16[5] expect 0x5000 mask 0xF000 // expect 0x5xxx (channel ID 5)
whismanoid 10:92aedaa14cce 686 // @test group TEST4_SCAN_0100 RAW_misoData16[6] expect 0x6000 mask 0xF000 // expect 0x6xxx (channel ID 6)
whismanoid 10:92aedaa14cce 687 // @test group TEST4_SCAN_0100 RAW_misoData16[7] expect 0x7000 mask 0xF000 // expect 0x7xxx (channel ID 7)
whismanoid 10:92aedaa14cce 688 // @test group TEST4_SCAN_0100 RAW_misoData16[8] expect 0x8000 mask 0xF000 // expect 0x8xxx (channel ID 8)
whismanoid 10:92aedaa14cce 689 // @test group TEST4_SCAN_0100 RAW_misoData16[9] expect 0x9000 mask 0xF000 // expect 0x9xxx (channel ID 9)
whismanoid 10:92aedaa14cce 690 // @test group TEST4_SCAN_0100 RAW_misoData16[10] expect 0xA000 mask 0xF000 // expect 0xaxxx (channel ID 10)
whismanoid 10:92aedaa14cce 691 // @test group TEST4_SCAN_0100 RAW_misoData16[11] expect 0xB000 mask 0xF000 // expect 0xbxxx (channel ID 11)
whismanoid 10:92aedaa14cce 692 // @test group TEST4_SCAN_0100 RAW_misoData16[12] expect 0xC000 mask 0xF000 // expect 0xcxxx (channel ID 12)
whismanoid 10:92aedaa14cce 693 // @test group TEST4_SCAN_0100 RAW_misoData16[13] expect 0xD000 mask 0xF000 // expect 0xdxxx (channel ID 13)
whismanoid 10:92aedaa14cce 694 // @test group TEST4_SCAN_0100 RAW_misoData16[14] expect 0xE000 mask 0xF000 // expect 0xexxx (channel ID 14)
whismanoid 10:92aedaa14cce 695 // @test group TEST4_SCAN_0100 RAW_misoData16[15] expect 0xF000 mask 0xF000 // expect 0xfxxx (channel ID 15)
whismanoid 9:8d47cb713984 696 // // Send MOSI data Expect MISO data Description
whismanoid 9:8d47cb713984 697 // // 1000_0000_0000_0000 xxxx_xxxx_xxxx_xxxx ADC_CONFIGURATION REFSEL=0 SPM[1:0]=0 ECHO=0
whismanoid 9:8d47cb713984 698 // // 0010_0111_1010_0100 xxxx_xxxx_xxxx_xxxx ADC_MODE_CONTROL Scan_0100_StandardExt CHSEL=15 RESET=1 CHANID=1
whismanoid 9:8d47cb713984 699 // // 0000_0000_0000_0000 0000_xxxx_xxxx_xxxx Channel ID tag = AIN0 expect high nybble 0
whismanoid 9:8d47cb713984 700 // // 0000_0000_0000_0000 0001_xxxx_xxxx_xxxx Channel ID tag = AIN1 expect high nybble 1
whismanoid 9:8d47cb713984 701 // // 0000_0000_0000_0000 0010_xxxx_xxxx_xxxx Channel ID tag = AIN2 expect high nybble 2
whismanoid 9:8d47cb713984 702 // // 0000_0000_0000_0000 0011_xxxx_xxxx_xxxx Channel ID tag = AIN3 expect high nybble 3
whismanoid 9:8d47cb713984 703 // //
whismanoid 9:8d47cb713984 704 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 705 // MOSI <-- 1000_0000_0000_0000 ADC_CONFIGURATION REFSEL=0 SPM[1:0]=0 ECHO=0");
whismanoid 10:92aedaa14cce 706 // @test tinyTester.print("1000_0000_0000_0000 ADC_CONFIGURATION REFSEL=0 SPM[1:0]=0 ECHO=0")
whismanoid 9:8d47cb713984 707 // SPIoutputCS(0); // drive CS low
whismanoid 9:8d47cb713984 708 // SPIwrite16bits(0x8000);
whismanoid 9:8d47cb713984 709 // SPIoutputCS(1); // drive CS high
whismanoid 9:8d47cb713984 710 // @test SPIoutputCS(0)
whismanoid 9:8d47cb713984 711 // @test SPIwrite16bits(0x8000)
whismanoid 9:8d47cb713984 712 // @test SPIoutputCS(1)
whismanoid 9:8d47cb713984 713 // //
whismanoid 9:8d47cb713984 714 // cmdLine.serial().printf(
whismanoid 9:8d47cb713984 715 // "
whismanoid 9:8d47cb713984 716 // MOSI <-- 0010_0111_1010_0100 ADC_MODE_CONTROL Scan_0100_StandardExt CHSEL=15 RESET=1 CHANID=1");
whismanoid 10:92aedaa14cce 717 // @test tinyTester.print("0010_0111_1010_0100 ADC_MODE_CONTROL Scan_0100_StandardExt")
whismanoid 10:92aedaa14cce 718 // @test tinyTester.print(" CHSEL=15 RESET=1 CHANID=1")
whismanoid 9:8d47cb713984 719 // SPIoutputCS(0); // drive CS low
whismanoid 9:8d47cb713984 720 // SPIwrite16bits(0x27a4);
whismanoid 9:8d47cb713984 721 // SPIoutputCS(1); // drive CS high
whismanoid 10:92aedaa14cce 722 // @test SPIoutputCS(0)
whismanoid 10:92aedaa14cce 723 // @test SPIwrite16bits(0x27a4)
whismanoid 10:92aedaa14cce 724 // @test SPIoutputCS(1)
whismanoid 10:92aedaa14cce 725 // //
whismanoid 9:8d47cb713984 726 // @future test SPIoutputCS(0)
whismanoid 10:92aedaa14cce 727 // @future SPIread16bits() expect 0x0000
whismanoid 10:92aedaa14cce 728 // @future SPIread16bits() expect 0x0000 mask 0xF000
whismanoid 10:92aedaa14cce 729 // @future test SPIread16bits() expect 0x1000 mask 0xF000
whismanoid 10:92aedaa14cce 730 // @future test SPIread16bits() expect 0x2000 mask 0xF000
whismanoid 10:92aedaa14cce 731 // @future test SPIread16bits() expect 0x3000 mask 0xF000
whismanoid 10:92aedaa14cce 732 // @future test SPIread16bits() expect 0x4000 mask 0xF000
whismanoid 10:92aedaa14cce 733 // @future test SPIread16bits() expect 0x5000 mask 0xF000
whismanoid 10:92aedaa14cce 734 // @future test SPIread16bits() expect 0x6000 mask 0xF000
whismanoid 10:92aedaa14cce 735 // @future test SPIread16bits() expect 0x7000 mask 0xF000
whismanoid 10:92aedaa14cce 736 // @future test SPIread16bits() expect 0x8000 mask 0xF000
whismanoid 10:92aedaa14cce 737 // @future test SPIread16bits() expect 0x9000 mask 0xF000
whismanoid 10:92aedaa14cce 738 // @future test SPIread16bits() expect 0xA000 mask 0xF000
whismanoid 10:92aedaa14cce 739 // @future test SPIread16bits() expect 0xB000 mask 0xF000
whismanoid 10:92aedaa14cce 740 // @future test SPIread16bits() expect 0xC000 mask 0xF000
whismanoid 10:92aedaa14cce 741 // @future test SPIread16bits() expect 0xD000 mask 0xF000
whismanoid 10:92aedaa14cce 742 // @future test SPIread16bits() expect 0xE000 mask 0xF000
whismanoid 10:92aedaa14cce 743 // @future test SPIread16bits() expect 0xF000 mask 0xF000
whismanoid 9:8d47cb713984 744 // @future test SPIoutputCS(1)
whismanoid 9:8d47cb713984 745 // //
whismanoid 9:8d47cb713984 746 // for (int channelIndex = 0; channelIndex < 16; channelIndex++) {
whismanoid 9:8d47cb713984 747 // //~ cmdLine.serial().printf("
whismanoid 9:8d47cb713984 748 // MISO --> expect 0000_xxxx_xxxx_xxxx");
whismanoid 9:8d47cb713984 749 // SPIoutputCS(0); // drive CS low
whismanoid 9:8d47cb713984 750 // RAW_misoData16[channelIndex] = SPIread16bits();
whismanoid 9:8d47cb713984 751 // SPIoutputCS(1); // drive CS high
whismanoid 9:8d47cb713984 752 // int expect_channelId = channelIndex;
whismanoid 9:8d47cb713984 753 // int actual_channelId = (RAW_misoData16[channelIndex] >> 12) & 0x000F;
whismanoid 9:8d47cb713984 754 // if (actual_channelId != expect_channelId)
whismanoid 9:8d47cb713984 755 // {
whismanoid 9:8d47cb713984 756 // tinyTester.FAIL();
whismanoid 9:8d47cb713984 757 // cmdLine.serial().printf("MISO --> 0x%4.4x", (RAW_misoData16[channelIndex] & 0xFFFF));
whismanoid 9:8d47cb713984 758 // cmdLine.serial().printf(" expect 0x%1.1xxxx (channel ID %d)", expect_channelId, expect_channelId);
whismanoid 9:8d47cb713984 759 // cmdLine.serial().printf(" but got 0x%1.1xxxx", actual_channelId);
whismanoid 9:8d47cb713984 760 // }
whismanoid 9:8d47cb713984 761 // else
whismanoid 9:8d47cb713984 762 // {
whismanoid 9:8d47cb713984 763 // tinyTester.PASS();
whismanoid 9:8d47cb713984 764 // cmdLine.serial().printf("MISO --> 0x%4.4x", (RAW_misoData16[channelIndex] & 0xFFFF));
whismanoid 9:8d47cb713984 765 // cmdLine.serial().printf(" expect 0x%1.1xxxx (channel ID %d)", expect_channelId, expect_channelId);
whismanoid 9:8d47cb713984 766 // }
whismanoid 9:8d47cb713984 767 // }
whismanoid 10:92aedaa14cce 768 // @future test tinyTester.print("NumWords=16")
whismanoid 10:92aedaa14cce 769 // @future test NumWords=16
whismanoid 10:92aedaa14cce 770 // @future test tinyTester.print("ReadAINcode()")
whismanoid 10:92aedaa14cce 771 // @future test ReadAINcode()
whismanoid 10:92aedaa14cce 772 // @future test tinyTester.print("TODO: expect RAW_misoData16[0..15]>>12&0x000F == 0..15 channelId")
whismanoid 10:92aedaa14cce 773 // @future test RAW_misoData16[0] expect 0x0000 mask 0xF000
whismanoid 10:92aedaa14cce 774 // @future test RAW_misoData16[1] expect 0x1000 mask 0xF000
whismanoid 10:92aedaa14cce 775 // @future test RAW_misoData16[2] expect 0x2000 mask 0xF000
whismanoid 10:92aedaa14cce 776 // @future test RAW_misoData16[3] expect 0x3000 mask 0xF000
whismanoid 9:8d47cb713984 777 // //
whismanoid 9:8d47cb713984 778 // // MAX11131 SelfTest: MAX11131 Supports Internal Clock Modes (CNVST, EOC)
whismanoid 9:8d47cb713984 779 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 780 // ");
whismanoid 9:8d47cb713984 781 // cmdLine.serial().printf(
whismanoid 9:8d47cb713984 782 // "
whismanoid 9:8d47cb713984 783 // 1.1: Test Scan_0011_StandardInt -- verify Internal Clock signals (CNVST, EOC)");
whismanoid 10:92aedaa14cce 784 // @test group TEST11_SCAN_0011 // 1.1: Test Scan_0011_StandardInt -- verify Internal Clock CNVST,EOC (enabled by default)
whismanoid 10:92aedaa14cce 785 // @test group TEST11_SCAN_0011 tinyTester.print("1.1: Test Scan_0011_StandardInt -- verify Internal Clock CNVST,EOC")
whismanoid 9:8d47cb713984 786 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 787 // MAX11131.Init()");
whismanoid 10:92aedaa14cce 788 // @future test tinyTester.print("_______")
whismanoid 10:92aedaa14cce 789 // @test group TEST11_SCAN_0011 Init();
whismanoid 10:92aedaa14cce 790 // @test group TEST11_SCAN_0011 SPIoutputCS(0); // drive CS low
whismanoid 9:8d47cb713984 791 // RAW_misoData16[0] = SPIread16bits();
whismanoid 10:92aedaa14cce 792 // @test group TEST11_SCAN_0011 group TEST11_SCAN_0011 SPIoutputCS(1); // drive CS high
whismanoid 9:8d47cb713984 793 // //
whismanoid 9:8d47cb713984 794 // // tinyTester.DigitalIn_Read_Expect_WarnOnly replaces SelfTest_MAX11131_EOC_expect
whismanoid 9:8d47cb713984 795 // tinyTester.DigitalIn_Read_Expect_WarnOnly(EOCb_pin, "EOC", 1, "initial value before sending commands");
whismanoid 9:8d47cb713984 796 // //
whismanoid 9:8d47cb713984 797 // // Send MOSI data Expect MISO data Description
whismanoid 9:8d47cb713984 798 // // 1000_0000_0000_0000 xxxx_xxxx_xxxx_xxxx ADC_CONFIGURATION REFSEL=0 SPM[1:0]=0 ECHO=0 No Averaging
whismanoid 9:8d47cb713984 799 // // 0001_1001_1010_0000 xxxx_xxxx_xxxx_xxxx ADC_MODE_CONTROL Scan_0011_StandardInt CHSEL=3 RESET=1 SWCNV=0
whismanoid 9:8d47cb713984 800 // // 0000_0000_0000_0000 0000_xxxx_xxxx_xxxx Channel ID tag = AIN0 expect high nybble 0
whismanoid 9:8d47cb713984 801 // // 0000_0000_0000_0000 0001_xxxx_xxxx_xxxx Channel ID tag = AIN1 expect high nybble 1
whismanoid 9:8d47cb713984 802 // // 0000_0000_0000_0000 0010_xxxx_xxxx_xxxx Channel ID tag = AIN2 expect high nybble 2
whismanoid 9:8d47cb713984 803 // // 0000_0000_0000_0000 0011_xxxx_xxxx_xxxx Channel ID tag = AIN3 expect high nybble 3
whismanoid 9:8d47cb713984 804 // //
whismanoid 9:8d47cb713984 805 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 806 // MOSI <-- 1000_0000_0000_0000 ADC_CONFIGURATION REFSEL=0 SPM[1:0]=0 ECHO=0");
whismanoid 10:92aedaa14cce 807 // @test group TEST11_SCAN_0011 tinyTester.print("1000_0000_0000_0000 ADC_CONFIGURATION REFSEL=0 SPM[1:0]=0 ECHO=0")
whismanoid 10:92aedaa14cce 808 // @test group TEST11_SCAN_0011 SPIoutputCS(0); // drive CS low
whismanoid 10:92aedaa14cce 809 // @test group TEST11_SCAN_0011 SPIwrite16bits(0x8000);
whismanoid 10:92aedaa14cce 810 // @test group TEST11_SCAN_0011 SPIoutputCS(1); // drive CS high
whismanoid 9:8d47cb713984 811 // //
whismanoid 9:8d47cb713984 812 // cmdLine.serial().printf(
whismanoid 9:8d47cb713984 813 // "
whismanoid 9:8d47cb713984 814 // MOSI <-- 0001_1001_1010_0000 ADC_MODE_CONTROL Scan_0011_StandardInt CHSEL=3 RESET=1 SWCNV=0");
whismanoid 10:92aedaa14cce 815 // @test group TEST11_SCAN_0011 tinyTester.print("0001_1001_1010_0000 ADC_MODE_CONTROL Scan_0011_StandardInt")
whismanoid 10:92aedaa14cce 816 // @test group TEST11_SCAN_0011 tinyTester.print(" CHSEL=3 RESET=1 SWCNV=0")
whismanoid 10:92aedaa14cce 817 // @test group TEST11_SCAN_0011 SPIoutputCS(0); // drive CS low
whismanoid 10:92aedaa14cce 818 // @test group TEST11_SCAN_0011 SPIwrite16bits(0x19a0);
whismanoid 10:92aedaa14cce 819 // @test group TEST11_SCAN_0011 SPIoutputCS(1); // drive CS high
whismanoid 9:8d47cb713984 820 // //
whismanoid 9:8d47cb713984 821 // for (int channelIndex = 0; channelIndex < 4; channelIndex++) {
whismanoid 9:8d47cb713984 822 // //~ cmdLine.serial().printf("
whismanoid 9:8d47cb713984 823 // MISO --> expect 0000_xxxx_xxxx_xxxx");
whismanoid 9:8d47cb713984 824 // //~ wait_ms(200); // delay
whismanoid 9:8d47cb713984 825 // CNVSToutputPulseLow();
whismanoid 9:8d47cb713984 826 // //~ CNVSToutputValue(0);
whismanoid 9:8d47cb713984 827 // //~ wait_ms(100); // delay
whismanoid 9:8d47cb713984 828 // //~ CNVSToutputValue(1);
whismanoid 9:8d47cb713984 829 // // EOCinputWaitUntilLow(); // infinite wait hazard, need to fail if timeout exceeded
whismanoid 9:8d47cb713984 830 // // tinyTester.DigitalIn_Read_Expect_WarnOnly replaces SelfTest_MAX11131_EOC_expect
whismanoid 9:8d47cb713984 831 // tinyTester.DigitalIn_Read_Expect_WarnOnly(EOCb_pin, "EOC", 0, "after CNVST pulse");
whismanoid 9:8d47cb713984 832 // SPIoutputCS(0); // drive CS low
whismanoid 9:8d47cb713984 833 // RAW_misoData16[channelIndex] = SPIread16bits();
whismanoid 9:8d47cb713984 834 // SPIoutputCS(1); // drive CS high
whismanoid 9:8d47cb713984 835 // // tinyTester.DigitalIn_Read_Expect_WarnOnly replaces SelfTest_MAX11131_EOC_expect
whismanoid 9:8d47cb713984 836 // tinyTester.DigitalIn_Read_Expect_WarnOnly(EOCb_pin, "EOC", 1, "after SPI read");
whismanoid 9:8d47cb713984 837 // int expect_channelId = channelIndex;
whismanoid 9:8d47cb713984 838 // int actual_channelId = (RAW_misoData16[channelIndex] >> 12) & 0x000F;
whismanoid 9:8d47cb713984 839 // if (actual_channelId != expect_channelId)
whismanoid 9:8d47cb713984 840 // {
whismanoid 9:8d47cb713984 841 // tinyTester.FAIL();
whismanoid 9:8d47cb713984 842 // cmdLine.serial().printf("MISO --> 0x%4.4x", (RAW_misoData16[channelIndex] & 0xFFFF));
whismanoid 9:8d47cb713984 843 // cmdLine.serial().printf(" expect 0x%1.1xxxx (channel ID %d)", expect_channelId, expect_channelId);
whismanoid 9:8d47cb713984 844 // cmdLine.serial().printf(" but got 0x%1.1xxxx", actual_channelId);
whismanoid 9:8d47cb713984 845 // }
whismanoid 9:8d47cb713984 846 // else
whismanoid 9:8d47cb713984 847 // {
whismanoid 9:8d47cb713984 848 // tinyTester.PASS();
whismanoid 9:8d47cb713984 849 // cmdLine.serial().printf("MISO --> 0x%4.4x", (RAW_misoData16[channelIndex] & 0xFFFF));
whismanoid 9:8d47cb713984 850 // cmdLine.serial().printf(" expect 0x%1.1xxxx (channel ID %d)", expect_channelId, expect_channelId);
whismanoid 9:8d47cb713984 851 // }
whismanoid 9:8d47cb713984 852 // }
whismanoid 9:8d47cb713984 853 // //
whismanoid 9:8d47cb713984 854 // // MAX11131 SelfTest: Test Fixture: MAX541ACPA+ to MAX32625MBED.AIN0/AIN4
whismanoid 9:8d47cb713984 855 // // Test Fixture: MAX541 connected to spi2
whismanoid 9:8d47cb713984 856 // // SPI spi2_max541(SPI2_MOSI, SPI2_MISO, SPI2_SCK); // mosi, miso, sclk spi2 TARGET_MAX32635MBED: P2_5 P2_6 P2_4 Arduino 2x3-pin header; microSD
whismanoid 9:8d47cb713984 857 // // DigitalOut spi2_max541_cs(SPI2_SS); // TARGET_MAX32635MBED: P2_7 Arduino 2x3-pin header
whismanoid 9:8d47cb713984 858 // // Test Fixture: MAX541 spi2 init
whismanoid 9:8d47cb713984 859 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 860 // ");
whismanoid 9:8d47cb713984 861 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 862 // 2.0: Test Fixture: MAX541 connected to spi2 (P2.4 P2.5 P2.7)?");
whismanoid 10:92aedaa14cce 863 // @future test tinyTester.print("_______")
whismanoid 9:8d47cb713984 864 // bool SelfTest_has_max541 = false;
whismanoid 9:8d47cb713984 865 // // Check actual MAX541 reference voltage
whismanoid 9:8d47cb713984 866 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 867 // Test Fixture: MAX541 midscale voltage measure with MAX32625MBED AIN0/4");
whismanoid 9:8d47cb713984 868 // max541.Set_Code(0x8000); // we don't know the fullscale voltage yet, so set code to midscale
whismanoid 9:8d47cb713984 869 // tinyTester.Wait_Output_Settling(); // wait for MAX541 to settle
whismanoid 9:8d47cb713984 870 // //
whismanoid 9:8d47cb713984 871 // double max541_midscale_V = analogInPin_fullScaleVoltage[4] * analogIn4.read(); // TARGET_MAX32630 J1.5 AIN_4 = AIN0 / 5.0 fullscale is 6.0V
whismanoid 9:8d47cb713984 872 // const int average_count = 100;
whismanoid 9:8d47cb713984 873 // const double average_K = 0.25;
whismanoid 9:8d47cb713984 874 // for (int count = 0; count < average_count; count++) {
whismanoid 9:8d47cb713984 875 // double measurement_V = analogInPin_fullScaleVoltage[4] * analogIn4.read(); // TARGET_MAX32630 J1.5 AIN_4 = AIN0 / 5.0 fullscale is 6.0V
whismanoid 9:8d47cb713984 876 // max541_midscale_V = ((1 - average_K) * max541_midscale_V) + (average_K * measurement_V);
whismanoid 9:8d47cb713984 877 // }
whismanoid 9:8d47cb713984 878 // if (max541_midscale_V > 1.0f) {
whismanoid 9:8d47cb713984 879 // max541.VRef = 2.0 * max541_midscale_V;
whismanoid 9:8d47cb713984 880 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 881 // Test Fixture: MAX541 midscale = %1.3fV, so fullscale = %1.3fV",
whismanoid 9:8d47cb713984 882 // max541_midscale_V, max541.VRef);
whismanoid 9:8d47cb713984 883 // // Detect whether MAX541 is really connected to MAX32625MBED.AIN0/AIN4
whismanoid 9:8d47cb713984 884 // voltageV = 1.0f;
whismanoid 9:8d47cb713984 885 // SelfTest_has_max541 = SelfTest_MAX541_Voltage(cmdLine, max541, voltageV);
whismanoid 9:8d47cb713984 886 // }
whismanoid 9:8d47cb713984 887 // if (SelfTest_has_max541) {
whismanoid 9:8d47cb713984 888 // voltageV = 0.0f;
whismanoid 9:8d47cb713984 889 // SelfTest_has_max541 = SelfTest_MAX541_Voltage(cmdLine, max541, voltageV);
whismanoid 9:8d47cb713984 890 // }
whismanoid 9:8d47cb713984 891 // if (SelfTest_has_max541) {
whismanoid 9:8d47cb713984 892 // voltageV = 2.7f;
whismanoid 9:8d47cb713984 893 // SelfTest_has_max541 = SelfTest_MAX541_Voltage(cmdLine, max541, voltageV);
whismanoid 9:8d47cb713984 894 // }
whismanoid 9:8d47cb713984 895 // if (SelfTest_has_max541) {
whismanoid 9:8d47cb713984 896 // voltageV = 1.65f;
whismanoid 9:8d47cb713984 897 // SelfTest_has_max541 = SelfTest_MAX541_Voltage(cmdLine, max541, voltageV);
whismanoid 9:8d47cb713984 898 // }
whismanoid 9:8d47cb713984 899 // if (SelfTest_has_max541) {
whismanoid 9:8d47cb713984 900 // voltageV = 2.0f;
whismanoid 9:8d47cb713984 901 // SelfTest_has_max541 = SelfTest_MAX541_Voltage(cmdLine, max541, voltageV);
whismanoid 9:8d47cb713984 902 // }
whismanoid 9:8d47cb713984 903 // if (SelfTest_has_max541) {
whismanoid 9:8d47cb713984 904 // voltageV = 0.25f;
whismanoid 9:8d47cb713984 905 // SelfTest_has_max541 = SelfTest_MAX541_Voltage(cmdLine, max541, voltageV);
whismanoid 9:8d47cb713984 906 // }
whismanoid 9:8d47cb713984 907 // if (SelfTest_has_max541) {
whismanoid 9:8d47cb713984 908 // voltageV = 0.5f;
whismanoid 9:8d47cb713984 909 // SelfTest_has_max541 = SelfTest_MAX541_Voltage(cmdLine, max541, voltageV);
whismanoid 9:8d47cb713984 910 // }
whismanoid 9:8d47cb713984 911 // if (SelfTest_has_max541) {
whismanoid 9:8d47cb713984 912 // voltageV = 1.0f;
whismanoid 9:8d47cb713984 913 // SelfTest_has_max541 = SelfTest_MAX541_Voltage(cmdLine, max541, voltageV);
whismanoid 9:8d47cb713984 914 // }
whismanoid 9:8d47cb713984 915 // if (SelfTest_has_max541 == false) {
whismanoid 9:8d47cb713984 916 // // don't fail just because we're missing the test fixture...
whismanoid 9:8d47cb713984 917 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 918 // Test Fixture: MAX541 not present");
whismanoid 9:8d47cb713984 919 // //~ g_SelfTest_nFail--;
whismanoid 9:8d47cb713984 920 // }
whismanoid 9:8d47cb713984 921 // //
whismanoid 9:8d47cb713984 922 // // TODO1: MAX11131 SelfTest: if Test Fixture: drive MAX541, compare MAX32625MBED.AIN0/AIN4 and MAX11131 AIN0
whismanoid 9:8d47cb713984 923 // // indirectly verify the reference voltage by reading a known input voltage
whismanoid 9:8d47cb713984 924 // if (SelfTest_has_max541) {
whismanoid 9:8d47cb713984 925 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 926 // ");
whismanoid 9:8d47cb713984 927 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 928 // 2.1: TODO1: Check MAX11131 reference voltage using Scan_0001_Manual");
whismanoid 10:92aedaa14cce 929 // @future test tinyTester.print("_______")
whismanoid 9:8d47cb713984 930 // voltageV = 1.0f;
whismanoid 9:8d47cb713984 931 // SelfTest_MAX541_Voltage(cmdLine, max541, voltageV);
whismanoid 9:8d47cb713984 932 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 933 // MAX11131.Init()");
whismanoid 9:8d47cb713984 934 // Init();
whismanoid 9:8d47cb713984 935 // // 1 ScanManual ch=0 pm=0 id=1
whismanoid 9:8d47cb713984 936 // channelNumber_0_15 = 0;
whismanoid 9:8d47cb713984 937 // PowerManagement_0_2 = 0;
whismanoid 9:8d47cb713984 938 // chan_id_0_1 = 1;
whismanoid 9:8d47cb713984 939 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 940 // MAX11131.channelNumber_0_15=%d", channelNumber_0_15);
whismanoid 9:8d47cb713984 941 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 942 // MAX11131.PowerManagement_0_2=%d", PowerManagement_0_2);
whismanoid 9:8d47cb713984 943 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 944 // MAX11131.chan_id_0_1=%d", chan_id_0_1);
whismanoid 9:8d47cb713984 945 // NumWords = ScanManual();
whismanoid 9:8d47cb713984 946 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 947 // MAX11131.ScanManual -- NumWords = %d",
whismanoid 9:8d47cb713984 948 // NumWords);
whismanoid 9:8d47cb713984 949 // NumWords = ScanManual();
whismanoid 9:8d47cb713984 950 // ReadAINcode();
whismanoid 9:8d47cb713984 951 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 952 // MAX11131.ReadAINcode");
whismanoid 9:8d47cb713984 953 // AINcode_print_value_externalClock(cmdLine, NumWords);
whismanoid 9:8d47cb713984 954 // //
whismanoid 9:8d47cb713984 955 // // 2.1: TODO1: Check MAX11131 reference voltage -- why we read 0xffff 2.4999V here?
whismanoid 9:8d47cb713984 956 // //
whismanoid 9:8d47cb713984 957 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 958 // MAX11131.ScanManual -- NumWords = %d",
whismanoid 9:8d47cb713984 959 // NumWords);
whismanoid 9:8d47cb713984 960 // // Read raw ADC codes from device into AINcode[] and RAW_misoData16[]
whismanoid 9:8d47cb713984 961 // // @pre one of the MAX11311_Scan functions was called, setting NumWords
whismanoid 9:8d47cb713984 962 // ReadAINcode();
whismanoid 9:8d47cb713984 963 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 964 // MAX11131.ReadAINcode");
whismanoid 9:8d47cb713984 965 // AINcode_print_value_externalClock(cmdLine, NumWords);
whismanoid 9:8d47cb713984 966 // //
whismanoid 9:8d47cb713984 967 // // 2.1: TODO1: Check MAX11131 reference voltage -- why we read 0xffff 2.4999V here?
whismanoid 9:8d47cb713984 968 // //
whismanoid 9:8d47cb713984 969 // // compare with mbed/Arduino AIN0-AIN3
whismanoid 9:8d47cb713984 970 // // MAX32625MBED.AIN4 = MAX11131.AIN0
whismanoid 9:8d47cb713984 971 // channelId = 0;
whismanoid 9:8d47cb713984 972 // value_u12 = AINcode[channelId];
whismanoid 9:8d47cb713984 973 // voltageV = VoltageOfCode(value_u12, channelId);
whismanoid 9:8d47cb713984 974 // //
whismanoid 9:8d47cb713984 975 // // tinyTester.Wait_Output_Settling replaces wait_ms
whismanoid 9:8d47cb713984 976 // tinyTester.Wait_Output_Settling();
whismanoid 9:8d47cb713984 977 // // tinyTester.AnalogIn0_Read_Expect_voltageV replaces SelfTest_AnalogInput_Expect_ch_V
whismanoid 9:8d47cb713984 978 // tinyTester.err_threshold = 0.100;
whismanoid 9:8d47cb713984 979 // tinyTester.AnalogIn0_Read_Expect_voltageV(voltageV);
whismanoid 9:8d47cb713984 980 // //
whismanoid 9:8d47cb713984 981 // }
whismanoid 9:8d47cb713984 982 // //
whismanoid 9:8d47cb713984 983 // if (SelfTest_has_max541) {
whismanoid 9:8d47cb713984 984 // voltageV = 1.0f;
whismanoid 9:8d47cb713984 985 // SelfTest_MAX541_Voltage(cmdLine, max541, voltageV);
whismanoid 9:8d47cb713984 986 // }
whismanoid 9:8d47cb713984 987 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 988 // ");
whismanoid 9:8d47cb713984 989 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 990 // 3.1: Test Scan_0001_Manual");
whismanoid 10:92aedaa14cce 991 // @future test tinyTester.print("_______")
whismanoid 9:8d47cb713984 992 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 993 // MAX11131.Init()");
whismanoid 9:8d47cb713984 994 // Init();
whismanoid 9:8d47cb713984 995 // // 1 ScanManual ch=0 pm=0 id=1
whismanoid 9:8d47cb713984 996 // channelNumber_0_15 = 0;
whismanoid 9:8d47cb713984 997 // PowerManagement_0_2 = 0;
whismanoid 9:8d47cb713984 998 // chan_id_0_1 = 1;
whismanoid 9:8d47cb713984 999 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 1000 // MAX11131.channelNumber_0_15=%d", channelNumber_0_15);
whismanoid 10:92aedaa14cce 1001 // @future test tinyTester.print("_______")
whismanoid 9:8d47cb713984 1002 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 1003 // MAX11131.PowerManagement_0_2=%d", PowerManagement_0_2);
whismanoid 10:92aedaa14cce 1004 // @future test tinyTester.print("_______")
whismanoid 9:8d47cb713984 1005 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 1006 // MAX11131.chan_id_0_1=%d", chan_id_0_1);
whismanoid 10:92aedaa14cce 1007 // @future test tinyTester.print("_______")
whismanoid 9:8d47cb713984 1008 // NumWords = ScanManual();
whismanoid 9:8d47cb713984 1009 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 1010 // MAX11131.ScanManual -- NumWords = %d",
whismanoid 9:8d47cb713984 1011 // NumWords);
whismanoid 10:92aedaa14cce 1012 // @future test tinyTester.print("_______")
whismanoid 9:8d47cb713984 1013 // // Read raw ADC codes from device into AINcode[] and RAW_misoData16[]
whismanoid 9:8d47cb713984 1014 // // @pre one of the MAX11311_Scan functions was called, setting NumWords
whismanoid 9:8d47cb713984 1015 // ReadAINcode();
whismanoid 9:8d47cb713984 1016 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 1017 // MAX11131.ReadAINcode");
whismanoid 10:92aedaa14cce 1018 // @future test tinyTester.print("_______")
whismanoid 9:8d47cb713984 1019 // AINcode_print_value_externalClock(cmdLine, NumWords);
whismanoid 9:8d47cb713984 1020 // // compare with mbed/Arduino AIN0-AIN3
whismanoid 9:8d47cb713984 1021 // // MAX32625MBED.AIN4 = MAX11131.AIN0
whismanoid 9:8d47cb713984 1022 // channelId = 0;
whismanoid 9:8d47cb713984 1023 // value_u12 = AINcode[channelId];
whismanoid 9:8d47cb713984 1024 // voltageV = VoltageOfCode(value_u12, channelId);
whismanoid 9:8d47cb713984 1025 // //
whismanoid 9:8d47cb713984 1026 // // tinyTester.Wait_Output_Settling replaces wait_ms
whismanoid 9:8d47cb713984 1027 // tinyTester.Wait_Output_Settling();
whismanoid 9:8d47cb713984 1028 // // tinyTester.AnalogIn0_Read_Expect_voltageV replaces SelfTest_AnalogInput_Expect_ch_V
whismanoid 9:8d47cb713984 1029 // tinyTester.err_threshold = 0.100;
whismanoid 9:8d47cb713984 1030 // tinyTester.AnalogIn0_Read_Expect_voltageV(voltageV);
whismanoid 9:8d47cb713984 1031 // //
whismanoid 9:8d47cb713984 1032 // //
whismanoid 9:8d47cb713984 1033 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 1034 // ");
whismanoid 9:8d47cb713984 1035 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 1036 // 3.4: Test Scan_0100_StandardExternalClock");
whismanoid 10:92aedaa14cce 1037 // @future test tinyTester.print("_______")
whismanoid 9:8d47cb713984 1038 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 1039 // MAX11131.Init()");
whismanoid 9:8d47cb713984 1040 // Init();
whismanoid 9:8d47cb713984 1041 // // MAX11131 > 4
whismanoid 9:8d47cb713984 1042 // // ScanStandardExternalClock ch=9 pm=0 id=1
whismanoid 9:8d47cb713984 1043 // // ScanRead_nWords_chanID nWords=10
whismanoid 9:8d47cb713984 1044 // // ch=0 xu=2964 = 0x0b94 = 1.8091V
whismanoid 9:8d47cb713984 1045 // // ch=1 xu=2227 = 0x08b3 = 1.3593V
whismanoid 9:8d47cb713984 1046 // // ch=2 xu=1570 = 0x0622 = 0.9583V
whismanoid 9:8d47cb713984 1047 // // ch=3 xu=865 = 0x0361 = 0.5280V
whismanoid 9:8d47cb713984 1048 // // ch=4 xu=630 = 0x0276 = 0.3845V
whismanoid 9:8d47cb713984 1049 // // ch=5 xu=594 = 0x0252 = 0.3625V
whismanoid 9:8d47cb713984 1050 // // ch=6 xu=461 = 0x01cd = 0.2814V
whismanoid 9:8d47cb713984 1051 // // ch=7 xu=364 = 0x016c = 0.2222V
whismanoid 9:8d47cb713984 1052 // // ch=8 xu=480 = 0x01e0 = 0.2930V
whismanoid 9:8d47cb713984 1053 // // ch=9 xu=616 = 0x0268 = 0.3760V
whismanoid 9:8d47cb713984 1054 // channelNumber_0_15 = 9;
whismanoid 9:8d47cb713984 1055 // PowerManagement_0_2 = 0;
whismanoid 9:8d47cb713984 1056 // chan_id_0_1 = 1;
whismanoid 9:8d47cb713984 1057 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 1058 // MAX11131.channelNumber_0_15=%d", channelNumber_0_15);
whismanoid 10:92aedaa14cce 1059 // @future test tinyTester.print("_______")
whismanoid 9:8d47cb713984 1060 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 1061 // MAX11131.PowerManagement_0_2=%d", PowerManagement_0_2);
whismanoid 10:92aedaa14cce 1062 // @future test tinyTester.print("_______")
whismanoid 9:8d47cb713984 1063 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 1064 // MAX11131.chan_id_0_1=%d", chan_id_0_1);
whismanoid 10:92aedaa14cce 1065 // @future test tinyTester.print("_______")
whismanoid 9:8d47cb713984 1066 // NumWords = ScanStandardExternalClock();
whismanoid 9:8d47cb713984 1067 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 1068 // MAX11131.ScanStandardExternalClock -- NumWords = %d",
whismanoid 9:8d47cb713984 1069 // NumWords);
whismanoid 10:92aedaa14cce 1070 // @future test tinyTester.print("_______")
whismanoid 9:8d47cb713984 1071 // // Read raw ADC codes from device into AINcode[] and RAW_misoData16[]
whismanoid 9:8d47cb713984 1072 // // @pre one of the MAX11311_Scan functions was called, setting NumWords
whismanoid 9:8d47cb713984 1073 // ReadAINcode();
whismanoid 9:8d47cb713984 1074 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 1075 // MAX11131.ReadAINcode");
whismanoid 10:92aedaa14cce 1076 // @future test tinyTester.print("_______")
whismanoid 9:8d47cb713984 1077 // // @post RAW_misoData16[index] contains the raw SPI Master-In,Slave-Out data
whismanoid 9:8d47cb713984 1078 // // @post AINcode[NUM_CHANNELS] contains the latest readings in LSBs
whismanoid 9:8d47cb713984 1079 // // expect NumWords == channelNumber_0_15 + 1;
whismanoid 9:8d47cb713984 1080 // // expect RAW_misoData16[index] msnybble 0,1,2,3,...
whismanoid 9:8d47cb713984 1081 // AINcode_print_value_externalClock(cmdLine, NumWords);
whismanoid 9:8d47cb713984 1082 // // compare with mbed/Arduino AIN0-AIN3
whismanoid 9:8d47cb713984 1083 // // MAX32625MBED.AIN4 = MAX11131.AIN0
whismanoid 9:8d47cb713984 1084 // channelId = 0;
whismanoid 9:8d47cb713984 1085 // value_u12 = AINcode[channelId];
whismanoid 9:8d47cb713984 1086 // voltageV = VoltageOfCode(value_u12, channelId);
whismanoid 9:8d47cb713984 1087 // // tinyTester.Wait_Output_Settling replaces wait_ms
whismanoid 9:8d47cb713984 1088 // tinyTester.Wait_Output_Settling();
whismanoid 9:8d47cb713984 1089 // // tinyTester.AnalogIn0_Read_Expect_voltageV replaces SelfTest_AnalogInput_Expect_ch_V
whismanoid 9:8d47cb713984 1090 // tinyTester.err_threshold = 0.100;
whismanoid 9:8d47cb713984 1091 // tinyTester.AnalogIn0_Read_Expect_voltageV(voltageV);
whismanoid 9:8d47cb713984 1092 // // compare MAX32625MBED.AIN5 = MAX11131.AIN1
whismanoid 9:8d47cb713984 1093 // //channelId = 1;
whismanoid 9:8d47cb713984 1094 // //value_u12 = AINcode[channelId];
whismanoid 9:8d47cb713984 1095 // //voltageV = VoltageOfCode(value_u12, channelId);
whismanoid 9:8d47cb713984 1096 // //SelfTest_AnalogInput_Expect_ch_V(cmdLine, 5, voltageV, 0.100);
whismanoid 9:8d47cb713984 1097 //
whismanoid 9:8d47cb713984 1098 //
whismanoid 9:8d47cb713984 1099 //
whismanoid 1:77f1ee332e4a 1100 void MAX11131::Init(void)
whismanoid 1:77f1ee332e4a 1101 {
whismanoid 1:77f1ee332e4a 1102
whismanoid 1:77f1ee332e4a 1103 //----------------------------------------
whismanoid 1:77f1ee332e4a 1104 // Nominal Full-Scale Voltage Reference
whismanoid 1:77f1ee332e4a 1105 VRef = 2.500;
whismanoid 1:77f1ee332e4a 1106
whismanoid 1:77f1ee332e4a 1107 //----------------------------------------
whismanoid 1:77f1ee332e4a 1108 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 1109 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 1110 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 1111 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 1112 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 1113 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 1114 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 1115 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 1116
whismanoid 1:77f1ee332e4a 1117 //----------------------------------------
whismanoid 1:77f1ee332e4a 1118 // define write-only register ADC_CONFIGURATION
whismanoid 1:77f1ee332e4a 1119 ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid 1:77f1ee332e4a 1120 const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid 1:77f1ee332e4a 1121 const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid 1:77f1ee332e4a 1122 const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid 1:77f1ee332e4a 1123 const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid 1:77f1ee332e4a 1124 const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid 1:77f1ee332e4a 1125 const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid 1:77f1ee332e4a 1126
whismanoid 1:77f1ee332e4a 1127 //----------------------------------------
whismanoid 1:77f1ee332e4a 1128 // define write-only registers UNIPOLAR,BIPOLAR,RANGE
whismanoid 1:77f1ee332e4a 1129 UNIPOLAR = 0x8800; //!< mosiData16 0x8800..0x8FFF format: 1 0 0 0 1 UCH0/1 UCH2/3 UCH4/5 UCH6/7 UCH8/9 UCH10/11 UCH12/13 UCH14/15 PDIFF_COM x x
whismanoid 1:77f1ee332e4a 1130 BIPOLAR = 0x9000; //!< mosiData16 0x9000..0x97FF format: 1 0 0 1 0 BCH0/1 BCH2/3 BCH4/5 BCH6/7 BCH8/9 BCH10/11 BCH12/13 BCH14/15 x x x
whismanoid 1:77f1ee332e4a 1131 RANGE = 0x9800; //!< mosiData16 0x9800..0x9FFF format: 1 0 0 1 1 RANGE0/1 RANGE2/3 RANGE4/5 RANGE6/7 RANGE8/9 RANGE10/11 RANGE12/13 RANGE14/15 x x x
whismanoid 1:77f1ee332e4a 1132 const int AIN_0_1_LSB = 10; // UNIPOLAR.UCH0/1 BIPOLAR.BCH0/1 RANGE.RANGE0/1
whismanoid 1:77f1ee332e4a 1133 const int AIN_2_3_LSB = 9; // UNIPOLAR.UCH2/3 BIPOLAR.BCH2/3 RANGE.RANGE2/3
whismanoid 1:77f1ee332e4a 1134 const int AIN_4_5_LSB = 8; // UNIPOLAR.UCH4/5 BIPOLAR.BCH4/5 RANGE.RANGE4/5
whismanoid 1:77f1ee332e4a 1135 const int AIN_6_7_LSB = 7; // UNIPOLAR.UCH6/7 BIPOLAR.BCH6/7 RANGE.RANGE6/7
whismanoid 1:77f1ee332e4a 1136 const int AIN_8_9_LSB = 6; // UNIPOLAR.UCH8/9 BIPOLAR.BCH8/9 RANGE.RANGE8/9
whismanoid 1:77f1ee332e4a 1137 const int AIN_10_11_LSB = 5; // UNIPOLAR.UCH10/11 BIPOLAR.BCH10/11 RANGE.RANGE10/11
whismanoid 1:77f1ee332e4a 1138 const int AIN_12_13_LSB = 4; // UNIPOLAR.UCH12/13 BIPOLAR.BCH12/13 RANGE.RANGE12/13
whismanoid 1:77f1ee332e4a 1139 const int AIN_14_15_LSB = 3; // UNIPOLAR.UCH14/15 BIPOLAR.BCH14/15 RANGE.RANGE14/15
whismanoid 1:77f1ee332e4a 1140 const int PDIFF_COMM_LSB = 2; const int PDIFF_COMM_BITS = 0x01; // UNIPOLAR.PDIFF_COM
whismanoid 1:77f1ee332e4a 1141 // Summary of Table 8:
whismanoid 1:77f1ee332e4a 1142 // UCH0/1=0, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1143 // UCH0/1=1, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 4:8a0ae95546fa 1144 // UCH0/1=0, BCH0/1=1, RANGE0/1=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1145 // UCH0/1=1, BCH0/1=1, RANGE0/1=0: reserved do not use
whismanoid 1:77f1ee332e4a 1146 // UCH0/1=0, BCH0/1=0, RANGE0/1=1: reserved do not use
whismanoid 1:77f1ee332e4a 1147 // UCH0/1=1, BCH0/1=0, RANGE0/1=1: reserved do not use
whismanoid 4:8a0ae95546fa 1148 // UCH0/1=0, BCH0/1=1, RANGE0/1=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1149 // UCH0/1=1, BCH0/1=1, RANGE0/1=1: reserved do not use
whismanoid 1:77f1ee332e4a 1150 // Both channels of a differential pair must be within Input Voltage Range (dynamic signal range) 0..VREF.
whismanoid 1:77f1ee332e4a 1151
whismanoid 1:77f1ee332e4a 1152 //----------------------------------------
whismanoid 1:77f1ee332e4a 1153 // define write-only registers CSCAN0,CSCAN1
whismanoid 1:77f1ee332e4a 1154 CSCAN0 = 0xA000; //!< mosiData16 0xA000..0xA7FF format: 1 0 1 0 0 CHSCAN15 CHSCAN14 CHSCAN13 CHSCAN12 CHSCAN11 CHSCAN10 CHSCAN9 CHSCAN8 x x x
whismanoid 1:77f1ee332e4a 1155 const int CHSCAN15_LSB = 10; // CSCAN0.CHSCAN15
whismanoid 1:77f1ee332e4a 1156 const int CHSCAN14_LSB = 9; // CSCAN0.CHSCAN14
whismanoid 1:77f1ee332e4a 1157 const int CHSCAN13_LSB = 8; // CSCAN0.CHSCAN13
whismanoid 1:77f1ee332e4a 1158 const int CHSCAN12_LSB = 7; // CSCAN0.CHSCAN12
whismanoid 1:77f1ee332e4a 1159 const int CHSCAN11_LSB = 6; // CSCAN0.CHSCAN11
whismanoid 1:77f1ee332e4a 1160 const int CHSCAN10_LSB = 5; // CSCAN0.CHSCAN10
whismanoid 1:77f1ee332e4a 1161 const int CHSCAN9_LSB = 4; // CSCAN0.CHSCAN9
whismanoid 1:77f1ee332e4a 1162 const int CHSCAN8_LSB = 3; // CSCAN0.CHSCAN8
whismanoid 1:77f1ee332e4a 1163 CSCAN1 = 0xA800; //!< mosiData16 0xA800..0xAFFF format: 1 0 1 0 1 CHSCAN7 CHSCAN6 CHSCAN5 CHSCAN4 CHSCAN3 CHSCAN2 CHSCAN1 CHSCAN0 x x x
whismanoid 1:77f1ee332e4a 1164 const int CHSCAN7_LSB = 10; // CSCAN1.CHSCAN7
whismanoid 1:77f1ee332e4a 1165 const int CHSCAN6_LSB = 9; // CSCAN1.CHSCAN6
whismanoid 1:77f1ee332e4a 1166 const int CHSCAN5_LSB = 8; // CSCAN1.CHSCAN5
whismanoid 1:77f1ee332e4a 1167 const int CHSCAN4_LSB = 7; // CSCAN1.CHSCAN4
whismanoid 1:77f1ee332e4a 1168 const int CHSCAN3_LSB = 6; // CSCAN1.CHSCAN3
whismanoid 1:77f1ee332e4a 1169 const int CHSCAN2_LSB = 5; // CSCAN1.CHSCAN2
whismanoid 1:77f1ee332e4a 1170 const int CHSCAN1_LSB = 4; // CSCAN1.CHSCAN1
whismanoid 1:77f1ee332e4a 1171 const int CHSCAN0_LSB = 3; // CSCAN1.CHSCAN0
whismanoid 1:77f1ee332e4a 1172
whismanoid 1:77f1ee332e4a 1173 //----------------------------------------
whismanoid 1:77f1ee332e4a 1174 // Initialize shadow of write-only register SAMPLESET.
whismanoid 1:77f1ee332e4a 1175 // Do not write to SAMPLESET at this time.
whismanoid 1:77f1ee332e4a 1176 // A write to SAMPLESET must be followed by specified number of pattern entry words.
whismanoid 1:77f1ee332e4a 1177 // See ScanSampleSetExternalClock function for details.
whismanoid 1:77f1ee332e4a 1178 SAMPLESET = 0xB000; //!< mosiData16 0xB000..0xB7FF format: 1 0 1 1 0 SEQ_LENGTH[7:0] x x x
whismanoid 1:77f1ee332e4a 1179 const int SAMPLESET_LSB = 3; const int SAMPLESET_BITS = 0xFF; // SAMPLESET.SEQ_LENGTH[7:0]
whismanoid 1:77f1ee332e4a 1180
whismanoid 1:77f1ee332e4a 1181 //----------------------------------------
whismanoid 1:77f1ee332e4a 1182 // Reset all registers: ADC_MODE_CONTROL.RESET[1:0] = 2
whismanoid 1:77f1ee332e4a 1183 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 1184 ADC_MODE_CONTROL |= ((2 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 1185
whismanoid 1:77f1ee332e4a 1186 //----------------------------------------
whismanoid 1:77f1ee332e4a 1187 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 1188 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 1189 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1190 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1191 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 1192 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1193
whismanoid 1:77f1ee332e4a 1194 #if REFSEL_0
whismanoid 1:77f1ee332e4a 1195
whismanoid 1:77f1ee332e4a 1196 //----------------------------------------
whismanoid 1:77f1ee332e4a 1197 // Global setting for all channels: ADC_CONFIGURATION.REFSEL=0: external single-ended reference
whismanoid 1:77f1ee332e4a 1198 // SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1199 // SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL: EXTERNAL SINGLE-ENDED
whismanoid 1:77f1ee332e4a 1200 // SELECT ADC CONFIGURATION register set REFSEL BIT TO 0
whismanoid 1:77f1ee332e4a 1201 ADC_CONFIGURATION &= ~ (( REFSEL_BITS) << REFSEL_LSB); // ADC_CONFIGURATION.REFSEL=0: external single-ended reference. (For the 16-channel chips: channel AIN15 is available.)
whismanoid 1:77f1ee332e4a 1202 #endif // REFSEL_0
whismanoid 1:77f1ee332e4a 1203
whismanoid 1:77f1ee332e4a 1204 #if REFSEL_1
whismanoid 1:77f1ee332e4a 1205
whismanoid 1:77f1ee332e4a 1206 //----------------------------------------
whismanoid 1:77f1ee332e4a 1207 // Global setting for all channels: ADC_CONFIGURATION.REFSEL=1: external differential reference (For the 16-channel chips: channel AIN15 is unavailable, the pin is assigned to REF-.)
whismanoid 1:77f1ee332e4a 1208 // SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1209 // SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL: EXTERNAL DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1210 // SELECT ADC CONFIGURATION register set REFSEL BIT TO 1
whismanoid 1:77f1ee332e4a 1211 ADC_CONFIGURATION |= ((1 & REFSEL_BITS) << REFSEL_LSB); // ADC_CONFIGURATION.REFSEL=1: external differential reference. (For the 16-channel chips: channel AIN15 is unavailable, the pin is assigned to REF-.)
whismanoid 1:77f1ee332e4a 1212 #endif // REFSEL_1
whismanoid 1:77f1ee332e4a 1213
whismanoid 1:77f1ee332e4a 1214 #if PDIFF_COMM_0
whismanoid 1:77f1ee332e4a 1215
whismanoid 1:77f1ee332e4a 1216 //----------------------------------------
whismanoid 1:77f1ee332e4a 1217 // Global setting for all channels: PDIFF_COMM
whismanoid 1:77f1ee332e4a 1218 UNIPOLAR &= ~ (( PDIFF_COMM_BITS) << PDIFF_COMM_LSB); // UNIPOLAR.PDIFF_COMM=0: all single-ended channels use GND as common
whismanoid 1:77f1ee332e4a 1219 #endif // PDIFF_COMM_0
whismanoid 1:77f1ee332e4a 1220
whismanoid 1:77f1ee332e4a 1221 #if PDIFF_COMM_1
whismanoid 1:77f1ee332e4a 1222
whismanoid 1:77f1ee332e4a 1223 //----------------------------------------
whismanoid 1:77f1ee332e4a 1224 // Global setting for all channels: PDIFF_COMM
whismanoid 1:77f1ee332e4a 1225 // SELECT UNIPOLAR AND register set BIT PDIFF_COM TO 1 FOR PSEUDODIFFERENTIAL SELECTION
whismanoid 1:77f1ee332e4a 1226 UNIPOLAR |= ((1 & PDIFF_COMM_BITS) << PDIFF_COMM_LSB); // UNIPOLAR.PDIFF_COMM=1: all single-ended channels are pseudo-differential with REF- as common
whismanoid 1:77f1ee332e4a 1227 #endif // PDIFF_COMM_1
whismanoid 1:77f1ee332e4a 1228
whismanoid 1:77f1ee332e4a 1229 #if AIN_0_1_SingleEnded
whismanoid 1:77f1ee332e4a 1230
whismanoid 1:77f1ee332e4a 1231 //----------------------------------------
whismanoid 1:77f1ee332e4a 1232 // ADC Channels AIN0, AIN1 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 1233 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1234 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1235 // AIN0 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1236 // AIN1 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1237 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 1238 // AIN0 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1239 // AIN1 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1240 //
whismanoid 1:77f1ee332e4a 1241 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 1242 UNIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 1243 BIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 1244 RANGE &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 1245 // UCH0/1=0, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1246 #endif // AIN_0_1_SingleEnded
whismanoid 1:77f1ee332e4a 1247
whismanoid 1:77f1ee332e4a 1248 #if AIN_0_1_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1249
whismanoid 1:77f1ee332e4a 1250 //----------------------------------------
whismanoid 1:77f1ee332e4a 1251 // ADC Channels AIN0, AIN1 = Differential Unipolar (AIN0 > AIN1)
whismanoid 1:77f1ee332e4a 1252 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1253 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1254 // AIN0, AIN1 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1255 // AIN0 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1256 // AIN1 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1257 //
whismanoid 1:77f1ee332e4a 1258 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 1259 UNIPOLAR |= (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 1260 BIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 1261 RANGE &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 1262 // UCH0/1=1, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1263 #endif // AIN_0_1_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1264
whismanoid 1:77f1ee332e4a 1265 #if AIN_0_1_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1266
whismanoid 1:77f1ee332e4a 1267 //----------------------------------------
whismanoid 1:77f1ee332e4a 1268 // ADC Channels AIN0, AIN1 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1269 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1270 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 1271 // AIN0, AIN1 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 1272 // AIN0 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1273 // AIN1 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1274 //
whismanoid 1:77f1ee332e4a 1275 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1276 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 1277 UNIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 1278 BIPOLAR |= (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 1279 RANGE &= ~ (1 << AIN_0_1_LSB);
whismanoid 4:8a0ae95546fa 1280 // UCH0/1=0, BCH0/1=1, RANGE0/1=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1281 #endif // AIN_0_1_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1282
whismanoid 1:77f1ee332e4a 1283 #if AIN_0_1_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1284
whismanoid 1:77f1ee332e4a 1285 //----------------------------------------
whismanoid 1:77f1ee332e4a 1286 // ADC Channels AIN0, AIN1 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1287 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1288 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 1289 // AIN0, AIN1 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 1290 // AIN0 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1291 // AIN1 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1292 //
whismanoid 1:77f1ee332e4a 1293 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1294 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 1295 UNIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 1296 BIPOLAR |= (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 1297 RANGE |= (1 << AIN_0_1_LSB);
whismanoid 4:8a0ae95546fa 1298 // UCH0/1=0, BCH0/1=1, RANGE0/1=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1299 #endif // AIN_0_1_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1300
whismanoid 1:77f1ee332e4a 1301 #if AIN_2_3_SingleEnded
whismanoid 1:77f1ee332e4a 1302
whismanoid 1:77f1ee332e4a 1303 //----------------------------------------
whismanoid 1:77f1ee332e4a 1304 // ADC Channels AIN2, AIN3 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 1305 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1306 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1307 // AIN2 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1308 // AIN3 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1309 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 1310 // AIN2 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1311 // AIN3 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1312 //
whismanoid 1:77f1ee332e4a 1313 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 1314 UNIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 1315 BIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 1316 RANGE &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 1317 // UCH2/3=0, BCH2/3=0, RANGE2/3=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1318 #endif // AIN_2_3_SingleEnded
whismanoid 1:77f1ee332e4a 1319
whismanoid 1:77f1ee332e4a 1320 #if AIN_2_3_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1321
whismanoid 1:77f1ee332e4a 1322 //----------------------------------------
whismanoid 1:77f1ee332e4a 1323 // ADC Channels AIN2, AIN3 = Differential Unipolar (AIN2 > AIN3)
whismanoid 1:77f1ee332e4a 1324 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1325 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1326 // AIN2, AIN3 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1327 // AIN2 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1328 // AIN3 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1329 //
whismanoid 1:77f1ee332e4a 1330 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 1331 UNIPOLAR |= (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 1332 BIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 1333 RANGE &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 1334 // UCH2/3=1, BCH2/3=0, RANGE2/3=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1335 #endif // AIN_2_3_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1336
whismanoid 1:77f1ee332e4a 1337 #if AIN_2_3_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1338
whismanoid 1:77f1ee332e4a 1339 //----------------------------------------
whismanoid 1:77f1ee332e4a 1340 // ADC Channels AIN2, AIN3 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1341 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1342 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 1343 // AIN2, AIN3 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 1344 // AIN2 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1345 // AIN3 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1346 //
whismanoid 1:77f1ee332e4a 1347 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1348 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 1349 UNIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 1350 BIPOLAR |= (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 1351 RANGE &= ~ (1 << AIN_2_3_LSB);
whismanoid 4:8a0ae95546fa 1352 // UCH2/3=0, BCH2/3=1, RANGE2/3=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1353 #endif // AIN_2_3_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1354
whismanoid 1:77f1ee332e4a 1355 #if AIN_2_3_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1356
whismanoid 1:77f1ee332e4a 1357 //----------------------------------------
whismanoid 1:77f1ee332e4a 1358 // ADC Channels AIN2, AIN3 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1359 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1360 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 1361 // AIN2, AIN3 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 1362 // AIN2 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1363 // AIN3 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1364 //
whismanoid 1:77f1ee332e4a 1365 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1366 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 1367 UNIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 1368 BIPOLAR |= (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 1369 RANGE |= (1 << AIN_2_3_LSB);
whismanoid 4:8a0ae95546fa 1370 // UCH2/3=0, BCH2/3=1, RANGE2/3=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1371 #endif // AIN_2_3_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1372
whismanoid 1:77f1ee332e4a 1373 #if AIN_4_5_SingleEnded
whismanoid 1:77f1ee332e4a 1374
whismanoid 1:77f1ee332e4a 1375 //----------------------------------------
whismanoid 1:77f1ee332e4a 1376 // ADC Channels AIN4, AIN5 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 1377 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1378 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1379 // AIN4 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1380 // AIN5 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1381 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 1382 // AIN4 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1383 // AIN5 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1384 //
whismanoid 1:77f1ee332e4a 1385 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 1386 UNIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 1387 BIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 1388 RANGE &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 1389 // UCH4/5=0, BCH4/5=0, RANGE4/5=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1390 #endif // AIN_4_5_SingleEnded
whismanoid 1:77f1ee332e4a 1391
whismanoid 1:77f1ee332e4a 1392 #if AIN_4_5_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1393
whismanoid 1:77f1ee332e4a 1394 //----------------------------------------
whismanoid 1:77f1ee332e4a 1395 // ADC Channels AIN4, AIN5 = Differential Unipolar (AIN4 > AIN5)
whismanoid 1:77f1ee332e4a 1396 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1397 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1398 // AIN4, AIN5 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1399 // AIN4 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1400 // AIN5 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1401 //
whismanoid 1:77f1ee332e4a 1402 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 1403 UNIPOLAR |= (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 1404 BIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 1405 RANGE &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 1406 // UCH4/5=1, BCH4/5=0, RANGE4/5=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1407 #endif // AIN_4_5_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1408
whismanoid 1:77f1ee332e4a 1409 #if AIN_4_5_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1410
whismanoid 1:77f1ee332e4a 1411 //----------------------------------------
whismanoid 1:77f1ee332e4a 1412 // ADC Channels AIN4, AIN5 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1413 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1414 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 1415 // AIN4, AIN5 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 1416 // AIN4 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1417 // AIN5 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1418 //
whismanoid 1:77f1ee332e4a 1419 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1420 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 1421 UNIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 1422 BIPOLAR |= (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 1423 RANGE &= ~ (1 << AIN_4_5_LSB);
whismanoid 4:8a0ae95546fa 1424 // UCH4/5=0, BCH4/5=1, RANGE4/5=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1425 #endif // AIN_4_5_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1426
whismanoid 1:77f1ee332e4a 1427 #if AIN_4_5_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1428
whismanoid 1:77f1ee332e4a 1429 //----------------------------------------
whismanoid 1:77f1ee332e4a 1430 // ADC Channels AIN4, AIN5 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1431 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1432 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 1433 // AIN4, AIN5 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 1434 // AIN4 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1435 // AIN5 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1436 //
whismanoid 1:77f1ee332e4a 1437 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1438 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 1439 UNIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 1440 BIPOLAR |= (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 1441 RANGE |= (1 << AIN_4_5_LSB);
whismanoid 4:8a0ae95546fa 1442 // UCH4/5=0, BCH4/5=1, RANGE4/5=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1443 #endif // AIN_4_5_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1444
whismanoid 1:77f1ee332e4a 1445 #if AIN_6_7_SingleEnded
whismanoid 1:77f1ee332e4a 1446
whismanoid 1:77f1ee332e4a 1447 //----------------------------------------
whismanoid 1:77f1ee332e4a 1448 // ADC Channels AIN6, AIN7 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 1449 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1450 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1451 // AIN6 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1452 // AIN7 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1453 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 1454 // AIN6 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1455 // AIN7 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1456 //
whismanoid 1:77f1ee332e4a 1457 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 1458 UNIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 1459 BIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 1460 RANGE &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 1461 // UCH6/7=0, BCH6/7=0, RANGE6/7=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1462 #endif // AIN_6_7_SingleEnded
whismanoid 1:77f1ee332e4a 1463
whismanoid 1:77f1ee332e4a 1464 #if AIN_6_7_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1465
whismanoid 1:77f1ee332e4a 1466 //----------------------------------------
whismanoid 1:77f1ee332e4a 1467 // ADC Channels AIN6, AIN7 = Differential Unipolar (AIN6 > AIN7)
whismanoid 1:77f1ee332e4a 1468 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1469 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1470 // AIN6, AIN7 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1471 // AIN6 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1472 // AIN7 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1473 //
whismanoid 1:77f1ee332e4a 1474 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 1475 UNIPOLAR |= (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 1476 BIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 1477 RANGE &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 1478 // UCH6/7=1, BCH6/7=0, RANGE6/7=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1479 #endif // AIN_6_7_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1480
whismanoid 1:77f1ee332e4a 1481 #if AIN_6_7_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1482
whismanoid 1:77f1ee332e4a 1483 //----------------------------------------
whismanoid 1:77f1ee332e4a 1484 // ADC Channels AIN6, AIN7 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1485 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1486 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 1487 // AIN6, AIN7 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 1488 // AIN6 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1489 // AIN7 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1490 //
whismanoid 1:77f1ee332e4a 1491 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1492 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 1493 UNIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 1494 BIPOLAR |= (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 1495 RANGE &= ~ (1 << AIN_6_7_LSB);
whismanoid 4:8a0ae95546fa 1496 // UCH6/7=0, BCH6/7=1, RANGE6/7=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1497 #endif // AIN_6_7_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1498
whismanoid 1:77f1ee332e4a 1499 #if AIN_6_7_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1500
whismanoid 1:77f1ee332e4a 1501 //----------------------------------------
whismanoid 1:77f1ee332e4a 1502 // ADC Channels AIN6, AIN7 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1503 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1504 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 1505 // AIN6, AIN7 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 1506 // AIN6 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1507 // AIN7 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1508 //
whismanoid 1:77f1ee332e4a 1509 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1510 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 1511 UNIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 1512 BIPOLAR |= (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 1513 RANGE |= (1 << AIN_6_7_LSB);
whismanoid 4:8a0ae95546fa 1514 // UCH6/7=0, BCH6/7=1, RANGE6/7=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1515 #endif // AIN_6_7_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1516
whismanoid 1:77f1ee332e4a 1517 #if AIN_8_9_SingleEnded
whismanoid 1:77f1ee332e4a 1518
whismanoid 1:77f1ee332e4a 1519 //----------------------------------------
whismanoid 1:77f1ee332e4a 1520 // ADC Channels AIN8, AIN9 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 1521 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1522 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1523 // AIN8 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1524 // AIN9 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1525 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 1526 // AIN8 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1527 // AIN9 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1528 //
whismanoid 1:77f1ee332e4a 1529 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 1530 UNIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 1531 BIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 1532 RANGE &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 1533 // UCH8/9=0, BCH8/9=0, RANGE8/9=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1534 #endif // AIN_8_9_SingleEnded
whismanoid 1:77f1ee332e4a 1535
whismanoid 1:77f1ee332e4a 1536 #if AIN_8_9_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1537
whismanoid 1:77f1ee332e4a 1538 //----------------------------------------
whismanoid 1:77f1ee332e4a 1539 // ADC Channels AIN8, AIN9 = Differential Unipolar (AIN8 > AIN9)
whismanoid 1:77f1ee332e4a 1540 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1541 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1542 // AIN8, AIN9 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1543 // AIN8 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1544 // AIN9 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1545 //
whismanoid 1:77f1ee332e4a 1546 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 1547 UNIPOLAR |= (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 1548 BIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 1549 RANGE &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 1550 // UCH8/9=1, BCH8/9=0, RANGE8/9=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1551 #endif // AIN_8_9_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1552
whismanoid 1:77f1ee332e4a 1553 #if AIN_8_9_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1554
whismanoid 1:77f1ee332e4a 1555 //----------------------------------------
whismanoid 1:77f1ee332e4a 1556 // ADC Channels AIN8, AIN9 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1557 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1558 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 1559 // AIN8, AIN9 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 1560 // AIN8 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1561 // AIN9 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1562 //
whismanoid 1:77f1ee332e4a 1563 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1564 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 1565 UNIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 1566 BIPOLAR |= (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 1567 RANGE &= ~ (1 << AIN_8_9_LSB);
whismanoid 4:8a0ae95546fa 1568 // UCH8/9=0, BCH8/9=1, RANGE8/9=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1569 #endif // AIN_8_9_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1570
whismanoid 1:77f1ee332e4a 1571 #if AIN_8_9_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1572
whismanoid 1:77f1ee332e4a 1573 //----------------------------------------
whismanoid 1:77f1ee332e4a 1574 // ADC Channels AIN8, AIN9 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1575 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1576 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 1577 // AIN8, AIN9 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 1578 // AIN8 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1579 // AIN9 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1580 //
whismanoid 1:77f1ee332e4a 1581 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1582 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 1583 UNIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 1584 BIPOLAR |= (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 1585 RANGE |= (1 << AIN_8_9_LSB);
whismanoid 4:8a0ae95546fa 1586 // UCH8/9=0, BCH8/9=1, RANGE8/9=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1587 #endif // AIN_8_9_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1588
whismanoid 1:77f1ee332e4a 1589 #if AIN_10_11_SingleEnded
whismanoid 1:77f1ee332e4a 1590
whismanoid 1:77f1ee332e4a 1591 //----------------------------------------
whismanoid 1:77f1ee332e4a 1592 // ADC Channels AIN10, AIN11 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 1593 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1594 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1595 // AIN10 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1596 // AIN11 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1597 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 1598 // AIN10 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1599 // AIN11 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1600 //
whismanoid 1:77f1ee332e4a 1601 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 1602 UNIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1603 BIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1604 RANGE &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1605 // UCH10/11=0, BCH10/11=0, RANGE10/11=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1606 #endif // AIN_10_11_SingleEnded
whismanoid 1:77f1ee332e4a 1607
whismanoid 1:77f1ee332e4a 1608 #if AIN_10_11_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1609
whismanoid 1:77f1ee332e4a 1610 //----------------------------------------
whismanoid 1:77f1ee332e4a 1611 // ADC Channels AIN10, AIN11 = Differential Unipolar (AIN10 > AIN11)
whismanoid 1:77f1ee332e4a 1612 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1613 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1614 // AIN10, AIN11 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1615 // AIN10 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1616 // AIN11 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1617 //
whismanoid 1:77f1ee332e4a 1618 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 1619 UNIPOLAR |= (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1620 BIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1621 RANGE &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1622 // UCH10/11=1, BCH10/11=0, RANGE10/11=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1623 #endif // AIN_10_11_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1624
whismanoid 1:77f1ee332e4a 1625 #if AIN_10_11_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1626
whismanoid 1:77f1ee332e4a 1627 //----------------------------------------
whismanoid 1:77f1ee332e4a 1628 // ADC Channels AIN10, AIN11 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1629 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1630 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 1631 // AIN10, AIN11 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 1632 // AIN10 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1633 // AIN11 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1634 //
whismanoid 1:77f1ee332e4a 1635 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1636 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 1637 UNIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1638 BIPOLAR |= (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1639 RANGE &= ~ (1 << AIN_10_11_LSB);
whismanoid 4:8a0ae95546fa 1640 // UCH10/11=0, BCH10/11=1, RANGE10/11=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1641 #endif // AIN_10_11_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1642
whismanoid 1:77f1ee332e4a 1643 #if AIN_10_11_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1644
whismanoid 1:77f1ee332e4a 1645 //----------------------------------------
whismanoid 1:77f1ee332e4a 1646 // ADC Channels AIN10, AIN11 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1647 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1648 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 1649 // AIN10, AIN11 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 1650 // AIN10 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1651 // AIN11 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1652 //
whismanoid 1:77f1ee332e4a 1653 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1654 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 1655 UNIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1656 BIPOLAR |= (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1657 RANGE |= (1 << AIN_10_11_LSB);
whismanoid 4:8a0ae95546fa 1658 // UCH10/11=0, BCH10/11=1, RANGE10/11=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1659 #endif // AIN_10_11_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1660
whismanoid 1:77f1ee332e4a 1661 #if AIN_12_13_SingleEnded
whismanoid 1:77f1ee332e4a 1662
whismanoid 1:77f1ee332e4a 1663 //----------------------------------------
whismanoid 1:77f1ee332e4a 1664 // ADC Channels AIN12, AIN13 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 1665 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1666 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1667 // AIN12 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1668 // AIN13 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1669 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 1670 // AIN12 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1671 // AIN13 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1672 //
whismanoid 1:77f1ee332e4a 1673 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 1674 UNIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1675 BIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1676 RANGE &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1677 // UCH12/13=0, BCH12/13=0, RANGE12/13=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1678 #endif // AIN_12_13_SingleEnded
whismanoid 1:77f1ee332e4a 1679
whismanoid 1:77f1ee332e4a 1680 #if AIN_12_13_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1681
whismanoid 1:77f1ee332e4a 1682 //----------------------------------------
whismanoid 1:77f1ee332e4a 1683 // ADC Channels AIN12, AIN13 = Differential Unipolar (AIN12 > AIN13)
whismanoid 1:77f1ee332e4a 1684 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1685 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1686 // AIN12, AIN13 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1687 // AIN12 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1688 // AIN13 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1689 //
whismanoid 1:77f1ee332e4a 1690 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 1691 UNIPOLAR |= (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1692 BIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1693 RANGE &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1694 // UCH12/13=1, BCH12/13=0, RANGE12/13=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1695 #endif // AIN_12_13_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1696
whismanoid 1:77f1ee332e4a 1697 #if AIN_12_13_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1698
whismanoid 1:77f1ee332e4a 1699 //----------------------------------------
whismanoid 1:77f1ee332e4a 1700 // ADC Channels AIN12, AIN13 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1701 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1702 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 1703 // AIN12, AIN13 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 1704 // AIN12 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1705 // AIN13 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1706 //
whismanoid 1:77f1ee332e4a 1707 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1708 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 1709 UNIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1710 BIPOLAR |= (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1711 RANGE &= ~ (1 << AIN_12_13_LSB);
whismanoid 4:8a0ae95546fa 1712 // UCH12/13=0, BCH12/13=1, RANGE12/13=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1713 #endif // AIN_12_13_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1714
whismanoid 1:77f1ee332e4a 1715 #if AIN_12_13_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1716
whismanoid 1:77f1ee332e4a 1717 //----------------------------------------
whismanoid 1:77f1ee332e4a 1718 // ADC Channels AIN12, AIN13 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1719 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1720 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 1721 // AIN12, AIN13 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 1722 // AIN12 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1723 // AIN13 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1724 //
whismanoid 1:77f1ee332e4a 1725 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1726 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 1727 UNIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1728 BIPOLAR |= (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1729 RANGE |= (1 << AIN_12_13_LSB);
whismanoid 4:8a0ae95546fa 1730 // UCH12/13=0, BCH12/13=1, RANGE12/13=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1731 #endif // AIN_12_13_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1732
whismanoid 1:77f1ee332e4a 1733 #if AIN_14_15_SingleEnded
whismanoid 1:77f1ee332e4a 1734
whismanoid 1:77f1ee332e4a 1735 //----------------------------------------
whismanoid 1:77f1ee332e4a 1736 // ADC Channels AIN14, AIN15 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 1737 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1738 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1739 // AIN14 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1740 // AIN15 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1741 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 1742 // AIN14 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1743 // AIN15 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1744 //
whismanoid 1:77f1ee332e4a 1745 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 1746 UNIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1747 BIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1748 RANGE &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1749 // UCH14/15=0, BCH14/15=0, RANGE14/15=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1750 #endif // AIN_14_15_SingleEnded
whismanoid 1:77f1ee332e4a 1751
whismanoid 1:77f1ee332e4a 1752 #if AIN_14_15_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1753
whismanoid 1:77f1ee332e4a 1754 //----------------------------------------
whismanoid 1:77f1ee332e4a 1755 // ADC Channels AIN14, AIN15 = Differential Unipolar (AIN14 > AIN15)
whismanoid 1:77f1ee332e4a 1756 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1757 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1758 // AIN14, AIN15 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1759 // AIN14 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1760 // AIN15 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1761 //
whismanoid 1:77f1ee332e4a 1762 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 1763 UNIPOLAR |= (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1764 BIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1765 RANGE &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1766 // UCH14/15=1, BCH14/15=0, RANGE14/15=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1767 #endif // AIN_14_15_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1768
whismanoid 1:77f1ee332e4a 1769 #if AIN_14_15_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1770
whismanoid 1:77f1ee332e4a 1771 //----------------------------------------
whismanoid 1:77f1ee332e4a 1772 // ADC Channels AIN14, AIN15 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1773 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1774 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 1775 // AIN14, AIN15 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 1776 // AIN14 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1777 // AIN15 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1778 //
whismanoid 1:77f1ee332e4a 1779 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1780 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 1781 UNIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1782 BIPOLAR |= (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1783 RANGE &= ~ (1 << AIN_14_15_LSB);
whismanoid 4:8a0ae95546fa 1784 // UCH14/15=0, BCH14/15=1, RANGE14/15=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1785 #endif // AIN_14_15_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1786
whismanoid 1:77f1ee332e4a 1787 #if AIN_14_15_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1788
whismanoid 1:77f1ee332e4a 1789 //----------------------------------------
whismanoid 1:77f1ee332e4a 1790 // ADC Channels AIN14, AIN15 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1791 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1792 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 1793 // AIN14, AIN15 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 1794 // AIN14 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1795 // AIN15 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1796 //
whismanoid 1:77f1ee332e4a 1797 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1798 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 1799 UNIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1800 BIPOLAR |= (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1801 RANGE |= (1 << AIN_14_15_LSB);
whismanoid 4:8a0ae95546fa 1802 // UCH14/15=0, BCH14/15=1, RANGE14/15=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1803 #endif // AIN_14_15_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1804
whismanoid 1:77f1ee332e4a 1805 //----------------------------------------
whismanoid 1:77f1ee332e4a 1806 // SPI write ADC CONFIGURATION register
whismanoid 1:77f1ee332e4a 1807 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 1808 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1809 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1810 SPIwrite16bits(ADC_CONFIGURATION);
whismanoid 1:77f1ee332e4a 1811 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1812
whismanoid 1:77f1ee332e4a 1813 //----------------------------------------
whismanoid 1:77f1ee332e4a 1814 // SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid 1:77f1ee332e4a 1815 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1816 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1817 SPIwrite16bits(UNIPOLAR);
whismanoid 1:77f1ee332e4a 1818 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1819 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1820 SPIwrite16bits(BIPOLAR);
whismanoid 1:77f1ee332e4a 1821 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1822 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1823 SPIwrite16bits(RANGE);
whismanoid 1:77f1ee332e4a 1824 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1825
whismanoid 1:77f1ee332e4a 1826 //----------------------------------------
whismanoid 1:77f1ee332e4a 1827 // SPI write CSCAN0 CSCAN1 registers
whismanoid 1:77f1ee332e4a 1828 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1829 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1830 SPIwrite16bits(CSCAN0);
whismanoid 1:77f1ee332e4a 1831 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1832 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1833 SPIwrite16bits(CSCAN1);
whismanoid 1:77f1ee332e4a 1834 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1835 }
whismanoid 1:77f1ee332e4a 1836
whismanoid 1:77f1ee332e4a 1837 //----------------------------------------
whismanoid 6:cb7bdeb185d0 1838 // Menu item 'IS'
whismanoid 1:77f1ee332e4a 1839 // ADC Channels AIN(channelId), AIN(channelId+1) = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 1840 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1841 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1842 // AIN(channelId) is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1843 // AIN(channelId+1) is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1844 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 1845 // AIN(channelId) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1846 // AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1847 //
whismanoid 6:cb7bdeb185d0 1848 void MAX11131::Reconfigure_SingleEnded(int channel_0_15)
whismanoid 1:77f1ee332e4a 1849 {
whismanoid 1:77f1ee332e4a 1850
whismanoid 1:77f1ee332e4a 1851 //----------------------------------------
whismanoid 1:77f1ee332e4a 1852 // UCH(ch)/(ch+1)=0, BCH(ch)/(ch+1)=0, RANGE(ch)/(ch+1)=0:
whismanoid 1:77f1ee332e4a 1853 // AIN(ch)/AIN(ch+1) two independent single-ended inputs,
whismanoid 1:77f1ee332e4a 1854 // unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1855 //
whismanoid 6:cb7bdeb185d0 1856 const int channelPairIndex = channel_0_15 / 2;
whismanoid 1:77f1ee332e4a 1857 const int bitmask = (1 << (10 - channelPairIndex));
whismanoid 1:77f1ee332e4a 1858 UNIPOLAR &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1859 BIPOLAR &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1860 RANGE &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1861
whismanoid 1:77f1ee332e4a 1862 //----------------------------------------
whismanoid 1:77f1ee332e4a 1863 // SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid 1:77f1ee332e4a 1864 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1865 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1866 SPIwrite16bits(UNIPOLAR);
whismanoid 1:77f1ee332e4a 1867 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1868 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1869 SPIwrite16bits(BIPOLAR);
whismanoid 1:77f1ee332e4a 1870 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1871 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1872 SPIwrite16bits(RANGE);
whismanoid 1:77f1ee332e4a 1873 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1874 }
whismanoid 1:77f1ee332e4a 1875
whismanoid 1:77f1ee332e4a 1876 //----------------------------------------
whismanoid 6:cb7bdeb185d0 1877 // Menu item 'IU'
whismanoid 1:77f1ee332e4a 1878 // ADC Channels AIN(channelId), AIN(channelId+1) = Differential Unipolar (AIN(channelId) > AIN(channelId+1))
whismanoid 1:77f1ee332e4a 1879 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1880 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1881 // AIN(channelId), AIN(channelId+1) are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1882 // AIN(channelId) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1883 // AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1884 //
whismanoid 6:cb7bdeb185d0 1885 void MAX11131::Reconfigure_DifferentialUnipolar(int channel_0_15)
whismanoid 1:77f1ee332e4a 1886 {
whismanoid 1:77f1ee332e4a 1887
whismanoid 1:77f1ee332e4a 1888 //----------------------------------------
whismanoid 1:77f1ee332e4a 1889 // UCH(ch)/(ch+1)=1, BCH(ch)/(ch+1)=0, RANGE(ch)/(ch+1)=0:
whismanoid 1:77f1ee332e4a 1890 // AIN(ch)/AIN(ch+1) differential input pair,
whismanoid 1:77f1ee332e4a 1891 // unipolar code (AIN(ch)>AIN(ch+1)) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1892 //
whismanoid 6:cb7bdeb185d0 1893 const int channelPairIndex = channel_0_15 / 2;
whismanoid 1:77f1ee332e4a 1894 const int bitmask = (1 << (10 - channelPairIndex));
whismanoid 1:77f1ee332e4a 1895 UNIPOLAR |= bitmask;
whismanoid 1:77f1ee332e4a 1896 BIPOLAR &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1897 RANGE &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1898 // UCH0/1=1, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1899
whismanoid 1:77f1ee332e4a 1900 //----------------------------------------
whismanoid 1:77f1ee332e4a 1901 // SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid 1:77f1ee332e4a 1902 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1903 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1904 SPIwrite16bits(UNIPOLAR);
whismanoid 1:77f1ee332e4a 1905 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1906 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1907 SPIwrite16bits(BIPOLAR);
whismanoid 1:77f1ee332e4a 1908 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1909 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1910 SPIwrite16bits(RANGE);
whismanoid 1:77f1ee332e4a 1911 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1912 }
whismanoid 1:77f1ee332e4a 1913
whismanoid 1:77f1ee332e4a 1914 //----------------------------------------
whismanoid 6:cb7bdeb185d0 1915 // Menu item 'IB'
whismanoid 1:77f1ee332e4a 1916 // ADC Channels AIN(channelId), AIN(channelId+1) = Differential Bipolar
whismanoid 1:77f1ee332e4a 1917 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1918 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 1919 // AIN(channelId), AIN(channelId+1) are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 1920 // AIN(channelId) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1921 // AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1922 //
whismanoid 6:cb7bdeb185d0 1923 void MAX11131::Reconfigure_DifferentialBipolarFSVref(int channel_0_15)
whismanoid 1:77f1ee332e4a 1924 {
whismanoid 1:77f1ee332e4a 1925
whismanoid 1:77f1ee332e4a 1926 //----------------------------------------
whismanoid 1:77f1ee332e4a 1927 // UCH(ch)/(ch+1)=0, BCH(ch)/(ch+1)=1, RANGE(ch)/(ch+1)=0:
whismanoid 4:8a0ae95546fa 1928 // AIN(ch)/AIN(ch+1) differential input pair (+/-)(1/2)Vref,
whismanoid 1:77f1ee332e4a 1929 // bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1930 //
whismanoid 6:cb7bdeb185d0 1931 const int channelPairIndex = channel_0_15 / 2;
whismanoid 1:77f1ee332e4a 1932 const int bitmask = (1 << (10 - channelPairIndex));
whismanoid 1:77f1ee332e4a 1933 UNIPOLAR &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1934 BIPOLAR |= bitmask;
whismanoid 1:77f1ee332e4a 1935 RANGE &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1936
whismanoid 1:77f1ee332e4a 1937 //----------------------------------------
whismanoid 1:77f1ee332e4a 1938 // SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid 1:77f1ee332e4a 1939 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1940 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1941 SPIwrite16bits(UNIPOLAR);
whismanoid 1:77f1ee332e4a 1942 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1943 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1944 SPIwrite16bits(BIPOLAR);
whismanoid 1:77f1ee332e4a 1945 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1946 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1947 SPIwrite16bits(RANGE);
whismanoid 1:77f1ee332e4a 1948 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1949 }
whismanoid 1:77f1ee332e4a 1950
whismanoid 1:77f1ee332e4a 1951 //----------------------------------------
whismanoid 6:cb7bdeb185d0 1952 // Menu item 'IR'
whismanoid 1:77f1ee332e4a 1953 // ADC Channels AIN(channelId), AIN(channelId+1) = Differential Bipolar
whismanoid 1:77f1ee332e4a 1954 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1955 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 1956 // AIN(channelId), AIN(channelId+1) are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 1957 // AIN(channelId) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1958 // AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1959 //
whismanoid 6:cb7bdeb185d0 1960 void MAX11131::Reconfigure_DifferentialBipolarFS2Vref(int channel_0_15)
whismanoid 1:77f1ee332e4a 1961 {
whismanoid 1:77f1ee332e4a 1962
whismanoid 1:77f1ee332e4a 1963 //----------------------------------------
whismanoid 1:77f1ee332e4a 1964 // UCH(ch)/(ch+1)=0, BCH(ch)/(ch+1)=1, RANGE(ch)/(ch+1)=1:
whismanoid 4:8a0ae95546fa 1965 // AIN(ch)/AIN(ch+1) differential input pair (+/-)Vref,
whismanoid 1:77f1ee332e4a 1966 // bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1967 //
whismanoid 6:cb7bdeb185d0 1968 const int channelPairIndex = channel_0_15 / 2;
whismanoid 1:77f1ee332e4a 1969 const int bitmask = (1 << (10 - channelPairIndex));
whismanoid 1:77f1ee332e4a 1970 UNIPOLAR &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1971 BIPOLAR |= bitmask;
whismanoid 1:77f1ee332e4a 1972 RANGE |= bitmask;
whismanoid 4:8a0ae95546fa 1973 // UCH0/1=0, BCH0/1=1, RANGE0/1=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1974
whismanoid 1:77f1ee332e4a 1975 //----------------------------------------
whismanoid 1:77f1ee332e4a 1976 // SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid 1:77f1ee332e4a 1977 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1978 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1979 SPIwrite16bits(UNIPOLAR);
whismanoid 1:77f1ee332e4a 1980 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1981 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1982 SPIwrite16bits(BIPOLAR);
whismanoid 1:77f1ee332e4a 1983 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1984 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1985 SPIwrite16bits(RANGE);
whismanoid 1:77f1ee332e4a 1986 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1987 }
whismanoid 1:77f1ee332e4a 1988
whismanoid 1:77f1ee332e4a 1989 //----------------------------------------
whismanoid 1:77f1ee332e4a 1990 // SCAN_0000_NOP
whismanoid 1:77f1ee332e4a 1991 //
whismanoid 1:77f1ee332e4a 1992 // Shift 16 bits out of ADC, without changing configuration.
whismanoid 1:77f1ee332e4a 1993 // Note: @return data format depends on CHAN_ID bit:
whismanoid 1:77f1ee332e4a 1994 // "CH[3:0] DATA[11:0]" when CHAN_ID = 1, or
whismanoid 1:77f1ee332e4a 1995 // "0 DATA[11:0] x x x" when CHAN_ID = 0.
whismanoid 1:77f1ee332e4a 1996 int16_t MAX11131::ScanRead(void)
whismanoid 1:77f1ee332e4a 1997 {
whismanoid 1:77f1ee332e4a 1998
whismanoid 1:77f1ee332e4a 1999 //----------------------------------------
whismanoid 1:77f1ee332e4a 2000 // Read SPI data from device while MOSI (Maxim DIN) is 0. Effectively ADC_MODE_CONTROL SCAN[3:0] = SCAN_0000_NOP = 0
whismanoid 1:77f1ee332e4a 2001 SPI_MOSI_Semantic = 0; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2002 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2003 int16_t misoData16 = SPIread16bits();
whismanoid 1:77f1ee332e4a 2004 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2005 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 2006 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2007 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2008 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2009 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2010 return misoData16;
whismanoid 1:77f1ee332e4a 2011 }
whismanoid 0:f7d706d2904d 2012
whismanoid 1:77f1ee332e4a 2013 //----------------------------------------
whismanoid 1:77f1ee332e4a 2014 // SCAN_0000_NOP
whismanoid 1:77f1ee332e4a 2015 //
whismanoid 1:77f1ee332e4a 2016 // Read raw ADC codes from device into AINcode[] and RAW_misoData16[].
whismanoid 1:77f1ee332e4a 2017 // If internal clock mode with SWCNV=0, measurements will be triggered using CNVST pin.
whismanoid 1:77f1ee332e4a 2018 //
whismanoid 1:77f1ee332e4a 2019 // @pre one of the Scan functions was called, setting NumWords
whismanoid 6:cb7bdeb185d0 2020 // @param[in] NumWords: number of words to be read from the FIFO
whismanoid 1:77f1ee332e4a 2021 // @post RAW_misoData16[index] contains the raw SPI Master-In,Slave-Out data
whismanoid 1:77f1ee332e4a 2022 // @post AINcode[NUM_CHANNELS] contains the latest readings in LSBs
whismanoid 1:77f1ee332e4a 2023 //
whismanoid 1:77f1ee332e4a 2024 void MAX11131::ReadAINcode(void)
whismanoid 1:77f1ee332e4a 2025 {
whismanoid 1:77f1ee332e4a 2026
whismanoid 1:77f1ee332e4a 2027 //----------------------------------------
whismanoid 1:77f1ee332e4a 2028 // loop index for RAW_misoData16[SAMPLESET_MAX_ENTRIES];
whismanoid 1:77f1ee332e4a 2029 int index;
whismanoid 1:77f1ee332e4a 2030
whismanoid 1:77f1ee332e4a 2031 //----------------------------------------
whismanoid 1:77f1ee332e4a 2032 // If internal clock mode with SWCNV=0, trigger measurement using CNVST pin and wait for EOC pin.
whismanoid 1:77f1ee332e4a 2033 if (isExternalClock == 0)
whismanoid 1:77f1ee332e4a 2034 {
whismanoid 1:77f1ee332e4a 2035 if (swcnv_0_1 == 0)
whismanoid 1:77f1ee332e4a 2036 {
whismanoid 1:77f1ee332e4a 2037 // SWCNV=0: trigger measurement by driving CNVST/AIN14 pin low
whismanoid 1:77f1ee332e4a 2038 // for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 2039 // One CNVST pulse scans all requested channels and stores the results in the FIFO.
whismanoid 1:77f1ee332e4a 2040 CNVSToutputPulseLow();
whismanoid 1:77f1ee332e4a 2041 }
whismanoid 1:77f1ee332e4a 2042 // wait for EOC low (internal clock mode end of conversion)
whismanoid 1:77f1ee332e4a 2043 EOCinputWaitUntilLow();
whismanoid 1:77f1ee332e4a 2044 }
whismanoid 1:77f1ee332e4a 2045
whismanoid 1:77f1ee332e4a 2046 //----------------------------------------
whismanoid 1:77f1ee332e4a 2047 // Read raw ADC codes from device into AINcode[] and RAW_misoData16[].
whismanoid 1:77f1ee332e4a 2048 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 2049 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2050 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2051 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2052 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2053 switch(ScanMode)
whismanoid 1:77f1ee332e4a 2054 {
whismanoid 1:77f1ee332e4a 2055 //----------------------------------------
whismanoid 1:77f1ee332e4a 2056 // read data words
whismanoid 1:77f1ee332e4a 2057 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2058 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2059 case SCAN_0000_NOP:
whismanoid 1:77f1ee332e4a 2060 case SCAN_0011_StandardInternalClock:
whismanoid 1:77f1ee332e4a 2061 case SCAN_0101_UpperInternalClock:
whismanoid 1:77f1ee332e4a 2062 case SCAN_0111_CustomInternalClock:
whismanoid 1:77f1ee332e4a 2063 default:
whismanoid 1:77f1ee332e4a 2064 for (index = 0; index < NumWords; index++) {
whismanoid 1:77f1ee332e4a 2065 RAW_misoData16[index] = ScanRead();
whismanoid 1:77f1ee332e4a 2066 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2067 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2068 int16_t value_u12 = (RAW_misoData16[index] & 0x0FFF);
whismanoid 1:77f1ee332e4a 2069 int channelId = ((RAW_misoData16[index] >> 12) & 0x000F);
whismanoid 1:77f1ee332e4a 2070 AINcode[channelId] = value_u12;
whismanoid 1:77f1ee332e4a 2071 }
whismanoid 1:77f1ee332e4a 2072 break;
whismanoid 1:77f1ee332e4a 2073 //----------------------------------------
whismanoid 1:77f1ee332e4a 2074 // read data words
whismanoid 1:77f1ee332e4a 2075 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 2076 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2077 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2078 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2079 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2080 case SCAN_0001_Manual:
whismanoid 1:77f1ee332e4a 2081 case SCAN_0100_StandardExternalClock:
whismanoid 1:77f1ee332e4a 2082 case SCAN_0110_UpperExternalClock:
whismanoid 1:77f1ee332e4a 2083 case SCAN_1000_CustomExternalClock:
whismanoid 1:77f1ee332e4a 2084 case SCAN_1001_SampleSetExternalClock:
whismanoid 1:77f1ee332e4a 2085 if (chan_id_0_1 != 0) {
whismanoid 1:77f1ee332e4a 2086 for (index = 0; index < NumWords; index++) {
whismanoid 1:77f1ee332e4a 2087 RAW_misoData16[index] = ScanRead();
whismanoid 1:77f1ee332e4a 2088 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2089 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2090 int16_t value_u12 = (RAW_misoData16[index] & 0x0FFF);
whismanoid 1:77f1ee332e4a 2091 int channelId = ((RAW_misoData16[index] >> 12) & 0x000F);
whismanoid 1:77f1ee332e4a 2092 AINcode[channelId] = value_u12;
whismanoid 1:77f1ee332e4a 2093 }
whismanoid 1:77f1ee332e4a 2094 } else {
whismanoid 1:77f1ee332e4a 2095 for (index = 0; index < NumWords; index++) {
whismanoid 1:77f1ee332e4a 2096 RAW_misoData16[index] = ScanRead();
whismanoid 1:77f1ee332e4a 2097 int16_t value_u12 = ((RAW_misoData16[index] >> 3) & 0x0FFF);
whismanoid 1:77f1ee332e4a 2098 int channelId = channelNumber_0_15;
whismanoid 1:77f1ee332e4a 2099 AINcode[channelId] = value_u12;
whismanoid 1:77f1ee332e4a 2100 }
whismanoid 1:77f1ee332e4a 2101 }
whismanoid 1:77f1ee332e4a 2102 break;
whismanoid 1:77f1ee332e4a 2103 //----------------------------------------
whismanoid 1:77f1ee332e4a 2104 // read data words and calculate mean, stddev
whismanoid 1:77f1ee332e4a 2105 case SCAN_0010_Repeat:
whismanoid 1:77f1ee332e4a 2106 // ScanRead_nWords_chanID_mean(NumWords); // TODO1: missing function
whismanoid 1:77f1ee332e4a 2107 // was this function AINcode_print_value_chanID_mean(int nWords) in main?
whismanoid 1:77f1ee332e4a 2108 // But this function prints to standard output so can't be inside the driver.
whismanoid 1:77f1ee332e4a 2109 for (index = 0; index < NumWords; index++) {
whismanoid 1:77f1ee332e4a 2110 RAW_misoData16[index] = ScanRead();
whismanoid 1:77f1ee332e4a 2111 }
whismanoid 1:77f1ee332e4a 2112 break;
whismanoid 1:77f1ee332e4a 2113 }
whismanoid 1:77f1ee332e4a 2114 }
whismanoid 1:77f1ee332e4a 2115
whismanoid 1:77f1ee332e4a 2116 //----------------------------------------
whismanoid 1:77f1ee332e4a 2117 // Sign-Extend a right-aligned MAX11131 code into a signed 2's complement value.
whismanoid 1:77f1ee332e4a 2118 // Supports the bipolar transfer functions.
whismanoid 1:77f1ee332e4a 2119 // @param[in] value_u12: raw 12-bit MAX11131 code (right justified).
whismanoid 1:77f1ee332e4a 2120 // @return sign-extended 2's complement value.
whismanoid 1:77f1ee332e4a 2121 //
whismanoid 1:77f1ee332e4a 2122 int32_t MAX11131::TwosComplementValue(uint32_t regValue)
whismanoid 1:77f1ee332e4a 2123 {
whismanoid 1:77f1ee332e4a 2124 const uint16_t SIGN_BIT_12BIT = 0x0800;
whismanoid 1:77f1ee332e4a 2125 const uint16_t FULL_SCALE_CODE_12BIT = 0x0fff;
whismanoid 1:77f1ee332e4a 2126 if (((regValue & SIGN_BIT_12BIT) != 0) && !((regValue & (SIGN_BIT_12BIT << 1)) != 0))
whismanoid 1:77f1ee332e4a 2127 {
whismanoid 1:77f1ee332e4a 2128 // (bSignBitNegative && !bExtendedSignBitNegative)
whismanoid 1:77f1ee332e4a 2129 // Twos_Complement negative value
whismanoid 1:77f1ee332e4a 2130 int32_t Offset_regValue = (int32_t)(regValue - (FULL_SCALE_CODE_12BIT + 1));
whismanoid 1:77f1ee332e4a 2131 return Offset_regValue;
whismanoid 1:77f1ee332e4a 2132 }
whismanoid 1:77f1ee332e4a 2133 // Twos_Complement positive value or zero
whismanoid 1:77f1ee332e4a 2134 return (int32_t)regValue;
whismanoid 1:77f1ee332e4a 2135 }
whismanoid 1:77f1ee332e4a 2136
whismanoid 1:77f1ee332e4a 2137 //----------------------------------------
whismanoid 1:77f1ee332e4a 2138 // Return the physical voltage corresponding to MAX11131 code.
whismanoid 1:77f1ee332e4a 2139 // Does not perform any offset or gain correction.
whismanoid 1:77f1ee332e4a 2140 // @pre VRef = Voltage of REF input, in Volts
whismanoid 1:77f1ee332e4a 2141 // @param[in] value_u12: raw 12-bit MAX11131 code (right justified).
whismanoid 1:77f1ee332e4a 2142 // @param[in] channelId: AIN channel number.
whismanoid 1:77f1ee332e4a 2143 // @return physical voltage corresponding to MAX11131 code.
whismanoid 1:77f1ee332e4a 2144 //
whismanoid 1:77f1ee332e4a 2145 double MAX11131::VoltageOfCode(int16_t value_u12, int channelId)
whismanoid 1:77f1ee332e4a 2146 {
whismanoid 1:77f1ee332e4a 2147 int channelPairIndex = channelId / 2;
whismanoid 1:77f1ee332e4a 2148 // format: 1 0 0 0 1 UCH0/1 UCH2/3 UCH4/5 UCH6/7 UCH8/9 UCH10/11 UCH12/13 UCH14/15 PDIFF_COM x x
whismanoid 1:77f1ee332e4a 2149 int UCHn = (UNIPOLAR >> (10 - channelPairIndex)) & 0x01;
whismanoid 1:77f1ee332e4a 2150 int BCHn = (BIPOLAR >> (10 - channelPairIndex)) & 0x01;
whismanoid 1:77f1ee332e4a 2151 int RANGEn = (RANGE >> (10 - channelPairIndex)) & 0x01;
whismanoid 1:77f1ee332e4a 2152 if (UCHn)
whismanoid 1:77f1ee332e4a 2153 {
whismanoid 1:77f1ee332e4a 2154 // UCH0/1=1, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 2155 return (value_u12 * VRef / 4096);
whismanoid 1:77f1ee332e4a 2156 }
whismanoid 1:77f1ee332e4a 2157 else
whismanoid 1:77f1ee332e4a 2158 {
whismanoid 1:77f1ee332e4a 2159 if (BCHn)
whismanoid 1:77f1ee332e4a 2160 {
whismanoid 1:77f1ee332e4a 2161 if (RANGEn)
whismanoid 1:77f1ee332e4a 2162 {
whismanoid 4:8a0ae95546fa 2163 // UCH0/1=0, BCH0/1=1, RANGE0/1=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 2164 return (TwosComplementValue(value_u12) * VRef / 2048);
whismanoid 1:77f1ee332e4a 2165 }
whismanoid 1:77f1ee332e4a 2166 else
whismanoid 1:77f1ee332e4a 2167 {
whismanoid 4:8a0ae95546fa 2168 // UCH0/1=0, BCH0/1=1, RANGE0/1=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 2169 return (TwosComplementValue(value_u12) * VRef / 4096);
whismanoid 1:77f1ee332e4a 2170 }
whismanoid 1:77f1ee332e4a 2171 }
whismanoid 1:77f1ee332e4a 2172 else
whismanoid 1:77f1ee332e4a 2173 {
whismanoid 1:77f1ee332e4a 2174 // UCH0/1=0, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 2175 return (value_u12 * VRef / 4096);
whismanoid 1:77f1ee332e4a 2176 }
whismanoid 1:77f1ee332e4a 2177 }
whismanoid 1:77f1ee332e4a 2178 }
whismanoid 1:77f1ee332e4a 2179
whismanoid 1:77f1ee332e4a 2180 //----------------------------------------
whismanoid 1:77f1ee332e4a 2181 // SCAN_0001_Manual
whismanoid 1:77f1ee332e4a 2182 //
whismanoid 1:77f1ee332e4a 2183 // Measure ADC channel channelNumber_0_15 once.
whismanoid 1:77f1ee332e4a 2184 // External clock mode.
whismanoid 1:77f1ee332e4a 2185 // @param[in] channelNumber_0_15: AIN Channel Number
whismanoid 1:77f1ee332e4a 2186 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 2187 // @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2188 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 6:cb7bdeb185d0 2189 // @post NumWords = number of words to be read from the FIFO
whismanoid 1:77f1ee332e4a 2190 // For external clock modes, the data format depends on CHAN_ID.
whismanoid 1:77f1ee332e4a 2191 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2192 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2193 //
whismanoid 1:77f1ee332e4a 2194 int MAX11131::ScanManual(void)
whismanoid 1:77f1ee332e4a 2195 {
whismanoid 1:77f1ee332e4a 2196
whismanoid 1:77f1ee332e4a 2197 //----------------------------------------
whismanoid 2:50a0cf017492 2198 // define write-only register ADC_MODE_CONTROL
whismanoid 2:50a0cf017492 2199 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 2:50a0cf017492 2200 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 2:50a0cf017492 2201 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 2:50a0cf017492 2202 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 2203 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 2:50a0cf017492 2204 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 2:50a0cf017492 2205 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 2:50a0cf017492 2206
whismanoid 2:50a0cf017492 2207 //----------------------------------------
whismanoid 2:50a0cf017492 2208 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 2209 int needFIFOreset = (isExternalClock != 1);
whismanoid 2:50a0cf017492 2210 if (needFIFOreset) {
whismanoid 2:50a0cf017492 2211 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 2212 ADC_MODE_CONTROL = ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 2213 // Send SPI configuration to device
whismanoid 2:50a0cf017492 2214 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 2:50a0cf017492 2215 SPIoutputCS(0); // drive CS low
whismanoid 2:50a0cf017492 2216 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 2:50a0cf017492 2217 SPIoutputCS(1); // drive CS high
whismanoid 2:50a0cf017492 2218 ADC_MODE_CONTROL = 0;
whismanoid 2:50a0cf017492 2219 }
whismanoid 2:50a0cf017492 2220
whismanoid 2:50a0cf017492 2221 //----------------------------------------
whismanoid 1:77f1ee332e4a 2222 // number of words to read
whismanoid 1:77f1ee332e4a 2223 NumWords = 1;
whismanoid 1:77f1ee332e4a 2224
whismanoid 1:77f1ee332e4a 2225 //----------------------------------------
whismanoid 1:77f1ee332e4a 2226 // External Clock Mode
whismanoid 1:77f1ee332e4a 2227 isExternalClock = 1;
whismanoid 1:77f1ee332e4a 2228
whismanoid 1:77f1ee332e4a 2229 //----------------------------------------
whismanoid 1:77f1ee332e4a 2230 // update device driver global variable
whismanoid 1:77f1ee332e4a 2231 ScanMode = SCAN_0001_Manual;
whismanoid 1:77f1ee332e4a 2232
whismanoid 1:77f1ee332e4a 2233 //----------------------------------------
whismanoid 1:77f1ee332e4a 2234 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0001_Manual = 1
whismanoid 1:77f1ee332e4a 2235 //~ const int SCAN_0001_Manual = 1; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2236 ADC_MODE_CONTROL |= ((SCAN_0001_Manual & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2237
whismanoid 1:77f1ee332e4a 2238 //----------------------------------------
whismanoid 1:77f1ee332e4a 2239 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 2240 ADC_MODE_CONTROL |= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 2241
whismanoid 1:77f1ee332e4a 2242 //----------------------------------------
whismanoid 1:77f1ee332e4a 2243 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2244 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2245
whismanoid 1:77f1ee332e4a 2246 //----------------------------------------
whismanoid 1:77f1ee332e4a 2247 // ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid 1:77f1ee332e4a 2248 // (applicable to external clock mode only)
whismanoid 1:77f1ee332e4a 2249 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 2250 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2251 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2252 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2253 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2254 ADC_MODE_CONTROL |= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid 1:77f1ee332e4a 2255
whismanoid 1:77f1ee332e4a 2256 //----------------------------------------
whismanoid 1:77f1ee332e4a 2257 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2258 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2259 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2260 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2261 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2262 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2263
whismanoid 1:77f1ee332e4a 2264 //----------------------------------------
whismanoid 1:77f1ee332e4a 2265 // return number of words to read
whismanoid 1:77f1ee332e4a 2266 return NumWords;
whismanoid 1:77f1ee332e4a 2267 }
whismanoid 1:77f1ee332e4a 2268
whismanoid 1:77f1ee332e4a 2269 //----------------------------------------
whismanoid 1:77f1ee332e4a 2270 // SCAN_0010_Repeat
whismanoid 1:77f1ee332e4a 2271 //
whismanoid 1:77f1ee332e4a 2272 // Measure ADC channel channelNumber_0_15 repeatedly with averaging.
whismanoid 1:77f1ee332e4a 2273 // Internal clock mode.
whismanoid 1:77f1ee332e4a 2274 // @param[in] channelNumber_0_15: AIN Channel Number
whismanoid 1:77f1ee332e4a 2275 // @param[in] average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid 1:77f1ee332e4a 2276 // average_0_4_8_16_32=0 to disable averaging.
whismanoid 1:77f1ee332e4a 2277 // @param[in] nscan_4_8_12_16: Number of ScanRead() words to report.
whismanoid 1:77f1ee332e4a 2278 // @param[in] swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2279 // SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid 1:77f1ee332e4a 2280 // Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 2281 // SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid 1:77f1ee332e4a 2282 // CS must be held low for minimum of 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2283 // CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 2284 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 2285 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 6:cb7bdeb185d0 2286 // @post NumWords = number of words to be read from the FIFO
whismanoid 1:77f1ee332e4a 2287 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2288 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2289 //
whismanoid 1:77f1ee332e4a 2290 int MAX11131::ScanRepeat(void)
whismanoid 1:77f1ee332e4a 2291 {
whismanoid 1:77f1ee332e4a 2292
whismanoid 1:77f1ee332e4a 2293 //----------------------------------------
whismanoid 1:77f1ee332e4a 2294 // number of words to read
whismanoid 1:77f1ee332e4a 2295 NumWords = (nscan_4_8_12_16);
whismanoid 1:77f1ee332e4a 2296
whismanoid 1:77f1ee332e4a 2297 //----------------------------------------
whismanoid 1:77f1ee332e4a 2298 // Internal Clock Mode
whismanoid 1:77f1ee332e4a 2299 isExternalClock = 0;
whismanoid 1:77f1ee332e4a 2300
whismanoid 1:77f1ee332e4a 2301 //----------------------------------------
whismanoid 1:77f1ee332e4a 2302 // update device driver global variable
whismanoid 1:77f1ee332e4a 2303 ScanMode = SCAN_0010_Repeat;
whismanoid 1:77f1ee332e4a 2304
whismanoid 1:77f1ee332e4a 2305 //----------------------------------------
whismanoid 1:77f1ee332e4a 2306 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 2307 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 2308 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 2309 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 2310 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2311 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 2312 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2313 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2314
whismanoid 1:77f1ee332e4a 2315 //----------------------------------------
whismanoid 1:77f1ee332e4a 2316 // define write-only register ADC_CONFIGURATION
whismanoid 1:77f1ee332e4a 2317 ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid 1:77f1ee332e4a 2318 const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid 1:77f1ee332e4a 2319 const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid 1:77f1ee332e4a 2320 const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid 1:77f1ee332e4a 2321 const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid 1:77f1ee332e4a 2322 const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid 1:77f1ee332e4a 2323 const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid 1:77f1ee332e4a 2324
whismanoid 1:77f1ee332e4a 2325 //----------------------------------------
whismanoid 1:77f1ee332e4a 2326 // if average, ADC CONFIGURATION register set AVG and NAVG[1:0]
whismanoid 1:77f1ee332e4a 2327 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 2328 // if average, ADC CONFIGURATION register set AVG ON BIT TO 1
whismanoid 1:77f1ee332e4a 2329 // if average, ADC CONFIGURATION register set NAVG[1:0] TO N
whismanoid 1:77f1ee332e4a 2330 if (average_0_4_8_16_32 == 4) {
whismanoid 1:77f1ee332e4a 2331 // Enable Averaging of 4 samples (AVGON=1, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 2332 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2333 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2334 ADC_CONFIGURATION |= ((0 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2335 } else if (average_0_4_8_16_32 == 8) {
whismanoid 1:77f1ee332e4a 2336 // Enable Averaging of 8 samples (AVGON=1, NAVG[1:0]=1)
whismanoid 1:77f1ee332e4a 2337 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2338 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2339 ADC_CONFIGURATION |= ((1 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2340 } else if (average_0_4_8_16_32 == 16) {
whismanoid 1:77f1ee332e4a 2341 // Enable Averaging of 16 samples (AVGON=1, NAVG[1:0]=2)
whismanoid 1:77f1ee332e4a 2342 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2343 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2344 ADC_CONFIGURATION |= ((2 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2345 } else if (average_0_4_8_16_32 == 32) {
whismanoid 1:77f1ee332e4a 2346 // Enable Averaging of 32 samples (AVGON=1, NAVG[1:0]=3)
whismanoid 1:77f1ee332e4a 2347 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2348 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2349 ADC_CONFIGURATION |= ((3 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2350 } else {
whismanoid 1:77f1ee332e4a 2351 // Disable Averaging (AVGON=0, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 2352 ADC_CONFIGURATION &= ~ (( AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2353 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2354 }
whismanoid 1:77f1ee332e4a 2355
whismanoid 1:77f1ee332e4a 2356 //----------------------------------------
whismanoid 1:77f1ee332e4a 2357 // ADC CONFIGURATION register set NSCAN[1:0] for scan count
whismanoid 1:77f1ee332e4a 2358 // (applicable to SCAN_0010_Repeat only)
whismanoid 1:77f1ee332e4a 2359 if (nscan_4_8_12_16 == 4) {
whismanoid 1:77f1ee332e4a 2360 // Set scan count 4
whismanoid 1:77f1ee332e4a 2361 ADC_CONFIGURATION &= ~ (( NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 2362 ADC_CONFIGURATION |= ((0 & NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 2363 } else if (nscan_4_8_12_16 == 8) {
whismanoid 1:77f1ee332e4a 2364 // Set scan count 8
whismanoid 1:77f1ee332e4a 2365 ADC_CONFIGURATION &= ~ (( NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 2366 ADC_CONFIGURATION |= ((1 & NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 2367 } else if (nscan_4_8_12_16 == 12) {
whismanoid 1:77f1ee332e4a 2368 // Set scan count 12
whismanoid 1:77f1ee332e4a 2369 ADC_CONFIGURATION &= ~ (( NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 2370 ADC_CONFIGURATION |= ((2 & NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 2371 } else if (nscan_4_8_12_16 == 16) {
whismanoid 1:77f1ee332e4a 2372 // Set scan count 16
whismanoid 1:77f1ee332e4a 2373 ADC_CONFIGURATION &= ~ (( NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 2374 ADC_CONFIGURATION |= ((3 & NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 2375 }
whismanoid 1:77f1ee332e4a 2376
whismanoid 1:77f1ee332e4a 2377 //----------------------------------------
whismanoid 1:77f1ee332e4a 2378 // SPI write ADC CONFIGURATION register
whismanoid 1:77f1ee332e4a 2379 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2380 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2381 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2382 SPIwrite16bits(ADC_CONFIGURATION);
whismanoid 1:77f1ee332e4a 2383 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2384
whismanoid 1:77f1ee332e4a 2385 //----------------------------------------
whismanoid 1:77f1ee332e4a 2386 // Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid 1:77f1ee332e4a 2387 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2388 ADC_MODE_CONTROL |= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2389
whismanoid 1:77f1ee332e4a 2390 //----------------------------------------
whismanoid 1:77f1ee332e4a 2391 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0010_Repeat = 2
whismanoid 1:77f1ee332e4a 2392 //~ const int SCAN_0010_Repeat = 2; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2393 ADC_MODE_CONTROL |= ((SCAN_0010_Repeat & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2394
whismanoid 1:77f1ee332e4a 2395 //----------------------------------------
whismanoid 1:77f1ee332e4a 2396 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 2397 ADC_MODE_CONTROL |= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 2398
whismanoid 1:77f1ee332e4a 2399 //----------------------------------------
whismanoid 1:77f1ee332e4a 2400 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2401 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2402
whismanoid 1:77f1ee332e4a 2403 //----------------------------------------
whismanoid 1:77f1ee332e4a 2404 // ADC MODE CONTROL register set SWCNV if CNVST pin is not used
whismanoid 1:77f1ee332e4a 2405 // ADC MODE CONTROL REGISTER SELECT THE RIGHT SWCNV BIT
whismanoid 1:77f1ee332e4a 2406 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 2407 // SWCNV=1: trigger measurement on SPI CS rising edge; CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 2408 // SWCNV=0: trigger measurement by driving CNVST pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 2409 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 2410 ADC_MODE_CONTROL |= ((swcnv_0_1 & SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 2411 } else {
whismanoid 1:77f1ee332e4a 2412 ADC_MODE_CONTROL &= ~ (( SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 2413 }
whismanoid 1:77f1ee332e4a 2414
whismanoid 1:77f1ee332e4a 2415 //----------------------------------------
whismanoid 1:77f1ee332e4a 2416 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2417 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2418 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2419 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2420 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2421 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 2422 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2423 // NOTE: Figure 7 Internal Conversions with SWCNV=1 has an error, the 17th SCLK is mislabeled as "16" should be "17".
whismanoid 1:77f1ee332e4a 2424 SPIwrite24bits(ADC_MODE_CONTROL, 0);
whismanoid 1:77f1ee332e4a 2425 } else {
whismanoid 1:77f1ee332e4a 2426 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2427 }
whismanoid 1:77f1ee332e4a 2428 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2429
whismanoid 1:77f1ee332e4a 2430 //----------------------------------------
whismanoid 1:77f1ee332e4a 2431 // return number of words to read
whismanoid 1:77f1ee332e4a 2432 return NumWords;
whismanoid 1:77f1ee332e4a 2433 }
whismanoid 1:77f1ee332e4a 2434
whismanoid 1:77f1ee332e4a 2435 //----------------------------------------
whismanoid 1:77f1ee332e4a 2436 // SCAN_0011_StandardInternalClock
whismanoid 1:77f1ee332e4a 2437 //
whismanoid 1:77f1ee332e4a 2438 // Measure ADC channels in sequence from AIN0 to channelNumber_0_15.
whismanoid 1:77f1ee332e4a 2439 // Internal clock mode.
whismanoid 1:77f1ee332e4a 2440 // @param[in] channelNumber_0_15: AIN Channel Number
whismanoid 1:77f1ee332e4a 2441 // @param[in] average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid 1:77f1ee332e4a 2442 // average_0_4_8_16_32=0 to disable averaging.
whismanoid 1:77f1ee332e4a 2443 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 2444 // @param[in] swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2445 // SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid 1:77f1ee332e4a 2446 // Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 2447 // SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid 1:77f1ee332e4a 2448 // CS must be held low for minimum of 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2449 // CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 2450 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 6:cb7bdeb185d0 2451 // @post NumWords = number of words to be read from the FIFO
whismanoid 1:77f1ee332e4a 2452 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2453 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2454 //
whismanoid 1:77f1ee332e4a 2455 int MAX11131::ScanStandardInternalClock(void)
whismanoid 1:77f1ee332e4a 2456 {
whismanoid 1:77f1ee332e4a 2457
whismanoid 1:77f1ee332e4a 2458 //----------------------------------------
whismanoid 1:77f1ee332e4a 2459 // number of words to read
whismanoid 1:77f1ee332e4a 2460 NumWords = (1 + channelNumber_0_15);
whismanoid 1:77f1ee332e4a 2461
whismanoid 1:77f1ee332e4a 2462 //----------------------------------------
whismanoid 1:77f1ee332e4a 2463 // Internal Clock Mode
whismanoid 1:77f1ee332e4a 2464 isExternalClock = 0;
whismanoid 1:77f1ee332e4a 2465
whismanoid 1:77f1ee332e4a 2466 //----------------------------------------
whismanoid 1:77f1ee332e4a 2467 // update device driver global variable
whismanoid 1:77f1ee332e4a 2468 ScanMode = SCAN_0011_StandardInternalClock;
whismanoid 1:77f1ee332e4a 2469
whismanoid 1:77f1ee332e4a 2470 //----------------------------------------
whismanoid 1:77f1ee332e4a 2471 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 2472 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 2473 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 2474 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 2475 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2476 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 2477 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2478 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2479
whismanoid 1:77f1ee332e4a 2480 //----------------------------------------
whismanoid 1:77f1ee332e4a 2481 // define write-only register ADC_CONFIGURATION
whismanoid 1:77f1ee332e4a 2482 ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid 1:77f1ee332e4a 2483 const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid 1:77f1ee332e4a 2484 const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid 1:77f1ee332e4a 2485 const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid 1:77f1ee332e4a 2486 const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid 1:77f1ee332e4a 2487 const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid 1:77f1ee332e4a 2488 const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid 1:77f1ee332e4a 2489
whismanoid 1:77f1ee332e4a 2490 //----------------------------------------
whismanoid 1:77f1ee332e4a 2491 // if average, ADC CONFIGURATION register set AVG and NAVG[1:0]
whismanoid 1:77f1ee332e4a 2492 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 2493 // if average, ADC CONFIGURATION register set AVG ON BIT TO 1
whismanoid 1:77f1ee332e4a 2494 // if average, ADC CONFIGURATION register set NAVG[1:0] TO N
whismanoid 1:77f1ee332e4a 2495 if (average_0_4_8_16_32 == 4) {
whismanoid 1:77f1ee332e4a 2496 // Enable Averaging of 4 samples (AVGON=1, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 2497 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2498 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2499 ADC_CONFIGURATION |= ((0 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2500 } else if (average_0_4_8_16_32 == 8) {
whismanoid 1:77f1ee332e4a 2501 // Enable Averaging of 8 samples (AVGON=1, NAVG[1:0]=1)
whismanoid 1:77f1ee332e4a 2502 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2503 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2504 ADC_CONFIGURATION |= ((1 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2505 } else if (average_0_4_8_16_32 == 16) {
whismanoid 1:77f1ee332e4a 2506 // Enable Averaging of 16 samples (AVGON=1, NAVG[1:0]=2)
whismanoid 1:77f1ee332e4a 2507 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2508 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2509 ADC_CONFIGURATION |= ((2 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2510 } else if (average_0_4_8_16_32 == 32) {
whismanoid 1:77f1ee332e4a 2511 // Enable Averaging of 32 samples (AVGON=1, NAVG[1:0]=3)
whismanoid 1:77f1ee332e4a 2512 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2513 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2514 ADC_CONFIGURATION |= ((3 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2515 } else {
whismanoid 1:77f1ee332e4a 2516 // Disable Averaging (AVGON=0, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 2517 ADC_CONFIGURATION &= ~ (( AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2518 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2519 }
whismanoid 1:77f1ee332e4a 2520
whismanoid 1:77f1ee332e4a 2521 //----------------------------------------
whismanoid 1:77f1ee332e4a 2522 // SPI write ADC CONFIGURATION register
whismanoid 1:77f1ee332e4a 2523 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2524 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2525 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2526 SPIwrite16bits(ADC_CONFIGURATION);
whismanoid 1:77f1ee332e4a 2527 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2528
whismanoid 1:77f1ee332e4a 2529 //----------------------------------------
whismanoid 1:77f1ee332e4a 2530 // Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid 1:77f1ee332e4a 2531 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2532 ADC_MODE_CONTROL |= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2533
whismanoid 1:77f1ee332e4a 2534 //----------------------------------------
whismanoid 1:77f1ee332e4a 2535 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0011_StandardInternalClock = 3
whismanoid 1:77f1ee332e4a 2536 //~ const int SCAN_0011_StandardInternalClock = 3; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2537 ADC_MODE_CONTROL |= ((SCAN_0011_StandardInternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2538
whismanoid 1:77f1ee332e4a 2539 //----------------------------------------
whismanoid 1:77f1ee332e4a 2540 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 2541 ADC_MODE_CONTROL |= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 2542
whismanoid 1:77f1ee332e4a 2543 //----------------------------------------
whismanoid 1:77f1ee332e4a 2544 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2545 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2546
whismanoid 1:77f1ee332e4a 2547 //----------------------------------------
whismanoid 1:77f1ee332e4a 2548 // ADC MODE CONTROL register set SWCNV if CNVST pin is not used
whismanoid 1:77f1ee332e4a 2549 // ADC MODE CONTROL REGISTER SELECT THE RIGHT SWCNV BIT
whismanoid 1:77f1ee332e4a 2550 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 2551 // SWCNV=1: trigger measurement on SPI CS rising edge; CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 2552 // SWCNV=0: trigger measurement by driving CNVST pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 2553 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 2554 ADC_MODE_CONTROL |= ((swcnv_0_1 & SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 2555 } else {
whismanoid 1:77f1ee332e4a 2556 ADC_MODE_CONTROL &= ~ (( SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 2557 }
whismanoid 1:77f1ee332e4a 2558
whismanoid 1:77f1ee332e4a 2559 //----------------------------------------
whismanoid 1:77f1ee332e4a 2560 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2561 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2562 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2563 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2564 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2565 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 2566 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2567 // NOTE: Figure 7 Internal Conversions with SWCNV=1 has an error, the 17th SCLK is mislabeled as "16" should be "17".
whismanoid 1:77f1ee332e4a 2568 SPIwrite24bits(ADC_MODE_CONTROL, 0);
whismanoid 1:77f1ee332e4a 2569 } else {
whismanoid 1:77f1ee332e4a 2570 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2571 }
whismanoid 1:77f1ee332e4a 2572 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2573
whismanoid 1:77f1ee332e4a 2574 //----------------------------------------
whismanoid 1:77f1ee332e4a 2575 // return number of words to read
whismanoid 1:77f1ee332e4a 2576 return NumWords;
whismanoid 1:77f1ee332e4a 2577 }
whismanoid 1:77f1ee332e4a 2578
whismanoid 1:77f1ee332e4a 2579 //----------------------------------------
whismanoid 1:77f1ee332e4a 2580 // SCAN_0100_StandardExternalClock
whismanoid 1:77f1ee332e4a 2581 //
whismanoid 1:77f1ee332e4a 2582 // Measure ADC channels in sequence from AIN0 to channelNumber_0_15.
whismanoid 1:77f1ee332e4a 2583 // External clock mode.
whismanoid 1:77f1ee332e4a 2584 // @param[in] channelNumber_0_15: AIN Channel Number
whismanoid 1:77f1ee332e4a 2585 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 2586 // @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2587 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 6:cb7bdeb185d0 2588 // @post NumWords = number of words to be read from the FIFO
whismanoid 1:77f1ee332e4a 2589 // For external clock modes, the data format depends on CHAN_ID.
whismanoid 1:77f1ee332e4a 2590 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2591 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2592 //
whismanoid 1:77f1ee332e4a 2593 int MAX11131::ScanStandardExternalClock(void)
whismanoid 1:77f1ee332e4a 2594 {
whismanoid 1:77f1ee332e4a 2595
whismanoid 1:77f1ee332e4a 2596 //----------------------------------------
whismanoid 2:50a0cf017492 2597 // define write-only register ADC_MODE_CONTROL
whismanoid 2:50a0cf017492 2598 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 2:50a0cf017492 2599 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 2:50a0cf017492 2600 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 2:50a0cf017492 2601 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 2602 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 2:50a0cf017492 2603 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 2:50a0cf017492 2604 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 2:50a0cf017492 2605
whismanoid 2:50a0cf017492 2606 //----------------------------------------
whismanoid 2:50a0cf017492 2607 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 2608 int needFIFOreset = (isExternalClock != 1);
whismanoid 2:50a0cf017492 2609 if (needFIFOreset) {
whismanoid 2:50a0cf017492 2610 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 2611 ADC_MODE_CONTROL = ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 2612 // Send SPI configuration to device
whismanoid 2:50a0cf017492 2613 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 2:50a0cf017492 2614 SPIoutputCS(0); // drive CS low
whismanoid 2:50a0cf017492 2615 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 2:50a0cf017492 2616 SPIoutputCS(1); // drive CS high
whismanoid 2:50a0cf017492 2617 ADC_MODE_CONTROL = 0;
whismanoid 2:50a0cf017492 2618 }
whismanoid 2:50a0cf017492 2619
whismanoid 2:50a0cf017492 2620 //----------------------------------------
whismanoid 1:77f1ee332e4a 2621 // number of words to read
whismanoid 1:77f1ee332e4a 2622 NumWords = (1 + channelNumber_0_15);
whismanoid 1:77f1ee332e4a 2623
whismanoid 1:77f1ee332e4a 2624 //----------------------------------------
whismanoid 1:77f1ee332e4a 2625 // External Clock Mode
whismanoid 1:77f1ee332e4a 2626 isExternalClock = 1;
whismanoid 1:77f1ee332e4a 2627
whismanoid 1:77f1ee332e4a 2628 //----------------------------------------
whismanoid 1:77f1ee332e4a 2629 // update device driver global variable
whismanoid 1:77f1ee332e4a 2630 ScanMode = SCAN_0100_StandardExternalClock;
whismanoid 1:77f1ee332e4a 2631
whismanoid 1:77f1ee332e4a 2632 //----------------------------------------
whismanoid 1:77f1ee332e4a 2633 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0100_StandardExternalClock = 4
whismanoid 1:77f1ee332e4a 2634 //~ const int SCAN_0100_StandardExternalClock = 4; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2635 ADC_MODE_CONTROL |= ((SCAN_0100_StandardExternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2636
whismanoid 1:77f1ee332e4a 2637 //----------------------------------------
whismanoid 1:77f1ee332e4a 2638 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 2639 ADC_MODE_CONTROL |= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 2640
whismanoid 1:77f1ee332e4a 2641 //----------------------------------------
whismanoid 1:77f1ee332e4a 2642 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2643 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2644
whismanoid 1:77f1ee332e4a 2645 //----------------------------------------
whismanoid 1:77f1ee332e4a 2646 // ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid 1:77f1ee332e4a 2647 // (applicable to external clock mode only)
whismanoid 1:77f1ee332e4a 2648 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 2649 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2650 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2651 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2652 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2653 ADC_MODE_CONTROL |= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid 1:77f1ee332e4a 2654
whismanoid 1:77f1ee332e4a 2655 //----------------------------------------
whismanoid 1:77f1ee332e4a 2656 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2657 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2658 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2659 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2660 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2661 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2662
whismanoid 1:77f1ee332e4a 2663 //----------------------------------------
whismanoid 1:77f1ee332e4a 2664 // return number of words to read
whismanoid 1:77f1ee332e4a 2665 return NumWords;
whismanoid 1:77f1ee332e4a 2666 }
whismanoid 1:77f1ee332e4a 2667
whismanoid 1:77f1ee332e4a 2668 //----------------------------------------
whismanoid 1:77f1ee332e4a 2669 // SCAN_0101_UpperInternalClock
whismanoid 1:77f1ee332e4a 2670 //
whismanoid 1:77f1ee332e4a 2671 // Measure ADC channels in sequence from channelNumber_0_15 to AIN15.
whismanoid 1:77f1ee332e4a 2672 // Internal clock mode.
whismanoid 1:77f1ee332e4a 2673 // @param[in] channelNumber_0_15: AIN Channel Number
whismanoid 1:77f1ee332e4a 2674 // @param[in] average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid 1:77f1ee332e4a 2675 // average_0_4_8_16_32=0 to disable averaging.
whismanoid 1:77f1ee332e4a 2676 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 2677 // @param[in] swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2678 // SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid 1:77f1ee332e4a 2679 // Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 2680 // SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid 1:77f1ee332e4a 2681 // CS must be held low for minimum of 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2682 // CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 2683 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 6:cb7bdeb185d0 2684 // @post NumWords = number of words to be read from the FIFO
whismanoid 1:77f1ee332e4a 2685 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2686 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2687 //
whismanoid 1:77f1ee332e4a 2688 int MAX11131::ScanUpperInternalClock(void)
whismanoid 1:77f1ee332e4a 2689 {
whismanoid 1:77f1ee332e4a 2690
whismanoid 1:77f1ee332e4a 2691 //----------------------------------------
whismanoid 1:77f1ee332e4a 2692 // number of words to read
whismanoid 1:77f1ee332e4a 2693 NumWords = (16 - channelNumber_0_15);
whismanoid 1:77f1ee332e4a 2694
whismanoid 1:77f1ee332e4a 2695 //----------------------------------------
whismanoid 1:77f1ee332e4a 2696 // Internal Clock Mode
whismanoid 1:77f1ee332e4a 2697 isExternalClock = 0;
whismanoid 1:77f1ee332e4a 2698
whismanoid 1:77f1ee332e4a 2699 //----------------------------------------
whismanoid 1:77f1ee332e4a 2700 // update device driver global variable
whismanoid 1:77f1ee332e4a 2701 ScanMode = SCAN_0101_UpperInternalClock;
whismanoid 1:77f1ee332e4a 2702
whismanoid 1:77f1ee332e4a 2703 //----------------------------------------
whismanoid 1:77f1ee332e4a 2704 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 2705 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 2706 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 2707 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 2708 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2709 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 2710 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2711 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2712
whismanoid 1:77f1ee332e4a 2713 //----------------------------------------
whismanoid 1:77f1ee332e4a 2714 // define write-only register ADC_CONFIGURATION
whismanoid 1:77f1ee332e4a 2715 ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid 1:77f1ee332e4a 2716 const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid 1:77f1ee332e4a 2717 const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid 1:77f1ee332e4a 2718 const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid 1:77f1ee332e4a 2719 const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid 1:77f1ee332e4a 2720 const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid 1:77f1ee332e4a 2721 const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid 1:77f1ee332e4a 2722
whismanoid 1:77f1ee332e4a 2723 //----------------------------------------
whismanoid 1:77f1ee332e4a 2724 // if average, ADC CONFIGURATION register set AVG and NAVG[1:0]
whismanoid 1:77f1ee332e4a 2725 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 2726 // if average, ADC CONFIGURATION register set AVG ON BIT TO 1
whismanoid 1:77f1ee332e4a 2727 // if average, ADC CONFIGURATION register set NAVG[1:0] TO N
whismanoid 1:77f1ee332e4a 2728 if (average_0_4_8_16_32 == 4) {
whismanoid 1:77f1ee332e4a 2729 // Enable Averaging of 4 samples (AVGON=1, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 2730 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2731 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2732 ADC_CONFIGURATION |= ((0 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2733 } else if (average_0_4_8_16_32 == 8) {
whismanoid 1:77f1ee332e4a 2734 // Enable Averaging of 8 samples (AVGON=1, NAVG[1:0]=1)
whismanoid 1:77f1ee332e4a 2735 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2736 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2737 ADC_CONFIGURATION |= ((1 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2738 } else if (average_0_4_8_16_32 == 16) {
whismanoid 1:77f1ee332e4a 2739 // Enable Averaging of 16 samples (AVGON=1, NAVG[1:0]=2)
whismanoid 1:77f1ee332e4a 2740 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2741 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2742 ADC_CONFIGURATION |= ((2 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2743 } else if (average_0_4_8_16_32 == 32) {
whismanoid 1:77f1ee332e4a 2744 // Enable Averaging of 32 samples (AVGON=1, NAVG[1:0]=3)
whismanoid 1:77f1ee332e4a 2745 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2746 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2747 ADC_CONFIGURATION |= ((3 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2748 } else {
whismanoid 1:77f1ee332e4a 2749 // Disable Averaging (AVGON=0, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 2750 ADC_CONFIGURATION &= ~ (( AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2751 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2752 }
whismanoid 1:77f1ee332e4a 2753
whismanoid 1:77f1ee332e4a 2754 //----------------------------------------
whismanoid 1:77f1ee332e4a 2755 // SPI write ADC CONFIGURATION register
whismanoid 1:77f1ee332e4a 2756 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2757 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2758 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2759 SPIwrite16bits(ADC_CONFIGURATION);
whismanoid 1:77f1ee332e4a 2760 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2761
whismanoid 1:77f1ee332e4a 2762 //----------------------------------------
whismanoid 1:77f1ee332e4a 2763 // Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid 1:77f1ee332e4a 2764 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2765 ADC_MODE_CONTROL |= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2766
whismanoid 1:77f1ee332e4a 2767 //----------------------------------------
whismanoid 1:77f1ee332e4a 2768 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0101_UpperInternalClock = 5
whismanoid 1:77f1ee332e4a 2769 //~ const int SCAN_0101_UpperInternalClock = 5; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2770 ADC_MODE_CONTROL |= ((SCAN_0101_UpperInternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2771
whismanoid 1:77f1ee332e4a 2772 //----------------------------------------
whismanoid 1:77f1ee332e4a 2773 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 2774 ADC_MODE_CONTROL |= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 2775
whismanoid 1:77f1ee332e4a 2776 //----------------------------------------
whismanoid 1:77f1ee332e4a 2777 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2778 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2779
whismanoid 1:77f1ee332e4a 2780 //----------------------------------------
whismanoid 1:77f1ee332e4a 2781 // ADC MODE CONTROL register set SWCNV if CNVST pin is not used
whismanoid 1:77f1ee332e4a 2782 // ADC MODE CONTROL REGISTER SELECT THE RIGHT SWCNV BIT
whismanoid 1:77f1ee332e4a 2783 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 2784 // SWCNV=1: trigger measurement on SPI CS rising edge; CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 2785 // SWCNV=0: trigger measurement by driving CNVST pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 2786 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 2787 ADC_MODE_CONTROL |= ((swcnv_0_1 & SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 2788 } else {
whismanoid 1:77f1ee332e4a 2789 ADC_MODE_CONTROL &= ~ (( SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 2790 }
whismanoid 1:77f1ee332e4a 2791
whismanoid 1:77f1ee332e4a 2792 //----------------------------------------
whismanoid 1:77f1ee332e4a 2793 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2794 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2795 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2796 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2797 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2798 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 2799 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2800 // NOTE: Figure 7 Internal Conversions with SWCNV=1 has an error, the 17th SCLK is mislabeled as "16" should be "17".
whismanoid 1:77f1ee332e4a 2801 SPIwrite24bits(ADC_MODE_CONTROL, 0);
whismanoid 1:77f1ee332e4a 2802 } else {
whismanoid 1:77f1ee332e4a 2803 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2804 }
whismanoid 1:77f1ee332e4a 2805 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2806
whismanoid 1:77f1ee332e4a 2807 //----------------------------------------
whismanoid 1:77f1ee332e4a 2808 // return number of words to read
whismanoid 1:77f1ee332e4a 2809 return NumWords;
whismanoid 1:77f1ee332e4a 2810 }
whismanoid 1:77f1ee332e4a 2811
whismanoid 1:77f1ee332e4a 2812 //----------------------------------------
whismanoid 1:77f1ee332e4a 2813 // SCAN_0110_UpperExternalClock
whismanoid 1:77f1ee332e4a 2814 //
whismanoid 1:77f1ee332e4a 2815 // Measure ADC channels in sequence from channelNumber_0_15 to AIN15.
whismanoid 1:77f1ee332e4a 2816 // External clock mode.
whismanoid 1:77f1ee332e4a 2817 // @param[in] channelNumber_0_15: AIN Channel Number
whismanoid 1:77f1ee332e4a 2818 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 2819 // @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2820 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 6:cb7bdeb185d0 2821 // @post NumWords = number of words to be read from the FIFO
whismanoid 1:77f1ee332e4a 2822 // For external clock modes, the data format depends on CHAN_ID.
whismanoid 1:77f1ee332e4a 2823 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2824 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2825 //
whismanoid 1:77f1ee332e4a 2826 int MAX11131::ScanUpperExternalClock(void)
whismanoid 1:77f1ee332e4a 2827 {
whismanoid 1:77f1ee332e4a 2828
whismanoid 1:77f1ee332e4a 2829 //----------------------------------------
whismanoid 2:50a0cf017492 2830 // define write-only register ADC_MODE_CONTROL
whismanoid 2:50a0cf017492 2831 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 2:50a0cf017492 2832 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 2:50a0cf017492 2833 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 2:50a0cf017492 2834 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 2835 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 2:50a0cf017492 2836 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 2:50a0cf017492 2837 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 2:50a0cf017492 2838
whismanoid 2:50a0cf017492 2839 //----------------------------------------
whismanoid 2:50a0cf017492 2840 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 2841 int needFIFOreset = (isExternalClock != 1);
whismanoid 2:50a0cf017492 2842 if (needFIFOreset) {
whismanoid 2:50a0cf017492 2843 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 2844 ADC_MODE_CONTROL = ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 2845 // Send SPI configuration to device
whismanoid 2:50a0cf017492 2846 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 2:50a0cf017492 2847 SPIoutputCS(0); // drive CS low
whismanoid 2:50a0cf017492 2848 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 2:50a0cf017492 2849 SPIoutputCS(1); // drive CS high
whismanoid 2:50a0cf017492 2850 ADC_MODE_CONTROL = 0;
whismanoid 2:50a0cf017492 2851 }
whismanoid 2:50a0cf017492 2852
whismanoid 2:50a0cf017492 2853 //----------------------------------------
whismanoid 1:77f1ee332e4a 2854 // number of words to read
whismanoid 1:77f1ee332e4a 2855 NumWords = (16 - channelNumber_0_15);
whismanoid 1:77f1ee332e4a 2856
whismanoid 1:77f1ee332e4a 2857 //----------------------------------------
whismanoid 1:77f1ee332e4a 2858 // External Clock Mode
whismanoid 1:77f1ee332e4a 2859 isExternalClock = 1;
whismanoid 1:77f1ee332e4a 2860
whismanoid 1:77f1ee332e4a 2861 //----------------------------------------
whismanoid 1:77f1ee332e4a 2862 // update device driver global variable
whismanoid 1:77f1ee332e4a 2863 ScanMode = SCAN_0110_UpperExternalClock;
whismanoid 1:77f1ee332e4a 2864
whismanoid 1:77f1ee332e4a 2865 //----------------------------------------
whismanoid 1:77f1ee332e4a 2866 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0110_UpperExternalClock = 6
whismanoid 1:77f1ee332e4a 2867 //~ const int SCAN_0110_UpperExternalClock = 6; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2868 ADC_MODE_CONTROL |= ((SCAN_0110_UpperExternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2869
whismanoid 1:77f1ee332e4a 2870 //----------------------------------------
whismanoid 1:77f1ee332e4a 2871 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 2872 ADC_MODE_CONTROL |= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 2873
whismanoid 1:77f1ee332e4a 2874 //----------------------------------------
whismanoid 1:77f1ee332e4a 2875 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2876 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2877
whismanoid 1:77f1ee332e4a 2878 //----------------------------------------
whismanoid 1:77f1ee332e4a 2879 // ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid 1:77f1ee332e4a 2880 // (applicable to external clock mode only)
whismanoid 1:77f1ee332e4a 2881 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 2882 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2883 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2884 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2885 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2886 ADC_MODE_CONTROL |= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid 1:77f1ee332e4a 2887
whismanoid 1:77f1ee332e4a 2888 //----------------------------------------
whismanoid 1:77f1ee332e4a 2889 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2890 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2891 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2892 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2893 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2894 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2895
whismanoid 1:77f1ee332e4a 2896 //----------------------------------------
whismanoid 1:77f1ee332e4a 2897 // return number of words to read
whismanoid 1:77f1ee332e4a 2898 return NumWords;
whismanoid 1:77f1ee332e4a 2899 }
whismanoid 1:77f1ee332e4a 2900
whismanoid 1:77f1ee332e4a 2901 //----------------------------------------
whismanoid 1:77f1ee332e4a 2902 // SCAN_0111_CustomInternalClock
whismanoid 1:77f1ee332e4a 2903 //
whismanoid 1:77f1ee332e4a 2904 // Measure selected ADC channels in sequence from AIN0 to AIN15,
whismanoid 1:77f1ee332e4a 2905 // using only the channels enabled by enabledChannelsMask.
whismanoid 1:77f1ee332e4a 2906 // Bit 0x0001 enables AIN0.
whismanoid 1:77f1ee332e4a 2907 // Bit 0x0002 enables AIN1.
whismanoid 1:77f1ee332e4a 2908 // Bit 0x0004 enables AIN2.
whismanoid 1:77f1ee332e4a 2909 // Bit 0x0008 enables AIN3.
whismanoid 1:77f1ee332e4a 2910 // Bit 0x0010 enables AIN4.
whismanoid 1:77f1ee332e4a 2911 // Bit 0x0020 enables AIN5.
whismanoid 1:77f1ee332e4a 2912 // Bit 0x0040 enables AIN6.
whismanoid 1:77f1ee332e4a 2913 // Bit 0x0080 enables AIN7.
whismanoid 1:77f1ee332e4a 2914 // Bit 0x0100 enables AIN8.
whismanoid 1:77f1ee332e4a 2915 // Bit 0x0200 enables AIN9.
whismanoid 1:77f1ee332e4a 2916 // Bit 0x0400 enables AIN10.
whismanoid 1:77f1ee332e4a 2917 // Bit 0x0800 enables AIN11.
whismanoid 1:77f1ee332e4a 2918 // Bit 0x1000 enables AIN12.
whismanoid 1:77f1ee332e4a 2919 // Bit 0x2000 enables AIN13.
whismanoid 1:77f1ee332e4a 2920 // Bit 0x4000 enables AIN14.
whismanoid 1:77f1ee332e4a 2921 // Bit 0x8000 enables AIN15.
whismanoid 1:77f1ee332e4a 2922 // Internal clock mode.
whismanoid 1:77f1ee332e4a 2923 // @param[in] enabledChannelsMask: Bitmap of AIN Channels to scan.
whismanoid 1:77f1ee332e4a 2924 // @param[in] average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid 1:77f1ee332e4a 2925 // average_0_4_8_16_32=0 to disable averaging.
whismanoid 1:77f1ee332e4a 2926 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 2927 // @param[in] swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2928 // SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid 1:77f1ee332e4a 2929 // Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 2930 // SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid 1:77f1ee332e4a 2931 // CS must be held low for minimum of 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2932 // CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 2933 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 6:cb7bdeb185d0 2934 // @post NumWords = number of words to be read from the FIFO
whismanoid 1:77f1ee332e4a 2935 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2936 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2937 //
whismanoid 1:77f1ee332e4a 2938 int MAX11131::ScanCustomInternalClock(void)
whismanoid 1:77f1ee332e4a 2939 {
whismanoid 1:77f1ee332e4a 2940
whismanoid 1:77f1ee332e4a 2941 //----------------------------------------
whismanoid 1:77f1ee332e4a 2942 // count nWords = number of set bits in enabledChannelsMask
whismanoid 1:77f1ee332e4a 2943 uint16_t bitMask;
whismanoid 1:77f1ee332e4a 2944 int nWords = 0;
whismanoid 1:77f1ee332e4a 2945 for (bitMask = 0x8000; bitMask != 0; bitMask = bitMask / 2)
whismanoid 1:77f1ee332e4a 2946 {
whismanoid 1:77f1ee332e4a 2947 if (enabledChannelsMask & bitMask)
whismanoid 1:77f1ee332e4a 2948 {
whismanoid 1:77f1ee332e4a 2949 nWords++;
whismanoid 1:77f1ee332e4a 2950 }
whismanoid 1:77f1ee332e4a 2951 }
whismanoid 1:77f1ee332e4a 2952
whismanoid 1:77f1ee332e4a 2953 //----------------------------------------
whismanoid 1:77f1ee332e4a 2954 // number of words to read
whismanoid 1:77f1ee332e4a 2955 NumWords = nWords;
whismanoid 1:77f1ee332e4a 2956
whismanoid 1:77f1ee332e4a 2957 //----------------------------------------
whismanoid 1:77f1ee332e4a 2958 // Internal Clock Mode
whismanoid 1:77f1ee332e4a 2959 isExternalClock = 0;
whismanoid 1:77f1ee332e4a 2960
whismanoid 1:77f1ee332e4a 2961 //----------------------------------------
whismanoid 1:77f1ee332e4a 2962 // update device driver global variable
whismanoid 1:77f1ee332e4a 2963 ScanMode = SCAN_0111_CustomInternalClock;
whismanoid 1:77f1ee332e4a 2964
whismanoid 1:77f1ee332e4a 2965 //----------------------------------------
whismanoid 1:77f1ee332e4a 2966 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 2967 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 2968 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 2969 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 2970 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2971 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 2972 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2973 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2974
whismanoid 1:77f1ee332e4a 2975 //----------------------------------------
whismanoid 1:77f1ee332e4a 2976 // define write-only register ADC_CONFIGURATION
whismanoid 1:77f1ee332e4a 2977 ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid 1:77f1ee332e4a 2978 const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid 1:77f1ee332e4a 2979 const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid 1:77f1ee332e4a 2980 const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid 1:77f1ee332e4a 2981 const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid 1:77f1ee332e4a 2982 const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid 1:77f1ee332e4a 2983 const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid 1:77f1ee332e4a 2984
whismanoid 1:77f1ee332e4a 2985 //----------------------------------------
whismanoid 1:77f1ee332e4a 2986 // define write-only registers CSCAN0,CSCAN1
whismanoid 1:77f1ee332e4a 2987 CSCAN0 = 0xA000; //!< mosiData16 0xA000..0xA7FF format: 1 0 1 0 0 CHSCAN15 CHSCAN14 CHSCAN13 CHSCAN12 CHSCAN11 CHSCAN10 CHSCAN9 CHSCAN8 x x x
whismanoid 1:77f1ee332e4a 2988 const int CHSCAN15_LSB = 10; // CSCAN0.CHSCAN15
whismanoid 1:77f1ee332e4a 2989 const int CHSCAN14_LSB = 9; // CSCAN0.CHSCAN14
whismanoid 1:77f1ee332e4a 2990 const int CHSCAN13_LSB = 8; // CSCAN0.CHSCAN13
whismanoid 1:77f1ee332e4a 2991 const int CHSCAN12_LSB = 7; // CSCAN0.CHSCAN12
whismanoid 1:77f1ee332e4a 2992 const int CHSCAN11_LSB = 6; // CSCAN0.CHSCAN11
whismanoid 1:77f1ee332e4a 2993 const int CHSCAN10_LSB = 5; // CSCAN0.CHSCAN10
whismanoid 1:77f1ee332e4a 2994 const int CHSCAN9_LSB = 4; // CSCAN0.CHSCAN9
whismanoid 1:77f1ee332e4a 2995 const int CHSCAN8_LSB = 3; // CSCAN0.CHSCAN8
whismanoid 1:77f1ee332e4a 2996 CSCAN1 = 0xA800; //!< mosiData16 0xA800..0xAFFF format: 1 0 1 0 1 CHSCAN7 CHSCAN6 CHSCAN5 CHSCAN4 CHSCAN3 CHSCAN2 CHSCAN1 CHSCAN0 x x x
whismanoid 1:77f1ee332e4a 2997 const int CHSCAN7_LSB = 10; // CSCAN1.CHSCAN7
whismanoid 1:77f1ee332e4a 2998 const int CHSCAN6_LSB = 9; // CSCAN1.CHSCAN6
whismanoid 1:77f1ee332e4a 2999 const int CHSCAN5_LSB = 8; // CSCAN1.CHSCAN5
whismanoid 1:77f1ee332e4a 3000 const int CHSCAN4_LSB = 7; // CSCAN1.CHSCAN4
whismanoid 1:77f1ee332e4a 3001 const int CHSCAN3_LSB = 6; // CSCAN1.CHSCAN3
whismanoid 1:77f1ee332e4a 3002 const int CHSCAN2_LSB = 5; // CSCAN1.CHSCAN2
whismanoid 1:77f1ee332e4a 3003 const int CHSCAN1_LSB = 4; // CSCAN1.CHSCAN1
whismanoid 1:77f1ee332e4a 3004 const int CHSCAN0_LSB = 3; // CSCAN1.CHSCAN0
whismanoid 1:77f1ee332e4a 3005
whismanoid 1:77f1ee332e4a 3006 //----------------------------------------
whismanoid 1:77f1ee332e4a 3007 // if average, ADC CONFIGURATION register set AVG and NAVG[1:0]
whismanoid 1:77f1ee332e4a 3008 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 3009 // if average, ADC CONFIGURATION register set AVG ON BIT TO 1
whismanoid 1:77f1ee332e4a 3010 // if average, ADC CONFIGURATION register set NAVG[1:0] TO N
whismanoid 1:77f1ee332e4a 3011 if (average_0_4_8_16_32 == 4) {
whismanoid 1:77f1ee332e4a 3012 // Enable Averaging of 4 samples (AVGON=1, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 3013 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 3014 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 3015 ADC_CONFIGURATION |= ((0 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 3016 } else if (average_0_4_8_16_32 == 8) {
whismanoid 1:77f1ee332e4a 3017 // Enable Averaging of 8 samples (AVGON=1, NAVG[1:0]=1)
whismanoid 1:77f1ee332e4a 3018 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 3019 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 3020 ADC_CONFIGURATION |= ((1 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 3021 } else if (average_0_4_8_16_32 == 16) {
whismanoid 1:77f1ee332e4a 3022 // Enable Averaging of 16 samples (AVGON=1, NAVG[1:0]=2)
whismanoid 1:77f1ee332e4a 3023 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 3024 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 3025 ADC_CONFIGURATION |= ((2 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 3026 } else if (average_0_4_8_16_32 == 32) {
whismanoid 1:77f1ee332e4a 3027 // Enable Averaging of 32 samples (AVGON=1, NAVG[1:0]=3)
whismanoid 1:77f1ee332e4a 3028 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 3029 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 3030 ADC_CONFIGURATION |= ((3 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 3031 } else {
whismanoid 1:77f1ee332e4a 3032 // Disable Averaging (AVGON=0, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 3033 ADC_CONFIGURATION &= ~ (( AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 3034 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 3035 }
whismanoid 1:77f1ee332e4a 3036
whismanoid 1:77f1ee332e4a 3037 //----------------------------------------
whismanoid 1:77f1ee332e4a 3038 // SPI write ADC CONFIGURATION register
whismanoid 1:77f1ee332e4a 3039 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 3040 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 3041 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 3042 SPIwrite16bits(ADC_CONFIGURATION);
whismanoid 1:77f1ee332e4a 3043 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 3044
whismanoid 1:77f1ee332e4a 3045 //----------------------------------------
whismanoid 1:77f1ee332e4a 3046 // SET CSCAN0 CSCAN1 REGISTERS from enabledChannelsMask
whismanoid 1:77f1ee332e4a 3047 CSCAN0 = 0xA000 | (((enabledChannelsMask >> 8) & 0xFF) << 3); // CSCAN0.CHSCAN[15:8]
whismanoid 1:77f1ee332e4a 3048 CSCAN1 = 0xA800 | (((enabledChannelsMask) & 0xFF) << 3); // CSCAN1.CHSCAN[7:0]
whismanoid 1:77f1ee332e4a 3049 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 3050 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 3051 SPIwrite16bits(CSCAN0);
whismanoid 1:77f1ee332e4a 3052 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 3053 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 3054 SPIwrite16bits(CSCAN1);
whismanoid 1:77f1ee332e4a 3055 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 3056
whismanoid 1:77f1ee332e4a 3057 //----------------------------------------
whismanoid 1:77f1ee332e4a 3058 // Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid 1:77f1ee332e4a 3059 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 3060 ADC_MODE_CONTROL |= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 3061
whismanoid 1:77f1ee332e4a 3062 //----------------------------------------
whismanoid 1:77f1ee332e4a 3063 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0111_CustomInternalClock = 7
whismanoid 1:77f1ee332e4a 3064 //~ const int SCAN_0111_CustomInternalClock = 7; // replaced local const with enum
whismanoid 1:77f1ee332e4a 3065 ADC_MODE_CONTROL |= ((SCAN_0111_CustomInternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 3066
whismanoid 1:77f1ee332e4a 3067 //----------------------------------------
whismanoid 1:77f1ee332e4a 3068 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 3069 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 3070
whismanoid 1:77f1ee332e4a 3071 //----------------------------------------
whismanoid 1:77f1ee332e4a 3072 // ADC MODE CONTROL register set SWCNV if CNVST pin is not used
whismanoid 1:77f1ee332e4a 3073 // ADC MODE CONTROL REGISTER SELECT THE RIGHT SWCNV BIT
whismanoid 1:77f1ee332e4a 3074 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 3075 // SWCNV=1: trigger measurement on SPI CS rising edge; CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 3076 // SWCNV=0: trigger measurement by driving CNVST pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 3077 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 3078 ADC_MODE_CONTROL |= ((swcnv_0_1 & SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 3079 } else {
whismanoid 1:77f1ee332e4a 3080 ADC_MODE_CONTROL &= ~ (( SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 3081 }
whismanoid 1:77f1ee332e4a 3082
whismanoid 1:77f1ee332e4a 3083 //----------------------------------------
whismanoid 1:77f1ee332e4a 3084 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 3085 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 3086 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 3087 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 3088 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 3089 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 3090 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 3091 // NOTE: Figure 7 Internal Conversions with SWCNV=1 has an error, the 17th SCLK is mislabeled as "16" should be "17".
whismanoid 1:77f1ee332e4a 3092 SPIwrite24bits(ADC_MODE_CONTROL, 0);
whismanoid 1:77f1ee332e4a 3093 } else {
whismanoid 1:77f1ee332e4a 3094 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 3095 }
whismanoid 1:77f1ee332e4a 3096 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 3097
whismanoid 1:77f1ee332e4a 3098 //----------------------------------------
whismanoid 1:77f1ee332e4a 3099 // return number of words to read
whismanoid 1:77f1ee332e4a 3100 return NumWords;
whismanoid 1:77f1ee332e4a 3101 }
whismanoid 1:77f1ee332e4a 3102
whismanoid 1:77f1ee332e4a 3103 //----------------------------------------
whismanoid 1:77f1ee332e4a 3104 // SCAN_1000_CustomExternalClock
whismanoid 1:77f1ee332e4a 3105 //
whismanoid 1:77f1ee332e4a 3106 // Measure selected ADC channels in sequence from AIN0 to AIN15,
whismanoid 1:77f1ee332e4a 3107 // using only the channels enabled by enabledChannelsMask.
whismanoid 1:77f1ee332e4a 3108 // Bit 0x0001 enables AIN0.
whismanoid 1:77f1ee332e4a 3109 // Bit 0x0002 enables AIN1.
whismanoid 1:77f1ee332e4a 3110 // Bit 0x0004 enables AIN2.
whismanoid 1:77f1ee332e4a 3111 // Bit 0x0008 enables AIN3.
whismanoid 1:77f1ee332e4a 3112 // Bit 0x0010 enables AIN4.
whismanoid 1:77f1ee332e4a 3113 // Bit 0x0020 enables AIN5.
whismanoid 1:77f1ee332e4a 3114 // Bit 0x0040 enables AIN6.
whismanoid 1:77f1ee332e4a 3115 // Bit 0x0080 enables AIN7.
whismanoid 1:77f1ee332e4a 3116 // Bit 0x0100 enables AIN8.
whismanoid 1:77f1ee332e4a 3117 // Bit 0x0200 enables AIN9.
whismanoid 1:77f1ee332e4a 3118 // Bit 0x0400 enables AIN10.
whismanoid 1:77f1ee332e4a 3119 // Bit 0x0800 enables AIN11.
whismanoid 1:77f1ee332e4a 3120 // Bit 0x1000 enables AIN12.
whismanoid 1:77f1ee332e4a 3121 // Bit 0x2000 enables AIN13.
whismanoid 1:77f1ee332e4a 3122 // Bit 0x4000 enables AIN14.
whismanoid 1:77f1ee332e4a 3123 // Bit 0x8000 enables AIN15.
whismanoid 1:77f1ee332e4a 3124 // External clock mode.
whismanoid 1:77f1ee332e4a 3125 // @param[in] enabledChannelsMask: Bitmap of AIN Channels to scan.
whismanoid 1:77f1ee332e4a 3126 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 3127 // @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 3128 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 6:cb7bdeb185d0 3129 // @post NumWords = number of words to be read from the FIFO
whismanoid 1:77f1ee332e4a 3130 // For external clock modes, the data format depends on CHAN_ID.
whismanoid 1:77f1ee332e4a 3131 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 3132 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 3133 //
whismanoid 1:77f1ee332e4a 3134 int MAX11131::ScanCustomExternalClock(void)
whismanoid 1:77f1ee332e4a 3135 {
whismanoid 1:77f1ee332e4a 3136
whismanoid 1:77f1ee332e4a 3137 //----------------------------------------
whismanoid 1:77f1ee332e4a 3138 // count nWords = number of set bits in enabledChannelsMask
whismanoid 1:77f1ee332e4a 3139 uint16_t bitMask;
whismanoid 1:77f1ee332e4a 3140 int nWords = 0;
whismanoid 1:77f1ee332e4a 3141 for (bitMask = 0x8000; bitMask != 0; bitMask = bitMask / 2)
whismanoid 1:77f1ee332e4a 3142 {
whismanoid 1:77f1ee332e4a 3143 if (enabledChannelsMask & bitMask)
whismanoid 1:77f1ee332e4a 3144 {
whismanoid 1:77f1ee332e4a 3145 nWords++;
whismanoid 1:77f1ee332e4a 3146 }
whismanoid 1:77f1ee332e4a 3147 }
whismanoid 1:77f1ee332e4a 3148
whismanoid 1:77f1ee332e4a 3149 //----------------------------------------
whismanoid 2:50a0cf017492 3150 // define write-only register ADC_MODE_CONTROL
whismanoid 2:50a0cf017492 3151 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 2:50a0cf017492 3152 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 2:50a0cf017492 3153 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 2:50a0cf017492 3154 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 3155 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 2:50a0cf017492 3156 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 2:50a0cf017492 3157 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 2:50a0cf017492 3158
whismanoid 2:50a0cf017492 3159 //----------------------------------------
whismanoid 2:50a0cf017492 3160 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 3161 int needFIFOreset = (isExternalClock != 1);
whismanoid 2:50a0cf017492 3162 if (needFIFOreset) {
whismanoid 2:50a0cf017492 3163 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 3164 ADC_MODE_CONTROL = ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 3165 // Send SPI configuration to device
whismanoid 2:50a0cf017492 3166 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 2:50a0cf017492 3167 SPIoutputCS(0); // drive CS low
whismanoid 2:50a0cf017492 3168 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 2:50a0cf017492 3169 SPIoutputCS(1); // drive CS high
whismanoid 2:50a0cf017492 3170 ADC_MODE_CONTROL = 0;
whismanoid 2:50a0cf017492 3171 }
whismanoid 2:50a0cf017492 3172
whismanoid 2:50a0cf017492 3173 //----------------------------------------
whismanoid 1:77f1ee332e4a 3174 // number of words to read
whismanoid 1:77f1ee332e4a 3175 NumWords = nWords;
whismanoid 1:77f1ee332e4a 3176
whismanoid 1:77f1ee332e4a 3177 //----------------------------------------
whismanoid 1:77f1ee332e4a 3178 // External Clock Mode
whismanoid 1:77f1ee332e4a 3179 isExternalClock = 1;
whismanoid 1:77f1ee332e4a 3180
whismanoid 1:77f1ee332e4a 3181 //----------------------------------------
whismanoid 1:77f1ee332e4a 3182 // update device driver global variable
whismanoid 1:77f1ee332e4a 3183 ScanMode = SCAN_1000_CustomExternalClock;
whismanoid 1:77f1ee332e4a 3184
whismanoid 1:77f1ee332e4a 3185 //----------------------------------------
whismanoid 1:77f1ee332e4a 3186 // define write-only registers CSCAN0,CSCAN1
whismanoid 1:77f1ee332e4a 3187 CSCAN0 = 0xA000; //!< mosiData16 0xA000..0xA7FF format: 1 0 1 0 0 CHSCAN15 CHSCAN14 CHSCAN13 CHSCAN12 CHSCAN11 CHSCAN10 CHSCAN9 CHSCAN8 x x x
whismanoid 1:77f1ee332e4a 3188 const int CHSCAN15_LSB = 10; // CSCAN0.CHSCAN15
whismanoid 1:77f1ee332e4a 3189 const int CHSCAN14_LSB = 9; // CSCAN0.CHSCAN14
whismanoid 1:77f1ee332e4a 3190 const int CHSCAN13_LSB = 8; // CSCAN0.CHSCAN13
whismanoid 1:77f1ee332e4a 3191 const int CHSCAN12_LSB = 7; // CSCAN0.CHSCAN12
whismanoid 1:77f1ee332e4a 3192 const int CHSCAN11_LSB = 6; // CSCAN0.CHSCAN11
whismanoid 1:77f1ee332e4a 3193 const int CHSCAN10_LSB = 5; // CSCAN0.CHSCAN10
whismanoid 1:77f1ee332e4a 3194 const int CHSCAN9_LSB = 4; // CSCAN0.CHSCAN9
whismanoid 1:77f1ee332e4a 3195 const int CHSCAN8_LSB = 3; // CSCAN0.CHSCAN8
whismanoid 1:77f1ee332e4a 3196 CSCAN1 = 0xA800; //!< mosiData16 0xA800..0xAFFF format: 1 0 1 0 1 CHSCAN7 CHSCAN6 CHSCAN5 CHSCAN4 CHSCAN3 CHSCAN2 CHSCAN1 CHSCAN0 x x x
whismanoid 1:77f1ee332e4a 3197 const int CHSCAN7_LSB = 10; // CSCAN1.CHSCAN7
whismanoid 1:77f1ee332e4a 3198 const int CHSCAN6_LSB = 9; // CSCAN1.CHSCAN6
whismanoid 1:77f1ee332e4a 3199 const int CHSCAN5_LSB = 8; // CSCAN1.CHSCAN5
whismanoid 1:77f1ee332e4a 3200 const int CHSCAN4_LSB = 7; // CSCAN1.CHSCAN4
whismanoid 1:77f1ee332e4a 3201 const int CHSCAN3_LSB = 6; // CSCAN1.CHSCAN3
whismanoid 1:77f1ee332e4a 3202 const int CHSCAN2_LSB = 5; // CSCAN1.CHSCAN2
whismanoid 1:77f1ee332e4a 3203 const int CHSCAN1_LSB = 4; // CSCAN1.CHSCAN1
whismanoid 1:77f1ee332e4a 3204 const int CHSCAN0_LSB = 3; // CSCAN1.CHSCAN0
whismanoid 1:77f1ee332e4a 3205
whismanoid 1:77f1ee332e4a 3206 //----------------------------------------
whismanoid 1:77f1ee332e4a 3207 // SET CSCAN0 CSCAN1 REGISTERS from enabledChannelsMask
whismanoid 1:77f1ee332e4a 3208 CSCAN0 = 0xA000 | (((enabledChannelsMask >> 8) & 0xFF) << 3); // CSCAN0.CHSCAN[15:8]
whismanoid 1:77f1ee332e4a 3209 CSCAN1 = 0xA800 | (((enabledChannelsMask) & 0xFF) << 3); // CSCAN1.CHSCAN[7:0]
whismanoid 1:77f1ee332e4a 3210 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 3211 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 3212 SPIwrite16bits(CSCAN0);
whismanoid 1:77f1ee332e4a 3213 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 3214 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 3215 SPIwrite16bits(CSCAN1);
whismanoid 1:77f1ee332e4a 3216 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 3217
whismanoid 1:77f1ee332e4a 3218 //----------------------------------------
whismanoid 1:77f1ee332e4a 3219 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_1000_CustomExternalClock = 8
whismanoid 1:77f1ee332e4a 3220 //~ const int SCAN_1000_CustomExternalClock = 8; // replaced local const with enum
whismanoid 1:77f1ee332e4a 3221 ADC_MODE_CONTROL |= ((SCAN_1000_CustomExternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 3222
whismanoid 1:77f1ee332e4a 3223 //----------------------------------------
whismanoid 1:77f1ee332e4a 3224 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 3225 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 3226
whismanoid 1:77f1ee332e4a 3227 //----------------------------------------
whismanoid 1:77f1ee332e4a 3228 // ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid 1:77f1ee332e4a 3229 // (applicable to external clock mode only)
whismanoid 1:77f1ee332e4a 3230 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 3231 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 3232 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 3233 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 3234 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 3235 ADC_MODE_CONTROL |= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid 1:77f1ee332e4a 3236
whismanoid 1:77f1ee332e4a 3237 //----------------------------------------
whismanoid 1:77f1ee332e4a 3238 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 3239 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 3240 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 3241 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 3242 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 3243 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 3244
whismanoid 1:77f1ee332e4a 3245 //----------------------------------------
whismanoid 1:77f1ee332e4a 3246 // return number of words to read
whismanoid 1:77f1ee332e4a 3247 return NumWords;
whismanoid 1:77f1ee332e4a 3248 }
whismanoid 1:77f1ee332e4a 3249
whismanoid 1:77f1ee332e4a 3250 //----------------------------------------
whismanoid 1:77f1ee332e4a 3251 // SCAN_1001_SampleSetExternalClock
whismanoid 1:77f1ee332e4a 3252 //
whismanoid 1:77f1ee332e4a 3253 // Measure ADC channels in an arbitrary pattern.
whismanoid 1:77f1ee332e4a 3254 // Channels can be visited in any order, with repetition allowed.
whismanoid 1:77f1ee332e4a 3255 // External clock mode.
whismanoid 1:77f1ee332e4a 3256 // @pre enabledChannelsPatternLength_1_256: number of channel selections
whismanoid 1:77f1ee332e4a 3257 // @pre enabledChannelsPattern: array containing channel selection pattern
whismanoid 1:77f1ee332e4a 3258 // In the array, one channel select per byte.
whismanoid 1:77f1ee332e4a 3259 // In the SPI interface, immediately after SAMPLESET register is written,
whismanoid 1:77f1ee332e4a 3260 // each byte encodes two channelNumber selections.
whismanoid 1:77f1ee332e4a 3261 // The high 4 bits encode the first channelNumber.
whismanoid 1:77f1ee332e4a 3262 // (((enabledChannelsPattern[0]) & 0x0F) << 4) | ((enabledChannelsPattern[1]) & 0x0F)
whismanoid 1:77f1ee332e4a 3263 // If it is an odd number of channels, additional nybbles will be ignored.
whismanoid 1:77f1ee332e4a 3264 // CS will be asserted low during the entire SAMPLESET pattern selection.
whismanoid 6:cb7bdeb185d0 3265 // @param[in] enabledChannelsPattern: array of channel select, one channel per byte
whismanoid 1:77f1ee332e4a 3266 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 3267 // @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 3268 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 6:cb7bdeb185d0 3269 // @post NumWords = number of words to be read from the FIFO
whismanoid 1:77f1ee332e4a 3270 // For external clock modes, the data format depends on CHAN_ID.
whismanoid 1:77f1ee332e4a 3271 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 3272 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 3273 //
whismanoid 1:77f1ee332e4a 3274 int MAX11131::ScanSampleSetExternalClock(void)
whismanoid 1:77f1ee332e4a 3275 {
whismanoid 1:77f1ee332e4a 3276
whismanoid 1:77f1ee332e4a 3277 //----------------------------------------
whismanoid 2:50a0cf017492 3278 // define write-only register ADC_MODE_CONTROL
whismanoid 2:50a0cf017492 3279 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 2:50a0cf017492 3280 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 2:50a0cf017492 3281 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 2:50a0cf017492 3282 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 3283 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 2:50a0cf017492 3284 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 2:50a0cf017492 3285 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 2:50a0cf017492 3286
whismanoid 2:50a0cf017492 3287 //----------------------------------------
whismanoid 2:50a0cf017492 3288 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 3289 int needFIFOreset = (isExternalClock != 1);
whismanoid 2:50a0cf017492 3290 if (needFIFOreset) {
whismanoid 2:50a0cf017492 3291 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 3292 ADC_MODE_CONTROL = ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 3293 // Send SPI configuration to device
whismanoid 2:50a0cf017492 3294 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 2:50a0cf017492 3295 SPIoutputCS(0); // drive CS low
whismanoid 2:50a0cf017492 3296 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 2:50a0cf017492 3297 SPIoutputCS(1); // drive CS high
whismanoid 2:50a0cf017492 3298 ADC_MODE_CONTROL = 0;
whismanoid 2:50a0cf017492 3299 }
whismanoid 2:50a0cf017492 3300
whismanoid 2:50a0cf017492 3301 //----------------------------------------
whismanoid 1:77f1ee332e4a 3302 // number of words to read
whismanoid 1:77f1ee332e4a 3303 NumWords = ((enabledChannelsPatternLength_1_256 != 0) ? enabledChannelsPatternLength_1_256 : 256 );
whismanoid 1:77f1ee332e4a 3304
whismanoid 1:77f1ee332e4a 3305 //----------------------------------------
whismanoid 1:77f1ee332e4a 3306 // External Clock Mode
whismanoid 1:77f1ee332e4a 3307 isExternalClock = 1;
whismanoid 1:77f1ee332e4a 3308
whismanoid 1:77f1ee332e4a 3309 //----------------------------------------
whismanoid 1:77f1ee332e4a 3310 // update device driver global variable
whismanoid 1:77f1ee332e4a 3311 ScanMode = SCAN_1001_SampleSetExternalClock;
whismanoid 1:77f1ee332e4a 3312
whismanoid 1:77f1ee332e4a 3313 //----------------------------------------
whismanoid 1:77f1ee332e4a 3314 // Initialize shadow of write-only register SAMPLESET.
whismanoid 1:77f1ee332e4a 3315 // Do not write to SAMPLESET at this time.
whismanoid 1:77f1ee332e4a 3316 // A write to SAMPLESET must be followed by specified number of pattern entry words.
whismanoid 1:77f1ee332e4a 3317 // See ScanSampleSetExternalClock function for details.
whismanoid 1:77f1ee332e4a 3318 SAMPLESET = 0xB000; //!< mosiData16 0xB000..0xB7FF format: 1 0 1 1 0 SEQ_LENGTH[7:0] x x x
whismanoid 1:77f1ee332e4a 3319 const int SAMPLESET_LSB = 3; const int SAMPLESET_BITS = 0xFF; // SAMPLESET.SEQ_LENGTH[7:0]
whismanoid 1:77f1ee332e4a 3320
whismanoid 1:77f1ee332e4a 3321 //----------------------------------------
whismanoid 1:77f1ee332e4a 3322 // SampleSet register set SEQ_DEPTH[7:0] TO SET CHANNEL CAPTURE DEPTH; FOLLOW SampleSet REGISTER WITH CHANNEL PATTERN OF THE SAME SIZE AS SEQUENCE DEPTH
whismanoid 1:77f1ee332e4a 3323 // NOTE: SAMPLESET.SEQ_LENGTH[7:0] is the number of channel entries in the pattern.
whismanoid 1:77f1ee332e4a 3324 // NOTE: Each channel entry is 4 bits. The first 4 bits are the first channel in the sequence.
whismanoid 1:77f1ee332e4a 3325 // NOTE: Channels can be repeated in any arbitrary order.
whismanoid 1:77f1ee332e4a 3326 // NOTE: The channel entry pattern is sent immediately after writing SAMPLESET.
whismanoid 1:77f1ee332e4a 3327 // NOTE: Keep CS low during the entire SAMPLESET pattern entry.
whismanoid 1:77f1ee332e4a 3328 const int seq_length_minus_one_0_255 = enabledChannelsPatternLength_1_256 - 1;
whismanoid 1:77f1ee332e4a 3329 SAMPLESET = 0xB000;
whismanoid 1:77f1ee332e4a 3330 //SAMPLESET &= ~ (( SAMPLESET_BITS) << SAMPLESET_LSB);
whismanoid 1:77f1ee332e4a 3331 SAMPLESET |= ((seq_length_minus_one_0_255 & SAMPLESET_BITS) << SAMPLESET_LSB);
whismanoid 1:77f1ee332e4a 3332 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 3333 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 3334 SPIwrite16bits(SAMPLESET); // SAMPLESET must be followed by several more bytes, length specified by SEQ_LENGTH[7:0]
whismanoid 1:77f1ee332e4a 3335 // pack enabledChannelsPattern[index] into nybbles
whismanoid 1:77f1ee332e4a 3336 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 3337 // NOTE: Send the sampleset pattern, with 4 entries packed into each 16-bit SPI word. Pad unused entries with 0.
whismanoid 1:77f1ee332e4a 3338 SPI_MOSI_Semantic = 2; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 3339 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 3340 // NOTE: Keep CS low during the entire SAMPLESET pattern entry.
whismanoid 1:77f1ee332e4a 3341 int entryIndex;
whismanoid 1:77f1ee332e4a 3342 for (entryIndex = 0; entryIndex < enabledChannelsPatternLength_1_256; entryIndex += 4)
whismanoid 1:77f1ee332e4a 3343 {
whismanoid 1:77f1ee332e4a 3344 uint16_t pack4channels = 0;
whismanoid 1:77f1ee332e4a 3345 pack4channels |= (((enabledChannelsPattern[entryIndex + 0]) & 0x0F) << 12);
whismanoid 1:77f1ee332e4a 3346 if ((entryIndex + 1) < enabledChannelsPatternLength_1_256) {
whismanoid 1:77f1ee332e4a 3347 pack4channels |= (((enabledChannelsPattern[entryIndex + 1]) & 0x0F) << 8);
whismanoid 1:77f1ee332e4a 3348 }
whismanoid 1:77f1ee332e4a 3349 if ((entryIndex + 2) < enabledChannelsPatternLength_1_256) {
whismanoid 1:77f1ee332e4a 3350 pack4channels |= (((enabledChannelsPattern[entryIndex + 2]) & 0x0F) << 4);
whismanoid 1:77f1ee332e4a 3351 }
whismanoid 1:77f1ee332e4a 3352 if ((entryIndex + 3) < enabledChannelsPatternLength_1_256) {
whismanoid 1:77f1ee332e4a 3353 pack4channels |= ((enabledChannelsPattern[entryIndex + 3]) & 0x0F);
whismanoid 1:77f1ee332e4a 3354 }
whismanoid 1:77f1ee332e4a 3355 SPIwrite16bits(pack4channels);
whismanoid 1:77f1ee332e4a 3356 }
whismanoid 1:77f1ee332e4a 3357 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 3358
whismanoid 1:77f1ee332e4a 3359 //----------------------------------------
whismanoid 1:77f1ee332e4a 3360 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_1001_SampleSetExternalClock = 9
whismanoid 1:77f1ee332e4a 3361 //~ const int SCAN_1001_SampleSetExternalClock = 9; // replaced local const with enum
whismanoid 1:77f1ee332e4a 3362 ADC_MODE_CONTROL |= ((SCAN_1001_SampleSetExternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 3363
whismanoid 1:77f1ee332e4a 3364 //----------------------------------------
whismanoid 1:77f1ee332e4a 3365 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 3366 ADC_MODE_CONTROL |= ((0 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 3367
whismanoid 1:77f1ee332e4a 3368 //----------------------------------------
whismanoid 1:77f1ee332e4a 3369 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 3370 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 3371
whismanoid 1:77f1ee332e4a 3372 //----------------------------------------
whismanoid 1:77f1ee332e4a 3373 // ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid 1:77f1ee332e4a 3374 // (applicable to external clock mode only)
whismanoid 1:77f1ee332e4a 3375 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 3376 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 3377 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 3378 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 3379 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 3380 ADC_MODE_CONTROL |= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid 1:77f1ee332e4a 3381
whismanoid 1:77f1ee332e4a 3382 //----------------------------------------
whismanoid 1:77f1ee332e4a 3383 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 3384 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 3385 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 3386 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 3387 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 3388 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 3389
whismanoid 1:77f1ee332e4a 3390 //----------------------------------------
whismanoid 1:77f1ee332e4a 3391 // return number of words to read
whismanoid 1:77f1ee332e4a 3392 return NumWords;
whismanoid 1:77f1ee332e4a 3393 }
whismanoid 1:77f1ee332e4a 3394
whismanoid 1:77f1ee332e4a 3395 //----------------------------------------
whismanoid 1:77f1ee332e4a 3396 // Example configure and perform some measurements in ScanManual mode.
whismanoid 1:77f1ee332e4a 3397 // @param[out] pd_mean = address for double mean (avearge)
whismanoid 1:77f1ee332e4a 3398 // @param[out] pd_variance = address for double variance (variance)
whismanoid 1:77f1ee332e4a 3399 // @param[out] pd_stddev = address for double stddev (standard deviation)
whismanoid 1:77f1ee332e4a 3400 // @param[out] pd_Sx = address for double Sx (sum of all X)
whismanoid 1:77f1ee332e4a 3401 // @param[out] pd_Sxx = address for double Sxx (sum of squares of each X)
whismanoid 1:77f1ee332e4a 3402 void MAX11131::Example_ScanManual(int channelNumber_0_15, int nWords,
whismanoid 1:77f1ee332e4a 3403 double* pd_mean, double* pd_variance, double* pd_stddev,
whismanoid 1:77f1ee332e4a 3404 double* pd_Sx, double* pd_Sxx)
whismanoid 1:77f1ee332e4a 3405 {
whismanoid 1:77f1ee332e4a 3406
whismanoid 1:77f1ee332e4a 3407 //----------------------------------------
whismanoid 1:77f1ee332e4a 3408 // configure and perform some measurements in ScanManual mode
whismanoid 1:77f1ee332e4a 3409 Init();
whismanoid 1:77f1ee332e4a 3410 channelNumber_0_15 = channelNumber_0_15; // Analog Input Channel Select AIN0..
whismanoid 1:77f1ee332e4a 3411 PowerManagement_0_2 = 0; // Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 3412 chan_id_0_1 = 1; // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 3413 // const int nWords = 100;
whismanoid 1:77f1ee332e4a 3414 double Sx = 0;
whismanoid 1:77f1ee332e4a 3415 double Sxx = 0;
whismanoid 1:77f1ee332e4a 3416 int index;
whismanoid 1:77f1ee332e4a 3417 ScanManual();
whismanoid 1:77f1ee332e4a 3418 for (index = 0; index < nWords; index++)
whismanoid 1:77f1ee332e4a 3419 {
whismanoid 1:77f1ee332e4a 3420 int16_t misoData16 = ScanRead();
whismanoid 1:77f1ee332e4a 3421 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 3422 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 3423 int16_t value_u12 = (misoData16 & 0x0FFF);
whismanoid 1:77f1ee332e4a 3424 int channelId = ((misoData16 >> 12) & 0x000F);
whismanoid 1:77f1ee332e4a 3425 Sx = Sx + value_u12;
whismanoid 1:77f1ee332e4a 3426 Sxx = Sxx + ((double)value_u12 * value_u12);
whismanoid 1:77f1ee332e4a 3427 }
whismanoid 1:77f1ee332e4a 3428 if (pd_Sx != 0) {
whismanoid 1:77f1ee332e4a 3429 *(pd_Sx) = Sx;
whismanoid 1:77f1ee332e4a 3430 }
whismanoid 1:77f1ee332e4a 3431 if (pd_Sxx != 0) {
whismanoid 1:77f1ee332e4a 3432 *(pd_Sxx) = Sxx;
whismanoid 1:77f1ee332e4a 3433 }
whismanoid 1:77f1ee332e4a 3434 if (pd_mean != 0) {
whismanoid 1:77f1ee332e4a 3435 *(pd_mean) = Sx / nWords;
whismanoid 1:77f1ee332e4a 3436 }
whismanoid 1:77f1ee332e4a 3437 if (nWords >= 2)
whismanoid 1:77f1ee332e4a 3438 {
whismanoid 1:77f1ee332e4a 3439 if (pd_variance != 0) {
whismanoid 1:77f1ee332e4a 3440 // TODO1: is this variance calculation too naive to work reliably?
whismanoid 1:77f1ee332e4a 3441 // see https://en.wikipedia.org/wiki/Algorithms_for_calculating_variance
whismanoid 1:77f1ee332e4a 3442 *(pd_variance) = (Sxx - ( Sx * Sx / nWords) ) / (nWords - 1);
whismanoid 1:77f1ee332e4a 3443 }
whismanoid 1:77f1ee332e4a 3444 if (pd_stddev != 0) {
whismanoid 9:8d47cb713984 3445 extern double sqrt(double);
whismanoid 1:77f1ee332e4a 3446 *(pd_stddev) = sqrt( *(pd_variance) );
whismanoid 1:77f1ee332e4a 3447 }
whismanoid 1:77f1ee332e4a 3448 }
whismanoid 1:77f1ee332e4a 3449 }
whismanoid 1:77f1ee332e4a 3450
whismanoid 1:77f1ee332e4a 3451
whismanoid 1:77f1ee332e4a 3452 // End of file