Maxim Integrated / MAX11131

Maxim Integrated MAX11131 SPI 12-bit 16-channel ADC with SampleSet

Dependents:   MAX11131BOB_Tester MAX11131BOB_12bit_16ch_SampleSet_SPI_ADC MAX11131BOB_Serial_Tester

MAX11131.cpp@1:77f1ee332e4a, 2019-06-17 (annotated)

Committer:
whismanoid
Date:
Mon Jun 17 05:37:06 2019 +0000
Revision:
1:77f1ee332e4a
Parent:
0:f7d706d2904d
Child:
2:50a0cf017492
remove serial port dependency from mbed hello; minor documentation updates

Who changed what in which revision?

UserRevisionLine numberNew contents of line
whismanoid 1:77f1ee332e4a 1 // /*******************************************************************************
whismanoid 1:77f1ee332e4a 2 // * Copyright (C) 2019 Maxim Integrated Products, Inc., All Rights Reserved.
whismanoid 1:77f1ee332e4a 3 // *
whismanoid 1:77f1ee332e4a 4 // * Permission is hereby granted, free of charge, to any person obtaining a
whismanoid 1:77f1ee332e4a 5 // * copy of this software and associated documentation files (the "Software"),
whismanoid 1:77f1ee332e4a 6 // * to deal in the Software without restriction, including without limitation
whismanoid 1:77f1ee332e4a 7 // * the rights to use, copy, modify, merge, publish, distribute, sublicense,
whismanoid 1:77f1ee332e4a 8 // * and/or sell copies of the Software, and to permit persons to whom the
whismanoid 1:77f1ee332e4a 9 // * Software is furnished to do so, subject to the following conditions:
whismanoid 1:77f1ee332e4a 10 // *
whismanoid 1:77f1ee332e4a 11 // * The above copyright notice and this permission notice shall be included
whismanoid 1:77f1ee332e4a 12 // * in all copies or substantial portions of the Software.
whismanoid 1:77f1ee332e4a 13 // *
whismanoid 1:77f1ee332e4a 14 // * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
whismanoid 1:77f1ee332e4a 15 // * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
whismanoid 1:77f1ee332e4a 16 // * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
whismanoid 1:77f1ee332e4a 17 // * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
whismanoid 1:77f1ee332e4a 18 // * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
whismanoid 1:77f1ee332e4a 19 // * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
whismanoid 1:77f1ee332e4a 20 // * OTHER DEALINGS IN THE SOFTWARE.
whismanoid 1:77f1ee332e4a 21 // *
whismanoid 1:77f1ee332e4a 22 // * Except as contained in this notice, the name of Maxim Integrated
whismanoid 1:77f1ee332e4a 23 // * Products, Inc. shall not be used except as stated in the Maxim Integrated
whismanoid 1:77f1ee332e4a 24 // * Products, Inc. Branding Policy.
whismanoid 1:77f1ee332e4a 25 // *
whismanoid 1:77f1ee332e4a 26 // * The mere transfer of this software does not imply any licenses
whismanoid 1:77f1ee332e4a 27 // * of trade secrets, proprietary technology, copyrights, patents,
whismanoid 1:77f1ee332e4a 28 // * trademarks, maskwork rights, or any other form of intellectual
whismanoid 1:77f1ee332e4a 29 // * property whatsoever. Maxim Integrated Products, Inc. retains all
whismanoid 1:77f1ee332e4a 30 // * ownership rights.
whismanoid 1:77f1ee332e4a 31 // *******************************************************************************
whismanoid 1:77f1ee332e4a 32 // */
whismanoid 1:77f1ee332e4a 33 // *********************************************************************
whismanoid 1:77f1ee332e4a 34 // @file MAX11131.cpp
whismanoid 1:77f1ee332e4a 35 // *********************************************************************
whismanoid 1:77f1ee332e4a 36 // Device Driver file
whismanoid 1:77f1ee332e4a 37 // DO NOT EDIT; except areas designated "CUSTOMIZE". Automatically generated file.
whismanoid 1:77f1ee332e4a 38 // generated by XMLSystemOfDevicesToMBED.py
whismanoid 1:77f1ee332e4a 39 // System Name = ExampleSystem
whismanoid 1:77f1ee332e4a 40 // System Description = Device driver example
whismanoid 1:77f1ee332e4a 41
whismanoid 1:77f1ee332e4a 42 #include "MAX11131.h"
whismanoid 1:77f1ee332e4a 43
whismanoid 1:77f1ee332e4a 44 // Device Name = MAX11131
whismanoid 1:77f1ee332e4a 45 // Device Description = 3Msps, Low-Power, Serial SPI 12-Bit, 16-Channel, Differential/Single-Ended Input, SAR ADC
whismanoid 1:77f1ee332e4a 46 // Device Manufacturer = Maxim Integrated
whismanoid 1:77f1ee332e4a 47 // Device PartNumber = MAX11131ATI+
whismanoid 1:77f1ee332e4a 48 // Device RegValue_Width = DataWidth16bit_HL
whismanoid 1:77f1ee332e4a 49 //
whismanoid 1:77f1ee332e4a 50 // ADC MaxOutputDataRate = 3Msps
whismanoid 1:77f1ee332e4a 51 // ADC NumChannels = 16
whismanoid 1:77f1ee332e4a 52 // ADC ResolutionBits = 12
whismanoid 1:77f1ee332e4a 53 //
whismanoid 1:77f1ee332e4a 54 // SPI CS = ActiveLow
whismanoid 1:77f1ee332e4a 55 // SPI FrameStart = CS
whismanoid 1:77f1ee332e4a 56 // SPI CPOL = 1
whismanoid 1:77f1ee332e4a 57 // SPI CPHA = 1
whismanoid 1:77f1ee332e4a 58 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 1:77f1ee332e4a 59 // SPI SCLK Idle High
whismanoid 1:77f1ee332e4a 60 // SPI SCLKMaxMHz = 48
whismanoid 1:77f1ee332e4a 61 // SPI SCLKMinMHz = 0.48
whismanoid 1:77f1ee332e4a 62 //
whismanoid 1:77f1ee332e4a 63 // InputPin Name = CNVST
whismanoid 1:77f1ee332e4a 64 // InputPin Description = Active-Low Conversion Start Input/Analog Input 14
whismanoid 1:77f1ee332e4a 65 // InputPin Function = Trigger
whismanoid 1:77f1ee332e4a 66 //
whismanoid 1:77f1ee332e4a 67 // InputPin Name = REF+
whismanoid 1:77f1ee332e4a 68 // InputPin Description = External Positive Reference Input. Apply a reference voltage at REF+. Bypass to GND with a 0.47uF capacitor.
whismanoid 1:77f1ee332e4a 69 // InputPin Function = Reference
whismanoid 1:77f1ee332e4a 70 //
whismanoid 1:77f1ee332e4a 71 // InputPin Name = REF-/AIN15
whismanoid 1:77f1ee332e4a 72 // InputPin Description = External Differential Reference Negative Input/Analog Input 15
whismanoid 1:77f1ee332e4a 73 // InputPin Function = Reference
whismanoid 1:77f1ee332e4a 74 //
whismanoid 1:77f1ee332e4a 75 // OutputPin Name = EOC
whismanoid 1:77f1ee332e4a 76 // OutputPin Description = End of Conversion Output. Data is valid after EOC pulls low (Internal clock mode only).
whismanoid 1:77f1ee332e4a 77 // OutputPin Function = Event
whismanoid 1:77f1ee332e4a 78 //
whismanoid 1:77f1ee332e4a 79 // SupplyPin Name = VDD
whismanoid 1:77f1ee332e4a 80 // SupplyPin Description = Power-Supply Input. Bypass to GND with a 10uF in parallel with a 0.1uF capacitors.
whismanoid 1:77f1ee332e4a 81 // SupplyPin VinMax = 3.6
whismanoid 1:77f1ee332e4a 82 // SupplyPin VinMin = 2.35
whismanoid 1:77f1ee332e4a 83 // SupplyPin Function = Analog
whismanoid 1:77f1ee332e4a 84 //
whismanoid 1:77f1ee332e4a 85 // SupplyPin Name = OVDD
whismanoid 1:77f1ee332e4a 86 // SupplyPin Description = Interface Digital Power-Supply Input. Bypass to GND with a 10uF in parallel with a 0.1uF capacitors.
whismanoid 1:77f1ee332e4a 87 // SupplyPin VinMax = 3.6
whismanoid 1:77f1ee332e4a 88 // SupplyPin VinMin = 1.5
whismanoid 1:77f1ee332e4a 89 // SupplyPin Function = Digital
whismanoid 1:77f1ee332e4a 90 //
whismanoid 1:77f1ee332e4a 91
whismanoid 1:77f1ee332e4a 92 // CODE GENERATOR: class constructor definition
whismanoid 1:77f1ee332e4a 93 MAX11131::MAX11131(SPI &spi, DigitalOut &cs_pin, // SPI interface
whismanoid 1:77f1ee332e4a 94 // CODE GENERATOR: class constructor definition gpio InputPin pins
whismanoid 1:77f1ee332e4a 95 DigitalOut &CNVST_pin, // Digital Trigger Input to MAX11131 device
whismanoid 1:77f1ee332e4a 96 // AnalogOut &REF__pin, // Reference Input to MAX11131 device
whismanoid 1:77f1ee332e4a 97 // AnalogOut &REF__AIN15_pin, // Reference Input to MAX11131 device
whismanoid 1:77f1ee332e4a 98 // CODE GENERATOR: class constructor definition gpio OutputPin pins
whismanoid 1:77f1ee332e4a 99 DigitalIn &EOC_pin, // Digital Event Output from MAX11131 device
whismanoid 1:77f1ee332e4a 100 // CODE GENERATOR: class constructor definition ic_variant
whismanoid 1:77f1ee332e4a 101 MAX11131_ic_t ic_variant)
whismanoid 1:77f1ee332e4a 102 // CODE GENERATOR: class constructor initializer list
whismanoid 1:77f1ee332e4a 103 : m_spi(spi), m_cs_pin(cs_pin), // SPI interface
whismanoid 1:77f1ee332e4a 104 // CODE GENERATOR: class constructor initializer list gpio InputPin pins
whismanoid 1:77f1ee332e4a 105 m_CNVST_pin(CNVST_pin), // Digital Trigger Input to MAX11131 device
whismanoid 1:77f1ee332e4a 106 // m_REF__pin(REF__pin), // Reference Input to MAX11131 device
whismanoid 1:77f1ee332e4a 107 // m_REF__AIN15_pin(REF__AIN15_pin), // Reference Input to MAX11131 device
whismanoid 1:77f1ee332e4a 108 // CODE GENERATOR: class constructor initializer list gpio OutputPin pins
whismanoid 1:77f1ee332e4a 109 m_EOC_pin(EOC_pin), // Digital Event Output from MAX11131 device
whismanoid 1:77f1ee332e4a 110 // CODE GENERATOR: class constructor initializer list ic_variant
whismanoid 1:77f1ee332e4a 111 m_ic_variant(ic_variant)
whismanoid 1:77f1ee332e4a 112 {
whismanoid 1:77f1ee332e4a 113 // CODE GENERATOR: class constructor definition SPI interface initialization
whismanoid 1:77f1ee332e4a 114 //
whismanoid 1:77f1ee332e4a 115 // SPI CS = ActiveLow
whismanoid 1:77f1ee332e4a 116 // SPI FrameStart = CS
whismanoid 1:77f1ee332e4a 117 m_SPI_cs_state = 1;
whismanoid 1:77f1ee332e4a 118 m_cs_pin = m_SPI_cs_state;
whismanoid 1:77f1ee332e4a 119
whismanoid 1:77f1ee332e4a 120 // SPI CPOL = 1
whismanoid 1:77f1ee332e4a 121 // SPI CPHA = 1
whismanoid 1:77f1ee332e4a 122 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 1:77f1ee332e4a 123 // SPI SCLK Idle High
whismanoid 1:77f1ee332e4a 124 m_SPI_dataMode = 3; //SPI_MODE3 // CPOL=1,CPHA=1: Rising Edge stable; SCLK idle High
whismanoid 1:77f1ee332e4a 125 m_spi.format(8,m_SPI_dataMode); // int bits_must_be_8, int mode=0_3 CPOL=0,CPHA=0
whismanoid 1:77f1ee332e4a 126
whismanoid 1:77f1ee332e4a 127 // SPI SCLKMaxMHz = 48
whismanoid 1:77f1ee332e4a 128 // SPI SCLKMinMHz = 0.48
whismanoid 1:77f1ee332e4a 129 //#define SPI_SCLK_Hz 48000000 // 48MHz
whismanoid 1:77f1ee332e4a 130 //#define SPI_SCLK_Hz 24000000 // 24MHz
whismanoid 1:77f1ee332e4a 131 //#define SPI_SCLK_Hz 12000000 // 12MHz
whismanoid 1:77f1ee332e4a 132 //#define SPI_SCLK_Hz 4000000 // 4MHz
whismanoid 1:77f1ee332e4a 133 //#define SPI_SCLK_Hz 2000000 // 2MHz
whismanoid 1:77f1ee332e4a 134 //#define SPI_SCLK_Hz 1000000 // 1MHz
whismanoid 1:77f1ee332e4a 135 m_SPI_SCLK_Hz = 12000000; // 12MHz; MAX11131 limit is 48MHz
whismanoid 1:77f1ee332e4a 136 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 1:77f1ee332e4a 137
whismanoid 1:77f1ee332e4a 138 // TODO1: CODE GENERATOR: class constructor definition gpio InputPin (Input to device) initialization
whismanoid 1:77f1ee332e4a 139 //
whismanoid 1:77f1ee332e4a 140 m_CNVST_pin = 1; // output logic high -- initial value in constructor
whismanoid 1:77f1ee332e4a 141 }
whismanoid 1:77f1ee332e4a 142
whismanoid 1:77f1ee332e4a 143 // CODE GENERATOR: class destructor definition
whismanoid 1:77f1ee332e4a 144 MAX11131::~MAX11131()
whismanoid 1:77f1ee332e4a 145 {
whismanoid 1:77f1ee332e4a 146 // do nothing
whismanoid 1:77f1ee332e4a 147 }
whismanoid 1:77f1ee332e4a 148
whismanoid 1:77f1ee332e4a 149 // CODE GENERATOR: spi_frequency setter definition
whismanoid 1:77f1ee332e4a 150 // set SPI SCLK frequency
whismanoid 1:77f1ee332e4a 151 void MAX11131::spi_frequency(int spi_sclk_Hz)
whismanoid 1:77f1ee332e4a 152 {
whismanoid 1:77f1ee332e4a 153 m_SPI_SCLK_Hz = spi_sclk_Hz;
whismanoid 1:77f1ee332e4a 154 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 1:77f1ee332e4a 155 }
whismanoid 1:77f1ee332e4a 156
whismanoid 1:77f1ee332e4a 157 // CODE GENERATOR: omit global g_MAX11131_device
whismanoid 1:77f1ee332e4a 158 // CODE GENERATOR: extern function declarations
whismanoid 1:77f1ee332e4a 159 // CODE GENERATOR: extern function requirement MAX11131::SPIoutputCS
whismanoid 1:77f1ee332e4a 160 // Assert SPI Chip Select
whismanoid 1:77f1ee332e4a 161 // SPI chip-select for MAX11131
whismanoid 1:77f1ee332e4a 162 //
whismanoid 1:77f1ee332e4a 163 void MAX11131::SPIoutputCS(int isLogicHigh)
whismanoid 1:77f1ee332e4a 164 {
whismanoid 1:77f1ee332e4a 165 // CODE GENERATOR: extern function definition for function SPIoutputCS
whismanoid 1:77f1ee332e4a 166 // CODE GENERATOR: extern function definition for standard SPI interface function SPIoutputCS(int isLogicHigh)
whismanoid 1:77f1ee332e4a 167 m_SPI_cs_state = isLogicHigh;
whismanoid 1:77f1ee332e4a 168 m_cs_pin = m_SPI_cs_state;
whismanoid 1:77f1ee332e4a 169 }
whismanoid 1:77f1ee332e4a 170
whismanoid 1:77f1ee332e4a 171 // CODE GENERATOR: extern function requirement MAX11131::SPIwrite16bits
whismanoid 1:77f1ee332e4a 172 // SPI write 16 bits
whismanoid 1:77f1ee332e4a 173 // SPI interface to MAX11131 shift 16 bits mosiData16 into MAX11131 DIN
whismanoid 1:77f1ee332e4a 174 // ignoring MAX11131 DOUT
whismanoid 1:77f1ee332e4a 175 //
whismanoid 1:77f1ee332e4a 176 void MAX11131::SPIwrite16bits(int16_t mosiData16)
whismanoid 1:77f1ee332e4a 177 {
whismanoid 1:77f1ee332e4a 178 // CODE GENERATOR: extern function definition for function SPIwrite16bits
whismanoid 1:77f1ee332e4a 179 // TODO1: CODE GENERATOR: extern function definition for standard SPI interface function SPIwrite16bits(int16_t mosiData16)
whismanoid 1:77f1ee332e4a 180 size_t byteCount = 2;
whismanoid 1:77f1ee332e4a 181 static char mosiData[2];
whismanoid 1:77f1ee332e4a 182 static char misoData[2];
whismanoid 1:77f1ee332e4a 183 mosiData[0] = (char)((mosiData16 >> 8) & 0xFF); // MSByte
whismanoid 1:77f1ee332e4a 184 mosiData[1] = (char)((mosiData16 >> 0) & 0xFF); // LSByte
whismanoid 1:77f1ee332e4a 185 //
whismanoid 1:77f1ee332e4a 186 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 1:77f1ee332e4a 187 //~ noInterrupts();
whismanoid 1:77f1ee332e4a 188 //
whismanoid 1:77f1ee332e4a 189 //~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid 1:77f1ee332e4a 190 //
whismanoid 1:77f1ee332e4a 191 unsigned int numBytesTransferred = m_spi.write(mosiData, byteCount, misoData, byteCount);
whismanoid 1:77f1ee332e4a 192 //~ m_spi.transfer(mosiData8_FF0000);
whismanoid 1:77f1ee332e4a 193 //~ m_spi.transfer(mosiData16_00FF00);
whismanoid 1:77f1ee332e4a 194 //~ m_spi.transfer(mosiData16_0000FF);
whismanoid 1:77f1ee332e4a 195 //
whismanoid 1:77f1ee332e4a 196 //~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid 1:77f1ee332e4a 197 //
whismanoid 1:77f1ee332e4a 198 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 1:77f1ee332e4a 199 //~ interrupts();
whismanoid 1:77f1ee332e4a 200 //
whismanoid 1:77f1ee332e4a 201 // VERIFY: SPIwrite24bits print diagnostic information
whismanoid 1:77f1ee332e4a 202 //cmdLine.serial().printf(" MOSI->"));
whismanoid 1:77f1ee332e4a 203 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 204 //Serial.print( (mosiData8_FF0000 & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 205 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 206 //Serial.print( (mosiData16_00FF00 & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 207 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 208 //Serial.print( (mosiData16_0000FF & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 209 // hex dump mosiData[0..byteCount-1]
whismanoid 1:77f1ee332e4a 210 #if 0 // HAS_MICROUSBSERIAL
whismanoid 1:77f1ee332e4a 211 cmdLine_microUSBserial.serial().printf("\r\nSPI");
whismanoid 1:77f1ee332e4a 212 if (byteCount > 7) {
whismanoid 1:77f1ee332e4a 213 cmdLine_microUSBserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 1:77f1ee332e4a 214 }
whismanoid 1:77f1ee332e4a 215 cmdLine_microUSBserial.serial().printf(" MOSI->");
whismanoid 1:77f1ee332e4a 216 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 1:77f1ee332e4a 217 {
whismanoid 1:77f1ee332e4a 218 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 1:77f1ee332e4a 219 }
whismanoid 1:77f1ee332e4a 220 // hex dump misoData[0..byteCount-1]
whismanoid 1:77f1ee332e4a 221 cmdLine_microUSBserial.serial().printf(" MISO<-");
whismanoid 1:77f1ee332e4a 222 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 1:77f1ee332e4a 223 {
whismanoid 1:77f1ee332e4a 224 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 1:77f1ee332e4a 225 }
whismanoid 1:77f1ee332e4a 226 cmdLine_microUSBserial.serial().printf(" ");
whismanoid 1:77f1ee332e4a 227 #endif
whismanoid 1:77f1ee332e4a 228 #if 0 // HAS_DAPLINK_SERIAL
whismanoid 1:77f1ee332e4a 229 cmdLine_DAPLINKserial.serial().printf("\r\nSPI");
whismanoid 1:77f1ee332e4a 230 if (byteCount > 7) {
whismanoid 1:77f1ee332e4a 231 cmdLine_DAPLINKserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 1:77f1ee332e4a 232 }
whismanoid 1:77f1ee332e4a 233 cmdLine_DAPLINKserial.serial().printf(" MOSI->");
whismanoid 1:77f1ee332e4a 234 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 1:77f1ee332e4a 235 {
whismanoid 1:77f1ee332e4a 236 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 1:77f1ee332e4a 237 }
whismanoid 1:77f1ee332e4a 238 // hex dump misoData[0..byteCount-1]
whismanoid 1:77f1ee332e4a 239 cmdLine_DAPLINKserial.serial().printf(" MISO<-");
whismanoid 1:77f1ee332e4a 240 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 1:77f1ee332e4a 241 {
whismanoid 1:77f1ee332e4a 242 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 1:77f1ee332e4a 243 }
whismanoid 1:77f1ee332e4a 244 cmdLine_DAPLINKserial.serial().printf(" ");
whismanoid 1:77f1ee332e4a 245 #endif
whismanoid 1:77f1ee332e4a 246 // VERIFY: DIAGNOSTIC: print MAX5715 device register write
whismanoid 1:77f1ee332e4a 247 // TODO: MAX5715_print_register_verbose(mosiData8_FF0000, mosiData16_00FFFF);
whismanoid 1:77f1ee332e4a 248 // TODO: print_verbose_SPI_diagnostic(mosiData16_FF00, mosiData16_00FF, misoData16_FF00, misoData16_00FF);
whismanoid 1:77f1ee332e4a 249 //
whismanoid 1:77f1ee332e4a 250 // int misoData16 = (misoData16_FF00 << 8) | misoData16_00FF;
whismanoid 1:77f1ee332e4a 251 // return misoData16;
whismanoid 1:77f1ee332e4a 252 }
whismanoid 1:77f1ee332e4a 253
whismanoid 1:77f1ee332e4a 254 // CODE GENERATOR: extern function requirement MAX11131::SPIwrite24bits
whismanoid 1:77f1ee332e4a 255 // SPI write 17-24 bits
whismanoid 1:77f1ee332e4a 256 // SPI interface to MAX11131 shift 16 bits mosiData16 into MAX11131 DIN
whismanoid 1:77f1ee332e4a 257 // followed by one additional SCLK byte.
whismanoid 1:77f1ee332e4a 258 // ignoring MAX11131 DOUT
whismanoid 1:77f1ee332e4a 259 //
whismanoid 1:77f1ee332e4a 260 void MAX11131::SPIwrite24bits(int16_t mosiData16_FFFF00, int8_t mosiData8_0000FF)
whismanoid 1:77f1ee332e4a 261 {
whismanoid 1:77f1ee332e4a 262 // CODE GENERATOR: extern function definition for function SPIwrite24bits
whismanoid 1:77f1ee332e4a 263 // TODO1: CODE GENERATOR: extern function definition for standard SPI interface function SPIwrite24bits(int16_t mosiData16_FFFF00, int8_t mosiData8_0000FF)
whismanoid 1:77f1ee332e4a 264 // TODO: implement SPIwrite24bits(int16_t mosiData16_FFFF00, int8_t mosiData8_0000FF)
whismanoid 1:77f1ee332e4a 265 size_t byteCount = 3;
whismanoid 1:77f1ee332e4a 266 static char mosiData[3];
whismanoid 1:77f1ee332e4a 267 static char misoData[3];
whismanoid 1:77f1ee332e4a 268 mosiData[0] = (char)((mosiData16_FFFF00 >> 8) & 0xFF); // MSByte
whismanoid 1:77f1ee332e4a 269 mosiData[1] = (char)((mosiData16_FFFF00 >> 0) & 0xFF); // LSByte
whismanoid 1:77f1ee332e4a 270 mosiData[2] = mosiData8_0000FF;
whismanoid 1:77f1ee332e4a 271 //
whismanoid 1:77f1ee332e4a 272 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 1:77f1ee332e4a 273 //~ noInterrupts();
whismanoid 1:77f1ee332e4a 274 //
whismanoid 1:77f1ee332e4a 275 //~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid 1:77f1ee332e4a 276 //
whismanoid 1:77f1ee332e4a 277 unsigned int numBytesTransferred = m_spi.write(mosiData, byteCount, misoData, byteCount);
whismanoid 1:77f1ee332e4a 278 //~ m_spi.transfer(mosiData8_FF0000);
whismanoid 1:77f1ee332e4a 279 //~ m_spi.transfer(mosiData16_00FF00);
whismanoid 1:77f1ee332e4a 280 //~ m_spi.transfer(mosiData16_0000FF);
whismanoid 1:77f1ee332e4a 281 //
whismanoid 1:77f1ee332e4a 282 //~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid 1:77f1ee332e4a 283 //
whismanoid 1:77f1ee332e4a 284 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 1:77f1ee332e4a 285 //~ interrupts();
whismanoid 1:77f1ee332e4a 286 //
whismanoid 1:77f1ee332e4a 287 // VERIFY: SPIwrite24bits print diagnostic information
whismanoid 1:77f1ee332e4a 288 //cmdLine.serial().printf(" MOSI->"));
whismanoid 1:77f1ee332e4a 289 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 290 //Serial.print( (mosiData8_FF0000 & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 291 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 292 //Serial.print( (mosiData16_00FF00 & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 293 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 294 //Serial.print( (mosiData16_0000FF & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 295 // hex dump mosiData[0..byteCount-1]
whismanoid 1:77f1ee332e4a 296 #if 0 // HAS_MICROUSBSERIAL
whismanoid 1:77f1ee332e4a 297 cmdLine_microUSBserial.serial().printf("\r\nSPI");
whismanoid 1:77f1ee332e4a 298 if (byteCount > 7) {
whismanoid 1:77f1ee332e4a 299 cmdLine_microUSBserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 1:77f1ee332e4a 300 }
whismanoid 1:77f1ee332e4a 301 cmdLine_microUSBserial.serial().printf(" MOSI->");
whismanoid 1:77f1ee332e4a 302 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 1:77f1ee332e4a 303 {
whismanoid 1:77f1ee332e4a 304 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 1:77f1ee332e4a 305 }
whismanoid 1:77f1ee332e4a 306 // hex dump misoData[0..byteCount-1]
whismanoid 1:77f1ee332e4a 307 cmdLine_microUSBserial.serial().printf(" MISO<-");
whismanoid 1:77f1ee332e4a 308 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 1:77f1ee332e4a 309 {
whismanoid 1:77f1ee332e4a 310 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 1:77f1ee332e4a 311 }
whismanoid 1:77f1ee332e4a 312 cmdLine_microUSBserial.serial().printf(" ");
whismanoid 1:77f1ee332e4a 313 #endif
whismanoid 1:77f1ee332e4a 314 #if 0 // HAS_DAPLINK_SERIAL
whismanoid 1:77f1ee332e4a 315 cmdLine_DAPLINKserial.serial().printf("\r\nSPI");
whismanoid 1:77f1ee332e4a 316 if (byteCount > 7) {
whismanoid 1:77f1ee332e4a 317 cmdLine_DAPLINKserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 1:77f1ee332e4a 318 }
whismanoid 1:77f1ee332e4a 319 cmdLine_DAPLINKserial.serial().printf(" MOSI->");
whismanoid 1:77f1ee332e4a 320 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 1:77f1ee332e4a 321 {
whismanoid 1:77f1ee332e4a 322 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 1:77f1ee332e4a 323 }
whismanoid 1:77f1ee332e4a 324 // hex dump misoData[0..byteCount-1]
whismanoid 1:77f1ee332e4a 325 cmdLine_DAPLINKserial.serial().printf(" MISO<-");
whismanoid 1:77f1ee332e4a 326 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 1:77f1ee332e4a 327 {
whismanoid 1:77f1ee332e4a 328 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 1:77f1ee332e4a 329 }
whismanoid 1:77f1ee332e4a 330 cmdLine_DAPLINKserial.serial().printf(" ");
whismanoid 1:77f1ee332e4a 331 #endif
whismanoid 1:77f1ee332e4a 332 // VERIFY: DIAGNOSTIC: print MAX5715 device register write
whismanoid 1:77f1ee332e4a 333 // TODO: MAX5715_print_register_verbose(mosiData8_FF0000, mosiData16_00FFFF);
whismanoid 1:77f1ee332e4a 334 //
whismanoid 1:77f1ee332e4a 335 // int misoData16 = (misoData16_FF00 << 8) | misoData16_00FF;
whismanoid 1:77f1ee332e4a 336 // return misoData16;
whismanoid 1:77f1ee332e4a 337 }
whismanoid 1:77f1ee332e4a 338
whismanoid 1:77f1ee332e4a 339 // CODE GENERATOR: extern function requirement MAX11131::SPIread16bits
whismanoid 1:77f1ee332e4a 340 // SPI read 16 bits while MOSI (MAX11131 DIN) is 0
whismanoid 1:77f1ee332e4a 341 // SPI interface to capture 16 bits miso data from MAX11131 DOUT
whismanoid 1:77f1ee332e4a 342 //
whismanoid 1:77f1ee332e4a 343 int16_t MAX11131::SPIread16bits()
whismanoid 1:77f1ee332e4a 344 {
whismanoid 1:77f1ee332e4a 345 // CODE GENERATOR: extern function definition for function SPIread16bits
whismanoid 1:77f1ee332e4a 346 // TODO1: CODE GENERATOR: extern function definition for standard SPI interface function int16_t SPIread16bits()
whismanoid 1:77f1ee332e4a 347 int mosiData16 = 0;
whismanoid 1:77f1ee332e4a 348 size_t byteCount = 2;
whismanoid 1:77f1ee332e4a 349 static char mosiData[2];
whismanoid 1:77f1ee332e4a 350 static char misoData[2];
whismanoid 1:77f1ee332e4a 351 mosiData[0] = (char)((mosiData16 >> 8) & 0xFF); // MSByte
whismanoid 1:77f1ee332e4a 352 mosiData[1] = (char)((mosiData16 >> 0) & 0xFF); // LSByte
whismanoid 1:77f1ee332e4a 353 //
whismanoid 1:77f1ee332e4a 354 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 1:77f1ee332e4a 355 //~ noInterrupts();
whismanoid 1:77f1ee332e4a 356 //
whismanoid 1:77f1ee332e4a 357 //~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid 1:77f1ee332e4a 358 //
whismanoid 1:77f1ee332e4a 359 unsigned int numBytesTransferred = m_spi.write(mosiData, byteCount, misoData, byteCount);
whismanoid 1:77f1ee332e4a 360 //~ m_spi.transfer(mosiData8_FF0000);
whismanoid 1:77f1ee332e4a 361 //~ m_spi.transfer(mosiData16_00FF00);
whismanoid 1:77f1ee332e4a 362 //~ m_spi.transfer(mosiData16_0000FF);
whismanoid 1:77f1ee332e4a 363 //
whismanoid 1:77f1ee332e4a 364 //~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid 1:77f1ee332e4a 365 //
whismanoid 1:77f1ee332e4a 366 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 1:77f1ee332e4a 367 //~ interrupts();
whismanoid 1:77f1ee332e4a 368 //
whismanoid 1:77f1ee332e4a 369 // VERIFY: SPIwrite24bits print diagnostic information
whismanoid 1:77f1ee332e4a 370 //cmdLine.serial().printf(" MOSI->"));
whismanoid 1:77f1ee332e4a 371 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 372 //Serial.print( (mosiData8_FF0000 & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 373 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 374 //Serial.print( (mosiData16_00FF00 & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 375 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 376 //Serial.print( (mosiData16_0000FF & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 377 // hex dump mosiData[0..byteCount-1]
whismanoid 1:77f1ee332e4a 378 #if 0 // HAS_MICROUSBSERIAL
whismanoid 1:77f1ee332e4a 379 cmdLine_microUSBserial.serial().printf("\r\nSPI");
whismanoid 1:77f1ee332e4a 380 if (byteCount > 7) {
whismanoid 1:77f1ee332e4a 381 cmdLine_microUSBserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 1:77f1ee332e4a 382 }
whismanoid 1:77f1ee332e4a 383 cmdLine_microUSBserial.serial().printf(" MOSI->");
whismanoid 1:77f1ee332e4a 384 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 1:77f1ee332e4a 385 {
whismanoid 1:77f1ee332e4a 386 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 1:77f1ee332e4a 387 }
whismanoid 1:77f1ee332e4a 388 // hex dump misoData[0..byteCount-1]
whismanoid 1:77f1ee332e4a 389 cmdLine_microUSBserial.serial().printf(" MISO<-");
whismanoid 1:77f1ee332e4a 390 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 1:77f1ee332e4a 391 {
whismanoid 1:77f1ee332e4a 392 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 1:77f1ee332e4a 393 }
whismanoid 1:77f1ee332e4a 394 cmdLine_microUSBserial.serial().printf(" ");
whismanoid 1:77f1ee332e4a 395 #endif
whismanoid 1:77f1ee332e4a 396 #if 0 // HAS_DAPLINK_SERIAL
whismanoid 1:77f1ee332e4a 397 cmdLine_DAPLINKserial.serial().printf("\r\nSPI");
whismanoid 1:77f1ee332e4a 398 if (byteCount > 7) {
whismanoid 1:77f1ee332e4a 399 cmdLine_DAPLINKserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 1:77f1ee332e4a 400 }
whismanoid 1:77f1ee332e4a 401 cmdLine_DAPLINKserial.serial().printf(" MOSI->");
whismanoid 1:77f1ee332e4a 402 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 1:77f1ee332e4a 403 {
whismanoid 1:77f1ee332e4a 404 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 1:77f1ee332e4a 405 }
whismanoid 1:77f1ee332e4a 406 // hex dump misoData[0..byteCount-1]
whismanoid 1:77f1ee332e4a 407 cmdLine_DAPLINKserial.serial().printf(" MISO<-");
whismanoid 1:77f1ee332e4a 408 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 1:77f1ee332e4a 409 {
whismanoid 1:77f1ee332e4a 410 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 1:77f1ee332e4a 411 }
whismanoid 1:77f1ee332e4a 412 cmdLine_DAPLINKserial.serial().printf(" ");
whismanoid 1:77f1ee332e4a 413 #endif
whismanoid 1:77f1ee332e4a 414 // VERIFY: DIAGNOSTIC: print MAX5715 device register write
whismanoid 1:77f1ee332e4a 415 // TODO: MAX5715_print_register_verbose(mosiData8_FF0000, mosiData16_00FFFF);
whismanoid 1:77f1ee332e4a 416 // TODO: print_verbose_SPI_diagnostic(mosiData16_FF00, mosiData16_00FF, misoData16_FF00, misoData16_00FF);
whismanoid 1:77f1ee332e4a 417 //
whismanoid 1:77f1ee332e4a 418 int misoData16 = (misoData[0] << 8) | misoData[1];
whismanoid 1:77f1ee332e4a 419 return misoData16;
whismanoid 1:77f1ee332e4a 420 }
whismanoid 1:77f1ee332e4a 421
whismanoid 1:77f1ee332e4a 422 // CODE GENERATOR: extern function requirement MAX11131::CNVSToutputPulseLow
whismanoid 1:77f1ee332e4a 423 // Assert MAX11131 CNVST convert start.
whismanoid 1:77f1ee332e4a 424 // Required when using any of the InternalClock modes with SWCNV 0.
whismanoid 1:77f1ee332e4a 425 // Trigger measurement by driving CNVST/AIN14 pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 426 //
whismanoid 1:77f1ee332e4a 427 void MAX11131::CNVSToutputPulseLow()
whismanoid 1:77f1ee332e4a 428 {
whismanoid 1:77f1ee332e4a 429 // CODE GENERATOR: extern function definition for function CNVSToutputPulseLow
whismanoid 1:77f1ee332e4a 430 // TODO1: CODE GENERATOR: extern function definition for gpio interface function CNVSToutputPulseLow
whismanoid 1:77f1ee332e4a 431 // TODO1: CODE GENERATOR: gpio pin CNVST assuming member function m_CNVST_pin
whismanoid 1:77f1ee332e4a 432 // TODO1: CODE GENERATOR: gpio direction output
whismanoid 1:77f1ee332e4a 433 // m_CNVST_pin.output(); // only applicable to DigitalInOut
whismanoid 1:77f1ee332e4a 434 // TODO1: CODE GENERATOR: gpio function PulseLow
whismanoid 1:77f1ee332e4a 435 m_CNVST_pin = 0; // output logic low
whismanoid 1:77f1ee332e4a 436 wait(0.01); // pulse low delay time
whismanoid 1:77f1ee332e4a 437 m_CNVST_pin = 1; // output logic high
whismanoid 1:77f1ee332e4a 438 }
whismanoid 1:77f1ee332e4a 439
whismanoid 1:77f1ee332e4a 440 // CODE GENERATOR: extern function requirement MAX11131::EOCinputWaitUntilLow
whismanoid 1:77f1ee332e4a 441 // Wait for MAX11131 EOC pin low, indicating end of conversion.
whismanoid 1:77f1ee332e4a 442 // Required when using any of the InternalClock modes.
whismanoid 1:77f1ee332e4a 443 //
whismanoid 1:77f1ee332e4a 444 void MAX11131::EOCinputWaitUntilLow()
whismanoid 1:77f1ee332e4a 445 {
whismanoid 1:77f1ee332e4a 446 // CODE GENERATOR: extern function definition for function EOCinputWaitUntilLow
whismanoid 1:77f1ee332e4a 447 // TODO1: CODE GENERATOR: extern function definition for gpio interface function EOCinputWaitUntilLow
whismanoid 1:77f1ee332e4a 448 // TODO1: CODE GENERATOR: gpio pin EOC assuming member function m_EOC_pin
whismanoid 1:77f1ee332e4a 449 // TODO1: CODE GENERATOR: gpio direction input
whismanoid 1:77f1ee332e4a 450 // m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid 1:77f1ee332e4a 451 // TODO1: CODE GENERATOR: gpio function WaitUntilLow
whismanoid 1:77f1ee332e4a 452 while (m_EOC_pin != 0)
whismanoid 1:77f1ee332e4a 453 {
whismanoid 1:77f1ee332e4a 454 // spinlock waiting for logic low pin state
whismanoid 1:77f1ee332e4a 455 }
whismanoid 1:77f1ee332e4a 456 }
whismanoid 1:77f1ee332e4a 457
whismanoid 1:77f1ee332e4a 458 // CODE GENERATOR: extern function requirement MAX11131::EOCinputValue
whismanoid 1:77f1ee332e4a 459 // Return the status of the MAX11131 EOC pin.
whismanoid 1:77f1ee332e4a 460 //
whismanoid 1:77f1ee332e4a 461 int MAX11131::EOCinputValue()
whismanoid 1:77f1ee332e4a 462 {
whismanoid 1:77f1ee332e4a 463 // CODE GENERATOR: extern function definition for function EOCinputValue
whismanoid 1:77f1ee332e4a 464 // TODO1: CODE GENERATOR: extern function definition for gpio interface function EOCinputValue
whismanoid 1:77f1ee332e4a 465 // TODO1: CODE GENERATOR: gpio pin EOC assuming member function m_EOC_pin
whismanoid 1:77f1ee332e4a 466 // TODO1: CODE GENERATOR: gpio direction input
whismanoid 1:77f1ee332e4a 467 // m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid 1:77f1ee332e4a 468 // TODO1: CODE GENERATOR: gpio function Value
whismanoid 1:77f1ee332e4a 469 return m_EOC_pin.read();
whismanoid 1:77f1ee332e4a 470 }
whismanoid 1:77f1ee332e4a 471
whismanoid 1:77f1ee332e4a 472 // CODE GENERATOR: class member function definitions
whismanoid 1:77f1ee332e4a 473 //----------------------------------------
whismanoid 1:77f1ee332e4a 474 // Initialize device
whismanoid 1:77f1ee332e4a 475 void MAX11131::Init(void)
whismanoid 1:77f1ee332e4a 476 {
whismanoid 1:77f1ee332e4a 477
whismanoid 1:77f1ee332e4a 478 //----------------------------------------
whismanoid 1:77f1ee332e4a 479 // Nominal Full-Scale Voltage Reference
whismanoid 1:77f1ee332e4a 480 VRef = 2.500;
whismanoid 1:77f1ee332e4a 481
whismanoid 1:77f1ee332e4a 482 //----------------------------------------
whismanoid 1:77f1ee332e4a 483 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 484 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 485 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 486 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 487 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 488 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 489 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 490 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 491
whismanoid 1:77f1ee332e4a 492 //----------------------------------------
whismanoid 1:77f1ee332e4a 493 // define write-only register ADC_CONFIGURATION
whismanoid 1:77f1ee332e4a 494 ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid 1:77f1ee332e4a 495 const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid 1:77f1ee332e4a 496 const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid 1:77f1ee332e4a 497 const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid 1:77f1ee332e4a 498 const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid 1:77f1ee332e4a 499 const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid 1:77f1ee332e4a 500 const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid 1:77f1ee332e4a 501
whismanoid 1:77f1ee332e4a 502 //----------------------------------------
whismanoid 1:77f1ee332e4a 503 // define write-only registers UNIPOLAR,BIPOLAR,RANGE
whismanoid 1:77f1ee332e4a 504 UNIPOLAR = 0x8800; //!< mosiData16 0x8800..0x8FFF format: 1 0 0 0 1 UCH0/1 UCH2/3 UCH4/5 UCH6/7 UCH8/9 UCH10/11 UCH12/13 UCH14/15 PDIFF_COM x x
whismanoid 1:77f1ee332e4a 505 BIPOLAR = 0x9000; //!< mosiData16 0x9000..0x97FF format: 1 0 0 1 0 BCH0/1 BCH2/3 BCH4/5 BCH6/7 BCH8/9 BCH10/11 BCH12/13 BCH14/15 x x x
whismanoid 1:77f1ee332e4a 506 RANGE = 0x9800; //!< mosiData16 0x9800..0x9FFF format: 1 0 0 1 1 RANGE0/1 RANGE2/3 RANGE4/5 RANGE6/7 RANGE8/9 RANGE10/11 RANGE12/13 RANGE14/15 x x x
whismanoid 1:77f1ee332e4a 507 const int AIN_0_1_LSB = 10; // UNIPOLAR.UCH0/1 BIPOLAR.BCH0/1 RANGE.RANGE0/1
whismanoid 1:77f1ee332e4a 508 const int AIN_2_3_LSB = 9; // UNIPOLAR.UCH2/3 BIPOLAR.BCH2/3 RANGE.RANGE2/3
whismanoid 1:77f1ee332e4a 509 const int AIN_4_5_LSB = 8; // UNIPOLAR.UCH4/5 BIPOLAR.BCH4/5 RANGE.RANGE4/5
whismanoid 1:77f1ee332e4a 510 const int AIN_6_7_LSB = 7; // UNIPOLAR.UCH6/7 BIPOLAR.BCH6/7 RANGE.RANGE6/7
whismanoid 1:77f1ee332e4a 511 const int AIN_8_9_LSB = 6; // UNIPOLAR.UCH8/9 BIPOLAR.BCH8/9 RANGE.RANGE8/9
whismanoid 1:77f1ee332e4a 512 const int AIN_10_11_LSB = 5; // UNIPOLAR.UCH10/11 BIPOLAR.BCH10/11 RANGE.RANGE10/11
whismanoid 1:77f1ee332e4a 513 const int AIN_12_13_LSB = 4; // UNIPOLAR.UCH12/13 BIPOLAR.BCH12/13 RANGE.RANGE12/13
whismanoid 1:77f1ee332e4a 514 const int AIN_14_15_LSB = 3; // UNIPOLAR.UCH14/15 BIPOLAR.BCH14/15 RANGE.RANGE14/15
whismanoid 1:77f1ee332e4a 515 const int PDIFF_COMM_LSB = 2; const int PDIFF_COMM_BITS = 0x01; // UNIPOLAR.PDIFF_COM
whismanoid 1:77f1ee332e4a 516 // Summary of Table 8:
whismanoid 1:77f1ee332e4a 517 // UCH0/1=0, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 518 // UCH0/1=1, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 519 // UCH0/1=0, BCH0/1=1, RANGE0/1=0: AIN0/AIN1 differential input pair ±½Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 520 // UCH0/1=1, BCH0/1=1, RANGE0/1=0: reserved do not use
whismanoid 1:77f1ee332e4a 521 // UCH0/1=0, BCH0/1=0, RANGE0/1=1: reserved do not use
whismanoid 1:77f1ee332e4a 522 // UCH0/1=1, BCH0/1=0, RANGE0/1=1: reserved do not use
whismanoid 1:77f1ee332e4a 523 // UCH0/1=0, BCH0/1=1, RANGE0/1=1: AIN0/AIN1 differential input pair ±Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 524 // UCH0/1=1, BCH0/1=1, RANGE0/1=1: reserved do not use
whismanoid 1:77f1ee332e4a 525 // Both channels of a differential pair must be within Input Voltage Range (dynamic signal range) 0..VREF.
whismanoid 1:77f1ee332e4a 526
whismanoid 1:77f1ee332e4a 527 //----------------------------------------
whismanoid 1:77f1ee332e4a 528 // define write-only registers CSCAN0,CSCAN1
whismanoid 1:77f1ee332e4a 529 CSCAN0 = 0xA000; //!< mosiData16 0xA000..0xA7FF format: 1 0 1 0 0 CHSCAN15 CHSCAN14 CHSCAN13 CHSCAN12 CHSCAN11 CHSCAN10 CHSCAN9 CHSCAN8 x x x
whismanoid 1:77f1ee332e4a 530 const int CHSCAN15_LSB = 10; // CSCAN0.CHSCAN15
whismanoid 1:77f1ee332e4a 531 const int CHSCAN14_LSB = 9; // CSCAN0.CHSCAN14
whismanoid 1:77f1ee332e4a 532 const int CHSCAN13_LSB = 8; // CSCAN0.CHSCAN13
whismanoid 1:77f1ee332e4a 533 const int CHSCAN12_LSB = 7; // CSCAN0.CHSCAN12
whismanoid 1:77f1ee332e4a 534 const int CHSCAN11_LSB = 6; // CSCAN0.CHSCAN11
whismanoid 1:77f1ee332e4a 535 const int CHSCAN10_LSB = 5; // CSCAN0.CHSCAN10
whismanoid 1:77f1ee332e4a 536 const int CHSCAN9_LSB = 4; // CSCAN0.CHSCAN9
whismanoid 1:77f1ee332e4a 537 const int CHSCAN8_LSB = 3; // CSCAN0.CHSCAN8
whismanoid 1:77f1ee332e4a 538 CSCAN1 = 0xA800; //!< mosiData16 0xA800..0xAFFF format: 1 0 1 0 1 CHSCAN7 CHSCAN6 CHSCAN5 CHSCAN4 CHSCAN3 CHSCAN2 CHSCAN1 CHSCAN0 x x x
whismanoid 1:77f1ee332e4a 539 const int CHSCAN7_LSB = 10; // CSCAN1.CHSCAN7
whismanoid 1:77f1ee332e4a 540 const int CHSCAN6_LSB = 9; // CSCAN1.CHSCAN6
whismanoid 1:77f1ee332e4a 541 const int CHSCAN5_LSB = 8; // CSCAN1.CHSCAN5
whismanoid 1:77f1ee332e4a 542 const int CHSCAN4_LSB = 7; // CSCAN1.CHSCAN4
whismanoid 1:77f1ee332e4a 543 const int CHSCAN3_LSB = 6; // CSCAN1.CHSCAN3
whismanoid 1:77f1ee332e4a 544 const int CHSCAN2_LSB = 5; // CSCAN1.CHSCAN2
whismanoid 1:77f1ee332e4a 545 const int CHSCAN1_LSB = 4; // CSCAN1.CHSCAN1
whismanoid 1:77f1ee332e4a 546 const int CHSCAN0_LSB = 3; // CSCAN1.CHSCAN0
whismanoid 1:77f1ee332e4a 547
whismanoid 1:77f1ee332e4a 548 //----------------------------------------
whismanoid 1:77f1ee332e4a 549 // Initialize shadow of write-only register SAMPLESET.
whismanoid 1:77f1ee332e4a 550 // Do not write to SAMPLESET at this time.
whismanoid 1:77f1ee332e4a 551 // A write to SAMPLESET must be followed by specified number of pattern entry words.
whismanoid 1:77f1ee332e4a 552 // See ScanSampleSetExternalClock function for details.
whismanoid 1:77f1ee332e4a 553 SAMPLESET = 0xB000; //!< mosiData16 0xB000..0xB7FF format: 1 0 1 1 0 SEQ_LENGTH[7:0] x x x
whismanoid 1:77f1ee332e4a 554 const int SAMPLESET_LSB = 3; const int SAMPLESET_BITS = 0xFF; // SAMPLESET.SEQ_LENGTH[7:0]
whismanoid 1:77f1ee332e4a 555
whismanoid 1:77f1ee332e4a 556 //----------------------------------------
whismanoid 1:77f1ee332e4a 557 // Reset all registers: ADC_MODE_CONTROL.RESET[1:0] = 2
whismanoid 1:77f1ee332e4a 558 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 559 ADC_MODE_CONTROL |= ((2 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 560
whismanoid 1:77f1ee332e4a 561 //----------------------------------------
whismanoid 1:77f1ee332e4a 562 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 563 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 564 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 565 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 566 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 567 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 568
whismanoid 1:77f1ee332e4a 569 #if REFSEL_0
whismanoid 1:77f1ee332e4a 570
whismanoid 1:77f1ee332e4a 571 //----------------------------------------
whismanoid 1:77f1ee332e4a 572 // Global setting for all channels: ADC_CONFIGURATION.REFSEL=0: external single-ended reference
whismanoid 1:77f1ee332e4a 573 // SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL
whismanoid 1:77f1ee332e4a 574 // SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL: EXTERNAL SINGLE-ENDED
whismanoid 1:77f1ee332e4a 575 // SELECT ADC CONFIGURATION register set REFSEL BIT TO 0
whismanoid 1:77f1ee332e4a 576 ADC_CONFIGURATION &= ~ (( REFSEL_BITS) << REFSEL_LSB); // ADC_CONFIGURATION.REFSEL=0: external single-ended reference. (For the 16-channel chips: channel AIN15 is available.)
whismanoid 1:77f1ee332e4a 577 #endif // REFSEL_0
whismanoid 1:77f1ee332e4a 578
whismanoid 1:77f1ee332e4a 579 #if REFSEL_1
whismanoid 1:77f1ee332e4a 580
whismanoid 1:77f1ee332e4a 581 //----------------------------------------
whismanoid 1:77f1ee332e4a 582 // Global setting for all channels: ADC_CONFIGURATION.REFSEL=1: external differential reference (For the 16-channel chips: channel AIN15 is unavailable, the pin is assigned to REF-.)
whismanoid 1:77f1ee332e4a 583 // SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL
whismanoid 1:77f1ee332e4a 584 // SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL: EXTERNAL DIFFERENTIAL
whismanoid 1:77f1ee332e4a 585 // SELECT ADC CONFIGURATION register set REFSEL BIT TO 1
whismanoid 1:77f1ee332e4a 586 ADC_CONFIGURATION |= ((1 & REFSEL_BITS) << REFSEL_LSB); // ADC_CONFIGURATION.REFSEL=1: external differential reference. (For the 16-channel chips: channel AIN15 is unavailable, the pin is assigned to REF-.)
whismanoid 1:77f1ee332e4a 587 #endif // REFSEL_1
whismanoid 1:77f1ee332e4a 588
whismanoid 1:77f1ee332e4a 589 #if PDIFF_COMM_0
whismanoid 1:77f1ee332e4a 590
whismanoid 1:77f1ee332e4a 591 //----------------------------------------
whismanoid 1:77f1ee332e4a 592 // Global setting for all channels: PDIFF_COMM
whismanoid 1:77f1ee332e4a 593 UNIPOLAR &= ~ (( PDIFF_COMM_BITS) << PDIFF_COMM_LSB); // UNIPOLAR.PDIFF_COMM=0: all single-ended channels use GND as common
whismanoid 1:77f1ee332e4a 594 #endif // PDIFF_COMM_0
whismanoid 1:77f1ee332e4a 595
whismanoid 1:77f1ee332e4a 596 #if PDIFF_COMM_1
whismanoid 1:77f1ee332e4a 597
whismanoid 1:77f1ee332e4a 598 //----------------------------------------
whismanoid 1:77f1ee332e4a 599 // Global setting for all channels: PDIFF_COMM
whismanoid 1:77f1ee332e4a 600 // SELECT UNIPOLAR AND register set BIT PDIFF_COM TO 1 FOR PSEUDODIFFERENTIAL SELECTION
whismanoid 1:77f1ee332e4a 601 UNIPOLAR |= ((1 & PDIFF_COMM_BITS) << PDIFF_COMM_LSB); // UNIPOLAR.PDIFF_COMM=1: all single-ended channels are pseudo-differential with REF- as common
whismanoid 1:77f1ee332e4a 602 #endif // PDIFF_COMM_1
whismanoid 1:77f1ee332e4a 603
whismanoid 1:77f1ee332e4a 604 #if AIN_0_1_SingleEnded
whismanoid 1:77f1ee332e4a 605
whismanoid 1:77f1ee332e4a 606 //----------------------------------------
whismanoid 1:77f1ee332e4a 607 // ADC Channels AIN0, AIN1 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 608 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 609 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 610 // AIN0 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 611 // AIN1 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 612 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 613 // AIN0 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 614 // AIN1 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 615 //
whismanoid 1:77f1ee332e4a 616 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 617 UNIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 618 BIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 619 RANGE &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 620 // UCH0/1=0, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 621 #endif // AIN_0_1_SingleEnded
whismanoid 1:77f1ee332e4a 622
whismanoid 1:77f1ee332e4a 623 #if AIN_0_1_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 624
whismanoid 1:77f1ee332e4a 625 //----------------------------------------
whismanoid 1:77f1ee332e4a 626 // ADC Channels AIN0, AIN1 = Differential Unipolar (AIN0 > AIN1)
whismanoid 1:77f1ee332e4a 627 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 628 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 629 // AIN0, AIN1 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 630 // AIN0 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 631 // AIN1 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 632 //
whismanoid 1:77f1ee332e4a 633 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 634 UNIPOLAR |= (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 635 BIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 636 RANGE &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 637 // UCH0/1=1, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 638 #endif // AIN_0_1_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 639
whismanoid 1:77f1ee332e4a 640 #if AIN_0_1_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 641
whismanoid 1:77f1ee332e4a 642 //----------------------------------------
whismanoid 1:77f1ee332e4a 643 // ADC Channels AIN0, AIN1 = Differential Bipolar
whismanoid 1:77f1ee332e4a 644 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 645 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 646 // AIN0, AIN1 are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid 1:77f1ee332e4a 647 // AIN0 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 648 // AIN1 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 649 //
whismanoid 1:77f1ee332e4a 650 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 651 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 652 UNIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 653 BIPOLAR |= (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 654 RANGE &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 655 // UCH0/1=0, BCH0/1=1, RANGE0/1=0: AIN0/AIN1 differential input pair ±½Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 656 #endif // AIN_0_1_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 657
whismanoid 1:77f1ee332e4a 658 #if AIN_0_1_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 659
whismanoid 1:77f1ee332e4a 660 //----------------------------------------
whismanoid 1:77f1ee332e4a 661 // ADC Channels AIN0, AIN1 = Differential Bipolar
whismanoid 1:77f1ee332e4a 662 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 663 // Voltage per LSB count = VREF/2048
whismanoid 1:77f1ee332e4a 664 // AIN0, AIN1 are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid 1:77f1ee332e4a 665 // AIN0 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 666 // AIN1 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 667 //
whismanoid 1:77f1ee332e4a 668 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 669 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 670 UNIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 671 BIPOLAR |= (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 672 RANGE |= (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 673 // UCH0/1=0, BCH0/1=1, RANGE0/1=1: AIN0/AIN1 differential input pair ±Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 674 #endif // AIN_0_1_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 675
whismanoid 1:77f1ee332e4a 676 #if AIN_2_3_SingleEnded
whismanoid 1:77f1ee332e4a 677
whismanoid 1:77f1ee332e4a 678 //----------------------------------------
whismanoid 1:77f1ee332e4a 679 // ADC Channels AIN2, AIN3 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 680 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 681 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 682 // AIN2 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 683 // AIN3 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 684 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 685 // AIN2 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 686 // AIN3 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 687 //
whismanoid 1:77f1ee332e4a 688 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 689 UNIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 690 BIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 691 RANGE &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 692 // UCH2/3=0, BCH2/3=0, RANGE2/3=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 693 #endif // AIN_2_3_SingleEnded
whismanoid 1:77f1ee332e4a 694
whismanoid 1:77f1ee332e4a 695 #if AIN_2_3_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 696
whismanoid 1:77f1ee332e4a 697 //----------------------------------------
whismanoid 1:77f1ee332e4a 698 // ADC Channels AIN2, AIN3 = Differential Unipolar (AIN2 > AIN3)
whismanoid 1:77f1ee332e4a 699 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 700 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 701 // AIN2, AIN3 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 702 // AIN2 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 703 // AIN3 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 704 //
whismanoid 1:77f1ee332e4a 705 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 706 UNIPOLAR |= (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 707 BIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 708 RANGE &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 709 // UCH2/3=1, BCH2/3=0, RANGE2/3=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 710 #endif // AIN_2_3_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 711
whismanoid 1:77f1ee332e4a 712 #if AIN_2_3_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 713
whismanoid 1:77f1ee332e4a 714 //----------------------------------------
whismanoid 1:77f1ee332e4a 715 // ADC Channels AIN2, AIN3 = Differential Bipolar
whismanoid 1:77f1ee332e4a 716 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 717 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 718 // AIN2, AIN3 are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid 1:77f1ee332e4a 719 // AIN2 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 720 // AIN3 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 721 //
whismanoid 1:77f1ee332e4a 722 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 723 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 724 UNIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 725 BIPOLAR |= (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 726 RANGE &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 727 // UCH2/3=0, BCH2/3=1, RANGE2/3=0: AIN0/AIN1 differential input pair ±½Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 728 #endif // AIN_2_3_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 729
whismanoid 1:77f1ee332e4a 730 #if AIN_2_3_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 731
whismanoid 1:77f1ee332e4a 732 //----------------------------------------
whismanoid 1:77f1ee332e4a 733 // ADC Channels AIN2, AIN3 = Differential Bipolar
whismanoid 1:77f1ee332e4a 734 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 735 // Voltage per LSB count = VREF/2048
whismanoid 1:77f1ee332e4a 736 // AIN2, AIN3 are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid 1:77f1ee332e4a 737 // AIN2 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 738 // AIN3 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 739 //
whismanoid 1:77f1ee332e4a 740 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 741 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 742 UNIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 743 BIPOLAR |= (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 744 RANGE |= (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 745 // UCH2/3=0, BCH2/3=1, RANGE2/3=1: AIN0/AIN1 differential input pair ±Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 746 #endif // AIN_2_3_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 747
whismanoid 1:77f1ee332e4a 748 #if AIN_4_5_SingleEnded
whismanoid 1:77f1ee332e4a 749
whismanoid 1:77f1ee332e4a 750 //----------------------------------------
whismanoid 1:77f1ee332e4a 751 // ADC Channels AIN4, AIN5 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 752 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 753 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 754 // AIN4 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 755 // AIN5 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 756 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 757 // AIN4 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 758 // AIN5 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 759 //
whismanoid 1:77f1ee332e4a 760 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 761 UNIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 762 BIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 763 RANGE &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 764 // UCH4/5=0, BCH4/5=0, RANGE4/5=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 765 #endif // AIN_4_5_SingleEnded
whismanoid 1:77f1ee332e4a 766
whismanoid 1:77f1ee332e4a 767 #if AIN_4_5_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 768
whismanoid 1:77f1ee332e4a 769 //----------------------------------------
whismanoid 1:77f1ee332e4a 770 // ADC Channels AIN4, AIN5 = Differential Unipolar (AIN4 > AIN5)
whismanoid 1:77f1ee332e4a 771 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 772 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 773 // AIN4, AIN5 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 774 // AIN4 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 775 // AIN5 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 776 //
whismanoid 1:77f1ee332e4a 777 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 778 UNIPOLAR |= (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 779 BIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 780 RANGE &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 781 // UCH4/5=1, BCH4/5=0, RANGE4/5=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 782 #endif // AIN_4_5_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 783
whismanoid 1:77f1ee332e4a 784 #if AIN_4_5_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 785
whismanoid 1:77f1ee332e4a 786 //----------------------------------------
whismanoid 1:77f1ee332e4a 787 // ADC Channels AIN4, AIN5 = Differential Bipolar
whismanoid 1:77f1ee332e4a 788 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 789 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 790 // AIN4, AIN5 are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid 1:77f1ee332e4a 791 // AIN4 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 792 // AIN5 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 793 //
whismanoid 1:77f1ee332e4a 794 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 795 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 796 UNIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 797 BIPOLAR |= (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 798 RANGE &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 799 // UCH4/5=0, BCH4/5=1, RANGE4/5=0: AIN0/AIN1 differential input pair ±½Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 800 #endif // AIN_4_5_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 801
whismanoid 1:77f1ee332e4a 802 #if AIN_4_5_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 803
whismanoid 1:77f1ee332e4a 804 //----------------------------------------
whismanoid 1:77f1ee332e4a 805 // ADC Channels AIN4, AIN5 = Differential Bipolar
whismanoid 1:77f1ee332e4a 806 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 807 // Voltage per LSB count = VREF/2048
whismanoid 1:77f1ee332e4a 808 // AIN4, AIN5 are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid 1:77f1ee332e4a 809 // AIN4 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 810 // AIN5 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 811 //
whismanoid 1:77f1ee332e4a 812 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 813 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 814 UNIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 815 BIPOLAR |= (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 816 RANGE |= (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 817 // UCH4/5=0, BCH4/5=1, RANGE4/5=1: AIN0/AIN1 differential input pair ±Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 818 #endif // AIN_4_5_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 819
whismanoid 1:77f1ee332e4a 820 #if AIN_6_7_SingleEnded
whismanoid 1:77f1ee332e4a 821
whismanoid 1:77f1ee332e4a 822 //----------------------------------------
whismanoid 1:77f1ee332e4a 823 // ADC Channels AIN6, AIN7 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 824 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 825 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 826 // AIN6 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 827 // AIN7 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 828 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 829 // AIN6 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 830 // AIN7 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 831 //
whismanoid 1:77f1ee332e4a 832 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 833 UNIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 834 BIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 835 RANGE &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 836 // UCH6/7=0, BCH6/7=0, RANGE6/7=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 837 #endif // AIN_6_7_SingleEnded
whismanoid 1:77f1ee332e4a 838
whismanoid 1:77f1ee332e4a 839 #if AIN_6_7_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 840
whismanoid 1:77f1ee332e4a 841 //----------------------------------------
whismanoid 1:77f1ee332e4a 842 // ADC Channels AIN6, AIN7 = Differential Unipolar (AIN6 > AIN7)
whismanoid 1:77f1ee332e4a 843 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 844 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 845 // AIN6, AIN7 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 846 // AIN6 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 847 // AIN7 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 848 //
whismanoid 1:77f1ee332e4a 849 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 850 UNIPOLAR |= (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 851 BIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 852 RANGE &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 853 // UCH6/7=1, BCH6/7=0, RANGE6/7=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 854 #endif // AIN_6_7_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 855
whismanoid 1:77f1ee332e4a 856 #if AIN_6_7_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 857
whismanoid 1:77f1ee332e4a 858 //----------------------------------------
whismanoid 1:77f1ee332e4a 859 // ADC Channels AIN6, AIN7 = Differential Bipolar
whismanoid 1:77f1ee332e4a 860 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 861 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 862 // AIN6, AIN7 are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid 1:77f1ee332e4a 863 // AIN6 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 864 // AIN7 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 865 //
whismanoid 1:77f1ee332e4a 866 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 867 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 868 UNIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 869 BIPOLAR |= (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 870 RANGE &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 871 // UCH6/7=0, BCH6/7=1, RANGE6/7=0: AIN0/AIN1 differential input pair ±½Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 872 #endif // AIN_6_7_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 873
whismanoid 1:77f1ee332e4a 874 #if AIN_6_7_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 875
whismanoid 1:77f1ee332e4a 876 //----------------------------------------
whismanoid 1:77f1ee332e4a 877 // ADC Channels AIN6, AIN7 = Differential Bipolar
whismanoid 1:77f1ee332e4a 878 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 879 // Voltage per LSB count = VREF/2048
whismanoid 1:77f1ee332e4a 880 // AIN6, AIN7 are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid 1:77f1ee332e4a 881 // AIN6 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 882 // AIN7 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 883 //
whismanoid 1:77f1ee332e4a 884 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 885 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 886 UNIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 887 BIPOLAR |= (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 888 RANGE |= (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 889 // UCH6/7=0, BCH6/7=1, RANGE6/7=1: AIN0/AIN1 differential input pair ±Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 890 #endif // AIN_6_7_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 891
whismanoid 1:77f1ee332e4a 892 #if AIN_8_9_SingleEnded
whismanoid 1:77f1ee332e4a 893
whismanoid 1:77f1ee332e4a 894 //----------------------------------------
whismanoid 1:77f1ee332e4a 895 // ADC Channels AIN8, AIN9 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 896 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 897 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 898 // AIN8 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 899 // AIN9 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 900 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 901 // AIN8 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 902 // AIN9 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 903 //
whismanoid 1:77f1ee332e4a 904 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 905 UNIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 906 BIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 907 RANGE &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 908 // UCH8/9=0, BCH8/9=0, RANGE8/9=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 909 #endif // AIN_8_9_SingleEnded
whismanoid 1:77f1ee332e4a 910
whismanoid 1:77f1ee332e4a 911 #if AIN_8_9_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 912
whismanoid 1:77f1ee332e4a 913 //----------------------------------------
whismanoid 1:77f1ee332e4a 914 // ADC Channels AIN8, AIN9 = Differential Unipolar (AIN8 > AIN9)
whismanoid 1:77f1ee332e4a 915 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 916 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 917 // AIN8, AIN9 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 918 // AIN8 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 919 // AIN9 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 920 //
whismanoid 1:77f1ee332e4a 921 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 922 UNIPOLAR |= (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 923 BIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 924 RANGE &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 925 // UCH8/9=1, BCH8/9=0, RANGE8/9=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 926 #endif // AIN_8_9_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 927
whismanoid 1:77f1ee332e4a 928 #if AIN_8_9_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 929
whismanoid 1:77f1ee332e4a 930 //----------------------------------------
whismanoid 1:77f1ee332e4a 931 // ADC Channels AIN8, AIN9 = Differential Bipolar
whismanoid 1:77f1ee332e4a 932 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 933 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 934 // AIN8, AIN9 are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid 1:77f1ee332e4a 935 // AIN8 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 936 // AIN9 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 937 //
whismanoid 1:77f1ee332e4a 938 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 939 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 940 UNIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 941 BIPOLAR |= (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 942 RANGE &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 943 // UCH8/9=0, BCH8/9=1, RANGE8/9=0: AIN0/AIN1 differential input pair ±½Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 944 #endif // AIN_8_9_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 945
whismanoid 1:77f1ee332e4a 946 #if AIN_8_9_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 947
whismanoid 1:77f1ee332e4a 948 //----------------------------------------
whismanoid 1:77f1ee332e4a 949 // ADC Channels AIN8, AIN9 = Differential Bipolar
whismanoid 1:77f1ee332e4a 950 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 951 // Voltage per LSB count = VREF/2048
whismanoid 1:77f1ee332e4a 952 // AIN8, AIN9 are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid 1:77f1ee332e4a 953 // AIN8 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 954 // AIN9 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 955 //
whismanoid 1:77f1ee332e4a 956 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 957 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 958 UNIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 959 BIPOLAR |= (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 960 RANGE |= (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 961 // UCH8/9=0, BCH8/9=1, RANGE8/9=1: AIN0/AIN1 differential input pair ±Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 962 #endif // AIN_8_9_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 963
whismanoid 1:77f1ee332e4a 964 #if AIN_10_11_SingleEnded
whismanoid 1:77f1ee332e4a 965
whismanoid 1:77f1ee332e4a 966 //----------------------------------------
whismanoid 1:77f1ee332e4a 967 // ADC Channels AIN10, AIN11 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 968 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 969 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 970 // AIN10 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 971 // AIN11 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 972 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 973 // AIN10 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 974 // AIN11 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 975 //
whismanoid 1:77f1ee332e4a 976 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 977 UNIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 978 BIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 979 RANGE &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 980 // UCH10/11=0, BCH10/11=0, RANGE10/11=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 981 #endif // AIN_10_11_SingleEnded
whismanoid 1:77f1ee332e4a 982
whismanoid 1:77f1ee332e4a 983 #if AIN_10_11_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 984
whismanoid 1:77f1ee332e4a 985 //----------------------------------------
whismanoid 1:77f1ee332e4a 986 // ADC Channels AIN10, AIN11 = Differential Unipolar (AIN10 > AIN11)
whismanoid 1:77f1ee332e4a 987 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 988 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 989 // AIN10, AIN11 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 990 // AIN10 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 991 // AIN11 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 992 //
whismanoid 1:77f1ee332e4a 993 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 994 UNIPOLAR |= (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 995 BIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 996 RANGE &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 997 // UCH10/11=1, BCH10/11=0, RANGE10/11=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 998 #endif // AIN_10_11_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 999
whismanoid 1:77f1ee332e4a 1000 #if AIN_10_11_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1001
whismanoid 1:77f1ee332e4a 1002 //----------------------------------------
whismanoid 1:77f1ee332e4a 1003 // ADC Channels AIN10, AIN11 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1004 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1005 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1006 // AIN10, AIN11 are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid 1:77f1ee332e4a 1007 // AIN10 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1008 // AIN11 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1009 //
whismanoid 1:77f1ee332e4a 1010 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1011 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 1012 UNIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1013 BIPOLAR |= (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1014 RANGE &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1015 // UCH10/11=0, BCH10/11=1, RANGE10/11=0: AIN0/AIN1 differential input pair ±½Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1016 #endif // AIN_10_11_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1017
whismanoid 1:77f1ee332e4a 1018 #if AIN_10_11_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1019
whismanoid 1:77f1ee332e4a 1020 //----------------------------------------
whismanoid 1:77f1ee332e4a 1021 // ADC Channels AIN10, AIN11 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1022 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1023 // Voltage per LSB count = VREF/2048
whismanoid 1:77f1ee332e4a 1024 // AIN10, AIN11 are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid 1:77f1ee332e4a 1025 // AIN10 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1026 // AIN11 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1027 //
whismanoid 1:77f1ee332e4a 1028 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1029 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 1030 UNIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1031 BIPOLAR |= (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1032 RANGE |= (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1033 // UCH10/11=0, BCH10/11=1, RANGE10/11=1: AIN0/AIN1 differential input pair ±Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1034 #endif // AIN_10_11_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1035
whismanoid 1:77f1ee332e4a 1036 #if AIN_12_13_SingleEnded
whismanoid 1:77f1ee332e4a 1037
whismanoid 1:77f1ee332e4a 1038 //----------------------------------------
whismanoid 1:77f1ee332e4a 1039 // ADC Channels AIN12, AIN13 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 1040 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1041 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1042 // AIN12 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1043 // AIN13 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1044 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 1045 // AIN12 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1046 // AIN13 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1047 //
whismanoid 1:77f1ee332e4a 1048 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 1049 UNIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1050 BIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1051 RANGE &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1052 // UCH12/13=0, BCH12/13=0, RANGE12/13=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1053 #endif // AIN_12_13_SingleEnded
whismanoid 1:77f1ee332e4a 1054
whismanoid 1:77f1ee332e4a 1055 #if AIN_12_13_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1056
whismanoid 1:77f1ee332e4a 1057 //----------------------------------------
whismanoid 1:77f1ee332e4a 1058 // ADC Channels AIN12, AIN13 = Differential Unipolar (AIN12 > AIN13)
whismanoid 1:77f1ee332e4a 1059 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1060 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1061 // AIN12, AIN13 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1062 // AIN12 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1063 // AIN13 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1064 //
whismanoid 1:77f1ee332e4a 1065 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 1066 UNIPOLAR |= (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1067 BIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1068 RANGE &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1069 // UCH12/13=1, BCH12/13=0, RANGE12/13=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1070 #endif // AIN_12_13_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1071
whismanoid 1:77f1ee332e4a 1072 #if AIN_12_13_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1073
whismanoid 1:77f1ee332e4a 1074 //----------------------------------------
whismanoid 1:77f1ee332e4a 1075 // ADC Channels AIN12, AIN13 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1076 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1077 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1078 // AIN12, AIN13 are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid 1:77f1ee332e4a 1079 // AIN12 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1080 // AIN13 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1081 //
whismanoid 1:77f1ee332e4a 1082 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1083 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 1084 UNIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1085 BIPOLAR |= (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1086 RANGE &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1087 // UCH12/13=0, BCH12/13=1, RANGE12/13=0: AIN0/AIN1 differential input pair ±½Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1088 #endif // AIN_12_13_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1089
whismanoid 1:77f1ee332e4a 1090 #if AIN_12_13_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1091
whismanoid 1:77f1ee332e4a 1092 //----------------------------------------
whismanoid 1:77f1ee332e4a 1093 // ADC Channels AIN12, AIN13 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1094 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1095 // Voltage per LSB count = VREF/2048
whismanoid 1:77f1ee332e4a 1096 // AIN12, AIN13 are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid 1:77f1ee332e4a 1097 // AIN12 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1098 // AIN13 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1099 //
whismanoid 1:77f1ee332e4a 1100 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1101 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 1102 UNIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1103 BIPOLAR |= (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1104 RANGE |= (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1105 // UCH12/13=0, BCH12/13=1, RANGE12/13=1: AIN0/AIN1 differential input pair ±Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1106 #endif // AIN_12_13_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1107
whismanoid 1:77f1ee332e4a 1108 #if AIN_14_15_SingleEnded
whismanoid 1:77f1ee332e4a 1109
whismanoid 1:77f1ee332e4a 1110 //----------------------------------------
whismanoid 1:77f1ee332e4a 1111 // ADC Channels AIN14, AIN15 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 1112 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1113 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1114 // AIN14 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1115 // AIN15 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1116 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 1117 // AIN14 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1118 // AIN15 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1119 //
whismanoid 1:77f1ee332e4a 1120 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 1121 UNIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1122 BIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1123 RANGE &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1124 // UCH14/15=0, BCH14/15=0, RANGE14/15=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1125 #endif // AIN_14_15_SingleEnded
whismanoid 1:77f1ee332e4a 1126
whismanoid 1:77f1ee332e4a 1127 #if AIN_14_15_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1128
whismanoid 1:77f1ee332e4a 1129 //----------------------------------------
whismanoid 1:77f1ee332e4a 1130 // ADC Channels AIN14, AIN15 = Differential Unipolar (AIN14 > AIN15)
whismanoid 1:77f1ee332e4a 1131 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1132 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1133 // AIN14, AIN15 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1134 // AIN14 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1135 // AIN15 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1136 //
whismanoid 1:77f1ee332e4a 1137 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 1138 UNIPOLAR |= (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1139 BIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1140 RANGE &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1141 // UCH14/15=1, BCH14/15=0, RANGE14/15=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1142 #endif // AIN_14_15_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1143
whismanoid 1:77f1ee332e4a 1144 #if AIN_14_15_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1145
whismanoid 1:77f1ee332e4a 1146 //----------------------------------------
whismanoid 1:77f1ee332e4a 1147 // ADC Channels AIN14, AIN15 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1148 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1149 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1150 // AIN14, AIN15 are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid 1:77f1ee332e4a 1151 // AIN14 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1152 // AIN15 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1153 //
whismanoid 1:77f1ee332e4a 1154 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1155 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 1156 UNIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1157 BIPOLAR |= (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1158 RANGE &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1159 // UCH14/15=0, BCH14/15=1, RANGE14/15=0: AIN0/AIN1 differential input pair ±½Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1160 #endif // AIN_14_15_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1161
whismanoid 1:77f1ee332e4a 1162 #if AIN_14_15_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1163
whismanoid 1:77f1ee332e4a 1164 //----------------------------------------
whismanoid 1:77f1ee332e4a 1165 // ADC Channels AIN14, AIN15 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1166 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1167 // Voltage per LSB count = VREF/2048
whismanoid 1:77f1ee332e4a 1168 // AIN14, AIN15 are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid 1:77f1ee332e4a 1169 // AIN14 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1170 // AIN15 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1171 //
whismanoid 1:77f1ee332e4a 1172 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1173 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 1174 UNIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1175 BIPOLAR |= (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1176 RANGE |= (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1177 // UCH14/15=0, BCH14/15=1, RANGE14/15=1: AIN0/AIN1 differential input pair ±Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1178 #endif // AIN_14_15_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1179
whismanoid 1:77f1ee332e4a 1180 //----------------------------------------
whismanoid 1:77f1ee332e4a 1181 // SPI write ADC CONFIGURATION register
whismanoid 1:77f1ee332e4a 1182 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 1183 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1184 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1185 SPIwrite16bits(ADC_CONFIGURATION);
whismanoid 1:77f1ee332e4a 1186 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1187
whismanoid 1:77f1ee332e4a 1188 //----------------------------------------
whismanoid 1:77f1ee332e4a 1189 // SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid 1:77f1ee332e4a 1190 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1191 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1192 SPIwrite16bits(UNIPOLAR);
whismanoid 1:77f1ee332e4a 1193 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1194 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1195 SPIwrite16bits(BIPOLAR);
whismanoid 1:77f1ee332e4a 1196 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1197 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1198 SPIwrite16bits(RANGE);
whismanoid 1:77f1ee332e4a 1199 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1200
whismanoid 1:77f1ee332e4a 1201 //----------------------------------------
whismanoid 1:77f1ee332e4a 1202 // SPI write CSCAN0 CSCAN1 registers
whismanoid 1:77f1ee332e4a 1203 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1204 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1205 SPIwrite16bits(CSCAN0);
whismanoid 1:77f1ee332e4a 1206 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1207 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1208 SPIwrite16bits(CSCAN1);
whismanoid 1:77f1ee332e4a 1209 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1210 }
whismanoid 1:77f1ee332e4a 1211
whismanoid 1:77f1ee332e4a 1212 //----------------------------------------
whismanoid 1:77f1ee332e4a 1213 // ADC Channels AIN(channelId), AIN(channelId+1) = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 1214 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1215 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1216 // AIN(channelId) is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1217 // AIN(channelId+1) is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1218 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 1219 // AIN(channelId) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1220 // AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1221 //
whismanoid 1:77f1ee332e4a 1222 void MAX11131::Reconfigure_SingleEnded(int channelNumber_0_15)
whismanoid 1:77f1ee332e4a 1223 {
whismanoid 1:77f1ee332e4a 1224
whismanoid 1:77f1ee332e4a 1225 //----------------------------------------
whismanoid 1:77f1ee332e4a 1226 // UCH(ch)/(ch+1)=0, BCH(ch)/(ch+1)=0, RANGE(ch)/(ch+1)=0:
whismanoid 1:77f1ee332e4a 1227 // AIN(ch)/AIN(ch+1) two independent single-ended inputs,
whismanoid 1:77f1ee332e4a 1228 // unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1229 //
whismanoid 1:77f1ee332e4a 1230 const int channelPairIndex = channelNumber_0_15 / 2;
whismanoid 1:77f1ee332e4a 1231 const int bitmask = (1 << (10 - channelPairIndex));
whismanoid 1:77f1ee332e4a 1232 UNIPOLAR &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1233 BIPOLAR &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1234 RANGE &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1235
whismanoid 1:77f1ee332e4a 1236 //----------------------------------------
whismanoid 1:77f1ee332e4a 1237 // SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid 1:77f1ee332e4a 1238 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1239 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1240 SPIwrite16bits(UNIPOLAR);
whismanoid 1:77f1ee332e4a 1241 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1242 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1243 SPIwrite16bits(BIPOLAR);
whismanoid 1:77f1ee332e4a 1244 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1245 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1246 SPIwrite16bits(RANGE);
whismanoid 1:77f1ee332e4a 1247 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1248 }
whismanoid 1:77f1ee332e4a 1249
whismanoid 1:77f1ee332e4a 1250 //----------------------------------------
whismanoid 1:77f1ee332e4a 1251 // ADC Channels AIN(channelId), AIN(channelId+1) = Differential Unipolar (AIN(channelId) > AIN(channelId+1))
whismanoid 1:77f1ee332e4a 1252 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1253 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1254 // AIN(channelId), AIN(channelId+1) are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1255 // AIN(channelId) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1256 // AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1257 //
whismanoid 1:77f1ee332e4a 1258 void MAX11131::Reconfigure_DifferentialUnipolar(int channelNumber_0_15)
whismanoid 1:77f1ee332e4a 1259 {
whismanoid 1:77f1ee332e4a 1260
whismanoid 1:77f1ee332e4a 1261 //----------------------------------------
whismanoid 1:77f1ee332e4a 1262 // UCH(ch)/(ch+1)=1, BCH(ch)/(ch+1)=0, RANGE(ch)/(ch+1)=0:
whismanoid 1:77f1ee332e4a 1263 // AIN(ch)/AIN(ch+1) differential input pair,
whismanoid 1:77f1ee332e4a 1264 // unipolar code (AIN(ch)>AIN(ch+1)) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1265 //
whismanoid 1:77f1ee332e4a 1266 const int channelPairIndex = channelNumber_0_15 / 2;
whismanoid 1:77f1ee332e4a 1267 const int bitmask = (1 << (10 - channelPairIndex));
whismanoid 1:77f1ee332e4a 1268 UNIPOLAR |= bitmask;
whismanoid 1:77f1ee332e4a 1269 BIPOLAR &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1270 RANGE &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1271 // UCH0/1=1, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1272
whismanoid 1:77f1ee332e4a 1273 //----------------------------------------
whismanoid 1:77f1ee332e4a 1274 // SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid 1:77f1ee332e4a 1275 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1276 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1277 SPIwrite16bits(UNIPOLAR);
whismanoid 1:77f1ee332e4a 1278 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1279 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1280 SPIwrite16bits(BIPOLAR);
whismanoid 1:77f1ee332e4a 1281 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1282 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1283 SPIwrite16bits(RANGE);
whismanoid 1:77f1ee332e4a 1284 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1285 }
whismanoid 1:77f1ee332e4a 1286
whismanoid 1:77f1ee332e4a 1287 //----------------------------------------
whismanoid 1:77f1ee332e4a 1288 // ADC Channels AIN(channelId), AIN(channelId+1) = Differential Bipolar
whismanoid 1:77f1ee332e4a 1289 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1290 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1291 // AIN(channelId), AIN(channelId+1) are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid 1:77f1ee332e4a 1292 // AIN(channelId) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1293 // AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1294 //
whismanoid 1:77f1ee332e4a 1295 void MAX11131::Reconfigure_DifferentialBipolarFSVref(int channelNumber_0_15)
whismanoid 1:77f1ee332e4a 1296 {
whismanoid 1:77f1ee332e4a 1297
whismanoid 1:77f1ee332e4a 1298 //----------------------------------------
whismanoid 1:77f1ee332e4a 1299 // UCH(ch)/(ch+1)=0, BCH(ch)/(ch+1)=1, RANGE(ch)/(ch+1)=0:
whismanoid 1:77f1ee332e4a 1300 // AIN(ch)/AIN(ch+1) differential input pair ±½Vref,
whismanoid 1:77f1ee332e4a 1301 // bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1302 //
whismanoid 1:77f1ee332e4a 1303 const int channelPairIndex = channelNumber_0_15 / 2;
whismanoid 1:77f1ee332e4a 1304 const int bitmask = (1 << (10 - channelPairIndex));
whismanoid 1:77f1ee332e4a 1305 UNIPOLAR &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1306 BIPOLAR |= bitmask;
whismanoid 1:77f1ee332e4a 1307 RANGE &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1308
whismanoid 1:77f1ee332e4a 1309 //----------------------------------------
whismanoid 1:77f1ee332e4a 1310 // SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid 1:77f1ee332e4a 1311 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1312 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1313 SPIwrite16bits(UNIPOLAR);
whismanoid 1:77f1ee332e4a 1314 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1315 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1316 SPIwrite16bits(BIPOLAR);
whismanoid 1:77f1ee332e4a 1317 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1318 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1319 SPIwrite16bits(RANGE);
whismanoid 1:77f1ee332e4a 1320 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1321 }
whismanoid 1:77f1ee332e4a 1322
whismanoid 1:77f1ee332e4a 1323 //----------------------------------------
whismanoid 1:77f1ee332e4a 1324 // ADC Channels AIN(channelId), AIN(channelId+1) = Differential Bipolar
whismanoid 1:77f1ee332e4a 1325 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1326 // Voltage per LSB count = VREF/2048
whismanoid 1:77f1ee332e4a 1327 // AIN(channelId), AIN(channelId+1) are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid 1:77f1ee332e4a 1328 // AIN(channelId) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1329 // AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1330 //
whismanoid 1:77f1ee332e4a 1331 void MAX11131::Reconfigure_DifferentialBipolarFS2Vref(int channelNumber_0_15)
whismanoid 1:77f1ee332e4a 1332 {
whismanoid 1:77f1ee332e4a 1333
whismanoid 1:77f1ee332e4a 1334 //----------------------------------------
whismanoid 1:77f1ee332e4a 1335 // UCH(ch)/(ch+1)=0, BCH(ch)/(ch+1)=1, RANGE(ch)/(ch+1)=1:
whismanoid 1:77f1ee332e4a 1336 // AIN(ch)/AIN(ch+1) differential input pair ±Vref,
whismanoid 1:77f1ee332e4a 1337 // bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1338 //
whismanoid 1:77f1ee332e4a 1339 const int channelPairIndex = channelNumber_0_15 / 2;
whismanoid 1:77f1ee332e4a 1340 const int bitmask = (1 << (10 - channelPairIndex));
whismanoid 1:77f1ee332e4a 1341 UNIPOLAR &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1342 BIPOLAR |= bitmask;
whismanoid 1:77f1ee332e4a 1343 RANGE |= bitmask;
whismanoid 1:77f1ee332e4a 1344 // UCH0/1=0, BCH0/1=1, RANGE0/1=1: AIN0/AIN1 differential input pair ±Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1345
whismanoid 1:77f1ee332e4a 1346 //----------------------------------------
whismanoid 1:77f1ee332e4a 1347 // SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid 1:77f1ee332e4a 1348 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1349 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1350 SPIwrite16bits(UNIPOLAR);
whismanoid 1:77f1ee332e4a 1351 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1352 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1353 SPIwrite16bits(BIPOLAR);
whismanoid 1:77f1ee332e4a 1354 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1355 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1356 SPIwrite16bits(RANGE);
whismanoid 1:77f1ee332e4a 1357 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1358 }
whismanoid 1:77f1ee332e4a 1359
whismanoid 1:77f1ee332e4a 1360 //----------------------------------------
whismanoid 1:77f1ee332e4a 1361 // SCAN_0000_NOP
whismanoid 1:77f1ee332e4a 1362 //
whismanoid 1:77f1ee332e4a 1363 // Shift 16 bits out of ADC, without changing configuration.
whismanoid 1:77f1ee332e4a 1364 // Note: @return data format depends on CHAN_ID bit:
whismanoid 1:77f1ee332e4a 1365 // "CH[3:0] DATA[11:0]" when CHAN_ID = 1, or
whismanoid 1:77f1ee332e4a 1366 // "0 DATA[11:0] x x x" when CHAN_ID = 0.
whismanoid 1:77f1ee332e4a 1367 int16_t MAX11131::ScanRead(void)
whismanoid 1:77f1ee332e4a 1368 {
whismanoid 1:77f1ee332e4a 1369
whismanoid 1:77f1ee332e4a 1370 //----------------------------------------
whismanoid 1:77f1ee332e4a 1371 // Read SPI data from device while MOSI (Maxim DIN) is 0. Effectively ADC_MODE_CONTROL SCAN[3:0] = SCAN_0000_NOP = 0
whismanoid 1:77f1ee332e4a 1372 SPI_MOSI_Semantic = 0; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1373 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1374 int16_t misoData16 = SPIread16bits();
whismanoid 1:77f1ee332e4a 1375 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1376 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 1377 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 1378 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1379 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 1380 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1381 return misoData16;
whismanoid 1:77f1ee332e4a 1382 }
whismanoid 0:f7d706d2904d 1383
whismanoid 1:77f1ee332e4a 1384 //----------------------------------------
whismanoid 1:77f1ee332e4a 1385 // SCAN_0000_NOP
whismanoid 1:77f1ee332e4a 1386 //
whismanoid 1:77f1ee332e4a 1387 // Read raw ADC codes from device into AINcode[] and RAW_misoData16[].
whismanoid 1:77f1ee332e4a 1388 // If internal clock mode with SWCNV=0, measurements will be triggered using CNVST pin.
whismanoid 1:77f1ee332e4a 1389 //
whismanoid 1:77f1ee332e4a 1390 // @pre one of the Scan functions was called, setting NumWords
whismanoid 1:77f1ee332e4a 1391 // @post RAW_misoData16[index] contains the raw SPI Master-In,Slave-Out data
whismanoid 1:77f1ee332e4a 1392 // @post AINcode[NUM_CHANNELS] contains the latest readings in LSBs
whismanoid 1:77f1ee332e4a 1393 //
whismanoid 1:77f1ee332e4a 1394 void MAX11131::ReadAINcode(void)
whismanoid 1:77f1ee332e4a 1395 {
whismanoid 1:77f1ee332e4a 1396
whismanoid 1:77f1ee332e4a 1397 //----------------------------------------
whismanoid 1:77f1ee332e4a 1398 // loop index for RAW_misoData16[SAMPLESET_MAX_ENTRIES];
whismanoid 1:77f1ee332e4a 1399 int index;
whismanoid 1:77f1ee332e4a 1400
whismanoid 1:77f1ee332e4a 1401 //----------------------------------------
whismanoid 1:77f1ee332e4a 1402 // If internal clock mode with SWCNV=0, trigger measurement using CNVST pin and wait for EOC pin.
whismanoid 1:77f1ee332e4a 1403 if (isExternalClock == 0)
whismanoid 1:77f1ee332e4a 1404 {
whismanoid 1:77f1ee332e4a 1405 if (swcnv_0_1 == 0)
whismanoid 1:77f1ee332e4a 1406 {
whismanoid 1:77f1ee332e4a 1407 // SWCNV=0: trigger measurement by driving CNVST/AIN14 pin low
whismanoid 1:77f1ee332e4a 1408 // for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 1409 // One CNVST pulse scans all requested channels and stores the results in the FIFO.
whismanoid 1:77f1ee332e4a 1410 CNVSToutputPulseLow();
whismanoid 1:77f1ee332e4a 1411 }
whismanoid 1:77f1ee332e4a 1412 // wait for EOC low (internal clock mode end of conversion)
whismanoid 1:77f1ee332e4a 1413 EOCinputWaitUntilLow();
whismanoid 1:77f1ee332e4a 1414 }
whismanoid 1:77f1ee332e4a 1415
whismanoid 1:77f1ee332e4a 1416 //----------------------------------------
whismanoid 1:77f1ee332e4a 1417 // Read raw ADC codes from device into AINcode[] and RAW_misoData16[].
whismanoid 1:77f1ee332e4a 1418 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 1419 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 1420 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1421 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 1422 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1423 switch(ScanMode)
whismanoid 1:77f1ee332e4a 1424 {
whismanoid 1:77f1ee332e4a 1425 //----------------------------------------
whismanoid 1:77f1ee332e4a 1426 // read data words
whismanoid 1:77f1ee332e4a 1427 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 1428 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1429 case SCAN_0000_NOP:
whismanoid 1:77f1ee332e4a 1430 case SCAN_0011_StandardInternalClock:
whismanoid 1:77f1ee332e4a 1431 case SCAN_0101_UpperInternalClock:
whismanoid 1:77f1ee332e4a 1432 case SCAN_0111_CustomInternalClock:
whismanoid 1:77f1ee332e4a 1433 default:
whismanoid 1:77f1ee332e4a 1434 for (index = 0; index < NumWords; index++) {
whismanoid 1:77f1ee332e4a 1435 RAW_misoData16[index] = ScanRead();
whismanoid 1:77f1ee332e4a 1436 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 1437 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1438 int16_t value_u12 = (RAW_misoData16[index] & 0x0FFF);
whismanoid 1:77f1ee332e4a 1439 int channelId = ((RAW_misoData16[index] >> 12) & 0x000F);
whismanoid 1:77f1ee332e4a 1440 AINcode[channelId] = value_u12;
whismanoid 1:77f1ee332e4a 1441 }
whismanoid 1:77f1ee332e4a 1442 break;
whismanoid 1:77f1ee332e4a 1443 //----------------------------------------
whismanoid 1:77f1ee332e4a 1444 // read data words
whismanoid 1:77f1ee332e4a 1445 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 1446 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 1447 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1448 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 1449 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1450 case SCAN_0001_Manual:
whismanoid 1:77f1ee332e4a 1451 case SCAN_0100_StandardExternalClock:
whismanoid 1:77f1ee332e4a 1452 case SCAN_0110_UpperExternalClock:
whismanoid 1:77f1ee332e4a 1453 case SCAN_1000_CustomExternalClock:
whismanoid 1:77f1ee332e4a 1454 case SCAN_1001_SampleSetExternalClock:
whismanoid 1:77f1ee332e4a 1455 if (chan_id_0_1 != 0) {
whismanoid 1:77f1ee332e4a 1456 for (index = 0; index < NumWords; index++) {
whismanoid 1:77f1ee332e4a 1457 RAW_misoData16[index] = ScanRead();
whismanoid 1:77f1ee332e4a 1458 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 1459 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1460 int16_t value_u12 = (RAW_misoData16[index] & 0x0FFF);
whismanoid 1:77f1ee332e4a 1461 int channelId = ((RAW_misoData16[index] >> 12) & 0x000F);
whismanoid 1:77f1ee332e4a 1462 AINcode[channelId] = value_u12;
whismanoid 1:77f1ee332e4a 1463 }
whismanoid 1:77f1ee332e4a 1464 } else {
whismanoid 1:77f1ee332e4a 1465 for (index = 0; index < NumWords; index++) {
whismanoid 1:77f1ee332e4a 1466 RAW_misoData16[index] = ScanRead();
whismanoid 1:77f1ee332e4a 1467 int16_t value_u12 = ((RAW_misoData16[index] >> 3) & 0x0FFF);
whismanoid 1:77f1ee332e4a 1468 int channelId = channelNumber_0_15;
whismanoid 1:77f1ee332e4a 1469 AINcode[channelId] = value_u12;
whismanoid 1:77f1ee332e4a 1470 }
whismanoid 1:77f1ee332e4a 1471 }
whismanoid 1:77f1ee332e4a 1472 break;
whismanoid 1:77f1ee332e4a 1473 //----------------------------------------
whismanoid 1:77f1ee332e4a 1474 // read data words and calculate mean, stddev
whismanoid 1:77f1ee332e4a 1475 case SCAN_0010_Repeat:
whismanoid 1:77f1ee332e4a 1476 // ScanRead_nWords_chanID_mean(NumWords); // TODO1: missing function
whismanoid 1:77f1ee332e4a 1477 // was this function AINcode_print_value_chanID_mean(int nWords) in main?
whismanoid 1:77f1ee332e4a 1478 // But this function prints to standard output so can't be inside the driver.
whismanoid 1:77f1ee332e4a 1479 for (index = 0; index < NumWords; index++) {
whismanoid 1:77f1ee332e4a 1480 RAW_misoData16[index] = ScanRead();
whismanoid 1:77f1ee332e4a 1481 }
whismanoid 1:77f1ee332e4a 1482 break;
whismanoid 1:77f1ee332e4a 1483 }
whismanoid 1:77f1ee332e4a 1484 }
whismanoid 1:77f1ee332e4a 1485
whismanoid 1:77f1ee332e4a 1486 //----------------------------------------
whismanoid 1:77f1ee332e4a 1487 // Sign-Extend a right-aligned MAX11131 code into a signed 2's complement value.
whismanoid 1:77f1ee332e4a 1488 // Supports the bipolar transfer functions.
whismanoid 1:77f1ee332e4a 1489 // @param[in] value_u12: raw 12-bit MAX11131 code (right justified).
whismanoid 1:77f1ee332e4a 1490 // @return sign-extended 2's complement value.
whismanoid 1:77f1ee332e4a 1491 //
whismanoid 1:77f1ee332e4a 1492 int32_t MAX11131::TwosComplementValue(uint32_t regValue)
whismanoid 1:77f1ee332e4a 1493 {
whismanoid 1:77f1ee332e4a 1494 const uint16_t SIGN_BIT_12BIT = 0x0800;
whismanoid 1:77f1ee332e4a 1495 const uint16_t FULL_SCALE_CODE_12BIT = 0x0fff;
whismanoid 1:77f1ee332e4a 1496 if (((regValue & SIGN_BIT_12BIT) != 0) && !((regValue & (SIGN_BIT_12BIT << 1)) != 0))
whismanoid 1:77f1ee332e4a 1497 {
whismanoid 1:77f1ee332e4a 1498 // (bSignBitNegative && !bExtendedSignBitNegative)
whismanoid 1:77f1ee332e4a 1499 // Twos_Complement negative value
whismanoid 1:77f1ee332e4a 1500 int32_t Offset_regValue = (int32_t)(regValue - (FULL_SCALE_CODE_12BIT + 1));
whismanoid 1:77f1ee332e4a 1501 return Offset_regValue;
whismanoid 1:77f1ee332e4a 1502 }
whismanoid 1:77f1ee332e4a 1503 // Twos_Complement positive value or zero
whismanoid 1:77f1ee332e4a 1504 return (int32_t)regValue;
whismanoid 1:77f1ee332e4a 1505 }
whismanoid 1:77f1ee332e4a 1506
whismanoid 1:77f1ee332e4a 1507 //----------------------------------------
whismanoid 1:77f1ee332e4a 1508 // Return the physical voltage corresponding to MAX11131 code.
whismanoid 1:77f1ee332e4a 1509 // Does not perform any offset or gain correction.
whismanoid 1:77f1ee332e4a 1510 // @pre VRef = Voltage of REF input, in Volts
whismanoid 1:77f1ee332e4a 1511 // @param[in] value_u12: raw 12-bit MAX11131 code (right justified).
whismanoid 1:77f1ee332e4a 1512 // @param[in] channelId: AIN channel number.
whismanoid 1:77f1ee332e4a 1513 // @return physical voltage corresponding to MAX11131 code.
whismanoid 1:77f1ee332e4a 1514 //
whismanoid 1:77f1ee332e4a 1515 double MAX11131::VoltageOfCode(int16_t value_u12, int channelId)
whismanoid 1:77f1ee332e4a 1516 {
whismanoid 1:77f1ee332e4a 1517 int channelPairIndex = channelId / 2;
whismanoid 1:77f1ee332e4a 1518 // format: 1 0 0 0 1 UCH0/1 UCH2/3 UCH4/5 UCH6/7 UCH8/9 UCH10/11 UCH12/13 UCH14/15 PDIFF_COM x x
whismanoid 1:77f1ee332e4a 1519 int UCHn = (UNIPOLAR >> (10 - channelPairIndex)) & 0x01;
whismanoid 1:77f1ee332e4a 1520 int BCHn = (BIPOLAR >> (10 - channelPairIndex)) & 0x01;
whismanoid 1:77f1ee332e4a 1521 int RANGEn = (RANGE >> (10 - channelPairIndex)) & 0x01;
whismanoid 1:77f1ee332e4a 1522 if (UCHn)
whismanoid 1:77f1ee332e4a 1523 {
whismanoid 1:77f1ee332e4a 1524 // UCH0/1=1, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1525 return (value_u12 * VRef / 4096);
whismanoid 1:77f1ee332e4a 1526 }
whismanoid 1:77f1ee332e4a 1527 else
whismanoid 1:77f1ee332e4a 1528 {
whismanoid 1:77f1ee332e4a 1529 if (BCHn)
whismanoid 1:77f1ee332e4a 1530 {
whismanoid 1:77f1ee332e4a 1531 if (RANGEn)
whismanoid 1:77f1ee332e4a 1532 {
whismanoid 1:77f1ee332e4a 1533 // UCH0/1=0, BCH0/1=1, RANGE0/1=1: AIN0/AIN1 differential input pair ±Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1534 return (TwosComplementValue(value_u12) * VRef / 2048);
whismanoid 1:77f1ee332e4a 1535 }
whismanoid 1:77f1ee332e4a 1536 else
whismanoid 1:77f1ee332e4a 1537 {
whismanoid 1:77f1ee332e4a 1538 // UCH0/1=0, BCH0/1=1, RANGE0/1=0: AIN0/AIN1 differential input pair ±½Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1539 return (TwosComplementValue(value_u12) * VRef / 4096);
whismanoid 1:77f1ee332e4a 1540 }
whismanoid 1:77f1ee332e4a 1541 }
whismanoid 1:77f1ee332e4a 1542 else
whismanoid 1:77f1ee332e4a 1543 {
whismanoid 1:77f1ee332e4a 1544 // UCH0/1=0, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1545 return (value_u12 * VRef / 4096);
whismanoid 1:77f1ee332e4a 1546 }
whismanoid 1:77f1ee332e4a 1547 }
whismanoid 1:77f1ee332e4a 1548 }
whismanoid 1:77f1ee332e4a 1549
whismanoid 1:77f1ee332e4a 1550 //----------------------------------------
whismanoid 1:77f1ee332e4a 1551 // SCAN_0001_Manual
whismanoid 1:77f1ee332e4a 1552 //
whismanoid 1:77f1ee332e4a 1553 // Measure ADC channel channelNumber_0_15 once.
whismanoid 1:77f1ee332e4a 1554 // External clock mode.
whismanoid 1:77f1ee332e4a 1555 // @param[in] channelNumber_0_15: AIN Channel Number
whismanoid 1:77f1ee332e4a 1556 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 1557 // @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 1558 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 1:77f1ee332e4a 1559 // For external clock modes, the data format depends on CHAN_ID.
whismanoid 1:77f1ee332e4a 1560 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 1561 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1562 //
whismanoid 1:77f1ee332e4a 1563 int MAX11131::ScanManual(void)
whismanoid 1:77f1ee332e4a 1564 {
whismanoid 1:77f1ee332e4a 1565
whismanoid 1:77f1ee332e4a 1566 //----------------------------------------
whismanoid 1:77f1ee332e4a 1567 // number of words to read
whismanoid 1:77f1ee332e4a 1568 NumWords = 1;
whismanoid 1:77f1ee332e4a 1569
whismanoid 1:77f1ee332e4a 1570 //----------------------------------------
whismanoid 1:77f1ee332e4a 1571 // External Clock Mode
whismanoid 1:77f1ee332e4a 1572 isExternalClock = 1;
whismanoid 1:77f1ee332e4a 1573
whismanoid 1:77f1ee332e4a 1574 //----------------------------------------
whismanoid 1:77f1ee332e4a 1575 // update device driver global variable
whismanoid 1:77f1ee332e4a 1576 ScanMode = SCAN_0001_Manual;
whismanoid 1:77f1ee332e4a 1577
whismanoid 1:77f1ee332e4a 1578 //----------------------------------------
whismanoid 1:77f1ee332e4a 1579 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 1580 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 1581 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 1582 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 1583 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 1584 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 1585 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 1586 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 1587
whismanoid 1:77f1ee332e4a 1588 //----------------------------------------
whismanoid 1:77f1ee332e4a 1589 // Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid 1:77f1ee332e4a 1590 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 1591 ADC_MODE_CONTROL |= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 1592
whismanoid 1:77f1ee332e4a 1593 //----------------------------------------
whismanoid 1:77f1ee332e4a 1594 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0001_Manual = 1
whismanoid 1:77f1ee332e4a 1595 //~ const int SCAN_0001_Manual = 1; // replaced local const with enum
whismanoid 1:77f1ee332e4a 1596 ADC_MODE_CONTROL |= ((SCAN_0001_Manual & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 1597
whismanoid 1:77f1ee332e4a 1598 //----------------------------------------
whismanoid 1:77f1ee332e4a 1599 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 1600 ADC_MODE_CONTROL |= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 1601
whismanoid 1:77f1ee332e4a 1602 //----------------------------------------
whismanoid 1:77f1ee332e4a 1603 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 1604 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 1605
whismanoid 1:77f1ee332e4a 1606 //----------------------------------------
whismanoid 1:77f1ee332e4a 1607 // ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid 1:77f1ee332e4a 1608 // (applicable to external clock mode only)
whismanoid 1:77f1ee332e4a 1609 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 1610 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 1611 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1612 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 1613 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1614 ADC_MODE_CONTROL |= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid 1:77f1ee332e4a 1615
whismanoid 1:77f1ee332e4a 1616 //----------------------------------------
whismanoid 1:77f1ee332e4a 1617 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 1618 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 1619 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1620 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1621 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 1622 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1623
whismanoid 1:77f1ee332e4a 1624 //----------------------------------------
whismanoid 1:77f1ee332e4a 1625 // return number of words to read
whismanoid 1:77f1ee332e4a 1626 return NumWords;
whismanoid 1:77f1ee332e4a 1627 }
whismanoid 1:77f1ee332e4a 1628
whismanoid 1:77f1ee332e4a 1629 //----------------------------------------
whismanoid 1:77f1ee332e4a 1630 // SCAN_0010_Repeat
whismanoid 1:77f1ee332e4a 1631 //
whismanoid 1:77f1ee332e4a 1632 // Measure ADC channel channelNumber_0_15 repeatedly with averaging.
whismanoid 1:77f1ee332e4a 1633 // Internal clock mode.
whismanoid 1:77f1ee332e4a 1634 // @param[in] channelNumber_0_15: AIN Channel Number
whismanoid 1:77f1ee332e4a 1635 // @param[in] average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid 1:77f1ee332e4a 1636 // average_0_4_8_16_32=0 to disable averaging.
whismanoid 1:77f1ee332e4a 1637 // @param[in] nscan_4_8_12_16: Number of ScanRead() words to report.
whismanoid 1:77f1ee332e4a 1638 // @param[in] swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 1639 // SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid 1:77f1ee332e4a 1640 // Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 1641 // SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid 1:77f1ee332e4a 1642 // CS must be held low for minimum of 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 1643 // CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 1644 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 1645 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 1:77f1ee332e4a 1646 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 1647 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1648 //
whismanoid 1:77f1ee332e4a 1649 int MAX11131::ScanRepeat(void)
whismanoid 1:77f1ee332e4a 1650 {
whismanoid 1:77f1ee332e4a 1651
whismanoid 1:77f1ee332e4a 1652 //----------------------------------------
whismanoid 1:77f1ee332e4a 1653 // number of words to read
whismanoid 1:77f1ee332e4a 1654 NumWords = (nscan_4_8_12_16);
whismanoid 1:77f1ee332e4a 1655
whismanoid 1:77f1ee332e4a 1656 //----------------------------------------
whismanoid 1:77f1ee332e4a 1657 // Internal Clock Mode
whismanoid 1:77f1ee332e4a 1658 isExternalClock = 0;
whismanoid 1:77f1ee332e4a 1659
whismanoid 1:77f1ee332e4a 1660 //----------------------------------------
whismanoid 1:77f1ee332e4a 1661 // update device driver global variable
whismanoid 1:77f1ee332e4a 1662 ScanMode = SCAN_0010_Repeat;
whismanoid 1:77f1ee332e4a 1663
whismanoid 1:77f1ee332e4a 1664 //----------------------------------------
whismanoid 1:77f1ee332e4a 1665 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 1666 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 1667 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 1668 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 1669 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 1670 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 1671 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 1672 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 1673
whismanoid 1:77f1ee332e4a 1674 //----------------------------------------
whismanoid 1:77f1ee332e4a 1675 // define write-only register ADC_CONFIGURATION
whismanoid 1:77f1ee332e4a 1676 ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid 1:77f1ee332e4a 1677 const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid 1:77f1ee332e4a 1678 const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid 1:77f1ee332e4a 1679 const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid 1:77f1ee332e4a 1680 const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid 1:77f1ee332e4a 1681 const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid 1:77f1ee332e4a 1682 const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid 1:77f1ee332e4a 1683
whismanoid 1:77f1ee332e4a 1684 //----------------------------------------
whismanoid 1:77f1ee332e4a 1685 // if average, ADC CONFIGURATION register set AVG and NAVG[1:0]
whismanoid 1:77f1ee332e4a 1686 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 1687 // if average, ADC CONFIGURATION register set AVG ON BIT TO 1
whismanoid 1:77f1ee332e4a 1688 // if average, ADC CONFIGURATION register set NAVG[1:0] TO N
whismanoid 1:77f1ee332e4a 1689 if (average_0_4_8_16_32 == 4) {
whismanoid 1:77f1ee332e4a 1690 // Enable Averaging of 4 samples (AVGON=1, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 1691 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 1692 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1693 ADC_CONFIGURATION |= ((0 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1694 } else if (average_0_4_8_16_32 == 8) {
whismanoid 1:77f1ee332e4a 1695 // Enable Averaging of 8 samples (AVGON=1, NAVG[1:0]=1)
whismanoid 1:77f1ee332e4a 1696 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 1697 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1698 ADC_CONFIGURATION |= ((1 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1699 } else if (average_0_4_8_16_32 == 16) {
whismanoid 1:77f1ee332e4a 1700 // Enable Averaging of 16 samples (AVGON=1, NAVG[1:0]=2)
whismanoid 1:77f1ee332e4a 1701 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 1702 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1703 ADC_CONFIGURATION |= ((2 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1704 } else if (average_0_4_8_16_32 == 32) {
whismanoid 1:77f1ee332e4a 1705 // Enable Averaging of 32 samples (AVGON=1, NAVG[1:0]=3)
whismanoid 1:77f1ee332e4a 1706 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 1707 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1708 ADC_CONFIGURATION |= ((3 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1709 } else {
whismanoid 1:77f1ee332e4a 1710 // Disable Averaging (AVGON=0, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 1711 ADC_CONFIGURATION &= ~ (( AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 1712 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1713 }
whismanoid 1:77f1ee332e4a 1714
whismanoid 1:77f1ee332e4a 1715 //----------------------------------------
whismanoid 1:77f1ee332e4a 1716 // ADC CONFIGURATION register set NSCAN[1:0] for scan count
whismanoid 1:77f1ee332e4a 1717 // (applicable to SCAN_0010_Repeat only)
whismanoid 1:77f1ee332e4a 1718 if (nscan_4_8_12_16 == 4) {
whismanoid 1:77f1ee332e4a 1719 // Set scan count 4
whismanoid 1:77f1ee332e4a 1720 ADC_CONFIGURATION &= ~ (( NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 1721 ADC_CONFIGURATION |= ((0 & NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 1722 } else if (nscan_4_8_12_16 == 8) {
whismanoid 1:77f1ee332e4a 1723 // Set scan count 8
whismanoid 1:77f1ee332e4a 1724 ADC_CONFIGURATION &= ~ (( NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 1725 ADC_CONFIGURATION |= ((1 & NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 1726 } else if (nscan_4_8_12_16 == 12) {
whismanoid 1:77f1ee332e4a 1727 // Set scan count 12
whismanoid 1:77f1ee332e4a 1728 ADC_CONFIGURATION &= ~ (( NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 1729 ADC_CONFIGURATION |= ((2 & NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 1730 } else if (nscan_4_8_12_16 == 16) {
whismanoid 1:77f1ee332e4a 1731 // Set scan count 16
whismanoid 1:77f1ee332e4a 1732 ADC_CONFIGURATION &= ~ (( NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 1733 ADC_CONFIGURATION |= ((3 & NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 1734 }
whismanoid 1:77f1ee332e4a 1735
whismanoid 1:77f1ee332e4a 1736 //----------------------------------------
whismanoid 1:77f1ee332e4a 1737 // SPI write ADC CONFIGURATION register
whismanoid 1:77f1ee332e4a 1738 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 1739 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1740 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1741 SPIwrite16bits(ADC_CONFIGURATION);
whismanoid 1:77f1ee332e4a 1742 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1743
whismanoid 1:77f1ee332e4a 1744 //----------------------------------------
whismanoid 1:77f1ee332e4a 1745 // Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid 1:77f1ee332e4a 1746 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 1747 ADC_MODE_CONTROL |= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 1748
whismanoid 1:77f1ee332e4a 1749 //----------------------------------------
whismanoid 1:77f1ee332e4a 1750 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0010_Repeat = 2
whismanoid 1:77f1ee332e4a 1751 //~ const int SCAN_0010_Repeat = 2; // replaced local const with enum
whismanoid 1:77f1ee332e4a 1752 ADC_MODE_CONTROL |= ((SCAN_0010_Repeat & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 1753
whismanoid 1:77f1ee332e4a 1754 //----------------------------------------
whismanoid 1:77f1ee332e4a 1755 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 1756 ADC_MODE_CONTROL |= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 1757
whismanoid 1:77f1ee332e4a 1758 //----------------------------------------
whismanoid 1:77f1ee332e4a 1759 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 1760 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 1761
whismanoid 1:77f1ee332e4a 1762 //----------------------------------------
whismanoid 1:77f1ee332e4a 1763 // ADC MODE CONTROL register set SWCNV if CNVST pin is not used
whismanoid 1:77f1ee332e4a 1764 // ADC MODE CONTROL REGISTER SELECT THE RIGHT SWCNV BIT
whismanoid 1:77f1ee332e4a 1765 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 1766 // SWCNV=1: trigger measurement on SPI CS rising edge; CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 1767 // SWCNV=0: trigger measurement by driving CNVST pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 1768 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 1769 ADC_MODE_CONTROL |= ((swcnv_0_1 & SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 1770 } else {
whismanoid 1:77f1ee332e4a 1771 ADC_MODE_CONTROL &= ~ (( SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 1772 }
whismanoid 1:77f1ee332e4a 1773
whismanoid 1:77f1ee332e4a 1774 //----------------------------------------
whismanoid 1:77f1ee332e4a 1775 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 1776 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 1777 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 1778 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1779 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1780 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 1781 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 1782 // NOTE: Figure 7 Internal Conversions with SWCNV=1 has an error, the 17th SCLK is mislabeled as "16" should be "17".
whismanoid 1:77f1ee332e4a 1783 SPIwrite24bits(ADC_MODE_CONTROL, 0);
whismanoid 1:77f1ee332e4a 1784 } else {
whismanoid 1:77f1ee332e4a 1785 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 1786 }
whismanoid 1:77f1ee332e4a 1787 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1788
whismanoid 1:77f1ee332e4a 1789 //----------------------------------------
whismanoid 1:77f1ee332e4a 1790 // return number of words to read
whismanoid 1:77f1ee332e4a 1791 return NumWords;
whismanoid 1:77f1ee332e4a 1792 }
whismanoid 1:77f1ee332e4a 1793
whismanoid 1:77f1ee332e4a 1794 //----------------------------------------
whismanoid 1:77f1ee332e4a 1795 // SCAN_0011_StandardInternalClock
whismanoid 1:77f1ee332e4a 1796 //
whismanoid 1:77f1ee332e4a 1797 // Measure ADC channels in sequence from AIN0 to channelNumber_0_15.
whismanoid 1:77f1ee332e4a 1798 // Internal clock mode.
whismanoid 1:77f1ee332e4a 1799 // @param[in] channelNumber_0_15: AIN Channel Number
whismanoid 1:77f1ee332e4a 1800 // @param[in] average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid 1:77f1ee332e4a 1801 // average_0_4_8_16_32=0 to disable averaging.
whismanoid 1:77f1ee332e4a 1802 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 1803 // @param[in] swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 1804 // SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid 1:77f1ee332e4a 1805 // Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 1806 // SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid 1:77f1ee332e4a 1807 // CS must be held low for minimum of 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 1808 // CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 1809 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 1:77f1ee332e4a 1810 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 1811 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1812 //
whismanoid 1:77f1ee332e4a 1813 int MAX11131::ScanStandardInternalClock(void)
whismanoid 1:77f1ee332e4a 1814 {
whismanoid 1:77f1ee332e4a 1815
whismanoid 1:77f1ee332e4a 1816 //----------------------------------------
whismanoid 1:77f1ee332e4a 1817 // number of words to read
whismanoid 1:77f1ee332e4a 1818 NumWords = (1 + channelNumber_0_15);
whismanoid 1:77f1ee332e4a 1819
whismanoid 1:77f1ee332e4a 1820 //----------------------------------------
whismanoid 1:77f1ee332e4a 1821 // Internal Clock Mode
whismanoid 1:77f1ee332e4a 1822 isExternalClock = 0;
whismanoid 1:77f1ee332e4a 1823
whismanoid 1:77f1ee332e4a 1824 //----------------------------------------
whismanoid 1:77f1ee332e4a 1825 // update device driver global variable
whismanoid 1:77f1ee332e4a 1826 ScanMode = SCAN_0011_StandardInternalClock;
whismanoid 1:77f1ee332e4a 1827
whismanoid 1:77f1ee332e4a 1828 //----------------------------------------
whismanoid 1:77f1ee332e4a 1829 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 1830 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 1831 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 1832 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 1833 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 1834 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 1835 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 1836 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 1837
whismanoid 1:77f1ee332e4a 1838 //----------------------------------------
whismanoid 1:77f1ee332e4a 1839 // define write-only register ADC_CONFIGURATION
whismanoid 1:77f1ee332e4a 1840 ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid 1:77f1ee332e4a 1841 const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid 1:77f1ee332e4a 1842 const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid 1:77f1ee332e4a 1843 const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid 1:77f1ee332e4a 1844 const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid 1:77f1ee332e4a 1845 const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid 1:77f1ee332e4a 1846 const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid 1:77f1ee332e4a 1847
whismanoid 1:77f1ee332e4a 1848 //----------------------------------------
whismanoid 1:77f1ee332e4a 1849 // if average, ADC CONFIGURATION register set AVG and NAVG[1:0]
whismanoid 1:77f1ee332e4a 1850 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 1851 // if average, ADC CONFIGURATION register set AVG ON BIT TO 1
whismanoid 1:77f1ee332e4a 1852 // if average, ADC CONFIGURATION register set NAVG[1:0] TO N
whismanoid 1:77f1ee332e4a 1853 if (average_0_4_8_16_32 == 4) {
whismanoid 1:77f1ee332e4a 1854 // Enable Averaging of 4 samples (AVGON=1, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 1855 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 1856 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1857 ADC_CONFIGURATION |= ((0 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1858 } else if (average_0_4_8_16_32 == 8) {
whismanoid 1:77f1ee332e4a 1859 // Enable Averaging of 8 samples (AVGON=1, NAVG[1:0]=1)
whismanoid 1:77f1ee332e4a 1860 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 1861 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1862 ADC_CONFIGURATION |= ((1 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1863 } else if (average_0_4_8_16_32 == 16) {
whismanoid 1:77f1ee332e4a 1864 // Enable Averaging of 16 samples (AVGON=1, NAVG[1:0]=2)
whismanoid 1:77f1ee332e4a 1865 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 1866 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1867 ADC_CONFIGURATION |= ((2 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1868 } else if (average_0_4_8_16_32 == 32) {
whismanoid 1:77f1ee332e4a 1869 // Enable Averaging of 32 samples (AVGON=1, NAVG[1:0]=3)
whismanoid 1:77f1ee332e4a 1870 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 1871 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1872 ADC_CONFIGURATION |= ((3 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1873 } else {
whismanoid 1:77f1ee332e4a 1874 // Disable Averaging (AVGON=0, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 1875 ADC_CONFIGURATION &= ~ (( AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 1876 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 1877 }
whismanoid 1:77f1ee332e4a 1878
whismanoid 1:77f1ee332e4a 1879 //----------------------------------------
whismanoid 1:77f1ee332e4a 1880 // SPI write ADC CONFIGURATION register
whismanoid 1:77f1ee332e4a 1881 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 1882 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1883 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1884 SPIwrite16bits(ADC_CONFIGURATION);
whismanoid 1:77f1ee332e4a 1885 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1886
whismanoid 1:77f1ee332e4a 1887 //----------------------------------------
whismanoid 1:77f1ee332e4a 1888 // Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid 1:77f1ee332e4a 1889 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 1890 ADC_MODE_CONTROL |= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 1891
whismanoid 1:77f1ee332e4a 1892 //----------------------------------------
whismanoid 1:77f1ee332e4a 1893 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0011_StandardInternalClock = 3
whismanoid 1:77f1ee332e4a 1894 //~ const int SCAN_0011_StandardInternalClock = 3; // replaced local const with enum
whismanoid 1:77f1ee332e4a 1895 ADC_MODE_CONTROL |= ((SCAN_0011_StandardInternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 1896
whismanoid 1:77f1ee332e4a 1897 //----------------------------------------
whismanoid 1:77f1ee332e4a 1898 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 1899 ADC_MODE_CONTROL |= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 1900
whismanoid 1:77f1ee332e4a 1901 //----------------------------------------
whismanoid 1:77f1ee332e4a 1902 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 1903 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 1904
whismanoid 1:77f1ee332e4a 1905 //----------------------------------------
whismanoid 1:77f1ee332e4a 1906 // ADC MODE CONTROL register set SWCNV if CNVST pin is not used
whismanoid 1:77f1ee332e4a 1907 // ADC MODE CONTROL REGISTER SELECT THE RIGHT SWCNV BIT
whismanoid 1:77f1ee332e4a 1908 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 1909 // SWCNV=1: trigger measurement on SPI CS rising edge; CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 1910 // SWCNV=0: trigger measurement by driving CNVST pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 1911 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 1912 ADC_MODE_CONTROL |= ((swcnv_0_1 & SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 1913 } else {
whismanoid 1:77f1ee332e4a 1914 ADC_MODE_CONTROL &= ~ (( SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 1915 }
whismanoid 1:77f1ee332e4a 1916
whismanoid 1:77f1ee332e4a 1917 //----------------------------------------
whismanoid 1:77f1ee332e4a 1918 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 1919 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 1920 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 1921 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1922 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1923 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 1924 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 1925 // NOTE: Figure 7 Internal Conversions with SWCNV=1 has an error, the 17th SCLK is mislabeled as "16" should be "17".
whismanoid 1:77f1ee332e4a 1926 SPIwrite24bits(ADC_MODE_CONTROL, 0);
whismanoid 1:77f1ee332e4a 1927 } else {
whismanoid 1:77f1ee332e4a 1928 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 1929 }
whismanoid 1:77f1ee332e4a 1930 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1931
whismanoid 1:77f1ee332e4a 1932 //----------------------------------------
whismanoid 1:77f1ee332e4a 1933 // return number of words to read
whismanoid 1:77f1ee332e4a 1934 return NumWords;
whismanoid 1:77f1ee332e4a 1935 }
whismanoid 1:77f1ee332e4a 1936
whismanoid 1:77f1ee332e4a 1937 //----------------------------------------
whismanoid 1:77f1ee332e4a 1938 // SCAN_0100_StandardExternalClock
whismanoid 1:77f1ee332e4a 1939 //
whismanoid 1:77f1ee332e4a 1940 // Measure ADC channels in sequence from AIN0 to channelNumber_0_15.
whismanoid 1:77f1ee332e4a 1941 // External clock mode.
whismanoid 1:77f1ee332e4a 1942 // @param[in] channelNumber_0_15: AIN Channel Number
whismanoid 1:77f1ee332e4a 1943 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 1944 // @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 1945 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 1:77f1ee332e4a 1946 // For external clock modes, the data format depends on CHAN_ID.
whismanoid 1:77f1ee332e4a 1947 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 1948 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1949 //
whismanoid 1:77f1ee332e4a 1950 int MAX11131::ScanStandardExternalClock(void)
whismanoid 1:77f1ee332e4a 1951 {
whismanoid 1:77f1ee332e4a 1952
whismanoid 1:77f1ee332e4a 1953 //----------------------------------------
whismanoid 1:77f1ee332e4a 1954 // number of words to read
whismanoid 1:77f1ee332e4a 1955 NumWords = (1 + channelNumber_0_15);
whismanoid 1:77f1ee332e4a 1956
whismanoid 1:77f1ee332e4a 1957 //----------------------------------------
whismanoid 1:77f1ee332e4a 1958 // External Clock Mode
whismanoid 1:77f1ee332e4a 1959 isExternalClock = 1;
whismanoid 1:77f1ee332e4a 1960
whismanoid 1:77f1ee332e4a 1961 //----------------------------------------
whismanoid 1:77f1ee332e4a 1962 // update device driver global variable
whismanoid 1:77f1ee332e4a 1963 ScanMode = SCAN_0100_StandardExternalClock;
whismanoid 1:77f1ee332e4a 1964
whismanoid 1:77f1ee332e4a 1965 //----------------------------------------
whismanoid 1:77f1ee332e4a 1966 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 1967 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 1968 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 1969 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 1970 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 1971 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 1972 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 1973 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 1974
whismanoid 1:77f1ee332e4a 1975 //----------------------------------------
whismanoid 1:77f1ee332e4a 1976 // Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid 1:77f1ee332e4a 1977 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 1978 ADC_MODE_CONTROL |= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 1979
whismanoid 1:77f1ee332e4a 1980 //----------------------------------------
whismanoid 1:77f1ee332e4a 1981 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0100_StandardExternalClock = 4
whismanoid 1:77f1ee332e4a 1982 //~ const int SCAN_0100_StandardExternalClock = 4; // replaced local const with enum
whismanoid 1:77f1ee332e4a 1983 ADC_MODE_CONTROL |= ((SCAN_0100_StandardExternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 1984
whismanoid 1:77f1ee332e4a 1985 //----------------------------------------
whismanoid 1:77f1ee332e4a 1986 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 1987 ADC_MODE_CONTROL |= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 1988
whismanoid 1:77f1ee332e4a 1989 //----------------------------------------
whismanoid 1:77f1ee332e4a 1990 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 1991 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 1992
whismanoid 1:77f1ee332e4a 1993 //----------------------------------------
whismanoid 1:77f1ee332e4a 1994 // ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid 1:77f1ee332e4a 1995 // (applicable to external clock mode only)
whismanoid 1:77f1ee332e4a 1996 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 1997 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 1998 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1999 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2000 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2001 ADC_MODE_CONTROL |= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid 1:77f1ee332e4a 2002
whismanoid 1:77f1ee332e4a 2003 //----------------------------------------
whismanoid 1:77f1ee332e4a 2004 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2005 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2006 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2007 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2008 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2009 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2010
whismanoid 1:77f1ee332e4a 2011 //----------------------------------------
whismanoid 1:77f1ee332e4a 2012 // return number of words to read
whismanoid 1:77f1ee332e4a 2013 return NumWords;
whismanoid 1:77f1ee332e4a 2014 }
whismanoid 1:77f1ee332e4a 2015
whismanoid 1:77f1ee332e4a 2016 //----------------------------------------
whismanoid 1:77f1ee332e4a 2017 // SCAN_0101_UpperInternalClock
whismanoid 1:77f1ee332e4a 2018 //
whismanoid 1:77f1ee332e4a 2019 // Measure ADC channels in sequence from channelNumber_0_15 to AIN15.
whismanoid 1:77f1ee332e4a 2020 // Internal clock mode.
whismanoid 1:77f1ee332e4a 2021 // @param[in] channelNumber_0_15: AIN Channel Number
whismanoid 1:77f1ee332e4a 2022 // @param[in] average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid 1:77f1ee332e4a 2023 // average_0_4_8_16_32=0 to disable averaging.
whismanoid 1:77f1ee332e4a 2024 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 2025 // @param[in] swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2026 // SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid 1:77f1ee332e4a 2027 // Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 2028 // SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid 1:77f1ee332e4a 2029 // CS must be held low for minimum of 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2030 // CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 2031 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 1:77f1ee332e4a 2032 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2033 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2034 //
whismanoid 1:77f1ee332e4a 2035 int MAX11131::ScanUpperInternalClock(void)
whismanoid 1:77f1ee332e4a 2036 {
whismanoid 1:77f1ee332e4a 2037
whismanoid 1:77f1ee332e4a 2038 //----------------------------------------
whismanoid 1:77f1ee332e4a 2039 // number of words to read
whismanoid 1:77f1ee332e4a 2040 NumWords = (16 - channelNumber_0_15);
whismanoid 1:77f1ee332e4a 2041
whismanoid 1:77f1ee332e4a 2042 //----------------------------------------
whismanoid 1:77f1ee332e4a 2043 // Internal Clock Mode
whismanoid 1:77f1ee332e4a 2044 isExternalClock = 0;
whismanoid 1:77f1ee332e4a 2045
whismanoid 1:77f1ee332e4a 2046 //----------------------------------------
whismanoid 1:77f1ee332e4a 2047 // update device driver global variable
whismanoid 1:77f1ee332e4a 2048 ScanMode = SCAN_0101_UpperInternalClock;
whismanoid 1:77f1ee332e4a 2049
whismanoid 1:77f1ee332e4a 2050 //----------------------------------------
whismanoid 1:77f1ee332e4a 2051 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 2052 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 2053 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 2054 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 2055 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2056 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 2057 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2058 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2059
whismanoid 1:77f1ee332e4a 2060 //----------------------------------------
whismanoid 1:77f1ee332e4a 2061 // define write-only register ADC_CONFIGURATION
whismanoid 1:77f1ee332e4a 2062 ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid 1:77f1ee332e4a 2063 const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid 1:77f1ee332e4a 2064 const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid 1:77f1ee332e4a 2065 const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid 1:77f1ee332e4a 2066 const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid 1:77f1ee332e4a 2067 const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid 1:77f1ee332e4a 2068 const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid 1:77f1ee332e4a 2069
whismanoid 1:77f1ee332e4a 2070 //----------------------------------------
whismanoid 1:77f1ee332e4a 2071 // if average, ADC CONFIGURATION register set AVG and NAVG[1:0]
whismanoid 1:77f1ee332e4a 2072 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 2073 // if average, ADC CONFIGURATION register set AVG ON BIT TO 1
whismanoid 1:77f1ee332e4a 2074 // if average, ADC CONFIGURATION register set NAVG[1:0] TO N
whismanoid 1:77f1ee332e4a 2075 if (average_0_4_8_16_32 == 4) {
whismanoid 1:77f1ee332e4a 2076 // Enable Averaging of 4 samples (AVGON=1, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 2077 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2078 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2079 ADC_CONFIGURATION |= ((0 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2080 } else if (average_0_4_8_16_32 == 8) {
whismanoid 1:77f1ee332e4a 2081 // Enable Averaging of 8 samples (AVGON=1, NAVG[1:0]=1)
whismanoid 1:77f1ee332e4a 2082 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2083 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2084 ADC_CONFIGURATION |= ((1 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2085 } else if (average_0_4_8_16_32 == 16) {
whismanoid 1:77f1ee332e4a 2086 // Enable Averaging of 16 samples (AVGON=1, NAVG[1:0]=2)
whismanoid 1:77f1ee332e4a 2087 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2088 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2089 ADC_CONFIGURATION |= ((2 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2090 } else if (average_0_4_8_16_32 == 32) {
whismanoid 1:77f1ee332e4a 2091 // Enable Averaging of 32 samples (AVGON=1, NAVG[1:0]=3)
whismanoid 1:77f1ee332e4a 2092 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2093 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2094 ADC_CONFIGURATION |= ((3 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2095 } else {
whismanoid 1:77f1ee332e4a 2096 // Disable Averaging (AVGON=0, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 2097 ADC_CONFIGURATION &= ~ (( AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2098 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2099 }
whismanoid 1:77f1ee332e4a 2100
whismanoid 1:77f1ee332e4a 2101 //----------------------------------------
whismanoid 1:77f1ee332e4a 2102 // SPI write ADC CONFIGURATION register
whismanoid 1:77f1ee332e4a 2103 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2104 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2105 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2106 SPIwrite16bits(ADC_CONFIGURATION);
whismanoid 1:77f1ee332e4a 2107 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2108
whismanoid 1:77f1ee332e4a 2109 //----------------------------------------
whismanoid 1:77f1ee332e4a 2110 // Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid 1:77f1ee332e4a 2111 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2112 ADC_MODE_CONTROL |= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2113
whismanoid 1:77f1ee332e4a 2114 //----------------------------------------
whismanoid 1:77f1ee332e4a 2115 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0101_UpperInternalClock = 5
whismanoid 1:77f1ee332e4a 2116 //~ const int SCAN_0101_UpperInternalClock = 5; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2117 ADC_MODE_CONTROL |= ((SCAN_0101_UpperInternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2118
whismanoid 1:77f1ee332e4a 2119 //----------------------------------------
whismanoid 1:77f1ee332e4a 2120 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 2121 ADC_MODE_CONTROL |= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 2122
whismanoid 1:77f1ee332e4a 2123 //----------------------------------------
whismanoid 1:77f1ee332e4a 2124 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2125 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2126
whismanoid 1:77f1ee332e4a 2127 //----------------------------------------
whismanoid 1:77f1ee332e4a 2128 // ADC MODE CONTROL register set SWCNV if CNVST pin is not used
whismanoid 1:77f1ee332e4a 2129 // ADC MODE CONTROL REGISTER SELECT THE RIGHT SWCNV BIT
whismanoid 1:77f1ee332e4a 2130 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 2131 // SWCNV=1: trigger measurement on SPI CS rising edge; CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 2132 // SWCNV=0: trigger measurement by driving CNVST pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 2133 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 2134 ADC_MODE_CONTROL |= ((swcnv_0_1 & SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 2135 } else {
whismanoid 1:77f1ee332e4a 2136 ADC_MODE_CONTROL &= ~ (( SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 2137 }
whismanoid 1:77f1ee332e4a 2138
whismanoid 1:77f1ee332e4a 2139 //----------------------------------------
whismanoid 1:77f1ee332e4a 2140 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2141 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2142 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2143 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2144 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2145 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 2146 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2147 // NOTE: Figure 7 Internal Conversions with SWCNV=1 has an error, the 17th SCLK is mislabeled as "16" should be "17".
whismanoid 1:77f1ee332e4a 2148 SPIwrite24bits(ADC_MODE_CONTROL, 0);
whismanoid 1:77f1ee332e4a 2149 } else {
whismanoid 1:77f1ee332e4a 2150 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2151 }
whismanoid 1:77f1ee332e4a 2152 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2153
whismanoid 1:77f1ee332e4a 2154 //----------------------------------------
whismanoid 1:77f1ee332e4a 2155 // return number of words to read
whismanoid 1:77f1ee332e4a 2156 return NumWords;
whismanoid 1:77f1ee332e4a 2157 }
whismanoid 1:77f1ee332e4a 2158
whismanoid 1:77f1ee332e4a 2159 //----------------------------------------
whismanoid 1:77f1ee332e4a 2160 // SCAN_0110_UpperExternalClock
whismanoid 1:77f1ee332e4a 2161 //
whismanoid 1:77f1ee332e4a 2162 // Measure ADC channels in sequence from channelNumber_0_15 to AIN15.
whismanoid 1:77f1ee332e4a 2163 // External clock mode.
whismanoid 1:77f1ee332e4a 2164 // @param[in] channelNumber_0_15: AIN Channel Number
whismanoid 1:77f1ee332e4a 2165 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 2166 // @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2167 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 1:77f1ee332e4a 2168 // For external clock modes, the data format depends on CHAN_ID.
whismanoid 1:77f1ee332e4a 2169 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2170 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2171 //
whismanoid 1:77f1ee332e4a 2172 int MAX11131::ScanUpperExternalClock(void)
whismanoid 1:77f1ee332e4a 2173 {
whismanoid 1:77f1ee332e4a 2174
whismanoid 1:77f1ee332e4a 2175 //----------------------------------------
whismanoid 1:77f1ee332e4a 2176 // number of words to read
whismanoid 1:77f1ee332e4a 2177 NumWords = (16 - channelNumber_0_15);
whismanoid 1:77f1ee332e4a 2178
whismanoid 1:77f1ee332e4a 2179 //----------------------------------------
whismanoid 1:77f1ee332e4a 2180 // External Clock Mode
whismanoid 1:77f1ee332e4a 2181 isExternalClock = 1;
whismanoid 1:77f1ee332e4a 2182
whismanoid 1:77f1ee332e4a 2183 //----------------------------------------
whismanoid 1:77f1ee332e4a 2184 // update device driver global variable
whismanoid 1:77f1ee332e4a 2185 ScanMode = SCAN_0110_UpperExternalClock;
whismanoid 1:77f1ee332e4a 2186
whismanoid 1:77f1ee332e4a 2187 //----------------------------------------
whismanoid 1:77f1ee332e4a 2188 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 2189 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 2190 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 2191 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 2192 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2193 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 2194 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2195 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2196
whismanoid 1:77f1ee332e4a 2197 //----------------------------------------
whismanoid 1:77f1ee332e4a 2198 // Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid 1:77f1ee332e4a 2199 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2200 ADC_MODE_CONTROL |= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2201
whismanoid 1:77f1ee332e4a 2202 //----------------------------------------
whismanoid 1:77f1ee332e4a 2203 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0110_UpperExternalClock = 6
whismanoid 1:77f1ee332e4a 2204 //~ const int SCAN_0110_UpperExternalClock = 6; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2205 ADC_MODE_CONTROL |= ((SCAN_0110_UpperExternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2206
whismanoid 1:77f1ee332e4a 2207 //----------------------------------------
whismanoid 1:77f1ee332e4a 2208 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 2209 ADC_MODE_CONTROL |= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 2210
whismanoid 1:77f1ee332e4a 2211 //----------------------------------------
whismanoid 1:77f1ee332e4a 2212 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2213 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2214
whismanoid 1:77f1ee332e4a 2215 //----------------------------------------
whismanoid 1:77f1ee332e4a 2216 // ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid 1:77f1ee332e4a 2217 // (applicable to external clock mode only)
whismanoid 1:77f1ee332e4a 2218 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 2219 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2220 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2221 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2222 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2223 ADC_MODE_CONTROL |= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid 1:77f1ee332e4a 2224
whismanoid 1:77f1ee332e4a 2225 //----------------------------------------
whismanoid 1:77f1ee332e4a 2226 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2227 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2228 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2229 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2230 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2231 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2232
whismanoid 1:77f1ee332e4a 2233 //----------------------------------------
whismanoid 1:77f1ee332e4a 2234 // return number of words to read
whismanoid 1:77f1ee332e4a 2235 return NumWords;
whismanoid 1:77f1ee332e4a 2236 }
whismanoid 1:77f1ee332e4a 2237
whismanoid 1:77f1ee332e4a 2238 //----------------------------------------
whismanoid 1:77f1ee332e4a 2239 // SCAN_0111_CustomInternalClock
whismanoid 1:77f1ee332e4a 2240 //
whismanoid 1:77f1ee332e4a 2241 // Measure selected ADC channels in sequence from AIN0 to AIN15,
whismanoid 1:77f1ee332e4a 2242 // using only the channels enabled by enabledChannelsMask.
whismanoid 1:77f1ee332e4a 2243 // Bit 0x0001 enables AIN0.
whismanoid 1:77f1ee332e4a 2244 // Bit 0x0002 enables AIN1.
whismanoid 1:77f1ee332e4a 2245 // Bit 0x0004 enables AIN2.
whismanoid 1:77f1ee332e4a 2246 // Bit 0x0008 enables AIN3.
whismanoid 1:77f1ee332e4a 2247 // Bit 0x0010 enables AIN4.
whismanoid 1:77f1ee332e4a 2248 // Bit 0x0020 enables AIN5.
whismanoid 1:77f1ee332e4a 2249 // Bit 0x0040 enables AIN6.
whismanoid 1:77f1ee332e4a 2250 // Bit 0x0080 enables AIN7.
whismanoid 1:77f1ee332e4a 2251 // Bit 0x0100 enables AIN8.
whismanoid 1:77f1ee332e4a 2252 // Bit 0x0200 enables AIN9.
whismanoid 1:77f1ee332e4a 2253 // Bit 0x0400 enables AIN10.
whismanoid 1:77f1ee332e4a 2254 // Bit 0x0800 enables AIN11.
whismanoid 1:77f1ee332e4a 2255 // Bit 0x1000 enables AIN12.
whismanoid 1:77f1ee332e4a 2256 // Bit 0x2000 enables AIN13.
whismanoid 1:77f1ee332e4a 2257 // Bit 0x4000 enables AIN14.
whismanoid 1:77f1ee332e4a 2258 // Bit 0x8000 enables AIN15.
whismanoid 1:77f1ee332e4a 2259 // Internal clock mode.
whismanoid 1:77f1ee332e4a 2260 // @param[in] enabledChannelsMask: Bitmap of AIN Channels to scan.
whismanoid 1:77f1ee332e4a 2261 // @param[in] average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid 1:77f1ee332e4a 2262 // average_0_4_8_16_32=0 to disable averaging.
whismanoid 1:77f1ee332e4a 2263 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 2264 // @param[in] swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2265 // SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid 1:77f1ee332e4a 2266 // Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 2267 // SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid 1:77f1ee332e4a 2268 // CS must be held low for minimum of 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2269 // CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 2270 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 1:77f1ee332e4a 2271 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2272 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2273 //
whismanoid 1:77f1ee332e4a 2274 int MAX11131::ScanCustomInternalClock(void)
whismanoid 1:77f1ee332e4a 2275 {
whismanoid 1:77f1ee332e4a 2276
whismanoid 1:77f1ee332e4a 2277 //----------------------------------------
whismanoid 1:77f1ee332e4a 2278 // count nWords = number of set bits in enabledChannelsMask
whismanoid 1:77f1ee332e4a 2279 uint16_t bitMask;
whismanoid 1:77f1ee332e4a 2280 int nWords = 0;
whismanoid 1:77f1ee332e4a 2281 for (bitMask = 0x8000; bitMask != 0; bitMask = bitMask / 2)
whismanoid 1:77f1ee332e4a 2282 {
whismanoid 1:77f1ee332e4a 2283 if (enabledChannelsMask & bitMask)
whismanoid 1:77f1ee332e4a 2284 {
whismanoid 1:77f1ee332e4a 2285 nWords++;
whismanoid 1:77f1ee332e4a 2286 }
whismanoid 1:77f1ee332e4a 2287 }
whismanoid 1:77f1ee332e4a 2288
whismanoid 1:77f1ee332e4a 2289 //----------------------------------------
whismanoid 1:77f1ee332e4a 2290 // number of words to read
whismanoid 1:77f1ee332e4a 2291 NumWords = nWords;
whismanoid 1:77f1ee332e4a 2292
whismanoid 1:77f1ee332e4a 2293 //----------------------------------------
whismanoid 1:77f1ee332e4a 2294 // Internal Clock Mode
whismanoid 1:77f1ee332e4a 2295 isExternalClock = 0;
whismanoid 1:77f1ee332e4a 2296
whismanoid 1:77f1ee332e4a 2297 //----------------------------------------
whismanoid 1:77f1ee332e4a 2298 // update device driver global variable
whismanoid 1:77f1ee332e4a 2299 ScanMode = SCAN_0111_CustomInternalClock;
whismanoid 1:77f1ee332e4a 2300
whismanoid 1:77f1ee332e4a 2301 //----------------------------------------
whismanoid 1:77f1ee332e4a 2302 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 2303 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 2304 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 2305 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 2306 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2307 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 2308 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2309 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2310
whismanoid 1:77f1ee332e4a 2311 //----------------------------------------
whismanoid 1:77f1ee332e4a 2312 // define write-only register ADC_CONFIGURATION
whismanoid 1:77f1ee332e4a 2313 ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid 1:77f1ee332e4a 2314 const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid 1:77f1ee332e4a 2315 const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid 1:77f1ee332e4a 2316 const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid 1:77f1ee332e4a 2317 const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid 1:77f1ee332e4a 2318 const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid 1:77f1ee332e4a 2319 const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid 1:77f1ee332e4a 2320
whismanoid 1:77f1ee332e4a 2321 //----------------------------------------
whismanoid 1:77f1ee332e4a 2322 // define write-only registers CSCAN0,CSCAN1
whismanoid 1:77f1ee332e4a 2323 CSCAN0 = 0xA000; //!< mosiData16 0xA000..0xA7FF format: 1 0 1 0 0 CHSCAN15 CHSCAN14 CHSCAN13 CHSCAN12 CHSCAN11 CHSCAN10 CHSCAN9 CHSCAN8 x x x
whismanoid 1:77f1ee332e4a 2324 const int CHSCAN15_LSB = 10; // CSCAN0.CHSCAN15
whismanoid 1:77f1ee332e4a 2325 const int CHSCAN14_LSB = 9; // CSCAN0.CHSCAN14
whismanoid 1:77f1ee332e4a 2326 const int CHSCAN13_LSB = 8; // CSCAN0.CHSCAN13
whismanoid 1:77f1ee332e4a 2327 const int CHSCAN12_LSB = 7; // CSCAN0.CHSCAN12
whismanoid 1:77f1ee332e4a 2328 const int CHSCAN11_LSB = 6; // CSCAN0.CHSCAN11
whismanoid 1:77f1ee332e4a 2329 const int CHSCAN10_LSB = 5; // CSCAN0.CHSCAN10
whismanoid 1:77f1ee332e4a 2330 const int CHSCAN9_LSB = 4; // CSCAN0.CHSCAN9
whismanoid 1:77f1ee332e4a 2331 const int CHSCAN8_LSB = 3; // CSCAN0.CHSCAN8
whismanoid 1:77f1ee332e4a 2332 CSCAN1 = 0xA800; //!< mosiData16 0xA800..0xAFFF format: 1 0 1 0 1 CHSCAN7 CHSCAN6 CHSCAN5 CHSCAN4 CHSCAN3 CHSCAN2 CHSCAN1 CHSCAN0 x x x
whismanoid 1:77f1ee332e4a 2333 const int CHSCAN7_LSB = 10; // CSCAN1.CHSCAN7
whismanoid 1:77f1ee332e4a 2334 const int CHSCAN6_LSB = 9; // CSCAN1.CHSCAN6
whismanoid 1:77f1ee332e4a 2335 const int CHSCAN5_LSB = 8; // CSCAN1.CHSCAN5
whismanoid 1:77f1ee332e4a 2336 const int CHSCAN4_LSB = 7; // CSCAN1.CHSCAN4
whismanoid 1:77f1ee332e4a 2337 const int CHSCAN3_LSB = 6; // CSCAN1.CHSCAN3
whismanoid 1:77f1ee332e4a 2338 const int CHSCAN2_LSB = 5; // CSCAN1.CHSCAN2
whismanoid 1:77f1ee332e4a 2339 const int CHSCAN1_LSB = 4; // CSCAN1.CHSCAN1
whismanoid 1:77f1ee332e4a 2340 const int CHSCAN0_LSB = 3; // CSCAN1.CHSCAN0
whismanoid 1:77f1ee332e4a 2341
whismanoid 1:77f1ee332e4a 2342 //----------------------------------------
whismanoid 1:77f1ee332e4a 2343 // if average, ADC CONFIGURATION register set AVG and NAVG[1:0]
whismanoid 1:77f1ee332e4a 2344 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 2345 // if average, ADC CONFIGURATION register set AVG ON BIT TO 1
whismanoid 1:77f1ee332e4a 2346 // if average, ADC CONFIGURATION register set NAVG[1:0] TO N
whismanoid 1:77f1ee332e4a 2347 if (average_0_4_8_16_32 == 4) {
whismanoid 1:77f1ee332e4a 2348 // Enable Averaging of 4 samples (AVGON=1, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 2349 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2350 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2351 ADC_CONFIGURATION |= ((0 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2352 } else if (average_0_4_8_16_32 == 8) {
whismanoid 1:77f1ee332e4a 2353 // Enable Averaging of 8 samples (AVGON=1, NAVG[1:0]=1)
whismanoid 1:77f1ee332e4a 2354 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2355 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2356 ADC_CONFIGURATION |= ((1 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2357 } else if (average_0_4_8_16_32 == 16) {
whismanoid 1:77f1ee332e4a 2358 // Enable Averaging of 16 samples (AVGON=1, NAVG[1:0]=2)
whismanoid 1:77f1ee332e4a 2359 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2360 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2361 ADC_CONFIGURATION |= ((2 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2362 } else if (average_0_4_8_16_32 == 32) {
whismanoid 1:77f1ee332e4a 2363 // Enable Averaging of 32 samples (AVGON=1, NAVG[1:0]=3)
whismanoid 1:77f1ee332e4a 2364 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2365 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2366 ADC_CONFIGURATION |= ((3 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2367 } else {
whismanoid 1:77f1ee332e4a 2368 // Disable Averaging (AVGON=0, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 2369 ADC_CONFIGURATION &= ~ (( AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2370 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2371 }
whismanoid 1:77f1ee332e4a 2372
whismanoid 1:77f1ee332e4a 2373 //----------------------------------------
whismanoid 1:77f1ee332e4a 2374 // SPI write ADC CONFIGURATION register
whismanoid 1:77f1ee332e4a 2375 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2376 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2377 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2378 SPIwrite16bits(ADC_CONFIGURATION);
whismanoid 1:77f1ee332e4a 2379 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2380
whismanoid 1:77f1ee332e4a 2381 //----------------------------------------
whismanoid 1:77f1ee332e4a 2382 // SET CSCAN0 CSCAN1 REGISTERS from enabledChannelsMask
whismanoid 1:77f1ee332e4a 2383 CSCAN0 = 0xA000 | (((enabledChannelsMask >> 8) & 0xFF) << 3); // CSCAN0.CHSCAN[15:8]
whismanoid 1:77f1ee332e4a 2384 CSCAN1 = 0xA800 | (((enabledChannelsMask) & 0xFF) << 3); // CSCAN1.CHSCAN[7:0]
whismanoid 1:77f1ee332e4a 2385 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2386 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2387 SPIwrite16bits(CSCAN0);
whismanoid 1:77f1ee332e4a 2388 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2389 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2390 SPIwrite16bits(CSCAN1);
whismanoid 1:77f1ee332e4a 2391 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2392
whismanoid 1:77f1ee332e4a 2393 //----------------------------------------
whismanoid 1:77f1ee332e4a 2394 // Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid 1:77f1ee332e4a 2395 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2396 ADC_MODE_CONTROL |= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2397
whismanoid 1:77f1ee332e4a 2398 //----------------------------------------
whismanoid 1:77f1ee332e4a 2399 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0111_CustomInternalClock = 7
whismanoid 1:77f1ee332e4a 2400 //~ const int SCAN_0111_CustomInternalClock = 7; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2401 ADC_MODE_CONTROL |= ((SCAN_0111_CustomInternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2402
whismanoid 1:77f1ee332e4a 2403 //----------------------------------------
whismanoid 1:77f1ee332e4a 2404 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2405 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2406
whismanoid 1:77f1ee332e4a 2407 //----------------------------------------
whismanoid 1:77f1ee332e4a 2408 // ADC MODE CONTROL register set SWCNV if CNVST pin is not used
whismanoid 1:77f1ee332e4a 2409 // ADC MODE CONTROL REGISTER SELECT THE RIGHT SWCNV BIT
whismanoid 1:77f1ee332e4a 2410 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 2411 // SWCNV=1: trigger measurement on SPI CS rising edge; CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 2412 // SWCNV=0: trigger measurement by driving CNVST pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 2413 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 2414 ADC_MODE_CONTROL |= ((swcnv_0_1 & SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 2415 } else {
whismanoid 1:77f1ee332e4a 2416 ADC_MODE_CONTROL &= ~ (( SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 2417 }
whismanoid 1:77f1ee332e4a 2418
whismanoid 1:77f1ee332e4a 2419 //----------------------------------------
whismanoid 1:77f1ee332e4a 2420 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2421 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2422 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2423 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2424 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2425 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 2426 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2427 // NOTE: Figure 7 Internal Conversions with SWCNV=1 has an error, the 17th SCLK is mislabeled as "16" should be "17".
whismanoid 1:77f1ee332e4a 2428 SPIwrite24bits(ADC_MODE_CONTROL, 0);
whismanoid 1:77f1ee332e4a 2429 } else {
whismanoid 1:77f1ee332e4a 2430 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2431 }
whismanoid 1:77f1ee332e4a 2432 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2433
whismanoid 1:77f1ee332e4a 2434 //----------------------------------------
whismanoid 1:77f1ee332e4a 2435 // return number of words to read
whismanoid 1:77f1ee332e4a 2436 return NumWords;
whismanoid 1:77f1ee332e4a 2437 }
whismanoid 1:77f1ee332e4a 2438
whismanoid 1:77f1ee332e4a 2439 //----------------------------------------
whismanoid 1:77f1ee332e4a 2440 // SCAN_1000_CustomExternalClock
whismanoid 1:77f1ee332e4a 2441 //
whismanoid 1:77f1ee332e4a 2442 // Measure selected ADC channels in sequence from AIN0 to AIN15,
whismanoid 1:77f1ee332e4a 2443 // using only the channels enabled by enabledChannelsMask.
whismanoid 1:77f1ee332e4a 2444 // Bit 0x0001 enables AIN0.
whismanoid 1:77f1ee332e4a 2445 // Bit 0x0002 enables AIN1.
whismanoid 1:77f1ee332e4a 2446 // Bit 0x0004 enables AIN2.
whismanoid 1:77f1ee332e4a 2447 // Bit 0x0008 enables AIN3.
whismanoid 1:77f1ee332e4a 2448 // Bit 0x0010 enables AIN4.
whismanoid 1:77f1ee332e4a 2449 // Bit 0x0020 enables AIN5.
whismanoid 1:77f1ee332e4a 2450 // Bit 0x0040 enables AIN6.
whismanoid 1:77f1ee332e4a 2451 // Bit 0x0080 enables AIN7.
whismanoid 1:77f1ee332e4a 2452 // Bit 0x0100 enables AIN8.
whismanoid 1:77f1ee332e4a 2453 // Bit 0x0200 enables AIN9.
whismanoid 1:77f1ee332e4a 2454 // Bit 0x0400 enables AIN10.
whismanoid 1:77f1ee332e4a 2455 // Bit 0x0800 enables AIN11.
whismanoid 1:77f1ee332e4a 2456 // Bit 0x1000 enables AIN12.
whismanoid 1:77f1ee332e4a 2457 // Bit 0x2000 enables AIN13.
whismanoid 1:77f1ee332e4a 2458 // Bit 0x4000 enables AIN14.
whismanoid 1:77f1ee332e4a 2459 // Bit 0x8000 enables AIN15.
whismanoid 1:77f1ee332e4a 2460 // External clock mode.
whismanoid 1:77f1ee332e4a 2461 // @param[in] enabledChannelsMask: Bitmap of AIN Channels to scan.
whismanoid 1:77f1ee332e4a 2462 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 2463 // @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2464 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 1:77f1ee332e4a 2465 // For external clock modes, the data format depends on CHAN_ID.
whismanoid 1:77f1ee332e4a 2466 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2467 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2468 //
whismanoid 1:77f1ee332e4a 2469 int MAX11131::ScanCustomExternalClock(void)
whismanoid 1:77f1ee332e4a 2470 {
whismanoid 1:77f1ee332e4a 2471
whismanoid 1:77f1ee332e4a 2472 //----------------------------------------
whismanoid 1:77f1ee332e4a 2473 // count nWords = number of set bits in enabledChannelsMask
whismanoid 1:77f1ee332e4a 2474 uint16_t bitMask;
whismanoid 1:77f1ee332e4a 2475 int nWords = 0;
whismanoid 1:77f1ee332e4a 2476 for (bitMask = 0x8000; bitMask != 0; bitMask = bitMask / 2)
whismanoid 1:77f1ee332e4a 2477 {
whismanoid 1:77f1ee332e4a 2478 if (enabledChannelsMask & bitMask)
whismanoid 1:77f1ee332e4a 2479 {
whismanoid 1:77f1ee332e4a 2480 nWords++;
whismanoid 1:77f1ee332e4a 2481 }
whismanoid 1:77f1ee332e4a 2482 }
whismanoid 1:77f1ee332e4a 2483
whismanoid 1:77f1ee332e4a 2484 //----------------------------------------
whismanoid 1:77f1ee332e4a 2485 // number of words to read
whismanoid 1:77f1ee332e4a 2486 NumWords = nWords;
whismanoid 1:77f1ee332e4a 2487
whismanoid 1:77f1ee332e4a 2488 //----------------------------------------
whismanoid 1:77f1ee332e4a 2489 // External Clock Mode
whismanoid 1:77f1ee332e4a 2490 isExternalClock = 1;
whismanoid 1:77f1ee332e4a 2491
whismanoid 1:77f1ee332e4a 2492 //----------------------------------------
whismanoid 1:77f1ee332e4a 2493 // update device driver global variable
whismanoid 1:77f1ee332e4a 2494 ScanMode = SCAN_1000_CustomExternalClock;
whismanoid 1:77f1ee332e4a 2495
whismanoid 1:77f1ee332e4a 2496 //----------------------------------------
whismanoid 1:77f1ee332e4a 2497 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 2498 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 2499 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 2500 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 2501 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2502 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 2503 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2504 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2505
whismanoid 1:77f1ee332e4a 2506 //----------------------------------------
whismanoid 1:77f1ee332e4a 2507 // define write-only registers CSCAN0,CSCAN1
whismanoid 1:77f1ee332e4a 2508 CSCAN0 = 0xA000; //!< mosiData16 0xA000..0xA7FF format: 1 0 1 0 0 CHSCAN15 CHSCAN14 CHSCAN13 CHSCAN12 CHSCAN11 CHSCAN10 CHSCAN9 CHSCAN8 x x x
whismanoid 1:77f1ee332e4a 2509 const int CHSCAN15_LSB = 10; // CSCAN0.CHSCAN15
whismanoid 1:77f1ee332e4a 2510 const int CHSCAN14_LSB = 9; // CSCAN0.CHSCAN14
whismanoid 1:77f1ee332e4a 2511 const int CHSCAN13_LSB = 8; // CSCAN0.CHSCAN13
whismanoid 1:77f1ee332e4a 2512 const int CHSCAN12_LSB = 7; // CSCAN0.CHSCAN12
whismanoid 1:77f1ee332e4a 2513 const int CHSCAN11_LSB = 6; // CSCAN0.CHSCAN11
whismanoid 1:77f1ee332e4a 2514 const int CHSCAN10_LSB = 5; // CSCAN0.CHSCAN10
whismanoid 1:77f1ee332e4a 2515 const int CHSCAN9_LSB = 4; // CSCAN0.CHSCAN9
whismanoid 1:77f1ee332e4a 2516 const int CHSCAN8_LSB = 3; // CSCAN0.CHSCAN8
whismanoid 1:77f1ee332e4a 2517 CSCAN1 = 0xA800; //!< mosiData16 0xA800..0xAFFF format: 1 0 1 0 1 CHSCAN7 CHSCAN6 CHSCAN5 CHSCAN4 CHSCAN3 CHSCAN2 CHSCAN1 CHSCAN0 x x x
whismanoid 1:77f1ee332e4a 2518 const int CHSCAN7_LSB = 10; // CSCAN1.CHSCAN7
whismanoid 1:77f1ee332e4a 2519 const int CHSCAN6_LSB = 9; // CSCAN1.CHSCAN6
whismanoid 1:77f1ee332e4a 2520 const int CHSCAN5_LSB = 8; // CSCAN1.CHSCAN5
whismanoid 1:77f1ee332e4a 2521 const int CHSCAN4_LSB = 7; // CSCAN1.CHSCAN4
whismanoid 1:77f1ee332e4a 2522 const int CHSCAN3_LSB = 6; // CSCAN1.CHSCAN3
whismanoid 1:77f1ee332e4a 2523 const int CHSCAN2_LSB = 5; // CSCAN1.CHSCAN2
whismanoid 1:77f1ee332e4a 2524 const int CHSCAN1_LSB = 4; // CSCAN1.CHSCAN1
whismanoid 1:77f1ee332e4a 2525 const int CHSCAN0_LSB = 3; // CSCAN1.CHSCAN0
whismanoid 1:77f1ee332e4a 2526
whismanoid 1:77f1ee332e4a 2527 //----------------------------------------
whismanoid 1:77f1ee332e4a 2528 // SET CSCAN0 CSCAN1 REGISTERS from enabledChannelsMask
whismanoid 1:77f1ee332e4a 2529 CSCAN0 = 0xA000 | (((enabledChannelsMask >> 8) & 0xFF) << 3); // CSCAN0.CHSCAN[15:8]
whismanoid 1:77f1ee332e4a 2530 CSCAN1 = 0xA800 | (((enabledChannelsMask) & 0xFF) << 3); // CSCAN1.CHSCAN[7:0]
whismanoid 1:77f1ee332e4a 2531 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2532 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2533 SPIwrite16bits(CSCAN0);
whismanoid 1:77f1ee332e4a 2534 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2535 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2536 SPIwrite16bits(CSCAN1);
whismanoid 1:77f1ee332e4a 2537 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2538
whismanoid 1:77f1ee332e4a 2539 //----------------------------------------
whismanoid 1:77f1ee332e4a 2540 // Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid 1:77f1ee332e4a 2541 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2542 ADC_MODE_CONTROL |= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2543
whismanoid 1:77f1ee332e4a 2544 //----------------------------------------
whismanoid 1:77f1ee332e4a 2545 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_1000_CustomExternalClock = 8
whismanoid 1:77f1ee332e4a 2546 //~ const int SCAN_1000_CustomExternalClock = 8; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2547 ADC_MODE_CONTROL |= ((SCAN_1000_CustomExternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2548
whismanoid 1:77f1ee332e4a 2549 //----------------------------------------
whismanoid 1:77f1ee332e4a 2550 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2551 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2552
whismanoid 1:77f1ee332e4a 2553 //----------------------------------------
whismanoid 1:77f1ee332e4a 2554 // ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid 1:77f1ee332e4a 2555 // (applicable to external clock mode only)
whismanoid 1:77f1ee332e4a 2556 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 2557 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2558 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2559 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2560 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2561 ADC_MODE_CONTROL |= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid 1:77f1ee332e4a 2562
whismanoid 1:77f1ee332e4a 2563 //----------------------------------------
whismanoid 1:77f1ee332e4a 2564 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2565 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2566 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2567 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2568 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2569 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2570
whismanoid 1:77f1ee332e4a 2571 //----------------------------------------
whismanoid 1:77f1ee332e4a 2572 // return number of words to read
whismanoid 1:77f1ee332e4a 2573 return NumWords;
whismanoid 1:77f1ee332e4a 2574 }
whismanoid 1:77f1ee332e4a 2575
whismanoid 1:77f1ee332e4a 2576 //----------------------------------------
whismanoid 1:77f1ee332e4a 2577 // SCAN_1001_SampleSetExternalClock
whismanoid 1:77f1ee332e4a 2578 //
whismanoid 1:77f1ee332e4a 2579 // Measure ADC channels in an arbitrary pattern.
whismanoid 1:77f1ee332e4a 2580 // Channels can be visited in any order, with repetition allowed.
whismanoid 1:77f1ee332e4a 2581 // External clock mode.
whismanoid 1:77f1ee332e4a 2582 // @pre enabledChannelsPatternLength_1_256: number of channel selections
whismanoid 1:77f1ee332e4a 2583 // @pre enabledChannelsPattern: array containing channel selection pattern
whismanoid 1:77f1ee332e4a 2584 // In the array, one channel select per byte.
whismanoid 1:77f1ee332e4a 2585 // In the SPI interface, immediately after SAMPLESET register is written,
whismanoid 1:77f1ee332e4a 2586 // each byte encodes two channelNumber selections.
whismanoid 1:77f1ee332e4a 2587 // The high 4 bits encode the first channelNumber.
whismanoid 1:77f1ee332e4a 2588 // (((enabledChannelsPattern[0]) & 0x0F) << 4) | ((enabledChannelsPattern[1]) & 0x0F)
whismanoid 1:77f1ee332e4a 2589 // If it is an odd number of channels, additional nybbles will be ignored.
whismanoid 1:77f1ee332e4a 2590 // CS will be asserted low during the entire SAMPLESET pattern selection.
whismanoid 1:77f1ee332e4a 2591 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 2592 // @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2593 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 1:77f1ee332e4a 2594 // For external clock modes, the data format depends on CHAN_ID.
whismanoid 1:77f1ee332e4a 2595 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2596 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2597 //
whismanoid 1:77f1ee332e4a 2598 int MAX11131::ScanSampleSetExternalClock(void)
whismanoid 1:77f1ee332e4a 2599 {
whismanoid 1:77f1ee332e4a 2600
whismanoid 1:77f1ee332e4a 2601 //----------------------------------------
whismanoid 1:77f1ee332e4a 2602 // number of words to read
whismanoid 1:77f1ee332e4a 2603 NumWords = ((enabledChannelsPatternLength_1_256 != 0) ? enabledChannelsPatternLength_1_256 : 256 );
whismanoid 1:77f1ee332e4a 2604
whismanoid 1:77f1ee332e4a 2605 //----------------------------------------
whismanoid 1:77f1ee332e4a 2606 // External Clock Mode
whismanoid 1:77f1ee332e4a 2607 isExternalClock = 1;
whismanoid 1:77f1ee332e4a 2608
whismanoid 1:77f1ee332e4a 2609 //----------------------------------------
whismanoid 1:77f1ee332e4a 2610 // update device driver global variable
whismanoid 1:77f1ee332e4a 2611 ScanMode = SCAN_1001_SampleSetExternalClock;
whismanoid 1:77f1ee332e4a 2612
whismanoid 1:77f1ee332e4a 2613 //----------------------------------------
whismanoid 1:77f1ee332e4a 2614 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 2615 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 2616 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 2617 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 2618 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2619 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 2620 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2621 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2622
whismanoid 1:77f1ee332e4a 2623 //----------------------------------------
whismanoid 1:77f1ee332e4a 2624 // Initialize shadow of write-only register SAMPLESET.
whismanoid 1:77f1ee332e4a 2625 // Do not write to SAMPLESET at this time.
whismanoid 1:77f1ee332e4a 2626 // A write to SAMPLESET must be followed by specified number of pattern entry words.
whismanoid 1:77f1ee332e4a 2627 // See ScanSampleSetExternalClock function for details.
whismanoid 1:77f1ee332e4a 2628 SAMPLESET = 0xB000; //!< mosiData16 0xB000..0xB7FF format: 1 0 1 1 0 SEQ_LENGTH[7:0] x x x
whismanoid 1:77f1ee332e4a 2629 const int SAMPLESET_LSB = 3; const int SAMPLESET_BITS = 0xFF; // SAMPLESET.SEQ_LENGTH[7:0]
whismanoid 1:77f1ee332e4a 2630
whismanoid 1:77f1ee332e4a 2631 //----------------------------------------
whismanoid 1:77f1ee332e4a 2632 // SampleSet register set SEQ_DEPTH[7:0] TO SET CHANNEL CAPTURE DEPTH; FOLLOW SampleSet REGISTER WITH CHANNEL PATTERN OF THE SAME SIZE AS SEQUENCE DEPTH
whismanoid 1:77f1ee332e4a 2633 // NOTE: SAMPLESET.SEQ_LENGTH[7:0] is the number of channel entries in the pattern.
whismanoid 1:77f1ee332e4a 2634 // NOTE: Each channel entry is 4 bits. The first 4 bits are the first channel in the sequence.
whismanoid 1:77f1ee332e4a 2635 // NOTE: Channels can be repeated in any arbitrary order.
whismanoid 1:77f1ee332e4a 2636 // NOTE: The channel entry pattern is sent immediately after writing SAMPLESET.
whismanoid 1:77f1ee332e4a 2637 // NOTE: Keep CS low during the entire SAMPLESET pattern entry.
whismanoid 1:77f1ee332e4a 2638 const int seq_length_minus_one_0_255 = enabledChannelsPatternLength_1_256 - 1;
whismanoid 1:77f1ee332e4a 2639 SAMPLESET = 0xB000;
whismanoid 1:77f1ee332e4a 2640 //SAMPLESET &= ~ (( SAMPLESET_BITS) << SAMPLESET_LSB);
whismanoid 1:77f1ee332e4a 2641 SAMPLESET |= ((seq_length_minus_one_0_255 & SAMPLESET_BITS) << SAMPLESET_LSB);
whismanoid 1:77f1ee332e4a 2642 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2643 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2644 SPIwrite16bits(SAMPLESET); // SAMPLESET must be followed by several more bytes, length specified by SEQ_LENGTH[7:0]
whismanoid 1:77f1ee332e4a 2645 // pack enabledChannelsPattern[index] into nybbles
whismanoid 1:77f1ee332e4a 2646 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2647 // NOTE: Send the sampleset pattern, with 4 entries packed into each 16-bit SPI word. Pad unused entries with 0.
whismanoid 1:77f1ee332e4a 2648 SPI_MOSI_Semantic = 2; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2649 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2650 // NOTE: Keep CS low during the entire SAMPLESET pattern entry.
whismanoid 1:77f1ee332e4a 2651 int entryIndex;
whismanoid 1:77f1ee332e4a 2652 for (entryIndex = 0; entryIndex < enabledChannelsPatternLength_1_256; entryIndex += 4)
whismanoid 1:77f1ee332e4a 2653 {
whismanoid 1:77f1ee332e4a 2654 uint16_t pack4channels = 0;
whismanoid 1:77f1ee332e4a 2655 pack4channels |= (((enabledChannelsPattern[entryIndex + 0]) & 0x0F) << 12);
whismanoid 1:77f1ee332e4a 2656 if ((entryIndex + 1) < enabledChannelsPatternLength_1_256) {
whismanoid 1:77f1ee332e4a 2657 pack4channels |= (((enabledChannelsPattern[entryIndex + 1]) & 0x0F) << 8);
whismanoid 1:77f1ee332e4a 2658 }
whismanoid 1:77f1ee332e4a 2659 if ((entryIndex + 2) < enabledChannelsPatternLength_1_256) {
whismanoid 1:77f1ee332e4a 2660 pack4channels |= (((enabledChannelsPattern[entryIndex + 2]) & 0x0F) << 4);
whismanoid 1:77f1ee332e4a 2661 }
whismanoid 1:77f1ee332e4a 2662 if ((entryIndex + 3) < enabledChannelsPatternLength_1_256) {
whismanoid 1:77f1ee332e4a 2663 pack4channels |= ((enabledChannelsPattern[entryIndex + 3]) & 0x0F);
whismanoid 1:77f1ee332e4a 2664 }
whismanoid 1:77f1ee332e4a 2665 SPIwrite16bits(pack4channels);
whismanoid 1:77f1ee332e4a 2666 }
whismanoid 1:77f1ee332e4a 2667 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2668
whismanoid 1:77f1ee332e4a 2669 //----------------------------------------
whismanoid 1:77f1ee332e4a 2670 // Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid 1:77f1ee332e4a 2671 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2672 ADC_MODE_CONTROL |= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2673
whismanoid 1:77f1ee332e4a 2674 //----------------------------------------
whismanoid 1:77f1ee332e4a 2675 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_1001_SampleSetExternalClock = 9
whismanoid 1:77f1ee332e4a 2676 //~ const int SCAN_1001_SampleSetExternalClock = 9; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2677 ADC_MODE_CONTROL |= ((SCAN_1001_SampleSetExternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2678
whismanoid 1:77f1ee332e4a 2679 //----------------------------------------
whismanoid 1:77f1ee332e4a 2680 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 2681 ADC_MODE_CONTROL |= ((0 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 2682
whismanoid 1:77f1ee332e4a 2683 //----------------------------------------
whismanoid 1:77f1ee332e4a 2684 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2685 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2686
whismanoid 1:77f1ee332e4a 2687 //----------------------------------------
whismanoid 1:77f1ee332e4a 2688 // ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid 1:77f1ee332e4a 2689 // (applicable to external clock mode only)
whismanoid 1:77f1ee332e4a 2690 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 2691 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2692 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2693 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2694 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2695 ADC_MODE_CONTROL |= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid 1:77f1ee332e4a 2696
whismanoid 1:77f1ee332e4a 2697 //----------------------------------------
whismanoid 1:77f1ee332e4a 2698 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2699 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2700 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2701 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2702 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2703 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2704
whismanoid 1:77f1ee332e4a 2705 //----------------------------------------
whismanoid 1:77f1ee332e4a 2706 // return number of words to read
whismanoid 1:77f1ee332e4a 2707 return NumWords;
whismanoid 1:77f1ee332e4a 2708 }
whismanoid 1:77f1ee332e4a 2709
whismanoid 1:77f1ee332e4a 2710 //----------------------------------------
whismanoid 1:77f1ee332e4a 2711 // Example configure and perform some measurements in ScanManual mode.
whismanoid 1:77f1ee332e4a 2712 // @param[out] pd_mean = address for double mean (avearge)
whismanoid 1:77f1ee332e4a 2713 // @param[out] pd_variance = address for double variance (variance)
whismanoid 1:77f1ee332e4a 2714 // @param[out] pd_stddev = address for double stddev (standard deviation)
whismanoid 1:77f1ee332e4a 2715 // @param[out] pd_Sx = address for double Sx (sum of all X)
whismanoid 1:77f1ee332e4a 2716 // @param[out] pd_Sxx = address for double Sxx (sum of squares of each X)
whismanoid 1:77f1ee332e4a 2717 void MAX11131::Example_ScanManual(int channelNumber_0_15, int nWords,
whismanoid 1:77f1ee332e4a 2718 double* pd_mean, double* pd_variance, double* pd_stddev,
whismanoid 1:77f1ee332e4a 2719 double* pd_Sx, double* pd_Sxx)
whismanoid 1:77f1ee332e4a 2720 {
whismanoid 1:77f1ee332e4a 2721
whismanoid 1:77f1ee332e4a 2722 //----------------------------------------
whismanoid 1:77f1ee332e4a 2723 // configure and perform some measurements in ScanManual mode
whismanoid 1:77f1ee332e4a 2724 Init();
whismanoid 1:77f1ee332e4a 2725 channelNumber_0_15 = channelNumber_0_15; // Analog Input Channel Select AIN0..
whismanoid 1:77f1ee332e4a 2726 PowerManagement_0_2 = 0; // Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 2727 chan_id_0_1 = 1; // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2728 // const int nWords = 100;
whismanoid 1:77f1ee332e4a 2729 double Sx = 0;
whismanoid 1:77f1ee332e4a 2730 double Sxx = 0;
whismanoid 1:77f1ee332e4a 2731 int index;
whismanoid 1:77f1ee332e4a 2732 ScanManual();
whismanoid 1:77f1ee332e4a 2733 for (index = 0; index < nWords; index++)
whismanoid 1:77f1ee332e4a 2734 {
whismanoid 1:77f1ee332e4a 2735 int16_t misoData16 = ScanRead();
whismanoid 1:77f1ee332e4a 2736 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2737 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2738 int16_t value_u12 = (misoData16 & 0x0FFF);
whismanoid 1:77f1ee332e4a 2739 int channelId = ((misoData16 >> 12) & 0x000F);
whismanoid 1:77f1ee332e4a 2740 Sx = Sx + value_u12;
whismanoid 1:77f1ee332e4a 2741 Sxx = Sxx + ((double)value_u12 * value_u12);
whismanoid 1:77f1ee332e4a 2742 }
whismanoid 1:77f1ee332e4a 2743 if (pd_Sx != 0) {
whismanoid 1:77f1ee332e4a 2744 *(pd_Sx) = Sx;
whismanoid 1:77f1ee332e4a 2745 }
whismanoid 1:77f1ee332e4a 2746 if (pd_Sxx != 0) {
whismanoid 1:77f1ee332e4a 2747 *(pd_Sxx) = Sxx;
whismanoid 1:77f1ee332e4a 2748 }
whismanoid 1:77f1ee332e4a 2749 if (pd_mean != 0) {
whismanoid 1:77f1ee332e4a 2750 *(pd_mean) = Sx / nWords;
whismanoid 1:77f1ee332e4a 2751 }
whismanoid 1:77f1ee332e4a 2752 if (nWords >= 2)
whismanoid 1:77f1ee332e4a 2753 {
whismanoid 1:77f1ee332e4a 2754 if (pd_variance != 0) {
whismanoid 1:77f1ee332e4a 2755 // TODO1: is this variance calculation too naive to work reliably?
whismanoid 1:77f1ee332e4a 2756 // see https://en.wikipedia.org/wiki/Algorithms_for_calculating_variance
whismanoid 1:77f1ee332e4a 2757 *(pd_variance) = (Sxx - ( Sx * Sx / nWords) ) / (nWords - 1);
whismanoid 1:77f1ee332e4a 2758 }
whismanoid 1:77f1ee332e4a 2759 if (pd_stddev != 0) {
whismanoid 1:77f1ee332e4a 2760 *(pd_stddev) = sqrt( *(pd_variance) );
whismanoid 1:77f1ee332e4a 2761 }
whismanoid 1:77f1ee332e4a 2762 }
whismanoid 1:77f1ee332e4a 2763 }
whismanoid 1:77f1ee332e4a 2764
whismanoid 1:77f1ee332e4a 2765
whismanoid 1:77f1ee332e4a 2766 // End of file