Maxim Integrated / MAX11131

Maxim Integrated MAX11131 SPI 12-bit 16-channel ADC with SampleSet

Dependents:   MAX11131BOB_Tester MAX11131BOB_12bit_16ch_SampleSet_SPI_ADC MAX11131BOB_Serial_Tester

MAX11131.cpp@9:8d47cb713984, 2021-04-13 (annotated)

Committer:
whismanoid
Date:
Tue Apr 13 21:25:12 2021 -0700
Revision:
9:8d47cb713984
Parent:
6:cb7bdeb185d0
Child:
10:92aedaa14cce
update platform support

Who changed what in which revision?

UserRevisionLine numberNew contents of line
whismanoid 9:8d47cb713984 1 // /*******************************************************************************
whismanoid 9:8d47cb713984 2 // * Copyright (C) 2021 Maxim Integrated Products, Inc., All Rights Reserved.
whismanoid 1:77f1ee332e4a 3 // *
whismanoid 1:77f1ee332e4a 4 // * Permission is hereby granted, free of charge, to any person obtaining a
whismanoid 1:77f1ee332e4a 5 // * copy of this software and associated documentation files (the "Software"),
whismanoid 1:77f1ee332e4a 6 // * to deal in the Software without restriction, including without limitation
whismanoid 1:77f1ee332e4a 7 // * the rights to use, copy, modify, merge, publish, distribute, sublicense,
whismanoid 1:77f1ee332e4a 8 // * and/or sell copies of the Software, and to permit persons to whom the
whismanoid 1:77f1ee332e4a 9 // * Software is furnished to do so, subject to the following conditions:
whismanoid 1:77f1ee332e4a 10 // *
whismanoid 1:77f1ee332e4a 11 // * The above copyright notice and this permission notice shall be included
whismanoid 1:77f1ee332e4a 12 // * in all copies or substantial portions of the Software.
whismanoid 1:77f1ee332e4a 13 // *
whismanoid 1:77f1ee332e4a 14 // * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
whismanoid 1:77f1ee332e4a 15 // * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
whismanoid 1:77f1ee332e4a 16 // * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
whismanoid 1:77f1ee332e4a 17 // * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
whismanoid 1:77f1ee332e4a 18 // * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
whismanoid 1:77f1ee332e4a 19 // * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
whismanoid 1:77f1ee332e4a 20 // * OTHER DEALINGS IN THE SOFTWARE.
whismanoid 1:77f1ee332e4a 21 // *
whismanoid 1:77f1ee332e4a 22 // * Except as contained in this notice, the name of Maxim Integrated
whismanoid 1:77f1ee332e4a 23 // * Products, Inc. shall not be used except as stated in the Maxim Integrated
whismanoid 1:77f1ee332e4a 24 // * Products, Inc. Branding Policy.
whismanoid 1:77f1ee332e4a 25 // *
whismanoid 1:77f1ee332e4a 26 // * The mere transfer of this software does not imply any licenses
whismanoid 1:77f1ee332e4a 27 // * of trade secrets, proprietary technology, copyrights, patents,
whismanoid 1:77f1ee332e4a 28 // * trademarks, maskwork rights, or any other form of intellectual
whismanoid 1:77f1ee332e4a 29 // * property whatsoever. Maxim Integrated Products, Inc. retains all
whismanoid 1:77f1ee332e4a 30 // * ownership rights.
whismanoid 1:77f1ee332e4a 31 // *******************************************************************************
whismanoid 1:77f1ee332e4a 32 // */
whismanoid 1:77f1ee332e4a 33 // *********************************************************************
whismanoid 1:77f1ee332e4a 34 // @file MAX11131.cpp
whismanoid 1:77f1ee332e4a 35 // *********************************************************************
whismanoid 1:77f1ee332e4a 36 // Device Driver file
whismanoid 1:77f1ee332e4a 37 // DO NOT EDIT; except areas designated "CUSTOMIZE". Automatically generated file.
whismanoid 1:77f1ee332e4a 38 // generated by XMLSystemOfDevicesToMBED.py
whismanoid 1:77f1ee332e4a 39 // System Name = ExampleSystem
whismanoid 1:77f1ee332e4a 40 // System Description = Device driver example
whismanoid 1:77f1ee332e4a 41
whismanoid 1:77f1ee332e4a 42 #include "MAX11131.h"
whismanoid 1:77f1ee332e4a 43
whismanoid 1:77f1ee332e4a 44 // Device Name = MAX11131
whismanoid 1:77f1ee332e4a 45 // Device Description = 3Msps, Low-Power, Serial SPI 12-Bit, 16-Channel, Differential/Single-Ended Input, SAR ADC
whismanoid 6:cb7bdeb185d0 46 // Device DeviceBriefDescription = 12-bit 3Msps 16-ch ADC
whismanoid 1:77f1ee332e4a 47 // Device Manufacturer = Maxim Integrated
whismanoid 1:77f1ee332e4a 48 // Device PartNumber = MAX11131ATI+
whismanoid 1:77f1ee332e4a 49 // Device RegValue_Width = DataWidth16bit_HL
whismanoid 1:77f1ee332e4a 50 //
whismanoid 1:77f1ee332e4a 51 // ADC MaxOutputDataRate = 3Msps
whismanoid 1:77f1ee332e4a 52 // ADC NumChannels = 16
whismanoid 1:77f1ee332e4a 53 // ADC ResolutionBits = 12
whismanoid 1:77f1ee332e4a 54 //
whismanoid 1:77f1ee332e4a 55 // SPI CS = ActiveLow
whismanoid 1:77f1ee332e4a 56 // SPI FrameStart = CS
whismanoid 1:77f1ee332e4a 57 // SPI CPOL = 1
whismanoid 1:77f1ee332e4a 58 // SPI CPHA = 1
whismanoid 1:77f1ee332e4a 59 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 1:77f1ee332e4a 60 // SPI SCLK Idle High
whismanoid 1:77f1ee332e4a 61 // SPI SCLKMaxMHz = 48
whismanoid 1:77f1ee332e4a 62 // SPI SCLKMinMHz = 0.48
whismanoid 1:77f1ee332e4a 63 //
whismanoid 1:77f1ee332e4a 64 // InputPin Name = CNVST
whismanoid 1:77f1ee332e4a 65 // InputPin Description = Active-Low Conversion Start Input/Analog Input 14
whismanoid 1:77f1ee332e4a 66 // InputPin Function = Trigger
whismanoid 1:77f1ee332e4a 67 //
whismanoid 1:77f1ee332e4a 68 // InputPin Name = REF+
whismanoid 1:77f1ee332e4a 69 // InputPin Description = External Positive Reference Input. Apply a reference voltage at REF+. Bypass to GND with a 0.47uF capacitor.
whismanoid 1:77f1ee332e4a 70 // InputPin Function = Reference
whismanoid 1:77f1ee332e4a 71 //
whismanoid 1:77f1ee332e4a 72 // InputPin Name = REF-/AIN15
whismanoid 1:77f1ee332e4a 73 // InputPin Description = External Differential Reference Negative Input/Analog Input 15
whismanoid 1:77f1ee332e4a 74 // InputPin Function = Reference
whismanoid 1:77f1ee332e4a 75 //
whismanoid 1:77f1ee332e4a 76 // OutputPin Name = EOC
whismanoid 1:77f1ee332e4a 77 // OutputPin Description = End of Conversion Output. Data is valid after EOC pulls low (Internal clock mode only).
whismanoid 1:77f1ee332e4a 78 // OutputPin Function = Event
whismanoid 1:77f1ee332e4a 79 //
whismanoid 1:77f1ee332e4a 80 // SupplyPin Name = VDD
whismanoid 1:77f1ee332e4a 81 // SupplyPin Description = Power-Supply Input. Bypass to GND with a 10uF in parallel with a 0.1uF capacitors.
whismanoid 1:77f1ee332e4a 82 // SupplyPin VinMax = 3.6
whismanoid 1:77f1ee332e4a 83 // SupplyPin VinMin = 2.35
whismanoid 1:77f1ee332e4a 84 // SupplyPin Function = Analog
whismanoid 1:77f1ee332e4a 85 //
whismanoid 1:77f1ee332e4a 86 // SupplyPin Name = OVDD
whismanoid 1:77f1ee332e4a 87 // SupplyPin Description = Interface Digital Power-Supply Input. Bypass to GND with a 10uF in parallel with a 0.1uF capacitors.
whismanoid 1:77f1ee332e4a 88 // SupplyPin VinMax = 3.6
whismanoid 1:77f1ee332e4a 89 // SupplyPin VinMin = 1.5
whismanoid 1:77f1ee332e4a 90 // SupplyPin Function = Digital
whismanoid 1:77f1ee332e4a 91 //
whismanoid 1:77f1ee332e4a 92
whismanoid 1:77f1ee332e4a 93 MAX11131::MAX11131(SPI &spi, DigitalOut &cs_pin, // SPI interface
whismanoid 1:77f1ee332e4a 94 DigitalOut &CNVST_pin, // Digital Trigger Input to MAX11131 device
whismanoid 6:cb7bdeb185d0 95 // AnalogOut &REF_plus_pin, // Reference Input to MAX11131 device
whismanoid 6:cb7bdeb185d0 96 // AnalogOut &REF_minus_slash_AIN15_pin, // Reference Input to MAX11131 device
whismanoid 1:77f1ee332e4a 97 DigitalIn &EOC_pin, // Digital Event Output from MAX11131 device
whismanoid 1:77f1ee332e4a 98 MAX11131_ic_t ic_variant)
whismanoid 1:77f1ee332e4a 99 : m_spi(spi), m_cs_pin(cs_pin), // SPI interface
whismanoid 1:77f1ee332e4a 100 m_CNVST_pin(CNVST_pin), // Digital Trigger Input to MAX11131 device
whismanoid 6:cb7bdeb185d0 101 // m_REF_plus_pin(REF_plus_pin), // Reference Input to MAX11131 device
whismanoid 6:cb7bdeb185d0 102 // m_REF_minus_slash_AIN15_pin(REF_minus_slash_AIN15_pin), // Reference Input to MAX11131 device
whismanoid 1:77f1ee332e4a 103 m_EOC_pin(EOC_pin), // Digital Event Output from MAX11131 device
whismanoid 1:77f1ee332e4a 104 m_ic_variant(ic_variant)
whismanoid 1:77f1ee332e4a 105 {
whismanoid 1:77f1ee332e4a 106 // SPI CS = ActiveLow
whismanoid 1:77f1ee332e4a 107 // SPI FrameStart = CS
whismanoid 1:77f1ee332e4a 108 m_SPI_cs_state = 1;
whismanoid 9:8d47cb713984 109 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 9:8d47cb713984 110 m_cs_pin = m_SPI_cs_state;
whismanoid 9:8d47cb713984 111 }
whismanoid 1:77f1ee332e4a 112
whismanoid 1:77f1ee332e4a 113 // SPI CPOL = 1
whismanoid 1:77f1ee332e4a 114 // SPI CPHA = 1
whismanoid 1:77f1ee332e4a 115 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 1:77f1ee332e4a 116 // SPI SCLK Idle High
whismanoid 6:cb7bdeb185d0 117 m_SPI_dataMode = 3; //SPI_MODE3; // CPOL=1,CPHA=1: Rising Edge stable; SCLK idle High
whismanoid 1:77f1ee332e4a 118 m_spi.format(8,m_SPI_dataMode); // int bits_must_be_8, int mode=0_3 CPOL=0,CPHA=0
whismanoid 1:77f1ee332e4a 119
whismanoid 1:77f1ee332e4a 120 // SPI SCLKMaxMHz = 48
whismanoid 1:77f1ee332e4a 121 // SPI SCLKMinMHz = 0.48
whismanoid 1:77f1ee332e4a 122 //#define SPI_SCLK_Hz 48000000 // 48MHz
whismanoid 1:77f1ee332e4a 123 //#define SPI_SCLK_Hz 24000000 // 24MHz
whismanoid 1:77f1ee332e4a 124 //#define SPI_SCLK_Hz 12000000 // 12MHz
whismanoid 3:621191a7e3fd 125 //#define SPI_SCLK_Hz 6000000 // 6MHz
whismanoid 1:77f1ee332e4a 126 //#define SPI_SCLK_Hz 4000000 // 4MHz
whismanoid 1:77f1ee332e4a 127 //#define SPI_SCLK_Hz 2000000 // 2MHz
whismanoid 1:77f1ee332e4a 128 //#define SPI_SCLK_Hz 1000000 // 1MHz
whismanoid 3:621191a7e3fd 129 #if defined(TARGET_MAX32600)
whismanoid 3:621191a7e3fd 130 // MAX11131BOB_Serial_Tester on MAX32600MBED limit SCLK=6MHz
whismanoid 3:621191a7e3fd 131 m_SPI_SCLK_Hz = 6000000; // 6MHz; MAX11131 limit is 48MHz
whismanoid 3:621191a7e3fd 132 #else
whismanoid 3:621191a7e3fd 133 // all other platforms
whismanoid 9:8d47cb713984 134 m_SPI_SCLK_Hz = 24000000; // platform limit 24MHz; MAX11131 limit is 48MHz
whismanoid 3:621191a7e3fd 135 #endif
whismanoid 1:77f1ee332e4a 136 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 1:77f1ee332e4a 137
whismanoid 6:cb7bdeb185d0 138 //
whismanoid 6:cb7bdeb185d0 139 // CNVST Trigger Input to MAX11131 device
whismanoid 6:cb7bdeb185d0 140 m_CNVST_pin = 1; // output logic high -- initial value in constructor
whismanoid 1:77f1ee332e4a 141 //
whismanoid 6:cb7bdeb185d0 142 // REF_plus Reference Input to MAX11131 device
whismanoid 6:cb7bdeb185d0 143 //
whismanoid 6:cb7bdeb185d0 144 // REF_minus_slash_AIN15 Reference Input to MAX11131 device
whismanoid 6:cb7bdeb185d0 145 //
whismanoid 6:cb7bdeb185d0 146 // EOC Event Output from device
whismanoid 1:77f1ee332e4a 147 }
whismanoid 1:77f1ee332e4a 148
whismanoid 1:77f1ee332e4a 149 MAX11131::~MAX11131()
whismanoid 1:77f1ee332e4a 150 {
whismanoid 1:77f1ee332e4a 151 // do nothing
whismanoid 1:77f1ee332e4a 152 }
whismanoid 1:77f1ee332e4a 153
whismanoid 6:cb7bdeb185d0 154 /// set SPI SCLK frequency
whismanoid 1:77f1ee332e4a 155 void MAX11131::spi_frequency(int spi_sclk_Hz)
whismanoid 1:77f1ee332e4a 156 {
whismanoid 1:77f1ee332e4a 157 m_SPI_SCLK_Hz = spi_sclk_Hz;
whismanoid 1:77f1ee332e4a 158 m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid 1:77f1ee332e4a 159 }
whismanoid 1:77f1ee332e4a 160
whismanoid 1:77f1ee332e4a 161 // Assert SPI Chip Select
whismanoid 1:77f1ee332e4a 162 // SPI chip-select for MAX11131
whismanoid 1:77f1ee332e4a 163 //
whismanoid 9:8d47cb713984 164 inline void MAX11131::SPIoutputCS(int isLogicHigh)
whismanoid 1:77f1ee332e4a 165 {
whismanoid 1:77f1ee332e4a 166 m_SPI_cs_state = isLogicHigh;
whismanoid 9:8d47cb713984 167 if (m_cs_pin.is_connected()) { // avoid mbed runtime error if pin is NC not connected
whismanoid 9:8d47cb713984 168 m_cs_pin = m_SPI_cs_state;
whismanoid 9:8d47cb713984 169 }
whismanoid 1:77f1ee332e4a 170 }
whismanoid 1:77f1ee332e4a 171
whismanoid 1:77f1ee332e4a 172 // SPI write 16 bits
whismanoid 1:77f1ee332e4a 173 // SPI interface to MAX11131 shift 16 bits mosiData16 into MAX11131 DIN
whismanoid 1:77f1ee332e4a 174 // ignoring MAX11131 DOUT
whismanoid 1:77f1ee332e4a 175 //
whismanoid 1:77f1ee332e4a 176 void MAX11131::SPIwrite16bits(int16_t mosiData16)
whismanoid 1:77f1ee332e4a 177 {
whismanoid 1:77f1ee332e4a 178 size_t byteCount = 2;
whismanoid 1:77f1ee332e4a 179 static char mosiData[2];
whismanoid 1:77f1ee332e4a 180 static char misoData[2];
whismanoid 1:77f1ee332e4a 181 mosiData[0] = (char)((mosiData16 >> 8) & 0xFF); // MSByte
whismanoid 1:77f1ee332e4a 182 mosiData[1] = (char)((mosiData16 >> 0) & 0xFF); // LSByte
whismanoid 1:77f1ee332e4a 183 //
whismanoid 1:77f1ee332e4a 184 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 1:77f1ee332e4a 185 //~ noInterrupts();
whismanoid 1:77f1ee332e4a 186 //
whismanoid 1:77f1ee332e4a 187 //~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid 1:77f1ee332e4a 188 //
whismanoid 1:77f1ee332e4a 189 unsigned int numBytesTransferred = m_spi.write(mosiData, byteCount, misoData, byteCount);
whismanoid 1:77f1ee332e4a 190 //~ m_spi.transfer(mosiData8_FF0000);
whismanoid 1:77f1ee332e4a 191 //~ m_spi.transfer(mosiData16_00FF00);
whismanoid 1:77f1ee332e4a 192 //~ m_spi.transfer(mosiData16_0000FF);
whismanoid 1:77f1ee332e4a 193 //
whismanoid 1:77f1ee332e4a 194 //~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid 1:77f1ee332e4a 195 //
whismanoid 1:77f1ee332e4a 196 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 1:77f1ee332e4a 197 //~ interrupts();
whismanoid 6:cb7bdeb185d0 198 // Optional Diagnostic function to print SPI transactions
whismanoid 6:cb7bdeb185d0 199 if (onSPIprint)
whismanoid 6:cb7bdeb185d0 200 {
whismanoid 6:cb7bdeb185d0 201 onSPIprint(byteCount, (uint8_t*)mosiData, (uint8_t*)misoData);
whismanoid 6:cb7bdeb185d0 202 }
whismanoid 1:77f1ee332e4a 203 //
whismanoid 1:77f1ee332e4a 204 // VERIFY: SPIwrite24bits print diagnostic information
whismanoid 1:77f1ee332e4a 205 //cmdLine.serial().printf(" MOSI->"));
whismanoid 1:77f1ee332e4a 206 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 207 //Serial.print( (mosiData8_FF0000 & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 208 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 209 //Serial.print( (mosiData16_00FF00 & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 210 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 211 //Serial.print( (mosiData16_0000FF & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 212 // hex dump mosiData[0..byteCount-1]
whismanoid 1:77f1ee332e4a 213 #if 0 // HAS_MICROUSBSERIAL
whismanoid 1:77f1ee332e4a 214 cmdLine_microUSBserial.serial().printf("\r\nSPI");
whismanoid 1:77f1ee332e4a 215 if (byteCount > 7) {
whismanoid 1:77f1ee332e4a 216 cmdLine_microUSBserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 1:77f1ee332e4a 217 }
whismanoid 1:77f1ee332e4a 218 cmdLine_microUSBserial.serial().printf(" MOSI->");
whismanoid 1:77f1ee332e4a 219 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 1:77f1ee332e4a 220 {
whismanoid 1:77f1ee332e4a 221 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 1:77f1ee332e4a 222 }
whismanoid 1:77f1ee332e4a 223 // hex dump misoData[0..byteCount-1]
whismanoid 9:8d47cb713984 224 cmdLine_microUSBserial.serial().printf(" MISO<-");
whismanoid 1:77f1ee332e4a 225 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 1:77f1ee332e4a 226 {
whismanoid 1:77f1ee332e4a 227 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 1:77f1ee332e4a 228 }
whismanoid 1:77f1ee332e4a 229 cmdLine_microUSBserial.serial().printf(" ");
whismanoid 1:77f1ee332e4a 230 #endif
whismanoid 1:77f1ee332e4a 231 #if 0 // HAS_DAPLINK_SERIAL
whismanoid 1:77f1ee332e4a 232 cmdLine_DAPLINKserial.serial().printf("\r\nSPI");
whismanoid 1:77f1ee332e4a 233 if (byteCount > 7) {
whismanoid 1:77f1ee332e4a 234 cmdLine_DAPLINKserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 1:77f1ee332e4a 235 }
whismanoid 1:77f1ee332e4a 236 cmdLine_DAPLINKserial.serial().printf(" MOSI->");
whismanoid 1:77f1ee332e4a 237 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 1:77f1ee332e4a 238 {
whismanoid 1:77f1ee332e4a 239 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 1:77f1ee332e4a 240 }
whismanoid 1:77f1ee332e4a 241 // hex dump misoData[0..byteCount-1]
whismanoid 9:8d47cb713984 242 cmdLine_DAPLINKserial.serial().printf(" MISO<-");
whismanoid 1:77f1ee332e4a 243 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 1:77f1ee332e4a 244 {
whismanoid 1:77f1ee332e4a 245 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 1:77f1ee332e4a 246 }
whismanoid 1:77f1ee332e4a 247 cmdLine_DAPLINKserial.serial().printf(" ");
whismanoid 1:77f1ee332e4a 248 #endif
whismanoid 1:77f1ee332e4a 249 // VERIFY: DIAGNOSTIC: print MAX5715 device register write
whismanoid 1:77f1ee332e4a 250 // TODO: MAX5715_print_register_verbose(mosiData8_FF0000, mosiData16_00FFFF);
whismanoid 1:77f1ee332e4a 251 // TODO: print_verbose_SPI_diagnostic(mosiData16_FF00, mosiData16_00FF, misoData16_FF00, misoData16_00FF);
whismanoid 1:77f1ee332e4a 252 //
whismanoid 1:77f1ee332e4a 253 // int misoData16 = (misoData16_FF00 << 8) | misoData16_00FF;
whismanoid 1:77f1ee332e4a 254 // return misoData16;
whismanoid 1:77f1ee332e4a 255 }
whismanoid 1:77f1ee332e4a 256
whismanoid 1:77f1ee332e4a 257 // SPI write 17-24 bits
whismanoid 1:77f1ee332e4a 258 // SPI interface to MAX11131 shift 16 bits mosiData16 into MAX11131 DIN
whismanoid 1:77f1ee332e4a 259 // followed by one additional SCLK byte.
whismanoid 1:77f1ee332e4a 260 // ignoring MAX11131 DOUT
whismanoid 1:77f1ee332e4a 261 //
whismanoid 1:77f1ee332e4a 262 void MAX11131::SPIwrite24bits(int16_t mosiData16_FFFF00, int8_t mosiData8_0000FF)
whismanoid 1:77f1ee332e4a 263 {
whismanoid 1:77f1ee332e4a 264 // TODO: implement SPIwrite24bits(int16_t mosiData16_FFFF00, int8_t mosiData8_0000FF)
whismanoid 1:77f1ee332e4a 265 size_t byteCount = 3;
whismanoid 1:77f1ee332e4a 266 static char mosiData[3];
whismanoid 1:77f1ee332e4a 267 static char misoData[3];
whismanoid 1:77f1ee332e4a 268 mosiData[0] = (char)((mosiData16_FFFF00 >> 8) & 0xFF); // MSByte
whismanoid 1:77f1ee332e4a 269 mosiData[1] = (char)((mosiData16_FFFF00 >> 0) & 0xFF); // LSByte
whismanoid 1:77f1ee332e4a 270 mosiData[2] = mosiData8_0000FF;
whismanoid 1:77f1ee332e4a 271 //
whismanoid 1:77f1ee332e4a 272 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 1:77f1ee332e4a 273 //~ noInterrupts();
whismanoid 1:77f1ee332e4a 274 //
whismanoid 1:77f1ee332e4a 275 //~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid 1:77f1ee332e4a 276 //
whismanoid 1:77f1ee332e4a 277 unsigned int numBytesTransferred = m_spi.write(mosiData, byteCount, misoData, byteCount);
whismanoid 1:77f1ee332e4a 278 //~ m_spi.transfer(mosiData8_FF0000);
whismanoid 1:77f1ee332e4a 279 //~ m_spi.transfer(mosiData16_00FF00);
whismanoid 1:77f1ee332e4a 280 //~ m_spi.transfer(mosiData16_0000FF);
whismanoid 1:77f1ee332e4a 281 //
whismanoid 1:77f1ee332e4a 282 //~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid 1:77f1ee332e4a 283 //
whismanoid 1:77f1ee332e4a 284 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 1:77f1ee332e4a 285 //~ interrupts();
whismanoid 6:cb7bdeb185d0 286 // Optional Diagnostic function to print SPI transactions
whismanoid 6:cb7bdeb185d0 287 if (onSPIprint)
whismanoid 6:cb7bdeb185d0 288 {
whismanoid 6:cb7bdeb185d0 289 onSPIprint(byteCount, (uint8_t*)mosiData, (uint8_t*)misoData);
whismanoid 6:cb7bdeb185d0 290 }
whismanoid 1:77f1ee332e4a 291 //
whismanoid 1:77f1ee332e4a 292 // VERIFY: SPIwrite24bits print diagnostic information
whismanoid 1:77f1ee332e4a 293 //cmdLine.serial().printf(" MOSI->"));
whismanoid 1:77f1ee332e4a 294 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 295 //Serial.print( (mosiData8_FF0000 & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 296 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 297 //Serial.print( (mosiData16_00FF00 & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 298 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 299 //Serial.print( (mosiData16_0000FF & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 300 // hex dump mosiData[0..byteCount-1]
whismanoid 1:77f1ee332e4a 301 #if 0 // HAS_MICROUSBSERIAL
whismanoid 1:77f1ee332e4a 302 cmdLine_microUSBserial.serial().printf("\r\nSPI");
whismanoid 1:77f1ee332e4a 303 if (byteCount > 7) {
whismanoid 1:77f1ee332e4a 304 cmdLine_microUSBserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 1:77f1ee332e4a 305 }
whismanoid 1:77f1ee332e4a 306 cmdLine_microUSBserial.serial().printf(" MOSI->");
whismanoid 1:77f1ee332e4a 307 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 1:77f1ee332e4a 308 {
whismanoid 1:77f1ee332e4a 309 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 1:77f1ee332e4a 310 }
whismanoid 1:77f1ee332e4a 311 // hex dump misoData[0..byteCount-1]
whismanoid 9:8d47cb713984 312 cmdLine_microUSBserial.serial().printf(" MISO<-");
whismanoid 1:77f1ee332e4a 313 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 1:77f1ee332e4a 314 {
whismanoid 1:77f1ee332e4a 315 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 1:77f1ee332e4a 316 }
whismanoid 1:77f1ee332e4a 317 cmdLine_microUSBserial.serial().printf(" ");
whismanoid 1:77f1ee332e4a 318 #endif
whismanoid 1:77f1ee332e4a 319 #if 0 // HAS_DAPLINK_SERIAL
whismanoid 1:77f1ee332e4a 320 cmdLine_DAPLINKserial.serial().printf("\r\nSPI");
whismanoid 1:77f1ee332e4a 321 if (byteCount > 7) {
whismanoid 1:77f1ee332e4a 322 cmdLine_DAPLINKserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 1:77f1ee332e4a 323 }
whismanoid 1:77f1ee332e4a 324 cmdLine_DAPLINKserial.serial().printf(" MOSI->");
whismanoid 1:77f1ee332e4a 325 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 1:77f1ee332e4a 326 {
whismanoid 1:77f1ee332e4a 327 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 1:77f1ee332e4a 328 }
whismanoid 1:77f1ee332e4a 329 // hex dump misoData[0..byteCount-1]
whismanoid 9:8d47cb713984 330 cmdLine_DAPLINKserial.serial().printf(" MISO<-");
whismanoid 1:77f1ee332e4a 331 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 1:77f1ee332e4a 332 {
whismanoid 1:77f1ee332e4a 333 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 1:77f1ee332e4a 334 }
whismanoid 1:77f1ee332e4a 335 cmdLine_DAPLINKserial.serial().printf(" ");
whismanoid 1:77f1ee332e4a 336 #endif
whismanoid 1:77f1ee332e4a 337 // VERIFY: DIAGNOSTIC: print MAX5715 device register write
whismanoid 1:77f1ee332e4a 338 // TODO: MAX5715_print_register_verbose(mosiData8_FF0000, mosiData16_00FFFF);
whismanoid 1:77f1ee332e4a 339 //
whismanoid 1:77f1ee332e4a 340 // int misoData16 = (misoData16_FF00 << 8) | misoData16_00FF;
whismanoid 1:77f1ee332e4a 341 // return misoData16;
whismanoid 1:77f1ee332e4a 342 }
whismanoid 1:77f1ee332e4a 343
whismanoid 1:77f1ee332e4a 344 // SPI read 16 bits while MOSI (MAX11131 DIN) is 0
whismanoid 1:77f1ee332e4a 345 // SPI interface to capture 16 bits miso data from MAX11131 DOUT
whismanoid 1:77f1ee332e4a 346 //
whismanoid 1:77f1ee332e4a 347 int16_t MAX11131::SPIread16bits()
whismanoid 1:77f1ee332e4a 348 {
whismanoid 1:77f1ee332e4a 349 int mosiData16 = 0;
whismanoid 1:77f1ee332e4a 350 size_t byteCount = 2;
whismanoid 1:77f1ee332e4a 351 static char mosiData[2];
whismanoid 1:77f1ee332e4a 352 static char misoData[2];
whismanoid 1:77f1ee332e4a 353 mosiData[0] = (char)((mosiData16 >> 8) & 0xFF); // MSByte
whismanoid 1:77f1ee332e4a 354 mosiData[1] = (char)((mosiData16 >> 0) & 0xFF); // LSByte
whismanoid 1:77f1ee332e4a 355 //
whismanoid 1:77f1ee332e4a 356 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 1:77f1ee332e4a 357 //~ noInterrupts();
whismanoid 1:77f1ee332e4a 358 //
whismanoid 1:77f1ee332e4a 359 //~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid 1:77f1ee332e4a 360 //
whismanoid 1:77f1ee332e4a 361 unsigned int numBytesTransferred = m_spi.write(mosiData, byteCount, misoData, byteCount);
whismanoid 1:77f1ee332e4a 362 //~ m_spi.transfer(mosiData8_FF0000);
whismanoid 1:77f1ee332e4a 363 //~ m_spi.transfer(mosiData16_00FF00);
whismanoid 1:77f1ee332e4a 364 //~ m_spi.transfer(mosiData16_0000FF);
whismanoid 1:77f1ee332e4a 365 //
whismanoid 1:77f1ee332e4a 366 //~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid 1:77f1ee332e4a 367 //
whismanoid 1:77f1ee332e4a 368 // Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid 1:77f1ee332e4a 369 //~ interrupts();
whismanoid 6:cb7bdeb185d0 370 // Optional Diagnostic function to print SPI transactions
whismanoid 6:cb7bdeb185d0 371 if (onSPIprint)
whismanoid 6:cb7bdeb185d0 372 {
whismanoid 6:cb7bdeb185d0 373 onSPIprint(byteCount, (uint8_t*)mosiData, (uint8_t*)misoData);
whismanoid 6:cb7bdeb185d0 374 }
whismanoid 1:77f1ee332e4a 375 //
whismanoid 1:77f1ee332e4a 376 // VERIFY: SPIwrite24bits print diagnostic information
whismanoid 1:77f1ee332e4a 377 //cmdLine.serial().printf(" MOSI->"));
whismanoid 1:77f1ee332e4a 378 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 379 //Serial.print( (mosiData8_FF0000 & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 380 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 381 //Serial.print( (mosiData16_00FF00 & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 382 //cmdLine.serial().printf(" 0x"));
whismanoid 1:77f1ee332e4a 383 //Serial.print( (mosiData16_0000FF & 0xFF), HEX);
whismanoid 1:77f1ee332e4a 384 // hex dump mosiData[0..byteCount-1]
whismanoid 1:77f1ee332e4a 385 #if 0 // HAS_MICROUSBSERIAL
whismanoid 1:77f1ee332e4a 386 cmdLine_microUSBserial.serial().printf("\r\nSPI");
whismanoid 1:77f1ee332e4a 387 if (byteCount > 7) {
whismanoid 1:77f1ee332e4a 388 cmdLine_microUSBserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 1:77f1ee332e4a 389 }
whismanoid 1:77f1ee332e4a 390 cmdLine_microUSBserial.serial().printf(" MOSI->");
whismanoid 1:77f1ee332e4a 391 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 1:77f1ee332e4a 392 {
whismanoid 1:77f1ee332e4a 393 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 1:77f1ee332e4a 394 }
whismanoid 1:77f1ee332e4a 395 // hex dump misoData[0..byteCount-1]
whismanoid 9:8d47cb713984 396 cmdLine_microUSBserial.serial().printf(" MISO<-");
whismanoid 1:77f1ee332e4a 397 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 1:77f1ee332e4a 398 {
whismanoid 1:77f1ee332e4a 399 cmdLine_microUSBserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 1:77f1ee332e4a 400 }
whismanoid 1:77f1ee332e4a 401 cmdLine_microUSBserial.serial().printf(" ");
whismanoid 1:77f1ee332e4a 402 #endif
whismanoid 1:77f1ee332e4a 403 #if 0 // HAS_DAPLINK_SERIAL
whismanoid 1:77f1ee332e4a 404 cmdLine_DAPLINKserial.serial().printf("\r\nSPI");
whismanoid 1:77f1ee332e4a 405 if (byteCount > 7) {
whismanoid 1:77f1ee332e4a 406 cmdLine_DAPLINKserial.serial().printf(" byteCount:%d", byteCount);
whismanoid 1:77f1ee332e4a 407 }
whismanoid 1:77f1ee332e4a 408 cmdLine_DAPLINKserial.serial().printf(" MOSI->");
whismanoid 1:77f1ee332e4a 409 for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid 1:77f1ee332e4a 410 {
whismanoid 1:77f1ee332e4a 411 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid 1:77f1ee332e4a 412 }
whismanoid 1:77f1ee332e4a 413 // hex dump misoData[0..byteCount-1]
whismanoid 9:8d47cb713984 414 cmdLine_DAPLINKserial.serial().printf(" MISO<-");
whismanoid 1:77f1ee332e4a 415 for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid 1:77f1ee332e4a 416 {
whismanoid 1:77f1ee332e4a 417 cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid 1:77f1ee332e4a 418 }
whismanoid 1:77f1ee332e4a 419 cmdLine_DAPLINKserial.serial().printf(" ");
whismanoid 1:77f1ee332e4a 420 #endif
whismanoid 1:77f1ee332e4a 421 // VERIFY: DIAGNOSTIC: print MAX5715 device register write
whismanoid 1:77f1ee332e4a 422 // TODO: MAX5715_print_register_verbose(mosiData8_FF0000, mosiData16_00FFFF);
whismanoid 1:77f1ee332e4a 423 // TODO: print_verbose_SPI_diagnostic(mosiData16_FF00, mosiData16_00FF, misoData16_FF00, misoData16_00FF);
whismanoid 1:77f1ee332e4a 424 //
whismanoid 1:77f1ee332e4a 425 int misoData16 = (misoData[0] << 8) | misoData[1];
whismanoid 1:77f1ee332e4a 426 return misoData16;
whismanoid 1:77f1ee332e4a 427 }
whismanoid 1:77f1ee332e4a 428
whismanoid 1:77f1ee332e4a 429 // Assert MAX11131 CNVST convert start.
whismanoid 1:77f1ee332e4a 430 // Required when using any of the InternalClock modes with SWCNV 0.
whismanoid 1:77f1ee332e4a 431 // Trigger measurement by driving CNVST/AIN14 pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 432 //
whismanoid 1:77f1ee332e4a 433 void MAX11131::CNVSToutputPulseLow()
whismanoid 1:77f1ee332e4a 434 {
whismanoid 1:77f1ee332e4a 435 // m_CNVST_pin.output(); // only applicable to DigitalInOut
whismanoid 1:77f1ee332e4a 436 m_CNVST_pin = 0; // output logic low
whismanoid 1:77f1ee332e4a 437 wait(0.01); // pulse low delay time
whismanoid 1:77f1ee332e4a 438 m_CNVST_pin = 1; // output logic high
whismanoid 1:77f1ee332e4a 439 }
whismanoid 1:77f1ee332e4a 440
whismanoid 1:77f1ee332e4a 441 // Wait for MAX11131 EOC pin low, indicating end of conversion.
whismanoid 1:77f1ee332e4a 442 // Required when using any of the InternalClock modes.
whismanoid 1:77f1ee332e4a 443 //
whismanoid 1:77f1ee332e4a 444 void MAX11131::EOCinputWaitUntilLow()
whismanoid 1:77f1ee332e4a 445 {
whismanoid 1:77f1ee332e4a 446 // m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid 1:77f1ee332e4a 447 while (m_EOC_pin != 0)
whismanoid 1:77f1ee332e4a 448 {
whismanoid 1:77f1ee332e4a 449 // spinlock waiting for logic low pin state
whismanoid 1:77f1ee332e4a 450 }
whismanoid 1:77f1ee332e4a 451 }
whismanoid 1:77f1ee332e4a 452
whismanoid 1:77f1ee332e4a 453 // Return the status of the MAX11131 EOC pin.
whismanoid 1:77f1ee332e4a 454 //
whismanoid 1:77f1ee332e4a 455 int MAX11131::EOCinputValue()
whismanoid 1:77f1ee332e4a 456 {
whismanoid 1:77f1ee332e4a 457 // m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid 1:77f1ee332e4a 458 return m_EOC_pin.read();
whismanoid 1:77f1ee332e4a 459 }
whismanoid 1:77f1ee332e4a 460
whismanoid 1:77f1ee332e4a 461 //----------------------------------------
whismanoid 6:cb7bdeb185d0 462 // Menu item '!'
whismanoid 1:77f1ee332e4a 463 // Initialize device
whismanoid 9:8d47cb713984 464 //
whismanoid 9:8d47cb713984 465 // TODO1: #170 MAX11131 Self Test for Test Fixture Firmware
whismanoid 9:8d47cb713984 466 // @future test group ____ // Verify function ____ (enabled by default)
whismanoid 9:8d47cb713984 467 //
whismanoid 9:8d47cb713984 468 // @future test group DACCodeOfVoltage // Verify function DACCodeOfVoltage (enabled by default)
whismanoid 9:8d47cb713984 469 // @future test group DACCodeOfVoltage tinyTester.blink_time_msec = 20 // quickly speed through the software verification
whismanoid 9:8d47cb713984 470 // @future test group DACCodeOfVoltage tinyTester.print("VRef = 2.500 MAX5171 14-bit LSB = 0.00015V")
whismanoid 9:8d47cb713984 471 // @future test group DACCodeOfVoltage VRef = 2.500
whismanoid 9:8d47cb713984 472 // @future test group DACCodeOfVoltage tinyTester.err_threshold = 0.00015259720441921504 // 14-bit LSB (2.500/16383)
whismanoid 9:8d47cb713984 473 // //
whismanoid 9:8d47cb713984 474 // @future test group DACCodeOfVoltage DACCodeOfVoltage(2.499847412109375) expect 0x3FFF
whismanoid 9:8d47cb713984 475 // //
whismanoid 9:8d47cb713984 476 // //
whismanoid 9:8d47cb713984 477 // @future test group CODE_LOAD // Verify function CODE_LOAD (enabled by default)
whismanoid 9:8d47cb713984 478 // @future test group CODE_LOAD tinyTester.blink_time_msec = 75 // default 75 resume hardware self test
whismanoid 9:8d47cb713984 479 // @future test group CODE_LOAD tinyTester.settle_time_msec = 250
whismanoid 9:8d47cb713984 480 // @future test Init()
whismanoid 9:8d47cb713984 481 // @future test VRef expect 2.500 // Nominal Full-Scale Voltage Reference
whismanoid 9:8d47cb713984 482 // //
whismanoid 9:8d47cb713984 483 // tinyTester.err_threshold = 0.030; // 30mV
whismanoid 9:8d47cb713984 484 // @future test group CODE_LOAD tinyTester.err_threshold = 0.030
whismanoid 9:8d47cb713984 485 // @future test group CODE_LOAD tinyTester.DigitalIn_Read_Expect_WarnOnly(UPO_pin, "UPO", 1, "UPO_pin is high after MAX5171 UPO_HIGH command")
whismanoid 9:8d47cb713984 486 // @future test group CODE_LOAD tinyTester.AnalogIn0_Read_Expect_voltageV(1.2500)
whismanoid 9:8d47cb713984 487 //
whismanoid 9:8d47cb713984 488 //
whismanoid 9:8d47cb713984 489 //
whismanoid 9:8d47cb713984 490 // TODO1: #170 MAX11131 Self Test for Test Fixture Firmware
whismanoid 9:8d47cb713984 491 // @future test group ____ // Verify function ____ (enabled by default)
whismanoid 9:8d47cb713984 492 // // MAX11131BOB self-test functions
whismanoid 9:8d47cb713984 493 // //~ SelfTest_FAIL(cmdLine);
whismanoid 9:8d47cb713984 494 // //~ cmdLine.serial().printf("test program not implemented yet");
whismanoid 9:8d47cb713984 495 // int16_t value_u12;
whismanoid 9:8d47cb713984 496 // int channelId;
whismanoid 9:8d47cb713984 497 // double voltageV = 0.5;
whismanoid 9:8d47cb713984 498 // //
whismanoid 9:8d47cb713984 499 // //cmdLine.serial().printf("
whismanoid 9:8d47cb713984 500 // 0.0: MAX11131.Init()");
whismanoid 9:8d47cb713984 501 // //Init();
whismanoid 9:8d47cb713984 502 // //
whismanoid 9:8d47cb713984 503 // // Device Testing: ADC commands, verify with on-board ADC and SPI framing
whismanoid 9:8d47cb713984 504 // //
whismanoid 9:8d47cb713984 505 // @test tinyTester.blink_time_msec = 75 // default 75 resume hardware self test
whismanoid 9:8d47cb713984 506 // tinyTester.blink_time_msec = 75;
whismanoid 9:8d47cb713984 507 // // MAX11131 SelfTest: MAX11131 SPI connections (Power Supply and GND, SCLK, MOSI, MISO, CS)
whismanoid 9:8d47cb713984 508 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 509 // ");
whismanoid 9:8d47cb713984 510 // cmdLine.serial().printf(
whismanoid 9:8d47cb713984 511 // "
whismanoid 9:8d47cb713984 512 // 1.0: Test Scan_0100_StandardExt -- verify SPI (VDD, GND, SCLK, MOSI, MISO, CS)");
whismanoid 9:8d47cb713984 513 // @test tinyTester.print("1.0: Test Scan_0100_StandardExt -- verify SPI (VDD, GND, SCLK, MOSI, MISO, CS)")
whismanoid 9:8d47cb713984 514 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 515 // MAX11131.Init()");
whismanoid 9:8d47cb713984 516 // Init();
whismanoid 9:8d47cb713984 517 // @future test Init()
whismanoid 9:8d47cb713984 518 // @future test VRef expect 2.500 // Nominal Full-Scale Voltage Reference
whismanoid 9:8d47cb713984 519 // // Send MOSI data Expect MISO data Description
whismanoid 9:8d47cb713984 520 // // 1000_0000_0000_0000 xxxx_xxxx_xxxx_xxxx ADC_CONFIGURATION REFSEL=0 SPM[1:0]=0 ECHO=0
whismanoid 9:8d47cb713984 521 // // 0010_0111_1010_0100 xxxx_xxxx_xxxx_xxxx ADC_MODE_CONTROL Scan_0100_StandardExt CHSEL=15 RESET=1 CHANID=1
whismanoid 9:8d47cb713984 522 // // 0000_0000_0000_0000 0000_xxxx_xxxx_xxxx Channel ID tag = AIN0 expect high nybble 0
whismanoid 9:8d47cb713984 523 // // 0000_0000_0000_0000 0001_xxxx_xxxx_xxxx Channel ID tag = AIN1 expect high nybble 1
whismanoid 9:8d47cb713984 524 // // 0000_0000_0000_0000 0010_xxxx_xxxx_xxxx Channel ID tag = AIN2 expect high nybble 2
whismanoid 9:8d47cb713984 525 // // 0000_0000_0000_0000 0011_xxxx_xxxx_xxxx Channel ID tag = AIN3 expect high nybble 3
whismanoid 9:8d47cb713984 526 // //
whismanoid 9:8d47cb713984 527 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 528 // MOSI <-- 1000_0000_0000_0000 ADC_CONFIGURATION REFSEL=0 SPM[1:0]=0 ECHO=0");
whismanoid 9:8d47cb713984 529 // SPIoutputCS(0); // drive CS low
whismanoid 9:8d47cb713984 530 // SPIwrite16bits(0x8000);
whismanoid 9:8d47cb713984 531 // SPIoutputCS(1); // drive CS high
whismanoid 9:8d47cb713984 532 // @test SPIoutputCS(0)
whismanoid 9:8d47cb713984 533 // @test SPIwrite16bits(0x8000)
whismanoid 9:8d47cb713984 534 // @test SPIoutputCS(1)
whismanoid 9:8d47cb713984 535 // //
whismanoid 9:8d47cb713984 536 // cmdLine.serial().printf(
whismanoid 9:8d47cb713984 537 // "
whismanoid 9:8d47cb713984 538 // MOSI <-- 0010_0111_1010_0100 ADC_MODE_CONTROL Scan_0100_StandardExt CHSEL=15 RESET=1 CHANID=1");
whismanoid 9:8d47cb713984 539 // SPIoutputCS(0); // drive CS low
whismanoid 9:8d47cb713984 540 // SPIwrite16bits(0x27a4);
whismanoid 9:8d47cb713984 541 // SPIoutputCS(1); // drive CS high
whismanoid 9:8d47cb713984 542 // @future test SPIoutputCS(0)
whismanoid 9:8d47cb713984 543 // @future test SPIwrite16bits(0x27a4)
whismanoid 9:8d47cb713984 544 // @future test SPIoutputCS(1)
whismanoid 9:8d47cb713984 545 // //
whismanoid 9:8d47cb713984 546 // for (int channelIndex = 0; channelIndex < 16; channelIndex++) {
whismanoid 9:8d47cb713984 547 // //~ cmdLine.serial().printf("
whismanoid 9:8d47cb713984 548 // MISO --> expect 0000_xxxx_xxxx_xxxx");
whismanoid 9:8d47cb713984 549 // SPIoutputCS(0); // drive CS low
whismanoid 9:8d47cb713984 550 // RAW_misoData16[channelIndex] = SPIread16bits();
whismanoid 9:8d47cb713984 551 // SPIoutputCS(1); // drive CS high
whismanoid 9:8d47cb713984 552 // int expect_channelId = channelIndex;
whismanoid 9:8d47cb713984 553 // int actual_channelId = (RAW_misoData16[channelIndex] >> 12) & 0x000F;
whismanoid 9:8d47cb713984 554 // if (actual_channelId != expect_channelId)
whismanoid 9:8d47cb713984 555 // {
whismanoid 9:8d47cb713984 556 // tinyTester.FAIL();
whismanoid 9:8d47cb713984 557 // cmdLine.serial().printf("MISO --> 0x%4.4x", (RAW_misoData16[channelIndex] & 0xFFFF));
whismanoid 9:8d47cb713984 558 // cmdLine.serial().printf(" expect 0x%1.1xxxx (channel ID %d)", expect_channelId, expect_channelId);
whismanoid 9:8d47cb713984 559 // cmdLine.serial().printf(" but got 0x%1.1xxxx", actual_channelId);
whismanoid 9:8d47cb713984 560 // }
whismanoid 9:8d47cb713984 561 // else
whismanoid 9:8d47cb713984 562 // {
whismanoid 9:8d47cb713984 563 // tinyTester.PASS();
whismanoid 9:8d47cb713984 564 // cmdLine.serial().printf("MISO --> 0x%4.4x", (RAW_misoData16[channelIndex] & 0xFFFF));
whismanoid 9:8d47cb713984 565 // cmdLine.serial().printf(" expect 0x%1.1xxxx (channel ID %d)", expect_channelId, expect_channelId);
whismanoid 9:8d47cb713984 566 // }
whismanoid 9:8d47cb713984 567 // }
whismanoid 9:8d47cb713984 568 // //
whismanoid 9:8d47cb713984 569 // // MAX11131 SelfTest: MAX11131 Supports Internal Clock Modes (CNVST, EOC)
whismanoid 9:8d47cb713984 570 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 571 // ");
whismanoid 9:8d47cb713984 572 // cmdLine.serial().printf(
whismanoid 9:8d47cb713984 573 // "
whismanoid 9:8d47cb713984 574 // 1.1: Test Scan_0011_StandardInt -- verify Internal Clock signals (CNVST, EOC)");
whismanoid 9:8d47cb713984 575 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 576 // MAX11131.Init()");
whismanoid 9:8d47cb713984 577 // Init();
whismanoid 9:8d47cb713984 578 // SPIoutputCS(0); // drive CS low
whismanoid 9:8d47cb713984 579 // RAW_misoData16[0] = SPIread16bits();
whismanoid 9:8d47cb713984 580 // SPIoutputCS(1); // drive CS high
whismanoid 9:8d47cb713984 581 // //
whismanoid 9:8d47cb713984 582 // // tinyTester.DigitalIn_Read_Expect_WarnOnly replaces SelfTest_MAX11131_EOC_expect
whismanoid 9:8d47cb713984 583 // tinyTester.DigitalIn_Read_Expect_WarnOnly(EOCb_pin, "EOC", 1, "initial value before sending commands");
whismanoid 9:8d47cb713984 584 // //
whismanoid 9:8d47cb713984 585 // // Send MOSI data Expect MISO data Description
whismanoid 9:8d47cb713984 586 // // 1000_0000_0000_0000 xxxx_xxxx_xxxx_xxxx ADC_CONFIGURATION REFSEL=0 SPM[1:0]=0 ECHO=0 No Averaging
whismanoid 9:8d47cb713984 587 // // 0001_1001_1010_0000 xxxx_xxxx_xxxx_xxxx ADC_MODE_CONTROL Scan_0011_StandardInt CHSEL=3 RESET=1 SWCNV=0
whismanoid 9:8d47cb713984 588 // // 0000_0000_0000_0000 0000_xxxx_xxxx_xxxx Channel ID tag = AIN0 expect high nybble 0
whismanoid 9:8d47cb713984 589 // // 0000_0000_0000_0000 0001_xxxx_xxxx_xxxx Channel ID tag = AIN1 expect high nybble 1
whismanoid 9:8d47cb713984 590 // // 0000_0000_0000_0000 0010_xxxx_xxxx_xxxx Channel ID tag = AIN2 expect high nybble 2
whismanoid 9:8d47cb713984 591 // // 0000_0000_0000_0000 0011_xxxx_xxxx_xxxx Channel ID tag = AIN3 expect high nybble 3
whismanoid 9:8d47cb713984 592 // //
whismanoid 9:8d47cb713984 593 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 594 // MOSI <-- 1000_0000_0000_0000 ADC_CONFIGURATION REFSEL=0 SPM[1:0]=0 ECHO=0");
whismanoid 9:8d47cb713984 595 // SPIoutputCS(0); // drive CS low
whismanoid 9:8d47cb713984 596 // SPIwrite16bits(0x8000);
whismanoid 9:8d47cb713984 597 // SPIoutputCS(1); // drive CS high
whismanoid 9:8d47cb713984 598 // //
whismanoid 9:8d47cb713984 599 // cmdLine.serial().printf(
whismanoid 9:8d47cb713984 600 // "
whismanoid 9:8d47cb713984 601 // MOSI <-- 0001_1001_1010_0000 ADC_MODE_CONTROL Scan_0011_StandardInt CHSEL=3 RESET=1 SWCNV=0");
whismanoid 9:8d47cb713984 602 // SPIoutputCS(0); // drive CS low
whismanoid 9:8d47cb713984 603 // SPIwrite16bits(0x19a0);
whismanoid 9:8d47cb713984 604 // SPIoutputCS(1); // drive CS high
whismanoid 9:8d47cb713984 605 // //
whismanoid 9:8d47cb713984 606 // for (int channelIndex = 0; channelIndex < 4; channelIndex++) {
whismanoid 9:8d47cb713984 607 // //~ cmdLine.serial().printf("
whismanoid 9:8d47cb713984 608 // MISO --> expect 0000_xxxx_xxxx_xxxx");
whismanoid 9:8d47cb713984 609 // //~ wait_ms(200); // delay
whismanoid 9:8d47cb713984 610 // CNVSToutputPulseLow();
whismanoid 9:8d47cb713984 611 // //~ CNVSToutputValue(0);
whismanoid 9:8d47cb713984 612 // //~ wait_ms(100); // delay
whismanoid 9:8d47cb713984 613 // //~ CNVSToutputValue(1);
whismanoid 9:8d47cb713984 614 // // EOCinputWaitUntilLow(); // infinite wait hazard, need to fail if timeout exceeded
whismanoid 9:8d47cb713984 615 // // tinyTester.DigitalIn_Read_Expect_WarnOnly replaces SelfTest_MAX11131_EOC_expect
whismanoid 9:8d47cb713984 616 // tinyTester.DigitalIn_Read_Expect_WarnOnly(EOCb_pin, "EOC", 0, "after CNVST pulse");
whismanoid 9:8d47cb713984 617 // SPIoutputCS(0); // drive CS low
whismanoid 9:8d47cb713984 618 // RAW_misoData16[channelIndex] = SPIread16bits();
whismanoid 9:8d47cb713984 619 // SPIoutputCS(1); // drive CS high
whismanoid 9:8d47cb713984 620 // // tinyTester.DigitalIn_Read_Expect_WarnOnly replaces SelfTest_MAX11131_EOC_expect
whismanoid 9:8d47cb713984 621 // tinyTester.DigitalIn_Read_Expect_WarnOnly(EOCb_pin, "EOC", 1, "after SPI read");
whismanoid 9:8d47cb713984 622 // int expect_channelId = channelIndex;
whismanoid 9:8d47cb713984 623 // int actual_channelId = (RAW_misoData16[channelIndex] >> 12) & 0x000F;
whismanoid 9:8d47cb713984 624 // if (actual_channelId != expect_channelId)
whismanoid 9:8d47cb713984 625 // {
whismanoid 9:8d47cb713984 626 // tinyTester.FAIL();
whismanoid 9:8d47cb713984 627 // cmdLine.serial().printf("MISO --> 0x%4.4x", (RAW_misoData16[channelIndex] & 0xFFFF));
whismanoid 9:8d47cb713984 628 // cmdLine.serial().printf(" expect 0x%1.1xxxx (channel ID %d)", expect_channelId, expect_channelId);
whismanoid 9:8d47cb713984 629 // cmdLine.serial().printf(" but got 0x%1.1xxxx", actual_channelId);
whismanoid 9:8d47cb713984 630 // }
whismanoid 9:8d47cb713984 631 // else
whismanoid 9:8d47cb713984 632 // {
whismanoid 9:8d47cb713984 633 // tinyTester.PASS();
whismanoid 9:8d47cb713984 634 // cmdLine.serial().printf("MISO --> 0x%4.4x", (RAW_misoData16[channelIndex] & 0xFFFF));
whismanoid 9:8d47cb713984 635 // cmdLine.serial().printf(" expect 0x%1.1xxxx (channel ID %d)", expect_channelId, expect_channelId);
whismanoid 9:8d47cb713984 636 // }
whismanoid 9:8d47cb713984 637 // }
whismanoid 9:8d47cb713984 638 // //
whismanoid 9:8d47cb713984 639 // // MAX11131 SelfTest: Test Fixture: MAX541ACPA+ to MAX32625MBED.AIN0/AIN4
whismanoid 9:8d47cb713984 640 // // Test Fixture: MAX541 connected to spi2
whismanoid 9:8d47cb713984 641 // // SPI spi2_max541(SPI2_MOSI, SPI2_MISO, SPI2_SCK); // mosi, miso, sclk spi2 TARGET_MAX32635MBED: P2_5 P2_6 P2_4 Arduino 2x3-pin header; microSD
whismanoid 9:8d47cb713984 642 // // DigitalOut spi2_max541_cs(SPI2_SS); // TARGET_MAX32635MBED: P2_7 Arduino 2x3-pin header
whismanoid 9:8d47cb713984 643 // // Test Fixture: MAX541 spi2 init
whismanoid 9:8d47cb713984 644 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 645 // ");
whismanoid 9:8d47cb713984 646 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 647 // 2.0: Test Fixture: MAX541 connected to spi2 (P2.4 P2.5 P2.7)?");
whismanoid 9:8d47cb713984 648 // bool SelfTest_has_max541 = false;
whismanoid 9:8d47cb713984 649 // // Check actual MAX541 reference voltage
whismanoid 9:8d47cb713984 650 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 651 // Test Fixture: MAX541 midscale voltage measure with MAX32625MBED AIN0/4");
whismanoid 9:8d47cb713984 652 // max541.Set_Code(0x8000); // we don't know the fullscale voltage yet, so set code to midscale
whismanoid 9:8d47cb713984 653 // tinyTester.Wait_Output_Settling(); // wait for MAX541 to settle
whismanoid 9:8d47cb713984 654 // //
whismanoid 9:8d47cb713984 655 // double max541_midscale_V = analogInPin_fullScaleVoltage[4] * analogIn4.read(); // TARGET_MAX32630 J1.5 AIN_4 = AIN0 / 5.0 fullscale is 6.0V
whismanoid 9:8d47cb713984 656 // const int average_count = 100;
whismanoid 9:8d47cb713984 657 // const double average_K = 0.25;
whismanoid 9:8d47cb713984 658 // for (int count = 0; count < average_count; count++) {
whismanoid 9:8d47cb713984 659 // double measurement_V = analogInPin_fullScaleVoltage[4] * analogIn4.read(); // TARGET_MAX32630 J1.5 AIN_4 = AIN0 / 5.0 fullscale is 6.0V
whismanoid 9:8d47cb713984 660 // max541_midscale_V = ((1 - average_K) * max541_midscale_V) + (average_K * measurement_V);
whismanoid 9:8d47cb713984 661 // }
whismanoid 9:8d47cb713984 662 // if (max541_midscale_V > 1.0f) {
whismanoid 9:8d47cb713984 663 // max541.VRef = 2.0 * max541_midscale_V;
whismanoid 9:8d47cb713984 664 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 665 // Test Fixture: MAX541 midscale = %1.3fV, so fullscale = %1.3fV",
whismanoid 9:8d47cb713984 666 // max541_midscale_V, max541.VRef);
whismanoid 9:8d47cb713984 667 // // Detect whether MAX541 is really connected to MAX32625MBED.AIN0/AIN4
whismanoid 9:8d47cb713984 668 // voltageV = 1.0f;
whismanoid 9:8d47cb713984 669 // SelfTest_has_max541 = SelfTest_MAX541_Voltage(cmdLine, max541, voltageV);
whismanoid 9:8d47cb713984 670 // }
whismanoid 9:8d47cb713984 671 // if (SelfTest_has_max541) {
whismanoid 9:8d47cb713984 672 // voltageV = 0.0f;
whismanoid 9:8d47cb713984 673 // SelfTest_has_max541 = SelfTest_MAX541_Voltage(cmdLine, max541, voltageV);
whismanoid 9:8d47cb713984 674 // }
whismanoid 9:8d47cb713984 675 // if (SelfTest_has_max541) {
whismanoid 9:8d47cb713984 676 // voltageV = 2.7f;
whismanoid 9:8d47cb713984 677 // SelfTest_has_max541 = SelfTest_MAX541_Voltage(cmdLine, max541, voltageV);
whismanoid 9:8d47cb713984 678 // }
whismanoid 9:8d47cb713984 679 // if (SelfTest_has_max541) {
whismanoid 9:8d47cb713984 680 // voltageV = 1.65f;
whismanoid 9:8d47cb713984 681 // SelfTest_has_max541 = SelfTest_MAX541_Voltage(cmdLine, max541, voltageV);
whismanoid 9:8d47cb713984 682 // }
whismanoid 9:8d47cb713984 683 // if (SelfTest_has_max541) {
whismanoid 9:8d47cb713984 684 // voltageV = 2.0f;
whismanoid 9:8d47cb713984 685 // SelfTest_has_max541 = SelfTest_MAX541_Voltage(cmdLine, max541, voltageV);
whismanoid 9:8d47cb713984 686 // }
whismanoid 9:8d47cb713984 687 // if (SelfTest_has_max541) {
whismanoid 9:8d47cb713984 688 // voltageV = 0.25f;
whismanoid 9:8d47cb713984 689 // SelfTest_has_max541 = SelfTest_MAX541_Voltage(cmdLine, max541, voltageV);
whismanoid 9:8d47cb713984 690 // }
whismanoid 9:8d47cb713984 691 // if (SelfTest_has_max541) {
whismanoid 9:8d47cb713984 692 // voltageV = 0.5f;
whismanoid 9:8d47cb713984 693 // SelfTest_has_max541 = SelfTest_MAX541_Voltage(cmdLine, max541, voltageV);
whismanoid 9:8d47cb713984 694 // }
whismanoid 9:8d47cb713984 695 // if (SelfTest_has_max541) {
whismanoid 9:8d47cb713984 696 // voltageV = 1.0f;
whismanoid 9:8d47cb713984 697 // SelfTest_has_max541 = SelfTest_MAX541_Voltage(cmdLine, max541, voltageV);
whismanoid 9:8d47cb713984 698 // }
whismanoid 9:8d47cb713984 699 // if (SelfTest_has_max541 == false) {
whismanoid 9:8d47cb713984 700 // // don't fail just because we're missing the test fixture...
whismanoid 9:8d47cb713984 701 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 702 // Test Fixture: MAX541 not present");
whismanoid 9:8d47cb713984 703 // //~ g_SelfTest_nFail--;
whismanoid 9:8d47cb713984 704 // }
whismanoid 9:8d47cb713984 705 // //
whismanoid 9:8d47cb713984 706 // // TODO1: MAX11131 SelfTest: if Test Fixture: drive MAX541, compare MAX32625MBED.AIN0/AIN4 and MAX11131 AIN0
whismanoid 9:8d47cb713984 707 // // indirectly verify the reference voltage by reading a known input voltage
whismanoid 9:8d47cb713984 708 // if (SelfTest_has_max541) {
whismanoid 9:8d47cb713984 709 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 710 // ");
whismanoid 9:8d47cb713984 711 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 712 // 2.1: TODO1: Check MAX11131 reference voltage using Scan_0001_Manual");
whismanoid 9:8d47cb713984 713 // voltageV = 1.0f;
whismanoid 9:8d47cb713984 714 // SelfTest_MAX541_Voltage(cmdLine, max541, voltageV);
whismanoid 9:8d47cb713984 715 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 716 // MAX11131.Init()");
whismanoid 9:8d47cb713984 717 // Init();
whismanoid 9:8d47cb713984 718 // // 1 ScanManual ch=0 pm=0 id=1
whismanoid 9:8d47cb713984 719 // channelNumber_0_15 = 0;
whismanoid 9:8d47cb713984 720 // PowerManagement_0_2 = 0;
whismanoid 9:8d47cb713984 721 // chan_id_0_1 = 1;
whismanoid 9:8d47cb713984 722 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 723 // MAX11131.channelNumber_0_15=%d", channelNumber_0_15);
whismanoid 9:8d47cb713984 724 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 725 // MAX11131.PowerManagement_0_2=%d", PowerManagement_0_2);
whismanoid 9:8d47cb713984 726 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 727 // MAX11131.chan_id_0_1=%d", chan_id_0_1);
whismanoid 9:8d47cb713984 728 // NumWords = ScanManual();
whismanoid 9:8d47cb713984 729 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 730 // MAX11131.ScanManual -- NumWords = %d",
whismanoid 9:8d47cb713984 731 // NumWords);
whismanoid 9:8d47cb713984 732 // NumWords = ScanManual();
whismanoid 9:8d47cb713984 733 // ReadAINcode();
whismanoid 9:8d47cb713984 734 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 735 // MAX11131.ReadAINcode");
whismanoid 9:8d47cb713984 736 // AINcode_print_value_externalClock(cmdLine, NumWords);
whismanoid 9:8d47cb713984 737 // //
whismanoid 9:8d47cb713984 738 // // 2.1: TODO1: Check MAX11131 reference voltage -- why we read 0xffff 2.4999V here?
whismanoid 9:8d47cb713984 739 // //
whismanoid 9:8d47cb713984 740 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 741 // MAX11131.ScanManual -- NumWords = %d",
whismanoid 9:8d47cb713984 742 // NumWords);
whismanoid 9:8d47cb713984 743 // // Read raw ADC codes from device into AINcode[] and RAW_misoData16[]
whismanoid 9:8d47cb713984 744 // // @pre one of the MAX11311_Scan functions was called, setting NumWords
whismanoid 9:8d47cb713984 745 // ReadAINcode();
whismanoid 9:8d47cb713984 746 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 747 // MAX11131.ReadAINcode");
whismanoid 9:8d47cb713984 748 // AINcode_print_value_externalClock(cmdLine, NumWords);
whismanoid 9:8d47cb713984 749 // //
whismanoid 9:8d47cb713984 750 // // 2.1: TODO1: Check MAX11131 reference voltage -- why we read 0xffff 2.4999V here?
whismanoid 9:8d47cb713984 751 // //
whismanoid 9:8d47cb713984 752 // // compare with mbed/Arduino AIN0-AIN3
whismanoid 9:8d47cb713984 753 // // MAX32625MBED.AIN4 = MAX11131.AIN0
whismanoid 9:8d47cb713984 754 // channelId = 0;
whismanoid 9:8d47cb713984 755 // value_u12 = AINcode[channelId];
whismanoid 9:8d47cb713984 756 // voltageV = VoltageOfCode(value_u12, channelId);
whismanoid 9:8d47cb713984 757 // //
whismanoid 9:8d47cb713984 758 // // tinyTester.Wait_Output_Settling replaces wait_ms
whismanoid 9:8d47cb713984 759 // tinyTester.Wait_Output_Settling();
whismanoid 9:8d47cb713984 760 // // tinyTester.AnalogIn0_Read_Expect_voltageV replaces SelfTest_AnalogInput_Expect_ch_V
whismanoid 9:8d47cb713984 761 // tinyTester.err_threshold = 0.100;
whismanoid 9:8d47cb713984 762 // tinyTester.AnalogIn0_Read_Expect_voltageV(voltageV);
whismanoid 9:8d47cb713984 763 // //
whismanoid 9:8d47cb713984 764 // }
whismanoid 9:8d47cb713984 765 // //
whismanoid 9:8d47cb713984 766 // if (SelfTest_has_max541) {
whismanoid 9:8d47cb713984 767 // voltageV = 1.0f;
whismanoid 9:8d47cb713984 768 // SelfTest_MAX541_Voltage(cmdLine, max541, voltageV);
whismanoid 9:8d47cb713984 769 // }
whismanoid 9:8d47cb713984 770 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 771 // ");
whismanoid 9:8d47cb713984 772 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 773 // 3.1: Test Scan_0001_Manual");
whismanoid 9:8d47cb713984 774 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 775 // MAX11131.Init()");
whismanoid 9:8d47cb713984 776 // Init();
whismanoid 9:8d47cb713984 777 // // 1 ScanManual ch=0 pm=0 id=1
whismanoid 9:8d47cb713984 778 // channelNumber_0_15 = 0;
whismanoid 9:8d47cb713984 779 // PowerManagement_0_2 = 0;
whismanoid 9:8d47cb713984 780 // chan_id_0_1 = 1;
whismanoid 9:8d47cb713984 781 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 782 // MAX11131.channelNumber_0_15=%d", channelNumber_0_15);
whismanoid 9:8d47cb713984 783 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 784 // MAX11131.PowerManagement_0_2=%d", PowerManagement_0_2);
whismanoid 9:8d47cb713984 785 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 786 // MAX11131.chan_id_0_1=%d", chan_id_0_1);
whismanoid 9:8d47cb713984 787 // NumWords = ScanManual();
whismanoid 9:8d47cb713984 788 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 789 // MAX11131.ScanManual -- NumWords = %d",
whismanoid 9:8d47cb713984 790 // NumWords);
whismanoid 9:8d47cb713984 791 // // Read raw ADC codes from device into AINcode[] and RAW_misoData16[]
whismanoid 9:8d47cb713984 792 // // @pre one of the MAX11311_Scan functions was called, setting NumWords
whismanoid 9:8d47cb713984 793 // ReadAINcode();
whismanoid 9:8d47cb713984 794 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 795 // MAX11131.ReadAINcode");
whismanoid 9:8d47cb713984 796 // AINcode_print_value_externalClock(cmdLine, NumWords);
whismanoid 9:8d47cb713984 797 // // compare with mbed/Arduino AIN0-AIN3
whismanoid 9:8d47cb713984 798 // // MAX32625MBED.AIN4 = MAX11131.AIN0
whismanoid 9:8d47cb713984 799 // channelId = 0;
whismanoid 9:8d47cb713984 800 // value_u12 = AINcode[channelId];
whismanoid 9:8d47cb713984 801 // voltageV = VoltageOfCode(value_u12, channelId);
whismanoid 9:8d47cb713984 802 // //
whismanoid 9:8d47cb713984 803 // // tinyTester.Wait_Output_Settling replaces wait_ms
whismanoid 9:8d47cb713984 804 // tinyTester.Wait_Output_Settling();
whismanoid 9:8d47cb713984 805 // // tinyTester.AnalogIn0_Read_Expect_voltageV replaces SelfTest_AnalogInput_Expect_ch_V
whismanoid 9:8d47cb713984 806 // tinyTester.err_threshold = 0.100;
whismanoid 9:8d47cb713984 807 // tinyTester.AnalogIn0_Read_Expect_voltageV(voltageV);
whismanoid 9:8d47cb713984 808 // //
whismanoid 9:8d47cb713984 809 // //
whismanoid 9:8d47cb713984 810 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 811 // ");
whismanoid 9:8d47cb713984 812 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 813 // 3.4: Test Scan_0100_StandardExternalClock");
whismanoid 9:8d47cb713984 814 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 815 // MAX11131.Init()");
whismanoid 9:8d47cb713984 816 // Init();
whismanoid 9:8d47cb713984 817 // // MAX11131 > 4
whismanoid 9:8d47cb713984 818 // // ScanStandardExternalClock ch=9 pm=0 id=1
whismanoid 9:8d47cb713984 819 // // ScanRead_nWords_chanID nWords=10
whismanoid 9:8d47cb713984 820 // // ch=0 xu=2964 = 0x0b94 = 1.8091V
whismanoid 9:8d47cb713984 821 // // ch=1 xu=2227 = 0x08b3 = 1.3593V
whismanoid 9:8d47cb713984 822 // // ch=2 xu=1570 = 0x0622 = 0.9583V
whismanoid 9:8d47cb713984 823 // // ch=3 xu=865 = 0x0361 = 0.5280V
whismanoid 9:8d47cb713984 824 // // ch=4 xu=630 = 0x0276 = 0.3845V
whismanoid 9:8d47cb713984 825 // // ch=5 xu=594 = 0x0252 = 0.3625V
whismanoid 9:8d47cb713984 826 // // ch=6 xu=461 = 0x01cd = 0.2814V
whismanoid 9:8d47cb713984 827 // // ch=7 xu=364 = 0x016c = 0.2222V
whismanoid 9:8d47cb713984 828 // // ch=8 xu=480 = 0x01e0 = 0.2930V
whismanoid 9:8d47cb713984 829 // // ch=9 xu=616 = 0x0268 = 0.3760V
whismanoid 9:8d47cb713984 830 // channelNumber_0_15 = 9;
whismanoid 9:8d47cb713984 831 // PowerManagement_0_2 = 0;
whismanoid 9:8d47cb713984 832 // chan_id_0_1 = 1;
whismanoid 9:8d47cb713984 833 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 834 // MAX11131.channelNumber_0_15=%d", channelNumber_0_15);
whismanoid 9:8d47cb713984 835 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 836 // MAX11131.PowerManagement_0_2=%d", PowerManagement_0_2);
whismanoid 9:8d47cb713984 837 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 838 // MAX11131.chan_id_0_1=%d", chan_id_0_1);
whismanoid 9:8d47cb713984 839 // NumWords = ScanStandardExternalClock();
whismanoid 9:8d47cb713984 840 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 841 // MAX11131.ScanStandardExternalClock -- NumWords = %d",
whismanoid 9:8d47cb713984 842 // NumWords);
whismanoid 9:8d47cb713984 843 // // Read raw ADC codes from device into AINcode[] and RAW_misoData16[]
whismanoid 9:8d47cb713984 844 // // @pre one of the MAX11311_Scan functions was called, setting NumWords
whismanoid 9:8d47cb713984 845 // ReadAINcode();
whismanoid 9:8d47cb713984 846 // cmdLine.serial().printf("
whismanoid 9:8d47cb713984 847 // MAX11131.ReadAINcode");
whismanoid 9:8d47cb713984 848 // // @post RAW_misoData16[index] contains the raw SPI Master-In,Slave-Out data
whismanoid 9:8d47cb713984 849 // // @post AINcode[NUM_CHANNELS] contains the latest readings in LSBs
whismanoid 9:8d47cb713984 850 // // expect NumWords == channelNumber_0_15 + 1;
whismanoid 9:8d47cb713984 851 // // expect RAW_misoData16[index] msnybble 0,1,2,3,...
whismanoid 9:8d47cb713984 852 // AINcode_print_value_externalClock(cmdLine, NumWords);
whismanoid 9:8d47cb713984 853 // // compare with mbed/Arduino AIN0-AIN3
whismanoid 9:8d47cb713984 854 // // MAX32625MBED.AIN4 = MAX11131.AIN0
whismanoid 9:8d47cb713984 855 // channelId = 0;
whismanoid 9:8d47cb713984 856 // value_u12 = AINcode[channelId];
whismanoid 9:8d47cb713984 857 // voltageV = VoltageOfCode(value_u12, channelId);
whismanoid 9:8d47cb713984 858 // // tinyTester.Wait_Output_Settling replaces wait_ms
whismanoid 9:8d47cb713984 859 // tinyTester.Wait_Output_Settling();
whismanoid 9:8d47cb713984 860 // // tinyTester.AnalogIn0_Read_Expect_voltageV replaces SelfTest_AnalogInput_Expect_ch_V
whismanoid 9:8d47cb713984 861 // tinyTester.err_threshold = 0.100;
whismanoid 9:8d47cb713984 862 // tinyTester.AnalogIn0_Read_Expect_voltageV(voltageV);
whismanoid 9:8d47cb713984 863 // // compare MAX32625MBED.AIN5 = MAX11131.AIN1
whismanoid 9:8d47cb713984 864 // //channelId = 1;
whismanoid 9:8d47cb713984 865 // //value_u12 = AINcode[channelId];
whismanoid 9:8d47cb713984 866 // //voltageV = VoltageOfCode(value_u12, channelId);
whismanoid 9:8d47cb713984 867 // //SelfTest_AnalogInput_Expect_ch_V(cmdLine, 5, voltageV, 0.100);
whismanoid 9:8d47cb713984 868 //
whismanoid 9:8d47cb713984 869 //
whismanoid 9:8d47cb713984 870 //
whismanoid 1:77f1ee332e4a 871 void MAX11131::Init(void)
whismanoid 1:77f1ee332e4a 872 {
whismanoid 1:77f1ee332e4a 873
whismanoid 1:77f1ee332e4a 874 //----------------------------------------
whismanoid 1:77f1ee332e4a 875 // Nominal Full-Scale Voltage Reference
whismanoid 1:77f1ee332e4a 876 VRef = 2.500;
whismanoid 1:77f1ee332e4a 877
whismanoid 1:77f1ee332e4a 878 //----------------------------------------
whismanoid 1:77f1ee332e4a 879 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 880 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 881 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 882 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 883 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 884 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 885 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 886 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 887
whismanoid 1:77f1ee332e4a 888 //----------------------------------------
whismanoid 1:77f1ee332e4a 889 // define write-only register ADC_CONFIGURATION
whismanoid 1:77f1ee332e4a 890 ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid 1:77f1ee332e4a 891 const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid 1:77f1ee332e4a 892 const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid 1:77f1ee332e4a 893 const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid 1:77f1ee332e4a 894 const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid 1:77f1ee332e4a 895 const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid 1:77f1ee332e4a 896 const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid 1:77f1ee332e4a 897
whismanoid 1:77f1ee332e4a 898 //----------------------------------------
whismanoid 1:77f1ee332e4a 899 // define write-only registers UNIPOLAR,BIPOLAR,RANGE
whismanoid 1:77f1ee332e4a 900 UNIPOLAR = 0x8800; //!< mosiData16 0x8800..0x8FFF format: 1 0 0 0 1 UCH0/1 UCH2/3 UCH4/5 UCH6/7 UCH8/9 UCH10/11 UCH12/13 UCH14/15 PDIFF_COM x x
whismanoid 1:77f1ee332e4a 901 BIPOLAR = 0x9000; //!< mosiData16 0x9000..0x97FF format: 1 0 0 1 0 BCH0/1 BCH2/3 BCH4/5 BCH6/7 BCH8/9 BCH10/11 BCH12/13 BCH14/15 x x x
whismanoid 1:77f1ee332e4a 902 RANGE = 0x9800; //!< mosiData16 0x9800..0x9FFF format: 1 0 0 1 1 RANGE0/1 RANGE2/3 RANGE4/5 RANGE6/7 RANGE8/9 RANGE10/11 RANGE12/13 RANGE14/15 x x x
whismanoid 1:77f1ee332e4a 903 const int AIN_0_1_LSB = 10; // UNIPOLAR.UCH0/1 BIPOLAR.BCH0/1 RANGE.RANGE0/1
whismanoid 1:77f1ee332e4a 904 const int AIN_2_3_LSB = 9; // UNIPOLAR.UCH2/3 BIPOLAR.BCH2/3 RANGE.RANGE2/3
whismanoid 1:77f1ee332e4a 905 const int AIN_4_5_LSB = 8; // UNIPOLAR.UCH4/5 BIPOLAR.BCH4/5 RANGE.RANGE4/5
whismanoid 1:77f1ee332e4a 906 const int AIN_6_7_LSB = 7; // UNIPOLAR.UCH6/7 BIPOLAR.BCH6/7 RANGE.RANGE6/7
whismanoid 1:77f1ee332e4a 907 const int AIN_8_9_LSB = 6; // UNIPOLAR.UCH8/9 BIPOLAR.BCH8/9 RANGE.RANGE8/9
whismanoid 1:77f1ee332e4a 908 const int AIN_10_11_LSB = 5; // UNIPOLAR.UCH10/11 BIPOLAR.BCH10/11 RANGE.RANGE10/11
whismanoid 1:77f1ee332e4a 909 const int AIN_12_13_LSB = 4; // UNIPOLAR.UCH12/13 BIPOLAR.BCH12/13 RANGE.RANGE12/13
whismanoid 1:77f1ee332e4a 910 const int AIN_14_15_LSB = 3; // UNIPOLAR.UCH14/15 BIPOLAR.BCH14/15 RANGE.RANGE14/15
whismanoid 1:77f1ee332e4a 911 const int PDIFF_COMM_LSB = 2; const int PDIFF_COMM_BITS = 0x01; // UNIPOLAR.PDIFF_COM
whismanoid 1:77f1ee332e4a 912 // Summary of Table 8:
whismanoid 1:77f1ee332e4a 913 // UCH0/1=0, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 914 // UCH0/1=1, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 4:8a0ae95546fa 915 // UCH0/1=0, BCH0/1=1, RANGE0/1=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 916 // UCH0/1=1, BCH0/1=1, RANGE0/1=0: reserved do not use
whismanoid 1:77f1ee332e4a 917 // UCH0/1=0, BCH0/1=0, RANGE0/1=1: reserved do not use
whismanoid 1:77f1ee332e4a 918 // UCH0/1=1, BCH0/1=0, RANGE0/1=1: reserved do not use
whismanoid 4:8a0ae95546fa 919 // UCH0/1=0, BCH0/1=1, RANGE0/1=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 920 // UCH0/1=1, BCH0/1=1, RANGE0/1=1: reserved do not use
whismanoid 1:77f1ee332e4a 921 // Both channels of a differential pair must be within Input Voltage Range (dynamic signal range) 0..VREF.
whismanoid 1:77f1ee332e4a 922
whismanoid 1:77f1ee332e4a 923 //----------------------------------------
whismanoid 1:77f1ee332e4a 924 // define write-only registers CSCAN0,CSCAN1
whismanoid 1:77f1ee332e4a 925 CSCAN0 = 0xA000; //!< mosiData16 0xA000..0xA7FF format: 1 0 1 0 0 CHSCAN15 CHSCAN14 CHSCAN13 CHSCAN12 CHSCAN11 CHSCAN10 CHSCAN9 CHSCAN8 x x x
whismanoid 1:77f1ee332e4a 926 const int CHSCAN15_LSB = 10; // CSCAN0.CHSCAN15
whismanoid 1:77f1ee332e4a 927 const int CHSCAN14_LSB = 9; // CSCAN0.CHSCAN14
whismanoid 1:77f1ee332e4a 928 const int CHSCAN13_LSB = 8; // CSCAN0.CHSCAN13
whismanoid 1:77f1ee332e4a 929 const int CHSCAN12_LSB = 7; // CSCAN0.CHSCAN12
whismanoid 1:77f1ee332e4a 930 const int CHSCAN11_LSB = 6; // CSCAN0.CHSCAN11
whismanoid 1:77f1ee332e4a 931 const int CHSCAN10_LSB = 5; // CSCAN0.CHSCAN10
whismanoid 1:77f1ee332e4a 932 const int CHSCAN9_LSB = 4; // CSCAN0.CHSCAN9
whismanoid 1:77f1ee332e4a 933 const int CHSCAN8_LSB = 3; // CSCAN0.CHSCAN8
whismanoid 1:77f1ee332e4a 934 CSCAN1 = 0xA800; //!< mosiData16 0xA800..0xAFFF format: 1 0 1 0 1 CHSCAN7 CHSCAN6 CHSCAN5 CHSCAN4 CHSCAN3 CHSCAN2 CHSCAN1 CHSCAN0 x x x
whismanoid 1:77f1ee332e4a 935 const int CHSCAN7_LSB = 10; // CSCAN1.CHSCAN7
whismanoid 1:77f1ee332e4a 936 const int CHSCAN6_LSB = 9; // CSCAN1.CHSCAN6
whismanoid 1:77f1ee332e4a 937 const int CHSCAN5_LSB = 8; // CSCAN1.CHSCAN5
whismanoid 1:77f1ee332e4a 938 const int CHSCAN4_LSB = 7; // CSCAN1.CHSCAN4
whismanoid 1:77f1ee332e4a 939 const int CHSCAN3_LSB = 6; // CSCAN1.CHSCAN3
whismanoid 1:77f1ee332e4a 940 const int CHSCAN2_LSB = 5; // CSCAN1.CHSCAN2
whismanoid 1:77f1ee332e4a 941 const int CHSCAN1_LSB = 4; // CSCAN1.CHSCAN1
whismanoid 1:77f1ee332e4a 942 const int CHSCAN0_LSB = 3; // CSCAN1.CHSCAN0
whismanoid 1:77f1ee332e4a 943
whismanoid 1:77f1ee332e4a 944 //----------------------------------------
whismanoid 1:77f1ee332e4a 945 // Initialize shadow of write-only register SAMPLESET.
whismanoid 1:77f1ee332e4a 946 // Do not write to SAMPLESET at this time.
whismanoid 1:77f1ee332e4a 947 // A write to SAMPLESET must be followed by specified number of pattern entry words.
whismanoid 1:77f1ee332e4a 948 // See ScanSampleSetExternalClock function for details.
whismanoid 1:77f1ee332e4a 949 SAMPLESET = 0xB000; //!< mosiData16 0xB000..0xB7FF format: 1 0 1 1 0 SEQ_LENGTH[7:0] x x x
whismanoid 1:77f1ee332e4a 950 const int SAMPLESET_LSB = 3; const int SAMPLESET_BITS = 0xFF; // SAMPLESET.SEQ_LENGTH[7:0]
whismanoid 1:77f1ee332e4a 951
whismanoid 1:77f1ee332e4a 952 //----------------------------------------
whismanoid 1:77f1ee332e4a 953 // Reset all registers: ADC_MODE_CONTROL.RESET[1:0] = 2
whismanoid 1:77f1ee332e4a 954 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 955 ADC_MODE_CONTROL |= ((2 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 956
whismanoid 1:77f1ee332e4a 957 //----------------------------------------
whismanoid 1:77f1ee332e4a 958 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 959 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 960 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 961 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 962 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 963 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 964
whismanoid 1:77f1ee332e4a 965 #if REFSEL_0
whismanoid 1:77f1ee332e4a 966
whismanoid 1:77f1ee332e4a 967 //----------------------------------------
whismanoid 1:77f1ee332e4a 968 // Global setting for all channels: ADC_CONFIGURATION.REFSEL=0: external single-ended reference
whismanoid 1:77f1ee332e4a 969 // SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL
whismanoid 1:77f1ee332e4a 970 // SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL: EXTERNAL SINGLE-ENDED
whismanoid 1:77f1ee332e4a 971 // SELECT ADC CONFIGURATION register set REFSEL BIT TO 0
whismanoid 1:77f1ee332e4a 972 ADC_CONFIGURATION &= ~ (( REFSEL_BITS) << REFSEL_LSB); // ADC_CONFIGURATION.REFSEL=0: external single-ended reference. (For the 16-channel chips: channel AIN15 is available.)
whismanoid 1:77f1ee332e4a 973 #endif // REFSEL_0
whismanoid 1:77f1ee332e4a 974
whismanoid 1:77f1ee332e4a 975 #if REFSEL_1
whismanoid 1:77f1ee332e4a 976
whismanoid 1:77f1ee332e4a 977 //----------------------------------------
whismanoid 1:77f1ee332e4a 978 // Global setting for all channels: ADC_CONFIGURATION.REFSEL=1: external differential reference (For the 16-channel chips: channel AIN15 is unavailable, the pin is assigned to REF-.)
whismanoid 1:77f1ee332e4a 979 // SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL
whismanoid 1:77f1ee332e4a 980 // SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL: EXTERNAL DIFFERENTIAL
whismanoid 1:77f1ee332e4a 981 // SELECT ADC CONFIGURATION register set REFSEL BIT TO 1
whismanoid 1:77f1ee332e4a 982 ADC_CONFIGURATION |= ((1 & REFSEL_BITS) << REFSEL_LSB); // ADC_CONFIGURATION.REFSEL=1: external differential reference. (For the 16-channel chips: channel AIN15 is unavailable, the pin is assigned to REF-.)
whismanoid 1:77f1ee332e4a 983 #endif // REFSEL_1
whismanoid 1:77f1ee332e4a 984
whismanoid 1:77f1ee332e4a 985 #if PDIFF_COMM_0
whismanoid 1:77f1ee332e4a 986
whismanoid 1:77f1ee332e4a 987 //----------------------------------------
whismanoid 1:77f1ee332e4a 988 // Global setting for all channels: PDIFF_COMM
whismanoid 1:77f1ee332e4a 989 UNIPOLAR &= ~ (( PDIFF_COMM_BITS) << PDIFF_COMM_LSB); // UNIPOLAR.PDIFF_COMM=0: all single-ended channels use GND as common
whismanoid 1:77f1ee332e4a 990 #endif // PDIFF_COMM_0
whismanoid 1:77f1ee332e4a 991
whismanoid 1:77f1ee332e4a 992 #if PDIFF_COMM_1
whismanoid 1:77f1ee332e4a 993
whismanoid 1:77f1ee332e4a 994 //----------------------------------------
whismanoid 1:77f1ee332e4a 995 // Global setting for all channels: PDIFF_COMM
whismanoid 1:77f1ee332e4a 996 // SELECT UNIPOLAR AND register set BIT PDIFF_COM TO 1 FOR PSEUDODIFFERENTIAL SELECTION
whismanoid 1:77f1ee332e4a 997 UNIPOLAR |= ((1 & PDIFF_COMM_BITS) << PDIFF_COMM_LSB); // UNIPOLAR.PDIFF_COMM=1: all single-ended channels are pseudo-differential with REF- as common
whismanoid 1:77f1ee332e4a 998 #endif // PDIFF_COMM_1
whismanoid 1:77f1ee332e4a 999
whismanoid 1:77f1ee332e4a 1000 #if AIN_0_1_SingleEnded
whismanoid 1:77f1ee332e4a 1001
whismanoid 1:77f1ee332e4a 1002 //----------------------------------------
whismanoid 1:77f1ee332e4a 1003 // ADC Channels AIN0, AIN1 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 1004 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1005 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1006 // AIN0 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1007 // AIN1 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1008 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 1009 // AIN0 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1010 // AIN1 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1011 //
whismanoid 1:77f1ee332e4a 1012 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 1013 UNIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 1014 BIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 1015 RANGE &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 1016 // UCH0/1=0, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1017 #endif // AIN_0_1_SingleEnded
whismanoid 1:77f1ee332e4a 1018
whismanoid 1:77f1ee332e4a 1019 #if AIN_0_1_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1020
whismanoid 1:77f1ee332e4a 1021 //----------------------------------------
whismanoid 1:77f1ee332e4a 1022 // ADC Channels AIN0, AIN1 = Differential Unipolar (AIN0 > AIN1)
whismanoid 1:77f1ee332e4a 1023 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1024 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1025 // AIN0, AIN1 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1026 // AIN0 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1027 // AIN1 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1028 //
whismanoid 1:77f1ee332e4a 1029 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 1030 UNIPOLAR |= (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 1031 BIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 1032 RANGE &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 1033 // UCH0/1=1, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1034 #endif // AIN_0_1_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1035
whismanoid 1:77f1ee332e4a 1036 #if AIN_0_1_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1037
whismanoid 1:77f1ee332e4a 1038 //----------------------------------------
whismanoid 1:77f1ee332e4a 1039 // ADC Channels AIN0, AIN1 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1040 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1041 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 1042 // AIN0, AIN1 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 1043 // AIN0 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1044 // AIN1 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1045 //
whismanoid 1:77f1ee332e4a 1046 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1047 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 1048 UNIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 1049 BIPOLAR |= (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 1050 RANGE &= ~ (1 << AIN_0_1_LSB);
whismanoid 4:8a0ae95546fa 1051 // UCH0/1=0, BCH0/1=1, RANGE0/1=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1052 #endif // AIN_0_1_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1053
whismanoid 1:77f1ee332e4a 1054 #if AIN_0_1_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1055
whismanoid 1:77f1ee332e4a 1056 //----------------------------------------
whismanoid 1:77f1ee332e4a 1057 // ADC Channels AIN0, AIN1 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1058 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1059 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 1060 // AIN0, AIN1 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 1061 // AIN0 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1062 // AIN1 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1063 //
whismanoid 1:77f1ee332e4a 1064 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1065 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 1066 UNIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 1067 BIPOLAR |= (1 << AIN_0_1_LSB);
whismanoid 1:77f1ee332e4a 1068 RANGE |= (1 << AIN_0_1_LSB);
whismanoid 4:8a0ae95546fa 1069 // UCH0/1=0, BCH0/1=1, RANGE0/1=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1070 #endif // AIN_0_1_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1071
whismanoid 1:77f1ee332e4a 1072 #if AIN_2_3_SingleEnded
whismanoid 1:77f1ee332e4a 1073
whismanoid 1:77f1ee332e4a 1074 //----------------------------------------
whismanoid 1:77f1ee332e4a 1075 // ADC Channels AIN2, AIN3 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 1076 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1077 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1078 // AIN2 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1079 // AIN3 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1080 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 1081 // AIN2 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1082 // AIN3 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1083 //
whismanoid 1:77f1ee332e4a 1084 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 1085 UNIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 1086 BIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 1087 RANGE &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 1088 // UCH2/3=0, BCH2/3=0, RANGE2/3=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1089 #endif // AIN_2_3_SingleEnded
whismanoid 1:77f1ee332e4a 1090
whismanoid 1:77f1ee332e4a 1091 #if AIN_2_3_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1092
whismanoid 1:77f1ee332e4a 1093 //----------------------------------------
whismanoid 1:77f1ee332e4a 1094 // ADC Channels AIN2, AIN3 = Differential Unipolar (AIN2 > AIN3)
whismanoid 1:77f1ee332e4a 1095 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1096 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1097 // AIN2, AIN3 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1098 // AIN2 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1099 // AIN3 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1100 //
whismanoid 1:77f1ee332e4a 1101 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 1102 UNIPOLAR |= (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 1103 BIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 1104 RANGE &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 1105 // UCH2/3=1, BCH2/3=0, RANGE2/3=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1106 #endif // AIN_2_3_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1107
whismanoid 1:77f1ee332e4a 1108 #if AIN_2_3_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1109
whismanoid 1:77f1ee332e4a 1110 //----------------------------------------
whismanoid 1:77f1ee332e4a 1111 // ADC Channels AIN2, AIN3 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1112 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1113 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 1114 // AIN2, AIN3 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 1115 // AIN2 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1116 // AIN3 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1117 //
whismanoid 1:77f1ee332e4a 1118 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1119 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 1120 UNIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 1121 BIPOLAR |= (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 1122 RANGE &= ~ (1 << AIN_2_3_LSB);
whismanoid 4:8a0ae95546fa 1123 // UCH2/3=0, BCH2/3=1, RANGE2/3=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1124 #endif // AIN_2_3_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1125
whismanoid 1:77f1ee332e4a 1126 #if AIN_2_3_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1127
whismanoid 1:77f1ee332e4a 1128 //----------------------------------------
whismanoid 1:77f1ee332e4a 1129 // ADC Channels AIN2, AIN3 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1130 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1131 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 1132 // AIN2, AIN3 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 1133 // AIN2 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1134 // AIN3 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1135 //
whismanoid 1:77f1ee332e4a 1136 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1137 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 1138 UNIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 1139 BIPOLAR |= (1 << AIN_2_3_LSB);
whismanoid 1:77f1ee332e4a 1140 RANGE |= (1 << AIN_2_3_LSB);
whismanoid 4:8a0ae95546fa 1141 // UCH2/3=0, BCH2/3=1, RANGE2/3=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1142 #endif // AIN_2_3_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1143
whismanoid 1:77f1ee332e4a 1144 #if AIN_4_5_SingleEnded
whismanoid 1:77f1ee332e4a 1145
whismanoid 1:77f1ee332e4a 1146 //----------------------------------------
whismanoid 1:77f1ee332e4a 1147 // ADC Channels AIN4, AIN5 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 1148 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1149 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1150 // AIN4 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1151 // AIN5 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1152 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 1153 // AIN4 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1154 // AIN5 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1155 //
whismanoid 1:77f1ee332e4a 1156 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 1157 UNIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 1158 BIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 1159 RANGE &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 1160 // UCH4/5=0, BCH4/5=0, RANGE4/5=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1161 #endif // AIN_4_5_SingleEnded
whismanoid 1:77f1ee332e4a 1162
whismanoid 1:77f1ee332e4a 1163 #if AIN_4_5_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1164
whismanoid 1:77f1ee332e4a 1165 //----------------------------------------
whismanoid 1:77f1ee332e4a 1166 // ADC Channels AIN4, AIN5 = Differential Unipolar (AIN4 > AIN5)
whismanoid 1:77f1ee332e4a 1167 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1168 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1169 // AIN4, AIN5 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1170 // AIN4 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1171 // AIN5 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1172 //
whismanoid 1:77f1ee332e4a 1173 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 1174 UNIPOLAR |= (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 1175 BIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 1176 RANGE &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 1177 // UCH4/5=1, BCH4/5=0, RANGE4/5=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1178 #endif // AIN_4_5_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1179
whismanoid 1:77f1ee332e4a 1180 #if AIN_4_5_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1181
whismanoid 1:77f1ee332e4a 1182 //----------------------------------------
whismanoid 1:77f1ee332e4a 1183 // ADC Channels AIN4, AIN5 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1184 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1185 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 1186 // AIN4, AIN5 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 1187 // AIN4 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1188 // AIN5 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1189 //
whismanoid 1:77f1ee332e4a 1190 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1191 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 1192 UNIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 1193 BIPOLAR |= (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 1194 RANGE &= ~ (1 << AIN_4_5_LSB);
whismanoid 4:8a0ae95546fa 1195 // UCH4/5=0, BCH4/5=1, RANGE4/5=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1196 #endif // AIN_4_5_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1197
whismanoid 1:77f1ee332e4a 1198 #if AIN_4_5_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1199
whismanoid 1:77f1ee332e4a 1200 //----------------------------------------
whismanoid 1:77f1ee332e4a 1201 // ADC Channels AIN4, AIN5 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1202 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1203 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 1204 // AIN4, AIN5 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 1205 // AIN4 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1206 // AIN5 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1207 //
whismanoid 1:77f1ee332e4a 1208 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1209 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 1210 UNIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 1211 BIPOLAR |= (1 << AIN_4_5_LSB);
whismanoid 1:77f1ee332e4a 1212 RANGE |= (1 << AIN_4_5_LSB);
whismanoid 4:8a0ae95546fa 1213 // UCH4/5=0, BCH4/5=1, RANGE4/5=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1214 #endif // AIN_4_5_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1215
whismanoid 1:77f1ee332e4a 1216 #if AIN_6_7_SingleEnded
whismanoid 1:77f1ee332e4a 1217
whismanoid 1:77f1ee332e4a 1218 //----------------------------------------
whismanoid 1:77f1ee332e4a 1219 // ADC Channels AIN6, AIN7 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 1220 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1221 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1222 // AIN6 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1223 // AIN7 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1224 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 1225 // AIN6 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1226 // AIN7 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1227 //
whismanoid 1:77f1ee332e4a 1228 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 1229 UNIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 1230 BIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 1231 RANGE &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 1232 // UCH6/7=0, BCH6/7=0, RANGE6/7=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1233 #endif // AIN_6_7_SingleEnded
whismanoid 1:77f1ee332e4a 1234
whismanoid 1:77f1ee332e4a 1235 #if AIN_6_7_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1236
whismanoid 1:77f1ee332e4a 1237 //----------------------------------------
whismanoid 1:77f1ee332e4a 1238 // ADC Channels AIN6, AIN7 = Differential Unipolar (AIN6 > AIN7)
whismanoid 1:77f1ee332e4a 1239 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1240 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1241 // AIN6, AIN7 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1242 // AIN6 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1243 // AIN7 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1244 //
whismanoid 1:77f1ee332e4a 1245 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 1246 UNIPOLAR |= (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 1247 BIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 1248 RANGE &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 1249 // UCH6/7=1, BCH6/7=0, RANGE6/7=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1250 #endif // AIN_6_7_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1251
whismanoid 1:77f1ee332e4a 1252 #if AIN_6_7_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1253
whismanoid 1:77f1ee332e4a 1254 //----------------------------------------
whismanoid 1:77f1ee332e4a 1255 // ADC Channels AIN6, AIN7 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1256 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1257 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 1258 // AIN6, AIN7 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 1259 // AIN6 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1260 // AIN7 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1261 //
whismanoid 1:77f1ee332e4a 1262 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1263 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 1264 UNIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 1265 BIPOLAR |= (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 1266 RANGE &= ~ (1 << AIN_6_7_LSB);
whismanoid 4:8a0ae95546fa 1267 // UCH6/7=0, BCH6/7=1, RANGE6/7=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1268 #endif // AIN_6_7_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1269
whismanoid 1:77f1ee332e4a 1270 #if AIN_6_7_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1271
whismanoid 1:77f1ee332e4a 1272 //----------------------------------------
whismanoid 1:77f1ee332e4a 1273 // ADC Channels AIN6, AIN7 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1274 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1275 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 1276 // AIN6, AIN7 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 1277 // AIN6 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1278 // AIN7 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1279 //
whismanoid 1:77f1ee332e4a 1280 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1281 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 1282 UNIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 1283 BIPOLAR |= (1 << AIN_6_7_LSB);
whismanoid 1:77f1ee332e4a 1284 RANGE |= (1 << AIN_6_7_LSB);
whismanoid 4:8a0ae95546fa 1285 // UCH6/7=0, BCH6/7=1, RANGE6/7=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1286 #endif // AIN_6_7_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1287
whismanoid 1:77f1ee332e4a 1288 #if AIN_8_9_SingleEnded
whismanoid 1:77f1ee332e4a 1289
whismanoid 1:77f1ee332e4a 1290 //----------------------------------------
whismanoid 1:77f1ee332e4a 1291 // ADC Channels AIN8, AIN9 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 1292 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1293 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1294 // AIN8 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1295 // AIN9 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1296 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 1297 // AIN8 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1298 // AIN9 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1299 //
whismanoid 1:77f1ee332e4a 1300 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 1301 UNIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 1302 BIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 1303 RANGE &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 1304 // UCH8/9=0, BCH8/9=0, RANGE8/9=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1305 #endif // AIN_8_9_SingleEnded
whismanoid 1:77f1ee332e4a 1306
whismanoid 1:77f1ee332e4a 1307 #if AIN_8_9_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1308
whismanoid 1:77f1ee332e4a 1309 //----------------------------------------
whismanoid 1:77f1ee332e4a 1310 // ADC Channels AIN8, AIN9 = Differential Unipolar (AIN8 > AIN9)
whismanoid 1:77f1ee332e4a 1311 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1312 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1313 // AIN8, AIN9 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1314 // AIN8 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1315 // AIN9 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1316 //
whismanoid 1:77f1ee332e4a 1317 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 1318 UNIPOLAR |= (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 1319 BIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 1320 RANGE &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 1321 // UCH8/9=1, BCH8/9=0, RANGE8/9=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1322 #endif // AIN_8_9_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1323
whismanoid 1:77f1ee332e4a 1324 #if AIN_8_9_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1325
whismanoid 1:77f1ee332e4a 1326 //----------------------------------------
whismanoid 1:77f1ee332e4a 1327 // ADC Channels AIN8, AIN9 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1328 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1329 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 1330 // AIN8, AIN9 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 1331 // AIN8 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1332 // AIN9 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1333 //
whismanoid 1:77f1ee332e4a 1334 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1335 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 1336 UNIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 1337 BIPOLAR |= (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 1338 RANGE &= ~ (1 << AIN_8_9_LSB);
whismanoid 4:8a0ae95546fa 1339 // UCH8/9=0, BCH8/9=1, RANGE8/9=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1340 #endif // AIN_8_9_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1341
whismanoid 1:77f1ee332e4a 1342 #if AIN_8_9_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1343
whismanoid 1:77f1ee332e4a 1344 //----------------------------------------
whismanoid 1:77f1ee332e4a 1345 // ADC Channels AIN8, AIN9 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1346 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1347 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 1348 // AIN8, AIN9 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 1349 // AIN8 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1350 // AIN9 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1351 //
whismanoid 1:77f1ee332e4a 1352 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1353 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 1354 UNIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 1355 BIPOLAR |= (1 << AIN_8_9_LSB);
whismanoid 1:77f1ee332e4a 1356 RANGE |= (1 << AIN_8_9_LSB);
whismanoid 4:8a0ae95546fa 1357 // UCH8/9=0, BCH8/9=1, RANGE8/9=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1358 #endif // AIN_8_9_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1359
whismanoid 1:77f1ee332e4a 1360 #if AIN_10_11_SingleEnded
whismanoid 1:77f1ee332e4a 1361
whismanoid 1:77f1ee332e4a 1362 //----------------------------------------
whismanoid 1:77f1ee332e4a 1363 // ADC Channels AIN10, AIN11 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 1364 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1365 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1366 // AIN10 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1367 // AIN11 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1368 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 1369 // AIN10 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1370 // AIN11 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1371 //
whismanoid 1:77f1ee332e4a 1372 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 1373 UNIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1374 BIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1375 RANGE &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1376 // UCH10/11=0, BCH10/11=0, RANGE10/11=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1377 #endif // AIN_10_11_SingleEnded
whismanoid 1:77f1ee332e4a 1378
whismanoid 1:77f1ee332e4a 1379 #if AIN_10_11_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1380
whismanoid 1:77f1ee332e4a 1381 //----------------------------------------
whismanoid 1:77f1ee332e4a 1382 // ADC Channels AIN10, AIN11 = Differential Unipolar (AIN10 > AIN11)
whismanoid 1:77f1ee332e4a 1383 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1384 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1385 // AIN10, AIN11 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1386 // AIN10 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1387 // AIN11 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1388 //
whismanoid 1:77f1ee332e4a 1389 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 1390 UNIPOLAR |= (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1391 BIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1392 RANGE &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1393 // UCH10/11=1, BCH10/11=0, RANGE10/11=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1394 #endif // AIN_10_11_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1395
whismanoid 1:77f1ee332e4a 1396 #if AIN_10_11_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1397
whismanoid 1:77f1ee332e4a 1398 //----------------------------------------
whismanoid 1:77f1ee332e4a 1399 // ADC Channels AIN10, AIN11 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1400 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1401 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 1402 // AIN10, AIN11 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 1403 // AIN10 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1404 // AIN11 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1405 //
whismanoid 1:77f1ee332e4a 1406 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1407 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 1408 UNIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1409 BIPOLAR |= (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1410 RANGE &= ~ (1 << AIN_10_11_LSB);
whismanoid 4:8a0ae95546fa 1411 // UCH10/11=0, BCH10/11=1, RANGE10/11=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1412 #endif // AIN_10_11_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1413
whismanoid 1:77f1ee332e4a 1414 #if AIN_10_11_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1415
whismanoid 1:77f1ee332e4a 1416 //----------------------------------------
whismanoid 1:77f1ee332e4a 1417 // ADC Channels AIN10, AIN11 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1418 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1419 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 1420 // AIN10, AIN11 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 1421 // AIN10 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1422 // AIN11 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1423 //
whismanoid 1:77f1ee332e4a 1424 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1425 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 1426 UNIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1427 BIPOLAR |= (1 << AIN_10_11_LSB);
whismanoid 1:77f1ee332e4a 1428 RANGE |= (1 << AIN_10_11_LSB);
whismanoid 4:8a0ae95546fa 1429 // UCH10/11=0, BCH10/11=1, RANGE10/11=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1430 #endif // AIN_10_11_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1431
whismanoid 1:77f1ee332e4a 1432 #if AIN_12_13_SingleEnded
whismanoid 1:77f1ee332e4a 1433
whismanoid 1:77f1ee332e4a 1434 //----------------------------------------
whismanoid 1:77f1ee332e4a 1435 // ADC Channels AIN12, AIN13 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 1436 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1437 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1438 // AIN12 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1439 // AIN13 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1440 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 1441 // AIN12 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1442 // AIN13 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1443 //
whismanoid 1:77f1ee332e4a 1444 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 1445 UNIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1446 BIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1447 RANGE &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1448 // UCH12/13=0, BCH12/13=0, RANGE12/13=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1449 #endif // AIN_12_13_SingleEnded
whismanoid 1:77f1ee332e4a 1450
whismanoid 1:77f1ee332e4a 1451 #if AIN_12_13_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1452
whismanoid 1:77f1ee332e4a 1453 //----------------------------------------
whismanoid 1:77f1ee332e4a 1454 // ADC Channels AIN12, AIN13 = Differential Unipolar (AIN12 > AIN13)
whismanoid 1:77f1ee332e4a 1455 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1456 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1457 // AIN12, AIN13 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1458 // AIN12 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1459 // AIN13 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1460 //
whismanoid 1:77f1ee332e4a 1461 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 1462 UNIPOLAR |= (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1463 BIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1464 RANGE &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1465 // UCH12/13=1, BCH12/13=0, RANGE12/13=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1466 #endif // AIN_12_13_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1467
whismanoid 1:77f1ee332e4a 1468 #if AIN_12_13_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1469
whismanoid 1:77f1ee332e4a 1470 //----------------------------------------
whismanoid 1:77f1ee332e4a 1471 // ADC Channels AIN12, AIN13 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1472 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1473 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 1474 // AIN12, AIN13 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 1475 // AIN12 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1476 // AIN13 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1477 //
whismanoid 1:77f1ee332e4a 1478 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1479 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 1480 UNIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1481 BIPOLAR |= (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1482 RANGE &= ~ (1 << AIN_12_13_LSB);
whismanoid 4:8a0ae95546fa 1483 // UCH12/13=0, BCH12/13=1, RANGE12/13=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1484 #endif // AIN_12_13_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1485
whismanoid 1:77f1ee332e4a 1486 #if AIN_12_13_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1487
whismanoid 1:77f1ee332e4a 1488 //----------------------------------------
whismanoid 1:77f1ee332e4a 1489 // ADC Channels AIN12, AIN13 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1490 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1491 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 1492 // AIN12, AIN13 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 1493 // AIN12 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1494 // AIN13 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1495 //
whismanoid 1:77f1ee332e4a 1496 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1497 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 1498 UNIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1499 BIPOLAR |= (1 << AIN_12_13_LSB);
whismanoid 1:77f1ee332e4a 1500 RANGE |= (1 << AIN_12_13_LSB);
whismanoid 4:8a0ae95546fa 1501 // UCH12/13=0, BCH12/13=1, RANGE12/13=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1502 #endif // AIN_12_13_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1503
whismanoid 1:77f1ee332e4a 1504 #if AIN_14_15_SingleEnded
whismanoid 1:77f1ee332e4a 1505
whismanoid 1:77f1ee332e4a 1506 //----------------------------------------
whismanoid 1:77f1ee332e4a 1507 // ADC Channels AIN14, AIN15 = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 1508 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1509 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1510 // AIN14 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1511 // AIN15 is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1512 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 1513 // AIN14 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1514 // AIN15 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1515 //
whismanoid 1:77f1ee332e4a 1516 // SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid 1:77f1ee332e4a 1517 UNIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1518 BIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1519 RANGE &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1520 // UCH14/15=0, BCH14/15=0, RANGE14/15=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1521 #endif // AIN_14_15_SingleEnded
whismanoid 1:77f1ee332e4a 1522
whismanoid 1:77f1ee332e4a 1523 #if AIN_14_15_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1524
whismanoid 1:77f1ee332e4a 1525 //----------------------------------------
whismanoid 1:77f1ee332e4a 1526 // ADC Channels AIN14, AIN15 = Differential Unipolar (AIN14 > AIN15)
whismanoid 1:77f1ee332e4a 1527 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1528 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1529 // AIN14, AIN15 are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1530 // AIN14 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1531 // AIN15 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1532 //
whismanoid 1:77f1ee332e4a 1533 // SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid 1:77f1ee332e4a 1534 UNIPOLAR |= (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1535 BIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1536 RANGE &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1537 // UCH14/15=1, BCH14/15=0, RANGE14/15=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1538 #endif // AIN_14_15_DifferentialUnipolar
whismanoid 1:77f1ee332e4a 1539
whismanoid 1:77f1ee332e4a 1540 #if AIN_14_15_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1541
whismanoid 1:77f1ee332e4a 1542 //----------------------------------------
whismanoid 1:77f1ee332e4a 1543 // ADC Channels AIN14, AIN15 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1544 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1545 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 1546 // AIN14, AIN15 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 1547 // AIN14 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1548 // AIN15 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1549 //
whismanoid 1:77f1ee332e4a 1550 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1551 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid 1:77f1ee332e4a 1552 UNIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1553 BIPOLAR |= (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1554 RANGE &= ~ (1 << AIN_14_15_LSB);
whismanoid 4:8a0ae95546fa 1555 // UCH14/15=0, BCH14/15=1, RANGE14/15=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1556 #endif // AIN_14_15_DifferentialBipolarFSVref
whismanoid 1:77f1ee332e4a 1557
whismanoid 1:77f1ee332e4a 1558 #if AIN_14_15_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1559
whismanoid 1:77f1ee332e4a 1560 //----------------------------------------
whismanoid 1:77f1ee332e4a 1561 // ADC Channels AIN14, AIN15 = Differential Bipolar
whismanoid 1:77f1ee332e4a 1562 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1563 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 1564 // AIN14, AIN15 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 1565 // AIN14 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1566 // AIN15 voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1567 //
whismanoid 1:77f1ee332e4a 1568 // SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid 1:77f1ee332e4a 1569 // SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid 1:77f1ee332e4a 1570 UNIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1571 BIPOLAR |= (1 << AIN_14_15_LSB);
whismanoid 1:77f1ee332e4a 1572 RANGE |= (1 << AIN_14_15_LSB);
whismanoid 4:8a0ae95546fa 1573 // UCH14/15=0, BCH14/15=1, RANGE14/15=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1574 #endif // AIN_14_15_DifferentialBipolarFS2Vref
whismanoid 1:77f1ee332e4a 1575
whismanoid 1:77f1ee332e4a 1576 //----------------------------------------
whismanoid 1:77f1ee332e4a 1577 // SPI write ADC CONFIGURATION register
whismanoid 1:77f1ee332e4a 1578 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 1579 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1580 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1581 SPIwrite16bits(ADC_CONFIGURATION);
whismanoid 1:77f1ee332e4a 1582 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1583
whismanoid 1:77f1ee332e4a 1584 //----------------------------------------
whismanoid 1:77f1ee332e4a 1585 // SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid 1:77f1ee332e4a 1586 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1587 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1588 SPIwrite16bits(UNIPOLAR);
whismanoid 1:77f1ee332e4a 1589 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1590 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1591 SPIwrite16bits(BIPOLAR);
whismanoid 1:77f1ee332e4a 1592 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1593 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1594 SPIwrite16bits(RANGE);
whismanoid 1:77f1ee332e4a 1595 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1596
whismanoid 1:77f1ee332e4a 1597 //----------------------------------------
whismanoid 1:77f1ee332e4a 1598 // SPI write CSCAN0 CSCAN1 registers
whismanoid 1:77f1ee332e4a 1599 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1600 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1601 SPIwrite16bits(CSCAN0);
whismanoid 1:77f1ee332e4a 1602 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1603 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1604 SPIwrite16bits(CSCAN1);
whismanoid 1:77f1ee332e4a 1605 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1606 }
whismanoid 1:77f1ee332e4a 1607
whismanoid 1:77f1ee332e4a 1608 //----------------------------------------
whismanoid 6:cb7bdeb185d0 1609 // Menu item 'IS'
whismanoid 1:77f1ee332e4a 1610 // ADC Channels AIN(channelId), AIN(channelId+1) = Both Single-Ended, Unipolar
whismanoid 1:77f1ee332e4a 1611 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1612 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1613 // AIN(channelId) is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1614 // AIN(channelId+1) is a Single-Ended input using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1615 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 1:77f1ee332e4a 1616 // AIN(channelId) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1617 // AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1618 //
whismanoid 6:cb7bdeb185d0 1619 void MAX11131::Reconfigure_SingleEnded(int channel_0_15)
whismanoid 1:77f1ee332e4a 1620 {
whismanoid 1:77f1ee332e4a 1621
whismanoid 1:77f1ee332e4a 1622 //----------------------------------------
whismanoid 1:77f1ee332e4a 1623 // UCH(ch)/(ch+1)=0, BCH(ch)/(ch+1)=0, RANGE(ch)/(ch+1)=0:
whismanoid 1:77f1ee332e4a 1624 // AIN(ch)/AIN(ch+1) two independent single-ended inputs,
whismanoid 1:77f1ee332e4a 1625 // unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1626 //
whismanoid 6:cb7bdeb185d0 1627 const int channelPairIndex = channel_0_15 / 2;
whismanoid 1:77f1ee332e4a 1628 const int bitmask = (1 << (10 - channelPairIndex));
whismanoid 1:77f1ee332e4a 1629 UNIPOLAR &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1630 BIPOLAR &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1631 RANGE &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1632
whismanoid 1:77f1ee332e4a 1633 //----------------------------------------
whismanoid 1:77f1ee332e4a 1634 // SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid 1:77f1ee332e4a 1635 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1636 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1637 SPIwrite16bits(UNIPOLAR);
whismanoid 1:77f1ee332e4a 1638 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1639 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1640 SPIwrite16bits(BIPOLAR);
whismanoid 1:77f1ee332e4a 1641 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1642 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1643 SPIwrite16bits(RANGE);
whismanoid 1:77f1ee332e4a 1644 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1645 }
whismanoid 1:77f1ee332e4a 1646
whismanoid 1:77f1ee332e4a 1647 //----------------------------------------
whismanoid 6:cb7bdeb185d0 1648 // Menu item 'IU'
whismanoid 1:77f1ee332e4a 1649 // ADC Channels AIN(channelId), AIN(channelId+1) = Differential Unipolar (AIN(channelId) > AIN(channelId+1))
whismanoid 1:77f1ee332e4a 1650 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1651 // Voltage per LSB count = VREF/4096
whismanoid 1:77f1ee332e4a 1652 // AIN(channelId), AIN(channelId+1) are a Differential pair using Unipolar transfer function.
whismanoid 1:77f1ee332e4a 1653 // AIN(channelId) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1654 // AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1655 //
whismanoid 6:cb7bdeb185d0 1656 void MAX11131::Reconfigure_DifferentialUnipolar(int channel_0_15)
whismanoid 1:77f1ee332e4a 1657 {
whismanoid 1:77f1ee332e4a 1658
whismanoid 1:77f1ee332e4a 1659 //----------------------------------------
whismanoid 1:77f1ee332e4a 1660 // UCH(ch)/(ch+1)=1, BCH(ch)/(ch+1)=0, RANGE(ch)/(ch+1)=0:
whismanoid 1:77f1ee332e4a 1661 // AIN(ch)/AIN(ch+1) differential input pair,
whismanoid 1:77f1ee332e4a 1662 // unipolar code (AIN(ch)>AIN(ch+1)) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1663 //
whismanoid 6:cb7bdeb185d0 1664 const int channelPairIndex = channel_0_15 / 2;
whismanoid 1:77f1ee332e4a 1665 const int bitmask = (1 << (10 - channelPairIndex));
whismanoid 1:77f1ee332e4a 1666 UNIPOLAR |= bitmask;
whismanoid 1:77f1ee332e4a 1667 BIPOLAR &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1668 RANGE &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1669 // UCH0/1=1, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1670
whismanoid 1:77f1ee332e4a 1671 //----------------------------------------
whismanoid 1:77f1ee332e4a 1672 // SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid 1:77f1ee332e4a 1673 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1674 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1675 SPIwrite16bits(UNIPOLAR);
whismanoid 1:77f1ee332e4a 1676 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1677 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1678 SPIwrite16bits(BIPOLAR);
whismanoid 1:77f1ee332e4a 1679 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1680 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1681 SPIwrite16bits(RANGE);
whismanoid 1:77f1ee332e4a 1682 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1683 }
whismanoid 1:77f1ee332e4a 1684
whismanoid 1:77f1ee332e4a 1685 //----------------------------------------
whismanoid 6:cb7bdeb185d0 1686 // Menu item 'IB'
whismanoid 1:77f1ee332e4a 1687 // ADC Channels AIN(channelId), AIN(channelId+1) = Differential Bipolar
whismanoid 1:77f1ee332e4a 1688 // Full Scale = VREF
whismanoid 1:77f1ee332e4a 1689 // Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 1690 // AIN(channelId), AIN(channelId+1) are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 1:77f1ee332e4a 1691 // AIN(channelId) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1692 // AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1693 //
whismanoid 6:cb7bdeb185d0 1694 void MAX11131::Reconfigure_DifferentialBipolarFSVref(int channel_0_15)
whismanoid 1:77f1ee332e4a 1695 {
whismanoid 1:77f1ee332e4a 1696
whismanoid 1:77f1ee332e4a 1697 //----------------------------------------
whismanoid 1:77f1ee332e4a 1698 // UCH(ch)/(ch+1)=0, BCH(ch)/(ch+1)=1, RANGE(ch)/(ch+1)=0:
whismanoid 4:8a0ae95546fa 1699 // AIN(ch)/AIN(ch+1) differential input pair (+/-)(1/2)Vref,
whismanoid 1:77f1ee332e4a 1700 // bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1701 //
whismanoid 6:cb7bdeb185d0 1702 const int channelPairIndex = channel_0_15 / 2;
whismanoid 1:77f1ee332e4a 1703 const int bitmask = (1 << (10 - channelPairIndex));
whismanoid 1:77f1ee332e4a 1704 UNIPOLAR &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1705 BIPOLAR |= bitmask;
whismanoid 1:77f1ee332e4a 1706 RANGE &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1707
whismanoid 1:77f1ee332e4a 1708 //----------------------------------------
whismanoid 1:77f1ee332e4a 1709 // SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid 1:77f1ee332e4a 1710 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1711 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1712 SPIwrite16bits(UNIPOLAR);
whismanoid 1:77f1ee332e4a 1713 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1714 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1715 SPIwrite16bits(BIPOLAR);
whismanoid 1:77f1ee332e4a 1716 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1717 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1718 SPIwrite16bits(RANGE);
whismanoid 1:77f1ee332e4a 1719 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1720 }
whismanoid 1:77f1ee332e4a 1721
whismanoid 1:77f1ee332e4a 1722 //----------------------------------------
whismanoid 6:cb7bdeb185d0 1723 // Menu item 'IR'
whismanoid 1:77f1ee332e4a 1724 // ADC Channels AIN(channelId), AIN(channelId+1) = Differential Bipolar
whismanoid 1:77f1ee332e4a 1725 // Full Scale = 2 * VREF
whismanoid 1:77f1ee332e4a 1726 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 1727 // AIN(channelId), AIN(channelId+1) are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 1:77f1ee332e4a 1728 // AIN(channelId) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1729 // AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid 1:77f1ee332e4a 1730 //
whismanoid 6:cb7bdeb185d0 1731 void MAX11131::Reconfigure_DifferentialBipolarFS2Vref(int channel_0_15)
whismanoid 1:77f1ee332e4a 1732 {
whismanoid 1:77f1ee332e4a 1733
whismanoid 1:77f1ee332e4a 1734 //----------------------------------------
whismanoid 1:77f1ee332e4a 1735 // UCH(ch)/(ch+1)=0, BCH(ch)/(ch+1)=1, RANGE(ch)/(ch+1)=1:
whismanoid 4:8a0ae95546fa 1736 // AIN(ch)/AIN(ch+1) differential input pair (+/-)Vref,
whismanoid 1:77f1ee332e4a 1737 // bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1738 //
whismanoid 6:cb7bdeb185d0 1739 const int channelPairIndex = channel_0_15 / 2;
whismanoid 1:77f1ee332e4a 1740 const int bitmask = (1 << (10 - channelPairIndex));
whismanoid 1:77f1ee332e4a 1741 UNIPOLAR &= ~ bitmask;
whismanoid 1:77f1ee332e4a 1742 BIPOLAR |= bitmask;
whismanoid 1:77f1ee332e4a 1743 RANGE |= bitmask;
whismanoid 4:8a0ae95546fa 1744 // UCH0/1=0, BCH0/1=1, RANGE0/1=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1745
whismanoid 1:77f1ee332e4a 1746 //----------------------------------------
whismanoid 1:77f1ee332e4a 1747 // SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid 1:77f1ee332e4a 1748 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1749 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1750 SPIwrite16bits(UNIPOLAR);
whismanoid 1:77f1ee332e4a 1751 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1752 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1753 SPIwrite16bits(BIPOLAR);
whismanoid 1:77f1ee332e4a 1754 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1755 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1756 SPIwrite16bits(RANGE);
whismanoid 1:77f1ee332e4a 1757 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1758 }
whismanoid 1:77f1ee332e4a 1759
whismanoid 1:77f1ee332e4a 1760 //----------------------------------------
whismanoid 1:77f1ee332e4a 1761 // SCAN_0000_NOP
whismanoid 1:77f1ee332e4a 1762 //
whismanoid 1:77f1ee332e4a 1763 // Shift 16 bits out of ADC, without changing configuration.
whismanoid 1:77f1ee332e4a 1764 // Note: @return data format depends on CHAN_ID bit:
whismanoid 1:77f1ee332e4a 1765 // "CH[3:0] DATA[11:0]" when CHAN_ID = 1, or
whismanoid 1:77f1ee332e4a 1766 // "0 DATA[11:0] x x x" when CHAN_ID = 0.
whismanoid 1:77f1ee332e4a 1767 int16_t MAX11131::ScanRead(void)
whismanoid 1:77f1ee332e4a 1768 {
whismanoid 1:77f1ee332e4a 1769
whismanoid 1:77f1ee332e4a 1770 //----------------------------------------
whismanoid 1:77f1ee332e4a 1771 // Read SPI data from device while MOSI (Maxim DIN) is 0. Effectively ADC_MODE_CONTROL SCAN[3:0] = SCAN_0000_NOP = 0
whismanoid 1:77f1ee332e4a 1772 SPI_MOSI_Semantic = 0; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 1773 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 1774 int16_t misoData16 = SPIread16bits();
whismanoid 1:77f1ee332e4a 1775 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 1776 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 1777 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 1778 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1779 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 1780 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1781 return misoData16;
whismanoid 1:77f1ee332e4a 1782 }
whismanoid 0:f7d706d2904d 1783
whismanoid 1:77f1ee332e4a 1784 //----------------------------------------
whismanoid 1:77f1ee332e4a 1785 // SCAN_0000_NOP
whismanoid 1:77f1ee332e4a 1786 //
whismanoid 1:77f1ee332e4a 1787 // Read raw ADC codes from device into AINcode[] and RAW_misoData16[].
whismanoid 1:77f1ee332e4a 1788 // If internal clock mode with SWCNV=0, measurements will be triggered using CNVST pin.
whismanoid 1:77f1ee332e4a 1789 //
whismanoid 1:77f1ee332e4a 1790 // @pre one of the Scan functions was called, setting NumWords
whismanoid 6:cb7bdeb185d0 1791 // @param[in] NumWords: number of words to be read from the FIFO
whismanoid 1:77f1ee332e4a 1792 // @post RAW_misoData16[index] contains the raw SPI Master-In,Slave-Out data
whismanoid 1:77f1ee332e4a 1793 // @post AINcode[NUM_CHANNELS] contains the latest readings in LSBs
whismanoid 1:77f1ee332e4a 1794 //
whismanoid 1:77f1ee332e4a 1795 void MAX11131::ReadAINcode(void)
whismanoid 1:77f1ee332e4a 1796 {
whismanoid 1:77f1ee332e4a 1797
whismanoid 1:77f1ee332e4a 1798 //----------------------------------------
whismanoid 1:77f1ee332e4a 1799 // loop index for RAW_misoData16[SAMPLESET_MAX_ENTRIES];
whismanoid 1:77f1ee332e4a 1800 int index;
whismanoid 1:77f1ee332e4a 1801
whismanoid 1:77f1ee332e4a 1802 //----------------------------------------
whismanoid 1:77f1ee332e4a 1803 // If internal clock mode with SWCNV=0, trigger measurement using CNVST pin and wait for EOC pin.
whismanoid 1:77f1ee332e4a 1804 if (isExternalClock == 0)
whismanoid 1:77f1ee332e4a 1805 {
whismanoid 1:77f1ee332e4a 1806 if (swcnv_0_1 == 0)
whismanoid 1:77f1ee332e4a 1807 {
whismanoid 1:77f1ee332e4a 1808 // SWCNV=0: trigger measurement by driving CNVST/AIN14 pin low
whismanoid 1:77f1ee332e4a 1809 // for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 1810 // One CNVST pulse scans all requested channels and stores the results in the FIFO.
whismanoid 1:77f1ee332e4a 1811 CNVSToutputPulseLow();
whismanoid 1:77f1ee332e4a 1812 }
whismanoid 1:77f1ee332e4a 1813 // wait for EOC low (internal clock mode end of conversion)
whismanoid 1:77f1ee332e4a 1814 EOCinputWaitUntilLow();
whismanoid 1:77f1ee332e4a 1815 }
whismanoid 1:77f1ee332e4a 1816
whismanoid 1:77f1ee332e4a 1817 //----------------------------------------
whismanoid 1:77f1ee332e4a 1818 // Read raw ADC codes from device into AINcode[] and RAW_misoData16[].
whismanoid 1:77f1ee332e4a 1819 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 1820 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 1821 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1822 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 1823 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1824 switch(ScanMode)
whismanoid 1:77f1ee332e4a 1825 {
whismanoid 1:77f1ee332e4a 1826 //----------------------------------------
whismanoid 1:77f1ee332e4a 1827 // read data words
whismanoid 1:77f1ee332e4a 1828 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 1829 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1830 case SCAN_0000_NOP:
whismanoid 1:77f1ee332e4a 1831 case SCAN_0011_StandardInternalClock:
whismanoid 1:77f1ee332e4a 1832 case SCAN_0101_UpperInternalClock:
whismanoid 1:77f1ee332e4a 1833 case SCAN_0111_CustomInternalClock:
whismanoid 1:77f1ee332e4a 1834 default:
whismanoid 1:77f1ee332e4a 1835 for (index = 0; index < NumWords; index++) {
whismanoid 1:77f1ee332e4a 1836 RAW_misoData16[index] = ScanRead();
whismanoid 1:77f1ee332e4a 1837 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 1838 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1839 int16_t value_u12 = (RAW_misoData16[index] & 0x0FFF);
whismanoid 1:77f1ee332e4a 1840 int channelId = ((RAW_misoData16[index] >> 12) & 0x000F);
whismanoid 1:77f1ee332e4a 1841 AINcode[channelId] = value_u12;
whismanoid 1:77f1ee332e4a 1842 }
whismanoid 1:77f1ee332e4a 1843 break;
whismanoid 1:77f1ee332e4a 1844 //----------------------------------------
whismanoid 1:77f1ee332e4a 1845 // read data words
whismanoid 1:77f1ee332e4a 1846 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 1847 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 1848 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1849 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 1850 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1851 case SCAN_0001_Manual:
whismanoid 1:77f1ee332e4a 1852 case SCAN_0100_StandardExternalClock:
whismanoid 1:77f1ee332e4a 1853 case SCAN_0110_UpperExternalClock:
whismanoid 1:77f1ee332e4a 1854 case SCAN_1000_CustomExternalClock:
whismanoid 1:77f1ee332e4a 1855 case SCAN_1001_SampleSetExternalClock:
whismanoid 1:77f1ee332e4a 1856 if (chan_id_0_1 != 0) {
whismanoid 1:77f1ee332e4a 1857 for (index = 0; index < NumWords; index++) {
whismanoid 1:77f1ee332e4a 1858 RAW_misoData16[index] = ScanRead();
whismanoid 1:77f1ee332e4a 1859 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 1860 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1861 int16_t value_u12 = (RAW_misoData16[index] & 0x0FFF);
whismanoid 1:77f1ee332e4a 1862 int channelId = ((RAW_misoData16[index] >> 12) & 0x000F);
whismanoid 1:77f1ee332e4a 1863 AINcode[channelId] = value_u12;
whismanoid 1:77f1ee332e4a 1864 }
whismanoid 1:77f1ee332e4a 1865 } else {
whismanoid 1:77f1ee332e4a 1866 for (index = 0; index < NumWords; index++) {
whismanoid 1:77f1ee332e4a 1867 RAW_misoData16[index] = ScanRead();
whismanoid 1:77f1ee332e4a 1868 int16_t value_u12 = ((RAW_misoData16[index] >> 3) & 0x0FFF);
whismanoid 1:77f1ee332e4a 1869 int channelId = channelNumber_0_15;
whismanoid 1:77f1ee332e4a 1870 AINcode[channelId] = value_u12;
whismanoid 1:77f1ee332e4a 1871 }
whismanoid 1:77f1ee332e4a 1872 }
whismanoid 1:77f1ee332e4a 1873 break;
whismanoid 1:77f1ee332e4a 1874 //----------------------------------------
whismanoid 1:77f1ee332e4a 1875 // read data words and calculate mean, stddev
whismanoid 1:77f1ee332e4a 1876 case SCAN_0010_Repeat:
whismanoid 1:77f1ee332e4a 1877 // ScanRead_nWords_chanID_mean(NumWords); // TODO1: missing function
whismanoid 1:77f1ee332e4a 1878 // was this function AINcode_print_value_chanID_mean(int nWords) in main?
whismanoid 1:77f1ee332e4a 1879 // But this function prints to standard output so can't be inside the driver.
whismanoid 1:77f1ee332e4a 1880 for (index = 0; index < NumWords; index++) {
whismanoid 1:77f1ee332e4a 1881 RAW_misoData16[index] = ScanRead();
whismanoid 1:77f1ee332e4a 1882 }
whismanoid 1:77f1ee332e4a 1883 break;
whismanoid 1:77f1ee332e4a 1884 }
whismanoid 1:77f1ee332e4a 1885 }
whismanoid 1:77f1ee332e4a 1886
whismanoid 1:77f1ee332e4a 1887 //----------------------------------------
whismanoid 1:77f1ee332e4a 1888 // Sign-Extend a right-aligned MAX11131 code into a signed 2's complement value.
whismanoid 1:77f1ee332e4a 1889 // Supports the bipolar transfer functions.
whismanoid 1:77f1ee332e4a 1890 // @param[in] value_u12: raw 12-bit MAX11131 code (right justified).
whismanoid 1:77f1ee332e4a 1891 // @return sign-extended 2's complement value.
whismanoid 1:77f1ee332e4a 1892 //
whismanoid 1:77f1ee332e4a 1893 int32_t MAX11131::TwosComplementValue(uint32_t regValue)
whismanoid 1:77f1ee332e4a 1894 {
whismanoid 1:77f1ee332e4a 1895 const uint16_t SIGN_BIT_12BIT = 0x0800;
whismanoid 1:77f1ee332e4a 1896 const uint16_t FULL_SCALE_CODE_12BIT = 0x0fff;
whismanoid 1:77f1ee332e4a 1897 if (((regValue & SIGN_BIT_12BIT) != 0) && !((regValue & (SIGN_BIT_12BIT << 1)) != 0))
whismanoid 1:77f1ee332e4a 1898 {
whismanoid 1:77f1ee332e4a 1899 // (bSignBitNegative && !bExtendedSignBitNegative)
whismanoid 1:77f1ee332e4a 1900 // Twos_Complement negative value
whismanoid 1:77f1ee332e4a 1901 int32_t Offset_regValue = (int32_t)(regValue - (FULL_SCALE_CODE_12BIT + 1));
whismanoid 1:77f1ee332e4a 1902 return Offset_regValue;
whismanoid 1:77f1ee332e4a 1903 }
whismanoid 1:77f1ee332e4a 1904 // Twos_Complement positive value or zero
whismanoid 1:77f1ee332e4a 1905 return (int32_t)regValue;
whismanoid 1:77f1ee332e4a 1906 }
whismanoid 1:77f1ee332e4a 1907
whismanoid 1:77f1ee332e4a 1908 //----------------------------------------
whismanoid 1:77f1ee332e4a 1909 // Return the physical voltage corresponding to MAX11131 code.
whismanoid 1:77f1ee332e4a 1910 // Does not perform any offset or gain correction.
whismanoid 1:77f1ee332e4a 1911 // @pre VRef = Voltage of REF input, in Volts
whismanoid 1:77f1ee332e4a 1912 // @param[in] value_u12: raw 12-bit MAX11131 code (right justified).
whismanoid 1:77f1ee332e4a 1913 // @param[in] channelId: AIN channel number.
whismanoid 1:77f1ee332e4a 1914 // @return physical voltage corresponding to MAX11131 code.
whismanoid 1:77f1ee332e4a 1915 //
whismanoid 1:77f1ee332e4a 1916 double MAX11131::VoltageOfCode(int16_t value_u12, int channelId)
whismanoid 1:77f1ee332e4a 1917 {
whismanoid 1:77f1ee332e4a 1918 int channelPairIndex = channelId / 2;
whismanoid 1:77f1ee332e4a 1919 // format: 1 0 0 0 1 UCH0/1 UCH2/3 UCH4/5 UCH6/7 UCH8/9 UCH10/11 UCH12/13 UCH14/15 PDIFF_COM x x
whismanoid 1:77f1ee332e4a 1920 int UCHn = (UNIPOLAR >> (10 - channelPairIndex)) & 0x01;
whismanoid 1:77f1ee332e4a 1921 int BCHn = (BIPOLAR >> (10 - channelPairIndex)) & 0x01;
whismanoid 1:77f1ee332e4a 1922 int RANGEn = (RANGE >> (10 - channelPairIndex)) & 0x01;
whismanoid 1:77f1ee332e4a 1923 if (UCHn)
whismanoid 1:77f1ee332e4a 1924 {
whismanoid 1:77f1ee332e4a 1925 // UCH0/1=1, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1926 return (value_u12 * VRef / 4096);
whismanoid 1:77f1ee332e4a 1927 }
whismanoid 1:77f1ee332e4a 1928 else
whismanoid 1:77f1ee332e4a 1929 {
whismanoid 1:77f1ee332e4a 1930 if (BCHn)
whismanoid 1:77f1ee332e4a 1931 {
whismanoid 1:77f1ee332e4a 1932 if (RANGEn)
whismanoid 1:77f1ee332e4a 1933 {
whismanoid 4:8a0ae95546fa 1934 // UCH0/1=0, BCH0/1=1, RANGE0/1=1: AIN0/AIN1 differential input pair (+/-)Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid 1:77f1ee332e4a 1935 return (TwosComplementValue(value_u12) * VRef / 2048);
whismanoid 1:77f1ee332e4a 1936 }
whismanoid 1:77f1ee332e4a 1937 else
whismanoid 1:77f1ee332e4a 1938 {
whismanoid 4:8a0ae95546fa 1939 // UCH0/1=0, BCH0/1=1, RANGE0/1=0: AIN0/AIN1 differential input pair (+/-)(1/2)Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1940 return (TwosComplementValue(value_u12) * VRef / 4096);
whismanoid 1:77f1ee332e4a 1941 }
whismanoid 1:77f1ee332e4a 1942 }
whismanoid 1:77f1ee332e4a 1943 else
whismanoid 1:77f1ee332e4a 1944 {
whismanoid 1:77f1ee332e4a 1945 // UCH0/1=0, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid 1:77f1ee332e4a 1946 return (value_u12 * VRef / 4096);
whismanoid 1:77f1ee332e4a 1947 }
whismanoid 1:77f1ee332e4a 1948 }
whismanoid 1:77f1ee332e4a 1949 }
whismanoid 1:77f1ee332e4a 1950
whismanoid 1:77f1ee332e4a 1951 //----------------------------------------
whismanoid 1:77f1ee332e4a 1952 // SCAN_0001_Manual
whismanoid 1:77f1ee332e4a 1953 //
whismanoid 1:77f1ee332e4a 1954 // Measure ADC channel channelNumber_0_15 once.
whismanoid 1:77f1ee332e4a 1955 // External clock mode.
whismanoid 1:77f1ee332e4a 1956 // @param[in] channelNumber_0_15: AIN Channel Number
whismanoid 1:77f1ee332e4a 1957 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 1958 // @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 1959 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 6:cb7bdeb185d0 1960 // @post NumWords = number of words to be read from the FIFO
whismanoid 1:77f1ee332e4a 1961 // For external clock modes, the data format depends on CHAN_ID.
whismanoid 1:77f1ee332e4a 1962 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 1963 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 1964 //
whismanoid 1:77f1ee332e4a 1965 int MAX11131::ScanManual(void)
whismanoid 1:77f1ee332e4a 1966 {
whismanoid 1:77f1ee332e4a 1967
whismanoid 1:77f1ee332e4a 1968 //----------------------------------------
whismanoid 2:50a0cf017492 1969 // define write-only register ADC_MODE_CONTROL
whismanoid 2:50a0cf017492 1970 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 2:50a0cf017492 1971 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 2:50a0cf017492 1972 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 2:50a0cf017492 1973 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 1974 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 2:50a0cf017492 1975 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 2:50a0cf017492 1976 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 2:50a0cf017492 1977
whismanoid 2:50a0cf017492 1978 //----------------------------------------
whismanoid 2:50a0cf017492 1979 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 1980 int needFIFOreset = (isExternalClock != 1);
whismanoid 2:50a0cf017492 1981 if (needFIFOreset) {
whismanoid 2:50a0cf017492 1982 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 1983 ADC_MODE_CONTROL = ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 1984 // Send SPI configuration to device
whismanoid 2:50a0cf017492 1985 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 2:50a0cf017492 1986 SPIoutputCS(0); // drive CS low
whismanoid 2:50a0cf017492 1987 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 2:50a0cf017492 1988 SPIoutputCS(1); // drive CS high
whismanoid 2:50a0cf017492 1989 ADC_MODE_CONTROL = 0;
whismanoid 2:50a0cf017492 1990 }
whismanoid 2:50a0cf017492 1991
whismanoid 2:50a0cf017492 1992 //----------------------------------------
whismanoid 1:77f1ee332e4a 1993 // number of words to read
whismanoid 1:77f1ee332e4a 1994 NumWords = 1;
whismanoid 1:77f1ee332e4a 1995
whismanoid 1:77f1ee332e4a 1996 //----------------------------------------
whismanoid 1:77f1ee332e4a 1997 // External Clock Mode
whismanoid 1:77f1ee332e4a 1998 isExternalClock = 1;
whismanoid 1:77f1ee332e4a 1999
whismanoid 1:77f1ee332e4a 2000 //----------------------------------------
whismanoid 1:77f1ee332e4a 2001 // update device driver global variable
whismanoid 1:77f1ee332e4a 2002 ScanMode = SCAN_0001_Manual;
whismanoid 1:77f1ee332e4a 2003
whismanoid 1:77f1ee332e4a 2004 //----------------------------------------
whismanoid 1:77f1ee332e4a 2005 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0001_Manual = 1
whismanoid 1:77f1ee332e4a 2006 //~ const int SCAN_0001_Manual = 1; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2007 ADC_MODE_CONTROL |= ((SCAN_0001_Manual & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2008
whismanoid 1:77f1ee332e4a 2009 //----------------------------------------
whismanoid 1:77f1ee332e4a 2010 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 2011 ADC_MODE_CONTROL |= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 2012
whismanoid 1:77f1ee332e4a 2013 //----------------------------------------
whismanoid 1:77f1ee332e4a 2014 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2015 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2016
whismanoid 1:77f1ee332e4a 2017 //----------------------------------------
whismanoid 1:77f1ee332e4a 2018 // ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid 1:77f1ee332e4a 2019 // (applicable to external clock mode only)
whismanoid 1:77f1ee332e4a 2020 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 2021 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2022 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2023 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2024 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2025 ADC_MODE_CONTROL |= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid 1:77f1ee332e4a 2026
whismanoid 1:77f1ee332e4a 2027 //----------------------------------------
whismanoid 1:77f1ee332e4a 2028 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2029 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2030 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2031 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2032 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2033 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2034
whismanoid 1:77f1ee332e4a 2035 //----------------------------------------
whismanoid 1:77f1ee332e4a 2036 // return number of words to read
whismanoid 1:77f1ee332e4a 2037 return NumWords;
whismanoid 1:77f1ee332e4a 2038 }
whismanoid 1:77f1ee332e4a 2039
whismanoid 1:77f1ee332e4a 2040 //----------------------------------------
whismanoid 1:77f1ee332e4a 2041 // SCAN_0010_Repeat
whismanoid 1:77f1ee332e4a 2042 //
whismanoid 1:77f1ee332e4a 2043 // Measure ADC channel channelNumber_0_15 repeatedly with averaging.
whismanoid 1:77f1ee332e4a 2044 // Internal clock mode.
whismanoid 1:77f1ee332e4a 2045 // @param[in] channelNumber_0_15: AIN Channel Number
whismanoid 1:77f1ee332e4a 2046 // @param[in] average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid 1:77f1ee332e4a 2047 // average_0_4_8_16_32=0 to disable averaging.
whismanoid 1:77f1ee332e4a 2048 // @param[in] nscan_4_8_12_16: Number of ScanRead() words to report.
whismanoid 1:77f1ee332e4a 2049 // @param[in] swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2050 // SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid 1:77f1ee332e4a 2051 // Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 2052 // SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid 1:77f1ee332e4a 2053 // CS must be held low for minimum of 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2054 // CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 2055 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 2056 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 6:cb7bdeb185d0 2057 // @post NumWords = number of words to be read from the FIFO
whismanoid 1:77f1ee332e4a 2058 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2059 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2060 //
whismanoid 1:77f1ee332e4a 2061 int MAX11131::ScanRepeat(void)
whismanoid 1:77f1ee332e4a 2062 {
whismanoid 1:77f1ee332e4a 2063
whismanoid 1:77f1ee332e4a 2064 //----------------------------------------
whismanoid 1:77f1ee332e4a 2065 // number of words to read
whismanoid 1:77f1ee332e4a 2066 NumWords = (nscan_4_8_12_16);
whismanoid 1:77f1ee332e4a 2067
whismanoid 1:77f1ee332e4a 2068 //----------------------------------------
whismanoid 1:77f1ee332e4a 2069 // Internal Clock Mode
whismanoid 1:77f1ee332e4a 2070 isExternalClock = 0;
whismanoid 1:77f1ee332e4a 2071
whismanoid 1:77f1ee332e4a 2072 //----------------------------------------
whismanoid 1:77f1ee332e4a 2073 // update device driver global variable
whismanoid 1:77f1ee332e4a 2074 ScanMode = SCAN_0010_Repeat;
whismanoid 1:77f1ee332e4a 2075
whismanoid 1:77f1ee332e4a 2076 //----------------------------------------
whismanoid 1:77f1ee332e4a 2077 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 2078 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 2079 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 2080 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 2081 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2082 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 2083 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2084 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2085
whismanoid 1:77f1ee332e4a 2086 //----------------------------------------
whismanoid 1:77f1ee332e4a 2087 // define write-only register ADC_CONFIGURATION
whismanoid 1:77f1ee332e4a 2088 ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid 1:77f1ee332e4a 2089 const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid 1:77f1ee332e4a 2090 const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid 1:77f1ee332e4a 2091 const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid 1:77f1ee332e4a 2092 const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid 1:77f1ee332e4a 2093 const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid 1:77f1ee332e4a 2094 const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid 1:77f1ee332e4a 2095
whismanoid 1:77f1ee332e4a 2096 //----------------------------------------
whismanoid 1:77f1ee332e4a 2097 // if average, ADC CONFIGURATION register set AVG and NAVG[1:0]
whismanoid 1:77f1ee332e4a 2098 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 2099 // if average, ADC CONFIGURATION register set AVG ON BIT TO 1
whismanoid 1:77f1ee332e4a 2100 // if average, ADC CONFIGURATION register set NAVG[1:0] TO N
whismanoid 1:77f1ee332e4a 2101 if (average_0_4_8_16_32 == 4) {
whismanoid 1:77f1ee332e4a 2102 // Enable Averaging of 4 samples (AVGON=1, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 2103 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2104 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2105 ADC_CONFIGURATION |= ((0 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2106 } else if (average_0_4_8_16_32 == 8) {
whismanoid 1:77f1ee332e4a 2107 // Enable Averaging of 8 samples (AVGON=1, NAVG[1:0]=1)
whismanoid 1:77f1ee332e4a 2108 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2109 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2110 ADC_CONFIGURATION |= ((1 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2111 } else if (average_0_4_8_16_32 == 16) {
whismanoid 1:77f1ee332e4a 2112 // Enable Averaging of 16 samples (AVGON=1, NAVG[1:0]=2)
whismanoid 1:77f1ee332e4a 2113 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2114 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2115 ADC_CONFIGURATION |= ((2 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2116 } else if (average_0_4_8_16_32 == 32) {
whismanoid 1:77f1ee332e4a 2117 // Enable Averaging of 32 samples (AVGON=1, NAVG[1:0]=3)
whismanoid 1:77f1ee332e4a 2118 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2119 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2120 ADC_CONFIGURATION |= ((3 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2121 } else {
whismanoid 1:77f1ee332e4a 2122 // Disable Averaging (AVGON=0, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 2123 ADC_CONFIGURATION &= ~ (( AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2124 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2125 }
whismanoid 1:77f1ee332e4a 2126
whismanoid 1:77f1ee332e4a 2127 //----------------------------------------
whismanoid 1:77f1ee332e4a 2128 // ADC CONFIGURATION register set NSCAN[1:0] for scan count
whismanoid 1:77f1ee332e4a 2129 // (applicable to SCAN_0010_Repeat only)
whismanoid 1:77f1ee332e4a 2130 if (nscan_4_8_12_16 == 4) {
whismanoid 1:77f1ee332e4a 2131 // Set scan count 4
whismanoid 1:77f1ee332e4a 2132 ADC_CONFIGURATION &= ~ (( NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 2133 ADC_CONFIGURATION |= ((0 & NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 2134 } else if (nscan_4_8_12_16 == 8) {
whismanoid 1:77f1ee332e4a 2135 // Set scan count 8
whismanoid 1:77f1ee332e4a 2136 ADC_CONFIGURATION &= ~ (( NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 2137 ADC_CONFIGURATION |= ((1 & NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 2138 } else if (nscan_4_8_12_16 == 12) {
whismanoid 1:77f1ee332e4a 2139 // Set scan count 12
whismanoid 1:77f1ee332e4a 2140 ADC_CONFIGURATION &= ~ (( NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 2141 ADC_CONFIGURATION |= ((2 & NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 2142 } else if (nscan_4_8_12_16 == 16) {
whismanoid 1:77f1ee332e4a 2143 // Set scan count 16
whismanoid 1:77f1ee332e4a 2144 ADC_CONFIGURATION &= ~ (( NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 2145 ADC_CONFIGURATION |= ((3 & NSCAN_BITS) << NSCAN_LSB);
whismanoid 1:77f1ee332e4a 2146 }
whismanoid 1:77f1ee332e4a 2147
whismanoid 1:77f1ee332e4a 2148 //----------------------------------------
whismanoid 1:77f1ee332e4a 2149 // SPI write ADC CONFIGURATION register
whismanoid 1:77f1ee332e4a 2150 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2151 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2152 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2153 SPIwrite16bits(ADC_CONFIGURATION);
whismanoid 1:77f1ee332e4a 2154 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2155
whismanoid 1:77f1ee332e4a 2156 //----------------------------------------
whismanoid 1:77f1ee332e4a 2157 // Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid 1:77f1ee332e4a 2158 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2159 ADC_MODE_CONTROL |= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2160
whismanoid 1:77f1ee332e4a 2161 //----------------------------------------
whismanoid 1:77f1ee332e4a 2162 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0010_Repeat = 2
whismanoid 1:77f1ee332e4a 2163 //~ const int SCAN_0010_Repeat = 2; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2164 ADC_MODE_CONTROL |= ((SCAN_0010_Repeat & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2165
whismanoid 1:77f1ee332e4a 2166 //----------------------------------------
whismanoid 1:77f1ee332e4a 2167 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 2168 ADC_MODE_CONTROL |= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 2169
whismanoid 1:77f1ee332e4a 2170 //----------------------------------------
whismanoid 1:77f1ee332e4a 2171 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2172 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2173
whismanoid 1:77f1ee332e4a 2174 //----------------------------------------
whismanoid 1:77f1ee332e4a 2175 // ADC MODE CONTROL register set SWCNV if CNVST pin is not used
whismanoid 1:77f1ee332e4a 2176 // ADC MODE CONTROL REGISTER SELECT THE RIGHT SWCNV BIT
whismanoid 1:77f1ee332e4a 2177 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 2178 // SWCNV=1: trigger measurement on SPI CS rising edge; CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 2179 // SWCNV=0: trigger measurement by driving CNVST pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 2180 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 2181 ADC_MODE_CONTROL |= ((swcnv_0_1 & SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 2182 } else {
whismanoid 1:77f1ee332e4a 2183 ADC_MODE_CONTROL &= ~ (( SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 2184 }
whismanoid 1:77f1ee332e4a 2185
whismanoid 1:77f1ee332e4a 2186 //----------------------------------------
whismanoid 1:77f1ee332e4a 2187 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2188 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2189 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2190 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2191 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2192 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 2193 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2194 // NOTE: Figure 7 Internal Conversions with SWCNV=1 has an error, the 17th SCLK is mislabeled as "16" should be "17".
whismanoid 1:77f1ee332e4a 2195 SPIwrite24bits(ADC_MODE_CONTROL, 0);
whismanoid 1:77f1ee332e4a 2196 } else {
whismanoid 1:77f1ee332e4a 2197 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2198 }
whismanoid 1:77f1ee332e4a 2199 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2200
whismanoid 1:77f1ee332e4a 2201 //----------------------------------------
whismanoid 1:77f1ee332e4a 2202 // return number of words to read
whismanoid 1:77f1ee332e4a 2203 return NumWords;
whismanoid 1:77f1ee332e4a 2204 }
whismanoid 1:77f1ee332e4a 2205
whismanoid 1:77f1ee332e4a 2206 //----------------------------------------
whismanoid 1:77f1ee332e4a 2207 // SCAN_0011_StandardInternalClock
whismanoid 1:77f1ee332e4a 2208 //
whismanoid 1:77f1ee332e4a 2209 // Measure ADC channels in sequence from AIN0 to channelNumber_0_15.
whismanoid 1:77f1ee332e4a 2210 // Internal clock mode.
whismanoid 1:77f1ee332e4a 2211 // @param[in] channelNumber_0_15: AIN Channel Number
whismanoid 1:77f1ee332e4a 2212 // @param[in] average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid 1:77f1ee332e4a 2213 // average_0_4_8_16_32=0 to disable averaging.
whismanoid 1:77f1ee332e4a 2214 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 2215 // @param[in] swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2216 // SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid 1:77f1ee332e4a 2217 // Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 2218 // SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid 1:77f1ee332e4a 2219 // CS must be held low for minimum of 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2220 // CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 2221 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 6:cb7bdeb185d0 2222 // @post NumWords = number of words to be read from the FIFO
whismanoid 1:77f1ee332e4a 2223 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2224 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2225 //
whismanoid 1:77f1ee332e4a 2226 int MAX11131::ScanStandardInternalClock(void)
whismanoid 1:77f1ee332e4a 2227 {
whismanoid 1:77f1ee332e4a 2228
whismanoid 1:77f1ee332e4a 2229 //----------------------------------------
whismanoid 1:77f1ee332e4a 2230 // number of words to read
whismanoid 1:77f1ee332e4a 2231 NumWords = (1 + channelNumber_0_15);
whismanoid 1:77f1ee332e4a 2232
whismanoid 1:77f1ee332e4a 2233 //----------------------------------------
whismanoid 1:77f1ee332e4a 2234 // Internal Clock Mode
whismanoid 1:77f1ee332e4a 2235 isExternalClock = 0;
whismanoid 1:77f1ee332e4a 2236
whismanoid 1:77f1ee332e4a 2237 //----------------------------------------
whismanoid 1:77f1ee332e4a 2238 // update device driver global variable
whismanoid 1:77f1ee332e4a 2239 ScanMode = SCAN_0011_StandardInternalClock;
whismanoid 1:77f1ee332e4a 2240
whismanoid 1:77f1ee332e4a 2241 //----------------------------------------
whismanoid 1:77f1ee332e4a 2242 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 2243 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 2244 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 2245 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 2246 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2247 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 2248 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2249 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2250
whismanoid 1:77f1ee332e4a 2251 //----------------------------------------
whismanoid 1:77f1ee332e4a 2252 // define write-only register ADC_CONFIGURATION
whismanoid 1:77f1ee332e4a 2253 ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid 1:77f1ee332e4a 2254 const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid 1:77f1ee332e4a 2255 const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid 1:77f1ee332e4a 2256 const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid 1:77f1ee332e4a 2257 const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid 1:77f1ee332e4a 2258 const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid 1:77f1ee332e4a 2259 const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid 1:77f1ee332e4a 2260
whismanoid 1:77f1ee332e4a 2261 //----------------------------------------
whismanoid 1:77f1ee332e4a 2262 // if average, ADC CONFIGURATION register set AVG and NAVG[1:0]
whismanoid 1:77f1ee332e4a 2263 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 2264 // if average, ADC CONFIGURATION register set AVG ON BIT TO 1
whismanoid 1:77f1ee332e4a 2265 // if average, ADC CONFIGURATION register set NAVG[1:0] TO N
whismanoid 1:77f1ee332e4a 2266 if (average_0_4_8_16_32 == 4) {
whismanoid 1:77f1ee332e4a 2267 // Enable Averaging of 4 samples (AVGON=1, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 2268 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2269 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2270 ADC_CONFIGURATION |= ((0 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2271 } else if (average_0_4_8_16_32 == 8) {
whismanoid 1:77f1ee332e4a 2272 // Enable Averaging of 8 samples (AVGON=1, NAVG[1:0]=1)
whismanoid 1:77f1ee332e4a 2273 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2274 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2275 ADC_CONFIGURATION |= ((1 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2276 } else if (average_0_4_8_16_32 == 16) {
whismanoid 1:77f1ee332e4a 2277 // Enable Averaging of 16 samples (AVGON=1, NAVG[1:0]=2)
whismanoid 1:77f1ee332e4a 2278 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2279 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2280 ADC_CONFIGURATION |= ((2 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2281 } else if (average_0_4_8_16_32 == 32) {
whismanoid 1:77f1ee332e4a 2282 // Enable Averaging of 32 samples (AVGON=1, NAVG[1:0]=3)
whismanoid 1:77f1ee332e4a 2283 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2284 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2285 ADC_CONFIGURATION |= ((3 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2286 } else {
whismanoid 1:77f1ee332e4a 2287 // Disable Averaging (AVGON=0, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 2288 ADC_CONFIGURATION &= ~ (( AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2289 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2290 }
whismanoid 1:77f1ee332e4a 2291
whismanoid 1:77f1ee332e4a 2292 //----------------------------------------
whismanoid 1:77f1ee332e4a 2293 // SPI write ADC CONFIGURATION register
whismanoid 1:77f1ee332e4a 2294 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2295 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2296 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2297 SPIwrite16bits(ADC_CONFIGURATION);
whismanoid 1:77f1ee332e4a 2298 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2299
whismanoid 1:77f1ee332e4a 2300 //----------------------------------------
whismanoid 1:77f1ee332e4a 2301 // Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid 1:77f1ee332e4a 2302 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2303 ADC_MODE_CONTROL |= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2304
whismanoid 1:77f1ee332e4a 2305 //----------------------------------------
whismanoid 1:77f1ee332e4a 2306 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0011_StandardInternalClock = 3
whismanoid 1:77f1ee332e4a 2307 //~ const int SCAN_0011_StandardInternalClock = 3; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2308 ADC_MODE_CONTROL |= ((SCAN_0011_StandardInternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2309
whismanoid 1:77f1ee332e4a 2310 //----------------------------------------
whismanoid 1:77f1ee332e4a 2311 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 2312 ADC_MODE_CONTROL |= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 2313
whismanoid 1:77f1ee332e4a 2314 //----------------------------------------
whismanoid 1:77f1ee332e4a 2315 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2316 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2317
whismanoid 1:77f1ee332e4a 2318 //----------------------------------------
whismanoid 1:77f1ee332e4a 2319 // ADC MODE CONTROL register set SWCNV if CNVST pin is not used
whismanoid 1:77f1ee332e4a 2320 // ADC MODE CONTROL REGISTER SELECT THE RIGHT SWCNV BIT
whismanoid 1:77f1ee332e4a 2321 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 2322 // SWCNV=1: trigger measurement on SPI CS rising edge; CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 2323 // SWCNV=0: trigger measurement by driving CNVST pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 2324 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 2325 ADC_MODE_CONTROL |= ((swcnv_0_1 & SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 2326 } else {
whismanoid 1:77f1ee332e4a 2327 ADC_MODE_CONTROL &= ~ (( SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 2328 }
whismanoid 1:77f1ee332e4a 2329
whismanoid 1:77f1ee332e4a 2330 //----------------------------------------
whismanoid 1:77f1ee332e4a 2331 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2332 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2333 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2334 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2335 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2336 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 2337 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2338 // NOTE: Figure 7 Internal Conversions with SWCNV=1 has an error, the 17th SCLK is mislabeled as "16" should be "17".
whismanoid 1:77f1ee332e4a 2339 SPIwrite24bits(ADC_MODE_CONTROL, 0);
whismanoid 1:77f1ee332e4a 2340 } else {
whismanoid 1:77f1ee332e4a 2341 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2342 }
whismanoid 1:77f1ee332e4a 2343 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2344
whismanoid 1:77f1ee332e4a 2345 //----------------------------------------
whismanoid 1:77f1ee332e4a 2346 // return number of words to read
whismanoid 1:77f1ee332e4a 2347 return NumWords;
whismanoid 1:77f1ee332e4a 2348 }
whismanoid 1:77f1ee332e4a 2349
whismanoid 1:77f1ee332e4a 2350 //----------------------------------------
whismanoid 1:77f1ee332e4a 2351 // SCAN_0100_StandardExternalClock
whismanoid 1:77f1ee332e4a 2352 //
whismanoid 1:77f1ee332e4a 2353 // Measure ADC channels in sequence from AIN0 to channelNumber_0_15.
whismanoid 1:77f1ee332e4a 2354 // External clock mode.
whismanoid 1:77f1ee332e4a 2355 // @param[in] channelNumber_0_15: AIN Channel Number
whismanoid 1:77f1ee332e4a 2356 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 2357 // @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2358 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 6:cb7bdeb185d0 2359 // @post NumWords = number of words to be read from the FIFO
whismanoid 1:77f1ee332e4a 2360 // For external clock modes, the data format depends on CHAN_ID.
whismanoid 1:77f1ee332e4a 2361 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2362 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2363 //
whismanoid 1:77f1ee332e4a 2364 int MAX11131::ScanStandardExternalClock(void)
whismanoid 1:77f1ee332e4a 2365 {
whismanoid 1:77f1ee332e4a 2366
whismanoid 1:77f1ee332e4a 2367 //----------------------------------------
whismanoid 2:50a0cf017492 2368 // define write-only register ADC_MODE_CONTROL
whismanoid 2:50a0cf017492 2369 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 2:50a0cf017492 2370 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 2:50a0cf017492 2371 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 2:50a0cf017492 2372 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 2373 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 2:50a0cf017492 2374 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 2:50a0cf017492 2375 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 2:50a0cf017492 2376
whismanoid 2:50a0cf017492 2377 //----------------------------------------
whismanoid 2:50a0cf017492 2378 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 2379 int needFIFOreset = (isExternalClock != 1);
whismanoid 2:50a0cf017492 2380 if (needFIFOreset) {
whismanoid 2:50a0cf017492 2381 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 2382 ADC_MODE_CONTROL = ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 2383 // Send SPI configuration to device
whismanoid 2:50a0cf017492 2384 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 2:50a0cf017492 2385 SPIoutputCS(0); // drive CS low
whismanoid 2:50a0cf017492 2386 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 2:50a0cf017492 2387 SPIoutputCS(1); // drive CS high
whismanoid 2:50a0cf017492 2388 ADC_MODE_CONTROL = 0;
whismanoid 2:50a0cf017492 2389 }
whismanoid 2:50a0cf017492 2390
whismanoid 2:50a0cf017492 2391 //----------------------------------------
whismanoid 1:77f1ee332e4a 2392 // number of words to read
whismanoid 1:77f1ee332e4a 2393 NumWords = (1 + channelNumber_0_15);
whismanoid 1:77f1ee332e4a 2394
whismanoid 1:77f1ee332e4a 2395 //----------------------------------------
whismanoid 1:77f1ee332e4a 2396 // External Clock Mode
whismanoid 1:77f1ee332e4a 2397 isExternalClock = 1;
whismanoid 1:77f1ee332e4a 2398
whismanoid 1:77f1ee332e4a 2399 //----------------------------------------
whismanoid 1:77f1ee332e4a 2400 // update device driver global variable
whismanoid 1:77f1ee332e4a 2401 ScanMode = SCAN_0100_StandardExternalClock;
whismanoid 1:77f1ee332e4a 2402
whismanoid 1:77f1ee332e4a 2403 //----------------------------------------
whismanoid 1:77f1ee332e4a 2404 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0100_StandardExternalClock = 4
whismanoid 1:77f1ee332e4a 2405 //~ const int SCAN_0100_StandardExternalClock = 4; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2406 ADC_MODE_CONTROL |= ((SCAN_0100_StandardExternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2407
whismanoid 1:77f1ee332e4a 2408 //----------------------------------------
whismanoid 1:77f1ee332e4a 2409 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 2410 ADC_MODE_CONTROL |= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 2411
whismanoid 1:77f1ee332e4a 2412 //----------------------------------------
whismanoid 1:77f1ee332e4a 2413 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2414 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2415
whismanoid 1:77f1ee332e4a 2416 //----------------------------------------
whismanoid 1:77f1ee332e4a 2417 // ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid 1:77f1ee332e4a 2418 // (applicable to external clock mode only)
whismanoid 1:77f1ee332e4a 2419 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 2420 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2421 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2422 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2423 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2424 ADC_MODE_CONTROL |= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid 1:77f1ee332e4a 2425
whismanoid 1:77f1ee332e4a 2426 //----------------------------------------
whismanoid 1:77f1ee332e4a 2427 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2428 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2429 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2430 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2431 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2432 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2433
whismanoid 1:77f1ee332e4a 2434 //----------------------------------------
whismanoid 1:77f1ee332e4a 2435 // return number of words to read
whismanoid 1:77f1ee332e4a 2436 return NumWords;
whismanoid 1:77f1ee332e4a 2437 }
whismanoid 1:77f1ee332e4a 2438
whismanoid 1:77f1ee332e4a 2439 //----------------------------------------
whismanoid 1:77f1ee332e4a 2440 // SCAN_0101_UpperInternalClock
whismanoid 1:77f1ee332e4a 2441 //
whismanoid 1:77f1ee332e4a 2442 // Measure ADC channels in sequence from channelNumber_0_15 to AIN15.
whismanoid 1:77f1ee332e4a 2443 // Internal clock mode.
whismanoid 1:77f1ee332e4a 2444 // @param[in] channelNumber_0_15: AIN Channel Number
whismanoid 1:77f1ee332e4a 2445 // @param[in] average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid 1:77f1ee332e4a 2446 // average_0_4_8_16_32=0 to disable averaging.
whismanoid 1:77f1ee332e4a 2447 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 2448 // @param[in] swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2449 // SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid 1:77f1ee332e4a 2450 // Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 2451 // SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid 1:77f1ee332e4a 2452 // CS must be held low for minimum of 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2453 // CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 2454 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 6:cb7bdeb185d0 2455 // @post NumWords = number of words to be read from the FIFO
whismanoid 1:77f1ee332e4a 2456 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2457 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2458 //
whismanoid 1:77f1ee332e4a 2459 int MAX11131::ScanUpperInternalClock(void)
whismanoid 1:77f1ee332e4a 2460 {
whismanoid 1:77f1ee332e4a 2461
whismanoid 1:77f1ee332e4a 2462 //----------------------------------------
whismanoid 1:77f1ee332e4a 2463 // number of words to read
whismanoid 1:77f1ee332e4a 2464 NumWords = (16 - channelNumber_0_15);
whismanoid 1:77f1ee332e4a 2465
whismanoid 1:77f1ee332e4a 2466 //----------------------------------------
whismanoid 1:77f1ee332e4a 2467 // Internal Clock Mode
whismanoid 1:77f1ee332e4a 2468 isExternalClock = 0;
whismanoid 1:77f1ee332e4a 2469
whismanoid 1:77f1ee332e4a 2470 //----------------------------------------
whismanoid 1:77f1ee332e4a 2471 // update device driver global variable
whismanoid 1:77f1ee332e4a 2472 ScanMode = SCAN_0101_UpperInternalClock;
whismanoid 1:77f1ee332e4a 2473
whismanoid 1:77f1ee332e4a 2474 //----------------------------------------
whismanoid 1:77f1ee332e4a 2475 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 2476 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 2477 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 2478 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 2479 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2480 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 2481 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2482 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2483
whismanoid 1:77f1ee332e4a 2484 //----------------------------------------
whismanoid 1:77f1ee332e4a 2485 // define write-only register ADC_CONFIGURATION
whismanoid 1:77f1ee332e4a 2486 ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid 1:77f1ee332e4a 2487 const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid 1:77f1ee332e4a 2488 const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid 1:77f1ee332e4a 2489 const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid 1:77f1ee332e4a 2490 const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid 1:77f1ee332e4a 2491 const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid 1:77f1ee332e4a 2492 const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid 1:77f1ee332e4a 2493
whismanoid 1:77f1ee332e4a 2494 //----------------------------------------
whismanoid 1:77f1ee332e4a 2495 // if average, ADC CONFIGURATION register set AVG and NAVG[1:0]
whismanoid 1:77f1ee332e4a 2496 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 2497 // if average, ADC CONFIGURATION register set AVG ON BIT TO 1
whismanoid 1:77f1ee332e4a 2498 // if average, ADC CONFIGURATION register set NAVG[1:0] TO N
whismanoid 1:77f1ee332e4a 2499 if (average_0_4_8_16_32 == 4) {
whismanoid 1:77f1ee332e4a 2500 // Enable Averaging of 4 samples (AVGON=1, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 2501 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2502 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2503 ADC_CONFIGURATION |= ((0 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2504 } else if (average_0_4_8_16_32 == 8) {
whismanoid 1:77f1ee332e4a 2505 // Enable Averaging of 8 samples (AVGON=1, NAVG[1:0]=1)
whismanoid 1:77f1ee332e4a 2506 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2507 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2508 ADC_CONFIGURATION |= ((1 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2509 } else if (average_0_4_8_16_32 == 16) {
whismanoid 1:77f1ee332e4a 2510 // Enable Averaging of 16 samples (AVGON=1, NAVG[1:0]=2)
whismanoid 1:77f1ee332e4a 2511 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2512 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2513 ADC_CONFIGURATION |= ((2 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2514 } else if (average_0_4_8_16_32 == 32) {
whismanoid 1:77f1ee332e4a 2515 // Enable Averaging of 32 samples (AVGON=1, NAVG[1:0]=3)
whismanoid 1:77f1ee332e4a 2516 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2517 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2518 ADC_CONFIGURATION |= ((3 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2519 } else {
whismanoid 1:77f1ee332e4a 2520 // Disable Averaging (AVGON=0, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 2521 ADC_CONFIGURATION &= ~ (( AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2522 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2523 }
whismanoid 1:77f1ee332e4a 2524
whismanoid 1:77f1ee332e4a 2525 //----------------------------------------
whismanoid 1:77f1ee332e4a 2526 // SPI write ADC CONFIGURATION register
whismanoid 1:77f1ee332e4a 2527 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2528 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2529 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2530 SPIwrite16bits(ADC_CONFIGURATION);
whismanoid 1:77f1ee332e4a 2531 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2532
whismanoid 1:77f1ee332e4a 2533 //----------------------------------------
whismanoid 1:77f1ee332e4a 2534 // Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid 1:77f1ee332e4a 2535 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2536 ADC_MODE_CONTROL |= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2537
whismanoid 1:77f1ee332e4a 2538 //----------------------------------------
whismanoid 1:77f1ee332e4a 2539 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0101_UpperInternalClock = 5
whismanoid 1:77f1ee332e4a 2540 //~ const int SCAN_0101_UpperInternalClock = 5; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2541 ADC_MODE_CONTROL |= ((SCAN_0101_UpperInternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2542
whismanoid 1:77f1ee332e4a 2543 //----------------------------------------
whismanoid 1:77f1ee332e4a 2544 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 2545 ADC_MODE_CONTROL |= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 2546
whismanoid 1:77f1ee332e4a 2547 //----------------------------------------
whismanoid 1:77f1ee332e4a 2548 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2549 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2550
whismanoid 1:77f1ee332e4a 2551 //----------------------------------------
whismanoid 1:77f1ee332e4a 2552 // ADC MODE CONTROL register set SWCNV if CNVST pin is not used
whismanoid 1:77f1ee332e4a 2553 // ADC MODE CONTROL REGISTER SELECT THE RIGHT SWCNV BIT
whismanoid 1:77f1ee332e4a 2554 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 2555 // SWCNV=1: trigger measurement on SPI CS rising edge; CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 2556 // SWCNV=0: trigger measurement by driving CNVST pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 2557 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 2558 ADC_MODE_CONTROL |= ((swcnv_0_1 & SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 2559 } else {
whismanoid 1:77f1ee332e4a 2560 ADC_MODE_CONTROL &= ~ (( SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 2561 }
whismanoid 1:77f1ee332e4a 2562
whismanoid 1:77f1ee332e4a 2563 //----------------------------------------
whismanoid 1:77f1ee332e4a 2564 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2565 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2566 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2567 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2568 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2569 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 2570 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2571 // NOTE: Figure 7 Internal Conversions with SWCNV=1 has an error, the 17th SCLK is mislabeled as "16" should be "17".
whismanoid 1:77f1ee332e4a 2572 SPIwrite24bits(ADC_MODE_CONTROL, 0);
whismanoid 1:77f1ee332e4a 2573 } else {
whismanoid 1:77f1ee332e4a 2574 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2575 }
whismanoid 1:77f1ee332e4a 2576 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2577
whismanoid 1:77f1ee332e4a 2578 //----------------------------------------
whismanoid 1:77f1ee332e4a 2579 // return number of words to read
whismanoid 1:77f1ee332e4a 2580 return NumWords;
whismanoid 1:77f1ee332e4a 2581 }
whismanoid 1:77f1ee332e4a 2582
whismanoid 1:77f1ee332e4a 2583 //----------------------------------------
whismanoid 1:77f1ee332e4a 2584 // SCAN_0110_UpperExternalClock
whismanoid 1:77f1ee332e4a 2585 //
whismanoid 1:77f1ee332e4a 2586 // Measure ADC channels in sequence from channelNumber_0_15 to AIN15.
whismanoid 1:77f1ee332e4a 2587 // External clock mode.
whismanoid 1:77f1ee332e4a 2588 // @param[in] channelNumber_0_15: AIN Channel Number
whismanoid 1:77f1ee332e4a 2589 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 2590 // @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2591 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 6:cb7bdeb185d0 2592 // @post NumWords = number of words to be read from the FIFO
whismanoid 1:77f1ee332e4a 2593 // For external clock modes, the data format depends on CHAN_ID.
whismanoid 1:77f1ee332e4a 2594 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2595 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2596 //
whismanoid 1:77f1ee332e4a 2597 int MAX11131::ScanUpperExternalClock(void)
whismanoid 1:77f1ee332e4a 2598 {
whismanoid 1:77f1ee332e4a 2599
whismanoid 1:77f1ee332e4a 2600 //----------------------------------------
whismanoid 2:50a0cf017492 2601 // define write-only register ADC_MODE_CONTROL
whismanoid 2:50a0cf017492 2602 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 2:50a0cf017492 2603 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 2:50a0cf017492 2604 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 2:50a0cf017492 2605 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 2606 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 2:50a0cf017492 2607 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 2:50a0cf017492 2608 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 2:50a0cf017492 2609
whismanoid 2:50a0cf017492 2610 //----------------------------------------
whismanoid 2:50a0cf017492 2611 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 2612 int needFIFOreset = (isExternalClock != 1);
whismanoid 2:50a0cf017492 2613 if (needFIFOreset) {
whismanoid 2:50a0cf017492 2614 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 2615 ADC_MODE_CONTROL = ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 2616 // Send SPI configuration to device
whismanoid 2:50a0cf017492 2617 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 2:50a0cf017492 2618 SPIoutputCS(0); // drive CS low
whismanoid 2:50a0cf017492 2619 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 2:50a0cf017492 2620 SPIoutputCS(1); // drive CS high
whismanoid 2:50a0cf017492 2621 ADC_MODE_CONTROL = 0;
whismanoid 2:50a0cf017492 2622 }
whismanoid 2:50a0cf017492 2623
whismanoid 2:50a0cf017492 2624 //----------------------------------------
whismanoid 1:77f1ee332e4a 2625 // number of words to read
whismanoid 1:77f1ee332e4a 2626 NumWords = (16 - channelNumber_0_15);
whismanoid 1:77f1ee332e4a 2627
whismanoid 1:77f1ee332e4a 2628 //----------------------------------------
whismanoid 1:77f1ee332e4a 2629 // External Clock Mode
whismanoid 1:77f1ee332e4a 2630 isExternalClock = 1;
whismanoid 1:77f1ee332e4a 2631
whismanoid 1:77f1ee332e4a 2632 //----------------------------------------
whismanoid 1:77f1ee332e4a 2633 // update device driver global variable
whismanoid 1:77f1ee332e4a 2634 ScanMode = SCAN_0110_UpperExternalClock;
whismanoid 1:77f1ee332e4a 2635
whismanoid 1:77f1ee332e4a 2636 //----------------------------------------
whismanoid 1:77f1ee332e4a 2637 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0110_UpperExternalClock = 6
whismanoid 1:77f1ee332e4a 2638 //~ const int SCAN_0110_UpperExternalClock = 6; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2639 ADC_MODE_CONTROL |= ((SCAN_0110_UpperExternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2640
whismanoid 1:77f1ee332e4a 2641 //----------------------------------------
whismanoid 1:77f1ee332e4a 2642 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 2643 ADC_MODE_CONTROL |= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 2644
whismanoid 1:77f1ee332e4a 2645 //----------------------------------------
whismanoid 1:77f1ee332e4a 2646 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2647 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2648
whismanoid 1:77f1ee332e4a 2649 //----------------------------------------
whismanoid 1:77f1ee332e4a 2650 // ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid 1:77f1ee332e4a 2651 // (applicable to external clock mode only)
whismanoid 1:77f1ee332e4a 2652 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 2653 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2654 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2655 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2656 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2657 ADC_MODE_CONTROL |= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid 1:77f1ee332e4a 2658
whismanoid 1:77f1ee332e4a 2659 //----------------------------------------
whismanoid 1:77f1ee332e4a 2660 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2661 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2662 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2663 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2664 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2665 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2666
whismanoid 1:77f1ee332e4a 2667 //----------------------------------------
whismanoid 1:77f1ee332e4a 2668 // return number of words to read
whismanoid 1:77f1ee332e4a 2669 return NumWords;
whismanoid 1:77f1ee332e4a 2670 }
whismanoid 1:77f1ee332e4a 2671
whismanoid 1:77f1ee332e4a 2672 //----------------------------------------
whismanoid 1:77f1ee332e4a 2673 // SCAN_0111_CustomInternalClock
whismanoid 1:77f1ee332e4a 2674 //
whismanoid 1:77f1ee332e4a 2675 // Measure selected ADC channels in sequence from AIN0 to AIN15,
whismanoid 1:77f1ee332e4a 2676 // using only the channels enabled by enabledChannelsMask.
whismanoid 1:77f1ee332e4a 2677 // Bit 0x0001 enables AIN0.
whismanoid 1:77f1ee332e4a 2678 // Bit 0x0002 enables AIN1.
whismanoid 1:77f1ee332e4a 2679 // Bit 0x0004 enables AIN2.
whismanoid 1:77f1ee332e4a 2680 // Bit 0x0008 enables AIN3.
whismanoid 1:77f1ee332e4a 2681 // Bit 0x0010 enables AIN4.
whismanoid 1:77f1ee332e4a 2682 // Bit 0x0020 enables AIN5.
whismanoid 1:77f1ee332e4a 2683 // Bit 0x0040 enables AIN6.
whismanoid 1:77f1ee332e4a 2684 // Bit 0x0080 enables AIN7.
whismanoid 1:77f1ee332e4a 2685 // Bit 0x0100 enables AIN8.
whismanoid 1:77f1ee332e4a 2686 // Bit 0x0200 enables AIN9.
whismanoid 1:77f1ee332e4a 2687 // Bit 0x0400 enables AIN10.
whismanoid 1:77f1ee332e4a 2688 // Bit 0x0800 enables AIN11.
whismanoid 1:77f1ee332e4a 2689 // Bit 0x1000 enables AIN12.
whismanoid 1:77f1ee332e4a 2690 // Bit 0x2000 enables AIN13.
whismanoid 1:77f1ee332e4a 2691 // Bit 0x4000 enables AIN14.
whismanoid 1:77f1ee332e4a 2692 // Bit 0x8000 enables AIN15.
whismanoid 1:77f1ee332e4a 2693 // Internal clock mode.
whismanoid 1:77f1ee332e4a 2694 // @param[in] enabledChannelsMask: Bitmap of AIN Channels to scan.
whismanoid 1:77f1ee332e4a 2695 // @param[in] average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid 1:77f1ee332e4a 2696 // average_0_4_8_16_32=0 to disable averaging.
whismanoid 1:77f1ee332e4a 2697 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 2698 // @param[in] swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2699 // SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid 1:77f1ee332e4a 2700 // Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 2701 // SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid 1:77f1ee332e4a 2702 // CS must be held low for minimum of 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2703 // CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 2704 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 6:cb7bdeb185d0 2705 // @post NumWords = number of words to be read from the FIFO
whismanoid 1:77f1ee332e4a 2706 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 2707 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2708 //
whismanoid 1:77f1ee332e4a 2709 int MAX11131::ScanCustomInternalClock(void)
whismanoid 1:77f1ee332e4a 2710 {
whismanoid 1:77f1ee332e4a 2711
whismanoid 1:77f1ee332e4a 2712 //----------------------------------------
whismanoid 1:77f1ee332e4a 2713 // count nWords = number of set bits in enabledChannelsMask
whismanoid 1:77f1ee332e4a 2714 uint16_t bitMask;
whismanoid 1:77f1ee332e4a 2715 int nWords = 0;
whismanoid 1:77f1ee332e4a 2716 for (bitMask = 0x8000; bitMask != 0; bitMask = bitMask / 2)
whismanoid 1:77f1ee332e4a 2717 {
whismanoid 1:77f1ee332e4a 2718 if (enabledChannelsMask & bitMask)
whismanoid 1:77f1ee332e4a 2719 {
whismanoid 1:77f1ee332e4a 2720 nWords++;
whismanoid 1:77f1ee332e4a 2721 }
whismanoid 1:77f1ee332e4a 2722 }
whismanoid 1:77f1ee332e4a 2723
whismanoid 1:77f1ee332e4a 2724 //----------------------------------------
whismanoid 1:77f1ee332e4a 2725 // number of words to read
whismanoid 1:77f1ee332e4a 2726 NumWords = nWords;
whismanoid 1:77f1ee332e4a 2727
whismanoid 1:77f1ee332e4a 2728 //----------------------------------------
whismanoid 1:77f1ee332e4a 2729 // Internal Clock Mode
whismanoid 1:77f1ee332e4a 2730 isExternalClock = 0;
whismanoid 1:77f1ee332e4a 2731
whismanoid 1:77f1ee332e4a 2732 //----------------------------------------
whismanoid 1:77f1ee332e4a 2733 // update device driver global variable
whismanoid 1:77f1ee332e4a 2734 ScanMode = SCAN_0111_CustomInternalClock;
whismanoid 1:77f1ee332e4a 2735
whismanoid 1:77f1ee332e4a 2736 //----------------------------------------
whismanoid 1:77f1ee332e4a 2737 // define write-only register ADC_MODE_CONTROL
whismanoid 1:77f1ee332e4a 2738 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 1:77f1ee332e4a 2739 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 1:77f1ee332e4a 2740 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 1:77f1ee332e4a 2741 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2742 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 2743 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2744 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 1:77f1ee332e4a 2745
whismanoid 1:77f1ee332e4a 2746 //----------------------------------------
whismanoid 1:77f1ee332e4a 2747 // define write-only register ADC_CONFIGURATION
whismanoid 1:77f1ee332e4a 2748 ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid 1:77f1ee332e4a 2749 const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid 1:77f1ee332e4a 2750 const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid 1:77f1ee332e4a 2751 const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid 1:77f1ee332e4a 2752 const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid 1:77f1ee332e4a 2753 const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid 1:77f1ee332e4a 2754 const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid 1:77f1ee332e4a 2755
whismanoid 1:77f1ee332e4a 2756 //----------------------------------------
whismanoid 1:77f1ee332e4a 2757 // define write-only registers CSCAN0,CSCAN1
whismanoid 1:77f1ee332e4a 2758 CSCAN0 = 0xA000; //!< mosiData16 0xA000..0xA7FF format: 1 0 1 0 0 CHSCAN15 CHSCAN14 CHSCAN13 CHSCAN12 CHSCAN11 CHSCAN10 CHSCAN9 CHSCAN8 x x x
whismanoid 1:77f1ee332e4a 2759 const int CHSCAN15_LSB = 10; // CSCAN0.CHSCAN15
whismanoid 1:77f1ee332e4a 2760 const int CHSCAN14_LSB = 9; // CSCAN0.CHSCAN14
whismanoid 1:77f1ee332e4a 2761 const int CHSCAN13_LSB = 8; // CSCAN0.CHSCAN13
whismanoid 1:77f1ee332e4a 2762 const int CHSCAN12_LSB = 7; // CSCAN0.CHSCAN12
whismanoid 1:77f1ee332e4a 2763 const int CHSCAN11_LSB = 6; // CSCAN0.CHSCAN11
whismanoid 1:77f1ee332e4a 2764 const int CHSCAN10_LSB = 5; // CSCAN0.CHSCAN10
whismanoid 1:77f1ee332e4a 2765 const int CHSCAN9_LSB = 4; // CSCAN0.CHSCAN9
whismanoid 1:77f1ee332e4a 2766 const int CHSCAN8_LSB = 3; // CSCAN0.CHSCAN8
whismanoid 1:77f1ee332e4a 2767 CSCAN1 = 0xA800; //!< mosiData16 0xA800..0xAFFF format: 1 0 1 0 1 CHSCAN7 CHSCAN6 CHSCAN5 CHSCAN4 CHSCAN3 CHSCAN2 CHSCAN1 CHSCAN0 x x x
whismanoid 1:77f1ee332e4a 2768 const int CHSCAN7_LSB = 10; // CSCAN1.CHSCAN7
whismanoid 1:77f1ee332e4a 2769 const int CHSCAN6_LSB = 9; // CSCAN1.CHSCAN6
whismanoid 1:77f1ee332e4a 2770 const int CHSCAN5_LSB = 8; // CSCAN1.CHSCAN5
whismanoid 1:77f1ee332e4a 2771 const int CHSCAN4_LSB = 7; // CSCAN1.CHSCAN4
whismanoid 1:77f1ee332e4a 2772 const int CHSCAN3_LSB = 6; // CSCAN1.CHSCAN3
whismanoid 1:77f1ee332e4a 2773 const int CHSCAN2_LSB = 5; // CSCAN1.CHSCAN2
whismanoid 1:77f1ee332e4a 2774 const int CHSCAN1_LSB = 4; // CSCAN1.CHSCAN1
whismanoid 1:77f1ee332e4a 2775 const int CHSCAN0_LSB = 3; // CSCAN1.CHSCAN0
whismanoid 1:77f1ee332e4a 2776
whismanoid 1:77f1ee332e4a 2777 //----------------------------------------
whismanoid 1:77f1ee332e4a 2778 // if average, ADC CONFIGURATION register set AVG and NAVG[1:0]
whismanoid 1:77f1ee332e4a 2779 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 2780 // if average, ADC CONFIGURATION register set AVG ON BIT TO 1
whismanoid 1:77f1ee332e4a 2781 // if average, ADC CONFIGURATION register set NAVG[1:0] TO N
whismanoid 1:77f1ee332e4a 2782 if (average_0_4_8_16_32 == 4) {
whismanoid 1:77f1ee332e4a 2783 // Enable Averaging of 4 samples (AVGON=1, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 2784 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2785 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2786 ADC_CONFIGURATION |= ((0 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2787 } else if (average_0_4_8_16_32 == 8) {
whismanoid 1:77f1ee332e4a 2788 // Enable Averaging of 8 samples (AVGON=1, NAVG[1:0]=1)
whismanoid 1:77f1ee332e4a 2789 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2790 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2791 ADC_CONFIGURATION |= ((1 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2792 } else if (average_0_4_8_16_32 == 16) {
whismanoid 1:77f1ee332e4a 2793 // Enable Averaging of 16 samples (AVGON=1, NAVG[1:0]=2)
whismanoid 1:77f1ee332e4a 2794 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2795 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2796 ADC_CONFIGURATION |= ((2 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2797 } else if (average_0_4_8_16_32 == 32) {
whismanoid 1:77f1ee332e4a 2798 // Enable Averaging of 32 samples (AVGON=1, NAVG[1:0]=3)
whismanoid 1:77f1ee332e4a 2799 ADC_CONFIGURATION |= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2800 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2801 ADC_CONFIGURATION |= ((3 & NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2802 } else {
whismanoid 1:77f1ee332e4a 2803 // Disable Averaging (AVGON=0, NAVG[1:0]=0)
whismanoid 1:77f1ee332e4a 2804 ADC_CONFIGURATION &= ~ (( AVGON_BITS) << AVGON_LSB);
whismanoid 1:77f1ee332e4a 2805 ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid 1:77f1ee332e4a 2806 }
whismanoid 1:77f1ee332e4a 2807
whismanoid 1:77f1ee332e4a 2808 //----------------------------------------
whismanoid 1:77f1ee332e4a 2809 // SPI write ADC CONFIGURATION register
whismanoid 1:77f1ee332e4a 2810 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2811 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2812 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2813 SPIwrite16bits(ADC_CONFIGURATION);
whismanoid 1:77f1ee332e4a 2814 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2815
whismanoid 1:77f1ee332e4a 2816 //----------------------------------------
whismanoid 1:77f1ee332e4a 2817 // SET CSCAN0 CSCAN1 REGISTERS from enabledChannelsMask
whismanoid 1:77f1ee332e4a 2818 CSCAN0 = 0xA000 | (((enabledChannelsMask >> 8) & 0xFF) << 3); // CSCAN0.CHSCAN[15:8]
whismanoid 1:77f1ee332e4a 2819 CSCAN1 = 0xA800 | (((enabledChannelsMask) & 0xFF) << 3); // CSCAN1.CHSCAN[7:0]
whismanoid 1:77f1ee332e4a 2820 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2821 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2822 SPIwrite16bits(CSCAN0);
whismanoid 1:77f1ee332e4a 2823 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2824 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2825 SPIwrite16bits(CSCAN1);
whismanoid 1:77f1ee332e4a 2826 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2827
whismanoid 1:77f1ee332e4a 2828 //----------------------------------------
whismanoid 1:77f1ee332e4a 2829 // Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid 1:77f1ee332e4a 2830 ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2831 ADC_MODE_CONTROL |= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 1:77f1ee332e4a 2832
whismanoid 1:77f1ee332e4a 2833 //----------------------------------------
whismanoid 1:77f1ee332e4a 2834 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0111_CustomInternalClock = 7
whismanoid 1:77f1ee332e4a 2835 //~ const int SCAN_0111_CustomInternalClock = 7; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2836 ADC_MODE_CONTROL |= ((SCAN_0111_CustomInternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2837
whismanoid 1:77f1ee332e4a 2838 //----------------------------------------
whismanoid 1:77f1ee332e4a 2839 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2840 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2841
whismanoid 1:77f1ee332e4a 2842 //----------------------------------------
whismanoid 1:77f1ee332e4a 2843 // ADC MODE CONTROL register set SWCNV if CNVST pin is not used
whismanoid 1:77f1ee332e4a 2844 // ADC MODE CONTROL REGISTER SELECT THE RIGHT SWCNV BIT
whismanoid 1:77f1ee332e4a 2845 // (applicable to internal clock mode only)
whismanoid 1:77f1ee332e4a 2846 // SWCNV=1: trigger measurement on SPI CS rising edge; CNVST pin is not used. (AIN14 is available)
whismanoid 1:77f1ee332e4a 2847 // SWCNV=0: trigger measurement by driving CNVST pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 1:77f1ee332e4a 2848 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 2849 ADC_MODE_CONTROL |= ((swcnv_0_1 & SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 2850 } else {
whismanoid 1:77f1ee332e4a 2851 ADC_MODE_CONTROL &= ~ (( SWCNV_BITS) << SWCNV_LSB);
whismanoid 1:77f1ee332e4a 2852 }
whismanoid 1:77f1ee332e4a 2853
whismanoid 1:77f1ee332e4a 2854 //----------------------------------------
whismanoid 1:77f1ee332e4a 2855 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 2856 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2857 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 2858 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2859 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2860 if (swcnv_0_1) {
whismanoid 1:77f1ee332e4a 2861 // If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid 1:77f1ee332e4a 2862 // NOTE: Figure 7 Internal Conversions with SWCNV=1 has an error, the 17th SCLK is mislabeled as "16" should be "17".
whismanoid 1:77f1ee332e4a 2863 SPIwrite24bits(ADC_MODE_CONTROL, 0);
whismanoid 1:77f1ee332e4a 2864 } else {
whismanoid 1:77f1ee332e4a 2865 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 2866 }
whismanoid 1:77f1ee332e4a 2867 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2868
whismanoid 1:77f1ee332e4a 2869 //----------------------------------------
whismanoid 1:77f1ee332e4a 2870 // return number of words to read
whismanoid 1:77f1ee332e4a 2871 return NumWords;
whismanoid 1:77f1ee332e4a 2872 }
whismanoid 1:77f1ee332e4a 2873
whismanoid 1:77f1ee332e4a 2874 //----------------------------------------
whismanoid 1:77f1ee332e4a 2875 // SCAN_1000_CustomExternalClock
whismanoid 1:77f1ee332e4a 2876 //
whismanoid 1:77f1ee332e4a 2877 // Measure selected ADC channels in sequence from AIN0 to AIN15,
whismanoid 1:77f1ee332e4a 2878 // using only the channels enabled by enabledChannelsMask.
whismanoid 1:77f1ee332e4a 2879 // Bit 0x0001 enables AIN0.
whismanoid 1:77f1ee332e4a 2880 // Bit 0x0002 enables AIN1.
whismanoid 1:77f1ee332e4a 2881 // Bit 0x0004 enables AIN2.
whismanoid 1:77f1ee332e4a 2882 // Bit 0x0008 enables AIN3.
whismanoid 1:77f1ee332e4a 2883 // Bit 0x0010 enables AIN4.
whismanoid 1:77f1ee332e4a 2884 // Bit 0x0020 enables AIN5.
whismanoid 1:77f1ee332e4a 2885 // Bit 0x0040 enables AIN6.
whismanoid 1:77f1ee332e4a 2886 // Bit 0x0080 enables AIN7.
whismanoid 1:77f1ee332e4a 2887 // Bit 0x0100 enables AIN8.
whismanoid 1:77f1ee332e4a 2888 // Bit 0x0200 enables AIN9.
whismanoid 1:77f1ee332e4a 2889 // Bit 0x0400 enables AIN10.
whismanoid 1:77f1ee332e4a 2890 // Bit 0x0800 enables AIN11.
whismanoid 1:77f1ee332e4a 2891 // Bit 0x1000 enables AIN12.
whismanoid 1:77f1ee332e4a 2892 // Bit 0x2000 enables AIN13.
whismanoid 1:77f1ee332e4a 2893 // Bit 0x4000 enables AIN14.
whismanoid 1:77f1ee332e4a 2894 // Bit 0x8000 enables AIN15.
whismanoid 1:77f1ee332e4a 2895 // External clock mode.
whismanoid 1:77f1ee332e4a 2896 // @param[in] enabledChannelsMask: Bitmap of AIN Channels to scan.
whismanoid 1:77f1ee332e4a 2897 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 2898 // @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 2899 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 6:cb7bdeb185d0 2900 // @post NumWords = number of words to be read from the FIFO
whismanoid 1:77f1ee332e4a 2901 // For external clock modes, the data format depends on CHAN_ID.
whismanoid 1:77f1ee332e4a 2902 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 2903 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 2904 //
whismanoid 1:77f1ee332e4a 2905 int MAX11131::ScanCustomExternalClock(void)
whismanoid 1:77f1ee332e4a 2906 {
whismanoid 1:77f1ee332e4a 2907
whismanoid 1:77f1ee332e4a 2908 //----------------------------------------
whismanoid 1:77f1ee332e4a 2909 // count nWords = number of set bits in enabledChannelsMask
whismanoid 1:77f1ee332e4a 2910 uint16_t bitMask;
whismanoid 1:77f1ee332e4a 2911 int nWords = 0;
whismanoid 1:77f1ee332e4a 2912 for (bitMask = 0x8000; bitMask != 0; bitMask = bitMask / 2)
whismanoid 1:77f1ee332e4a 2913 {
whismanoid 1:77f1ee332e4a 2914 if (enabledChannelsMask & bitMask)
whismanoid 1:77f1ee332e4a 2915 {
whismanoid 1:77f1ee332e4a 2916 nWords++;
whismanoid 1:77f1ee332e4a 2917 }
whismanoid 1:77f1ee332e4a 2918 }
whismanoid 1:77f1ee332e4a 2919
whismanoid 1:77f1ee332e4a 2920 //----------------------------------------
whismanoid 2:50a0cf017492 2921 // define write-only register ADC_MODE_CONTROL
whismanoid 2:50a0cf017492 2922 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 2:50a0cf017492 2923 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 2:50a0cf017492 2924 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 2:50a0cf017492 2925 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 2926 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 2:50a0cf017492 2927 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 2:50a0cf017492 2928 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 2:50a0cf017492 2929
whismanoid 2:50a0cf017492 2930 //----------------------------------------
whismanoid 2:50a0cf017492 2931 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 2932 int needFIFOreset = (isExternalClock != 1);
whismanoid 2:50a0cf017492 2933 if (needFIFOreset) {
whismanoid 2:50a0cf017492 2934 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 2935 ADC_MODE_CONTROL = ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 2936 // Send SPI configuration to device
whismanoid 2:50a0cf017492 2937 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 2:50a0cf017492 2938 SPIoutputCS(0); // drive CS low
whismanoid 2:50a0cf017492 2939 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 2:50a0cf017492 2940 SPIoutputCS(1); // drive CS high
whismanoid 2:50a0cf017492 2941 ADC_MODE_CONTROL = 0;
whismanoid 2:50a0cf017492 2942 }
whismanoid 2:50a0cf017492 2943
whismanoid 2:50a0cf017492 2944 //----------------------------------------
whismanoid 1:77f1ee332e4a 2945 // number of words to read
whismanoid 1:77f1ee332e4a 2946 NumWords = nWords;
whismanoid 1:77f1ee332e4a 2947
whismanoid 1:77f1ee332e4a 2948 //----------------------------------------
whismanoid 1:77f1ee332e4a 2949 // External Clock Mode
whismanoid 1:77f1ee332e4a 2950 isExternalClock = 1;
whismanoid 1:77f1ee332e4a 2951
whismanoid 1:77f1ee332e4a 2952 //----------------------------------------
whismanoid 1:77f1ee332e4a 2953 // update device driver global variable
whismanoid 1:77f1ee332e4a 2954 ScanMode = SCAN_1000_CustomExternalClock;
whismanoid 1:77f1ee332e4a 2955
whismanoid 1:77f1ee332e4a 2956 //----------------------------------------
whismanoid 1:77f1ee332e4a 2957 // define write-only registers CSCAN0,CSCAN1
whismanoid 1:77f1ee332e4a 2958 CSCAN0 = 0xA000; //!< mosiData16 0xA000..0xA7FF format: 1 0 1 0 0 CHSCAN15 CHSCAN14 CHSCAN13 CHSCAN12 CHSCAN11 CHSCAN10 CHSCAN9 CHSCAN8 x x x
whismanoid 1:77f1ee332e4a 2959 const int CHSCAN15_LSB = 10; // CSCAN0.CHSCAN15
whismanoid 1:77f1ee332e4a 2960 const int CHSCAN14_LSB = 9; // CSCAN0.CHSCAN14
whismanoid 1:77f1ee332e4a 2961 const int CHSCAN13_LSB = 8; // CSCAN0.CHSCAN13
whismanoid 1:77f1ee332e4a 2962 const int CHSCAN12_LSB = 7; // CSCAN0.CHSCAN12
whismanoid 1:77f1ee332e4a 2963 const int CHSCAN11_LSB = 6; // CSCAN0.CHSCAN11
whismanoid 1:77f1ee332e4a 2964 const int CHSCAN10_LSB = 5; // CSCAN0.CHSCAN10
whismanoid 1:77f1ee332e4a 2965 const int CHSCAN9_LSB = 4; // CSCAN0.CHSCAN9
whismanoid 1:77f1ee332e4a 2966 const int CHSCAN8_LSB = 3; // CSCAN0.CHSCAN8
whismanoid 1:77f1ee332e4a 2967 CSCAN1 = 0xA800; //!< mosiData16 0xA800..0xAFFF format: 1 0 1 0 1 CHSCAN7 CHSCAN6 CHSCAN5 CHSCAN4 CHSCAN3 CHSCAN2 CHSCAN1 CHSCAN0 x x x
whismanoid 1:77f1ee332e4a 2968 const int CHSCAN7_LSB = 10; // CSCAN1.CHSCAN7
whismanoid 1:77f1ee332e4a 2969 const int CHSCAN6_LSB = 9; // CSCAN1.CHSCAN6
whismanoid 1:77f1ee332e4a 2970 const int CHSCAN5_LSB = 8; // CSCAN1.CHSCAN5
whismanoid 1:77f1ee332e4a 2971 const int CHSCAN4_LSB = 7; // CSCAN1.CHSCAN4
whismanoid 1:77f1ee332e4a 2972 const int CHSCAN3_LSB = 6; // CSCAN1.CHSCAN3
whismanoid 1:77f1ee332e4a 2973 const int CHSCAN2_LSB = 5; // CSCAN1.CHSCAN2
whismanoid 1:77f1ee332e4a 2974 const int CHSCAN1_LSB = 4; // CSCAN1.CHSCAN1
whismanoid 1:77f1ee332e4a 2975 const int CHSCAN0_LSB = 3; // CSCAN1.CHSCAN0
whismanoid 1:77f1ee332e4a 2976
whismanoid 1:77f1ee332e4a 2977 //----------------------------------------
whismanoid 1:77f1ee332e4a 2978 // SET CSCAN0 CSCAN1 REGISTERS from enabledChannelsMask
whismanoid 1:77f1ee332e4a 2979 CSCAN0 = 0xA000 | (((enabledChannelsMask >> 8) & 0xFF) << 3); // CSCAN0.CHSCAN[15:8]
whismanoid 1:77f1ee332e4a 2980 CSCAN1 = 0xA800 | (((enabledChannelsMask) & 0xFF) << 3); // CSCAN1.CHSCAN[7:0]
whismanoid 1:77f1ee332e4a 2981 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 2982 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2983 SPIwrite16bits(CSCAN0);
whismanoid 1:77f1ee332e4a 2984 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2985 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 2986 SPIwrite16bits(CSCAN1);
whismanoid 1:77f1ee332e4a 2987 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 2988
whismanoid 1:77f1ee332e4a 2989 //----------------------------------------
whismanoid 1:77f1ee332e4a 2990 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_1000_CustomExternalClock = 8
whismanoid 1:77f1ee332e4a 2991 //~ const int SCAN_1000_CustomExternalClock = 8; // replaced local const with enum
whismanoid 1:77f1ee332e4a 2992 ADC_MODE_CONTROL |= ((SCAN_1000_CustomExternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 2993
whismanoid 1:77f1ee332e4a 2994 //----------------------------------------
whismanoid 1:77f1ee332e4a 2995 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 2996 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 2997
whismanoid 1:77f1ee332e4a 2998 //----------------------------------------
whismanoid 1:77f1ee332e4a 2999 // ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid 1:77f1ee332e4a 3000 // (applicable to external clock mode only)
whismanoid 1:77f1ee332e4a 3001 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 3002 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 3003 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 3004 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 3005 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 3006 ADC_MODE_CONTROL |= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid 1:77f1ee332e4a 3007
whismanoid 1:77f1ee332e4a 3008 //----------------------------------------
whismanoid 1:77f1ee332e4a 3009 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 3010 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 3011 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 3012 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 3013 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 3014 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 3015
whismanoid 1:77f1ee332e4a 3016 //----------------------------------------
whismanoid 1:77f1ee332e4a 3017 // return number of words to read
whismanoid 1:77f1ee332e4a 3018 return NumWords;
whismanoid 1:77f1ee332e4a 3019 }
whismanoid 1:77f1ee332e4a 3020
whismanoid 1:77f1ee332e4a 3021 //----------------------------------------
whismanoid 1:77f1ee332e4a 3022 // SCAN_1001_SampleSetExternalClock
whismanoid 1:77f1ee332e4a 3023 //
whismanoid 1:77f1ee332e4a 3024 // Measure ADC channels in an arbitrary pattern.
whismanoid 1:77f1ee332e4a 3025 // Channels can be visited in any order, with repetition allowed.
whismanoid 1:77f1ee332e4a 3026 // External clock mode.
whismanoid 1:77f1ee332e4a 3027 // @pre enabledChannelsPatternLength_1_256: number of channel selections
whismanoid 1:77f1ee332e4a 3028 // @pre enabledChannelsPattern: array containing channel selection pattern
whismanoid 1:77f1ee332e4a 3029 // In the array, one channel select per byte.
whismanoid 1:77f1ee332e4a 3030 // In the SPI interface, immediately after SAMPLESET register is written,
whismanoid 1:77f1ee332e4a 3031 // each byte encodes two channelNumber selections.
whismanoid 1:77f1ee332e4a 3032 // The high 4 bits encode the first channelNumber.
whismanoid 1:77f1ee332e4a 3033 // (((enabledChannelsPattern[0]) & 0x0F) << 4) | ((enabledChannelsPattern[1]) & 0x0F)
whismanoid 1:77f1ee332e4a 3034 // If it is an odd number of channels, additional nybbles will be ignored.
whismanoid 1:77f1ee332e4a 3035 // CS will be asserted low during the entire SAMPLESET pattern selection.
whismanoid 6:cb7bdeb185d0 3036 // @param[in] enabledChannelsPattern: array of channel select, one channel per byte
whismanoid 1:77f1ee332e4a 3037 // @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 1:77f1ee332e4a 3038 // @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 1:77f1ee332e4a 3039 // @return number of ScanRead() words needed to retrieve the data.
whismanoid 6:cb7bdeb185d0 3040 // @post NumWords = number of words to be read from the FIFO
whismanoid 1:77f1ee332e4a 3041 // For external clock modes, the data format depends on CHAN_ID.
whismanoid 1:77f1ee332e4a 3042 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 3043 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 3044 //
whismanoid 1:77f1ee332e4a 3045 int MAX11131::ScanSampleSetExternalClock(void)
whismanoid 1:77f1ee332e4a 3046 {
whismanoid 1:77f1ee332e4a 3047
whismanoid 1:77f1ee332e4a 3048 //----------------------------------------
whismanoid 2:50a0cf017492 3049 // define write-only register ADC_MODE_CONTROL
whismanoid 2:50a0cf017492 3050 ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 2:50a0cf017492 3051 const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 2:50a0cf017492 3052 const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid 2:50a0cf017492 3053 const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 3054 const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 2:50a0cf017492 3055 const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid 2:50a0cf017492 3056 const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid 2:50a0cf017492 3057
whismanoid 2:50a0cf017492 3058 //----------------------------------------
whismanoid 2:50a0cf017492 3059 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 3060 int needFIFOreset = (isExternalClock != 1);
whismanoid 2:50a0cf017492 3061 if (needFIFOreset) {
whismanoid 2:50a0cf017492 3062 // Apply a soft reset when changing from internal to external clock mode.
whismanoid 2:50a0cf017492 3063 ADC_MODE_CONTROL = ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 2:50a0cf017492 3064 // Send SPI configuration to device
whismanoid 2:50a0cf017492 3065 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 2:50a0cf017492 3066 SPIoutputCS(0); // drive CS low
whismanoid 2:50a0cf017492 3067 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 2:50a0cf017492 3068 SPIoutputCS(1); // drive CS high
whismanoid 2:50a0cf017492 3069 ADC_MODE_CONTROL = 0;
whismanoid 2:50a0cf017492 3070 }
whismanoid 2:50a0cf017492 3071
whismanoid 2:50a0cf017492 3072 //----------------------------------------
whismanoid 1:77f1ee332e4a 3073 // number of words to read
whismanoid 1:77f1ee332e4a 3074 NumWords = ((enabledChannelsPatternLength_1_256 != 0) ? enabledChannelsPatternLength_1_256 : 256 );
whismanoid 1:77f1ee332e4a 3075
whismanoid 1:77f1ee332e4a 3076 //----------------------------------------
whismanoid 1:77f1ee332e4a 3077 // External Clock Mode
whismanoid 1:77f1ee332e4a 3078 isExternalClock = 1;
whismanoid 1:77f1ee332e4a 3079
whismanoid 1:77f1ee332e4a 3080 //----------------------------------------
whismanoid 1:77f1ee332e4a 3081 // update device driver global variable
whismanoid 1:77f1ee332e4a 3082 ScanMode = SCAN_1001_SampleSetExternalClock;
whismanoid 1:77f1ee332e4a 3083
whismanoid 1:77f1ee332e4a 3084 //----------------------------------------
whismanoid 1:77f1ee332e4a 3085 // Initialize shadow of write-only register SAMPLESET.
whismanoid 1:77f1ee332e4a 3086 // Do not write to SAMPLESET at this time.
whismanoid 1:77f1ee332e4a 3087 // A write to SAMPLESET must be followed by specified number of pattern entry words.
whismanoid 1:77f1ee332e4a 3088 // See ScanSampleSetExternalClock function for details.
whismanoid 1:77f1ee332e4a 3089 SAMPLESET = 0xB000; //!< mosiData16 0xB000..0xB7FF format: 1 0 1 1 0 SEQ_LENGTH[7:0] x x x
whismanoid 1:77f1ee332e4a 3090 const int SAMPLESET_LSB = 3; const int SAMPLESET_BITS = 0xFF; // SAMPLESET.SEQ_LENGTH[7:0]
whismanoid 1:77f1ee332e4a 3091
whismanoid 1:77f1ee332e4a 3092 //----------------------------------------
whismanoid 1:77f1ee332e4a 3093 // SampleSet register set SEQ_DEPTH[7:0] TO SET CHANNEL CAPTURE DEPTH; FOLLOW SampleSet REGISTER WITH CHANNEL PATTERN OF THE SAME SIZE AS SEQUENCE DEPTH
whismanoid 1:77f1ee332e4a 3094 // NOTE: SAMPLESET.SEQ_LENGTH[7:0] is the number of channel entries in the pattern.
whismanoid 1:77f1ee332e4a 3095 // NOTE: Each channel entry is 4 bits. The first 4 bits are the first channel in the sequence.
whismanoid 1:77f1ee332e4a 3096 // NOTE: Channels can be repeated in any arbitrary order.
whismanoid 1:77f1ee332e4a 3097 // NOTE: The channel entry pattern is sent immediately after writing SAMPLESET.
whismanoid 1:77f1ee332e4a 3098 // NOTE: Keep CS low during the entire SAMPLESET pattern entry.
whismanoid 1:77f1ee332e4a 3099 const int seq_length_minus_one_0_255 = enabledChannelsPatternLength_1_256 - 1;
whismanoid 1:77f1ee332e4a 3100 SAMPLESET = 0xB000;
whismanoid 1:77f1ee332e4a 3101 //SAMPLESET &= ~ (( SAMPLESET_BITS) << SAMPLESET_LSB);
whismanoid 1:77f1ee332e4a 3102 SAMPLESET |= ((seq_length_minus_one_0_255 & SAMPLESET_BITS) << SAMPLESET_LSB);
whismanoid 1:77f1ee332e4a 3103 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 3104 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 3105 SPIwrite16bits(SAMPLESET); // SAMPLESET must be followed by several more bytes, length specified by SEQ_LENGTH[7:0]
whismanoid 1:77f1ee332e4a 3106 // pack enabledChannelsPattern[index] into nybbles
whismanoid 1:77f1ee332e4a 3107 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 3108 // NOTE: Send the sampleset pattern, with 4 entries packed into each 16-bit SPI word. Pad unused entries with 0.
whismanoid 1:77f1ee332e4a 3109 SPI_MOSI_Semantic = 2; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 3110 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 3111 // NOTE: Keep CS low during the entire SAMPLESET pattern entry.
whismanoid 1:77f1ee332e4a 3112 int entryIndex;
whismanoid 1:77f1ee332e4a 3113 for (entryIndex = 0; entryIndex < enabledChannelsPatternLength_1_256; entryIndex += 4)
whismanoid 1:77f1ee332e4a 3114 {
whismanoid 1:77f1ee332e4a 3115 uint16_t pack4channels = 0;
whismanoid 1:77f1ee332e4a 3116 pack4channels |= (((enabledChannelsPattern[entryIndex + 0]) & 0x0F) << 12);
whismanoid 1:77f1ee332e4a 3117 if ((entryIndex + 1) < enabledChannelsPatternLength_1_256) {
whismanoid 1:77f1ee332e4a 3118 pack4channels |= (((enabledChannelsPattern[entryIndex + 1]) & 0x0F) << 8);
whismanoid 1:77f1ee332e4a 3119 }
whismanoid 1:77f1ee332e4a 3120 if ((entryIndex + 2) < enabledChannelsPatternLength_1_256) {
whismanoid 1:77f1ee332e4a 3121 pack4channels |= (((enabledChannelsPattern[entryIndex + 2]) & 0x0F) << 4);
whismanoid 1:77f1ee332e4a 3122 }
whismanoid 1:77f1ee332e4a 3123 if ((entryIndex + 3) < enabledChannelsPatternLength_1_256) {
whismanoid 1:77f1ee332e4a 3124 pack4channels |= ((enabledChannelsPattern[entryIndex + 3]) & 0x0F);
whismanoid 1:77f1ee332e4a 3125 }
whismanoid 1:77f1ee332e4a 3126 SPIwrite16bits(pack4channels);
whismanoid 1:77f1ee332e4a 3127 }
whismanoid 1:77f1ee332e4a 3128 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 3129
whismanoid 1:77f1ee332e4a 3130 //----------------------------------------
whismanoid 1:77f1ee332e4a 3131 // ADC MODE CONTROL register set SCAN[3:0] TO SCAN_1001_SampleSetExternalClock = 9
whismanoid 1:77f1ee332e4a 3132 //~ const int SCAN_1001_SampleSetExternalClock = 9; // replaced local const with enum
whismanoid 1:77f1ee332e4a 3133 ADC_MODE_CONTROL |= ((SCAN_1001_SampleSetExternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid 1:77f1ee332e4a 3134
whismanoid 1:77f1ee332e4a 3135 //----------------------------------------
whismanoid 1:77f1ee332e4a 3136 // ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid 1:77f1ee332e4a 3137 ADC_MODE_CONTROL |= ((0 & CHSEL_BITS) << CHSEL_LSB);
whismanoid 1:77f1ee332e4a 3138
whismanoid 1:77f1ee332e4a 3139 //----------------------------------------
whismanoid 1:77f1ee332e4a 3140 // ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid 1:77f1ee332e4a 3141 ADC_MODE_CONTROL |= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid 1:77f1ee332e4a 3142
whismanoid 1:77f1ee332e4a 3143 //----------------------------------------
whismanoid 1:77f1ee332e4a 3144 // ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid 1:77f1ee332e4a 3145 // (applicable to external clock mode only)
whismanoid 1:77f1ee332e4a 3146 // For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid 1:77f1ee332e4a 3147 // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 3148 // when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 3149 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 3150 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 3151 ADC_MODE_CONTROL |= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid 1:77f1ee332e4a 3152
whismanoid 1:77f1ee332e4a 3153 //----------------------------------------
whismanoid 1:77f1ee332e4a 3154 // SPI write ADC MODE CONTROL register
whismanoid 1:77f1ee332e4a 3155 // Send SPI configuration to device
whismanoid 1:77f1ee332e4a 3156 SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 1:77f1ee332e4a 3157 SPIoutputCS(0); // drive CS low
whismanoid 1:77f1ee332e4a 3158 SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid 1:77f1ee332e4a 3159 SPIoutputCS(1); // drive CS high
whismanoid 1:77f1ee332e4a 3160
whismanoid 1:77f1ee332e4a 3161 //----------------------------------------
whismanoid 1:77f1ee332e4a 3162 // return number of words to read
whismanoid 1:77f1ee332e4a 3163 return NumWords;
whismanoid 1:77f1ee332e4a 3164 }
whismanoid 1:77f1ee332e4a 3165
whismanoid 1:77f1ee332e4a 3166 //----------------------------------------
whismanoid 1:77f1ee332e4a 3167 // Example configure and perform some measurements in ScanManual mode.
whismanoid 1:77f1ee332e4a 3168 // @param[out] pd_mean = address for double mean (avearge)
whismanoid 1:77f1ee332e4a 3169 // @param[out] pd_variance = address for double variance (variance)
whismanoid 1:77f1ee332e4a 3170 // @param[out] pd_stddev = address for double stddev (standard deviation)
whismanoid 1:77f1ee332e4a 3171 // @param[out] pd_Sx = address for double Sx (sum of all X)
whismanoid 1:77f1ee332e4a 3172 // @param[out] pd_Sxx = address for double Sxx (sum of squares of each X)
whismanoid 1:77f1ee332e4a 3173 void MAX11131::Example_ScanManual(int channelNumber_0_15, int nWords,
whismanoid 1:77f1ee332e4a 3174 double* pd_mean, double* pd_variance, double* pd_stddev,
whismanoid 1:77f1ee332e4a 3175 double* pd_Sx, double* pd_Sxx)
whismanoid 1:77f1ee332e4a 3176 {
whismanoid 1:77f1ee332e4a 3177
whismanoid 1:77f1ee332e4a 3178 //----------------------------------------
whismanoid 1:77f1ee332e4a 3179 // configure and perform some measurements in ScanManual mode
whismanoid 1:77f1ee332e4a 3180 Init();
whismanoid 1:77f1ee332e4a 3181 channelNumber_0_15 = channelNumber_0_15; // Analog Input Channel Select AIN0..
whismanoid 1:77f1ee332e4a 3182 PowerManagement_0_2 = 0; // Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 1:77f1ee332e4a 3183 chan_id_0_1 = 1; // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 1:77f1ee332e4a 3184 // const int nWords = 100;
whismanoid 1:77f1ee332e4a 3185 double Sx = 0;
whismanoid 1:77f1ee332e4a 3186 double Sxx = 0;
whismanoid 1:77f1ee332e4a 3187 int index;
whismanoid 1:77f1ee332e4a 3188 ScanManual();
whismanoid 1:77f1ee332e4a 3189 for (index = 0; index < nWords; index++)
whismanoid 1:77f1ee332e4a 3190 {
whismanoid 1:77f1ee332e4a 3191 int16_t misoData16 = ScanRead();
whismanoid 1:77f1ee332e4a 3192 // For internal clock modes, the data format always includes the channel address.
whismanoid 1:77f1ee332e4a 3193 // misoData16 = CH[3:0] DATA[11:0]
whismanoid 1:77f1ee332e4a 3194 int16_t value_u12 = (misoData16 & 0x0FFF);
whismanoid 1:77f1ee332e4a 3195 int channelId = ((misoData16 >> 12) & 0x000F);
whismanoid 1:77f1ee332e4a 3196 Sx = Sx + value_u12;
whismanoid 1:77f1ee332e4a 3197 Sxx = Sxx + ((double)value_u12 * value_u12);
whismanoid 1:77f1ee332e4a 3198 }
whismanoid 1:77f1ee332e4a 3199 if (pd_Sx != 0) {
whismanoid 1:77f1ee332e4a 3200 *(pd_Sx) = Sx;
whismanoid 1:77f1ee332e4a 3201 }
whismanoid 1:77f1ee332e4a 3202 if (pd_Sxx != 0) {
whismanoid 1:77f1ee332e4a 3203 *(pd_Sxx) = Sxx;
whismanoid 1:77f1ee332e4a 3204 }
whismanoid 1:77f1ee332e4a 3205 if (pd_mean != 0) {
whismanoid 1:77f1ee332e4a 3206 *(pd_mean) = Sx / nWords;
whismanoid 1:77f1ee332e4a 3207 }
whismanoid 1:77f1ee332e4a 3208 if (nWords >= 2)
whismanoid 1:77f1ee332e4a 3209 {
whismanoid 1:77f1ee332e4a 3210 if (pd_variance != 0) {
whismanoid 1:77f1ee332e4a 3211 // TODO1: is this variance calculation too naive to work reliably?
whismanoid 1:77f1ee332e4a 3212 // see https://en.wikipedia.org/wiki/Algorithms_for_calculating_variance
whismanoid 1:77f1ee332e4a 3213 *(pd_variance) = (Sxx - ( Sx * Sx / nWords) ) / (nWords - 1);
whismanoid 1:77f1ee332e4a 3214 }
whismanoid 1:77f1ee332e4a 3215 if (pd_stddev != 0) {
whismanoid 9:8d47cb713984 3216 extern double sqrt(double);
whismanoid 1:77f1ee332e4a 3217 *(pd_stddev) = sqrt( *(pd_variance) );
whismanoid 1:77f1ee332e4a 3218 }
whismanoid 1:77f1ee332e4a 3219 }
whismanoid 1:77f1ee332e4a 3220 }
whismanoid 1:77f1ee332e4a 3221
whismanoid 1:77f1ee332e4a 3222
whismanoid 1:77f1ee332e4a 3223 // End of file