MAX11131 - Maxim Integrated MAX11131 SPI 12-bit 16-channel A…

Maxim Integrated » Code » MAX11131

Maxim Integrated MAX11131 SPI 12-bit 16-channel ADC with SampleSet

Dependents: MAX11131BOB_Tester MAX11131BOB_12bit_16ch_SampleSet_SPI_ADC MAX11131BOB_Serial_Tester

MAX11131.cpp@0:f7d706d2904d, 2019-06-05 (annotated)

Committer:: whismanoid
Date:: Wed Jun 05 02:16:46 2019 +0000
Revision:: 0:f7d706d2904d
Child:: 1:77f1ee332e4a

initial commit

Who changed what in which revision?

User	Revision	Line number	New contents of line
whismanoid	0:f7d706d2904d	1	// /*******************************************************************************
whismanoid	0:f7d706d2904d	2	// * Copyright (C) 2019 Maxim Integrated Products, Inc., All Rights Reserved.
whismanoid	0:f7d706d2904d	3	// *
whismanoid	0:f7d706d2904d	4	// * Permission is hereby granted, free of charge, to any person obtaining a
whismanoid	0:f7d706d2904d	5	// * copy of this software and associated documentation files (the "Software"),
whismanoid	0:f7d706d2904d	6	// * to deal in the Software without restriction, including without limitation
whismanoid	0:f7d706d2904d	7	// * the rights to use, copy, modify, merge, publish, distribute, sublicense,
whismanoid	0:f7d706d2904d	8	// * and/or sell copies of the Software, and to permit persons to whom the
whismanoid	0:f7d706d2904d	9	// * Software is furnished to do so, subject to the following conditions:
whismanoid	0:f7d706d2904d	10	// *
whismanoid	0:f7d706d2904d	11	// * The above copyright notice and this permission notice shall be included
whismanoid	0:f7d706d2904d	12	// * in all copies or substantial portions of the Software.
whismanoid	0:f7d706d2904d	13	// *
whismanoid	0:f7d706d2904d	14	// * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
whismanoid	0:f7d706d2904d	15	// * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
whismanoid	0:f7d706d2904d	16	// * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
whismanoid	0:f7d706d2904d	17	// * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
whismanoid	0:f7d706d2904d	18	// * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
whismanoid	0:f7d706d2904d	19	// * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
whismanoid	0:f7d706d2904d	20	// * OTHER DEALINGS IN THE SOFTWARE.
whismanoid	0:f7d706d2904d	21	// *
whismanoid	0:f7d706d2904d	22	// * Except as contained in this notice, the name of Maxim Integrated
whismanoid	0:f7d706d2904d	23	// * Products, Inc. shall not be used except as stated in the Maxim Integrated
whismanoid	0:f7d706d2904d	24	// * Products, Inc. Branding Policy.
whismanoid	0:f7d706d2904d	25	// *
whismanoid	0:f7d706d2904d	26	// * The mere transfer of this software does not imply any licenses
whismanoid	0:f7d706d2904d	27	// * of trade secrets, proprietary technology, copyrights, patents,
whismanoid	0:f7d706d2904d	28	// * trademarks, maskwork rights, or any other form of intellectual
whismanoid	0:f7d706d2904d	29	// * property whatsoever. Maxim Integrated Products, Inc. retains all
whismanoid	0:f7d706d2904d	30	// * ownership rights.
whismanoid	0:f7d706d2904d	31	// *******************************************************************************
whismanoid	0:f7d706d2904d	32	// */
whismanoid	0:f7d706d2904d	33	// *********************************************************************
whismanoid	0:f7d706d2904d	34	// @file MAX11131.cpp
whismanoid	0:f7d706d2904d	35	// *********************************************************************
whismanoid	0:f7d706d2904d	36	// Device Driver file
whismanoid	0:f7d706d2904d	37	// DO NOT EDIT; except areas designated "CUSTOMIZE". Automatically generated file.
whismanoid	0:f7d706d2904d	38	// generated by XMLSystemOfDevicesToMBED.py
whismanoid	0:f7d706d2904d	39	// System Name = ExampleSystem
whismanoid	0:f7d706d2904d	40	// System Description = Device driver example
whismanoid	0:f7d706d2904d	41
whismanoid	0:f7d706d2904d	42	#include "MAX11131.h"
whismanoid	0:f7d706d2904d	43
whismanoid	0:f7d706d2904d	44	// Device Name = MAX11131
whismanoid	0:f7d706d2904d	45	// Device Description = 3Msps, Low-Power, Serial SPI 12-Bit, 16-Channel, Differential/Single-Ended Input, SAR ADC
whismanoid	0:f7d706d2904d	46	// Device Manufacturer = Maxim Integrated
whismanoid	0:f7d706d2904d	47	// Device PartNumber = MAX11131ATI+
whismanoid	0:f7d706d2904d	48	// Device RegValue_Width = DataWidth16bit_HL
whismanoid	0:f7d706d2904d	49	//
whismanoid	0:f7d706d2904d	50	// ADC MaxOutputDataRate = 3Msps
whismanoid	0:f7d706d2904d	51	// ADC NumChannels = 16
whismanoid	0:f7d706d2904d	52	// ADC ResolutionBits = 12
whismanoid	0:f7d706d2904d	53	//
whismanoid	0:f7d706d2904d	54	// SPI CS = ActiveLow
whismanoid	0:f7d706d2904d	55	// SPI FrameStart = CS
whismanoid	0:f7d706d2904d	56	// SPI CPOL = 1
whismanoid	0:f7d706d2904d	57	// SPI CPHA = 1
whismanoid	0:f7d706d2904d	58	// SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid	0:f7d706d2904d	59	// SPI SCLK Idle High
whismanoid	0:f7d706d2904d	60	// SPI SCLKMaxMHz = 48
whismanoid	0:f7d706d2904d	61	// SPI SCLKMinMHz = 0.48
whismanoid	0:f7d706d2904d	62	//
whismanoid	0:f7d706d2904d	63	// InputPin Name = CNVST
whismanoid	0:f7d706d2904d	64	// InputPin Description = Active-Low Conversion Start Input/Analog Input 14
whismanoid	0:f7d706d2904d	65	// InputPin Function = Trigger
whismanoid	0:f7d706d2904d	66	//
whismanoid	0:f7d706d2904d	67	// InputPin Name = REF+
whismanoid	0:f7d706d2904d	68	// InputPin Description = External Positive Reference Input. Apply a reference voltage at REF+. Bypass to GND with a 0.47uF capacitor.
whismanoid	0:f7d706d2904d	69	// InputPin Function = Reference
whismanoid	0:f7d706d2904d	70	//
whismanoid	0:f7d706d2904d	71	// InputPin Name = REF-/AIN15
whismanoid	0:f7d706d2904d	72	// InputPin Description = External Differential Reference Negative Input/Analog Input 15
whismanoid	0:f7d706d2904d	73	// InputPin Function = Reference
whismanoid	0:f7d706d2904d	74	//
whismanoid	0:f7d706d2904d	75	// OutputPin Name = EOC
whismanoid	0:f7d706d2904d	76	// OutputPin Description = End of Conversion Output. Data is valid after EOC pulls low (Internal clock mode only).
whismanoid	0:f7d706d2904d	77	// OutputPin Function = Event
whismanoid	0:f7d706d2904d	78	//
whismanoid	0:f7d706d2904d	79	// SupplyPin Name = VDD
whismanoid	0:f7d706d2904d	80	// SupplyPin Description = Power-Supply Input. Bypass to GND with a 10uF in parallel with a 0.1uF capacitors.
whismanoid	0:f7d706d2904d	81	// SupplyPin VinMax = 3.6
whismanoid	0:f7d706d2904d	82	// SupplyPin VinMin = 2.35
whismanoid	0:f7d706d2904d	83	// SupplyPin Function = Analog
whismanoid	0:f7d706d2904d	84	//
whismanoid	0:f7d706d2904d	85	// SupplyPin Name = OVDD
whismanoid	0:f7d706d2904d	86	// SupplyPin Description = Interface Digital Power-Supply Input. Bypass to GND with a 10uF in parallel with a 0.1uF capacitors.
whismanoid	0:f7d706d2904d	87	// SupplyPin VinMax = 3.6
whismanoid	0:f7d706d2904d	88	// SupplyPin VinMin = 1.5
whismanoid	0:f7d706d2904d	89	// SupplyPin Function = Digital
whismanoid	0:f7d706d2904d	90	//
whismanoid	0:f7d706d2904d	91
whismanoid	0:f7d706d2904d	92	// CODE GENERATOR: class constructor definition
whismanoid	0:f7d706d2904d	93	MAX11131::MAX11131(SPI &spi, DigitalOut &cs_pin, // SPI interface
whismanoid	0:f7d706d2904d	94	// CODE GENERATOR: class constructor definition gpio InputPin pins
whismanoid	0:f7d706d2904d	95	DigitalOut &CNVST_pin, // Digital Trigger Input to MAX11131 device
whismanoid	0:f7d706d2904d	96	// AnalogOut &REF__pin, // Reference Input to MAX11131 device
whismanoid	0:f7d706d2904d	97	// AnalogOut &REF__AIN15_pin, // Reference Input to MAX11131 device
whismanoid	0:f7d706d2904d	98	// CODE GENERATOR: class constructor definition gpio OutputPin pins
whismanoid	0:f7d706d2904d	99	DigitalIn &EOC_pin, // Digital Event Output from MAX11131 device
whismanoid	0:f7d706d2904d	100	// CODE GENERATOR: class constructor definition ic_variant
whismanoid	0:f7d706d2904d	101	MAX11131_ic_t ic_variant)
whismanoid	0:f7d706d2904d	102	// CODE GENERATOR: class constructor initializer list
whismanoid	0:f7d706d2904d	103	: m_spi(spi), m_cs_pin(cs_pin), // SPI interface
whismanoid	0:f7d706d2904d	104	// CODE GENERATOR: class constructor initializer list gpio InputPin pins
whismanoid	0:f7d706d2904d	105	m_CNVST_pin(CNVST_pin), // Digital Trigger Input to MAX11131 device
whismanoid	0:f7d706d2904d	106	// m_REF__pin(REF__pin), // Reference Input to MAX11131 device
whismanoid	0:f7d706d2904d	107	// m_REF__AIN15_pin(REF__AIN15_pin), // Reference Input to MAX11131 device
whismanoid	0:f7d706d2904d	108	// CODE GENERATOR: class constructor initializer list gpio OutputPin pins
whismanoid	0:f7d706d2904d	109	m_EOC_pin(EOC_pin), // Digital Event Output from MAX11131 device
whismanoid	0:f7d706d2904d	110	// CODE GENERATOR: class constructor initializer list ic_variant
whismanoid	0:f7d706d2904d	111	m_ic_variant(ic_variant)
whismanoid	0:f7d706d2904d	112	{
whismanoid	0:f7d706d2904d	113	// CODE GENERATOR: class constructor definition SPI interface initialization
whismanoid	0:f7d706d2904d	114	//
whismanoid	0:f7d706d2904d	115	// SPI CS = ActiveLow
whismanoid	0:f7d706d2904d	116	// SPI FrameStart = CS
whismanoid	0:f7d706d2904d	117	m_SPI_cs_state = 1;
whismanoid	0:f7d706d2904d	118	m_cs_pin = m_SPI_cs_state;
whismanoid	0:f7d706d2904d	119
whismanoid	0:f7d706d2904d	120	// SPI CPOL = 1
whismanoid	0:f7d706d2904d	121	// SPI CPHA = 1
whismanoid	0:f7d706d2904d	122	// SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid	0:f7d706d2904d	123	// SPI SCLK Idle High
whismanoid	0:f7d706d2904d	124	m_SPI_dataMode = 3; //SPI_MODE3 // CPOL=1,CPHA=1: Rising Edge stable; SCLK idle High
whismanoid	0:f7d706d2904d	125	m_spi.format(8,m_SPI_dataMode); // int bits_must_be_8, int mode=0_3 CPOL=0,CPHA=0
whismanoid	0:f7d706d2904d	126
whismanoid	0:f7d706d2904d	127	// SPI SCLKMaxMHz = 48
whismanoid	0:f7d706d2904d	128	// SPI SCLKMinMHz = 0.48
whismanoid	0:f7d706d2904d	129	//#define SPI_SCLK_Hz 48000000 // 48MHz
whismanoid	0:f7d706d2904d	130	//#define SPI_SCLK_Hz 24000000 // 24MHz
whismanoid	0:f7d706d2904d	131	//#define SPI_SCLK_Hz 12000000 // 12MHz
whismanoid	0:f7d706d2904d	132	//#define SPI_SCLK_Hz 4000000 // 4MHz
whismanoid	0:f7d706d2904d	133	//#define SPI_SCLK_Hz 2000000 // 2MHz
whismanoid	0:f7d706d2904d	134	//#define SPI_SCLK_Hz 1000000 // 1MHz
whismanoid	0:f7d706d2904d	135	m_SPI_SCLK_Hz = 12000000; // 12MHz; MAX11131 limit is 48MHz
whismanoid	0:f7d706d2904d	136	m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid	0:f7d706d2904d	137
whismanoid	0:f7d706d2904d	138	// TODO1: CODE GENERATOR: class constructor definition gpio InputPin (Input to device) initialization
whismanoid	0:f7d706d2904d	139	//
whismanoid	0:f7d706d2904d	140	m_CNVST_pin = 1; // output logic high -- initial value in constructor
whismanoid	0:f7d706d2904d	141	}
whismanoid	0:f7d706d2904d	142
whismanoid	0:f7d706d2904d	143	// CODE GENERATOR: class destructor definition
whismanoid	0:f7d706d2904d	144	MAX11131::~MAX11131()
whismanoid	0:f7d706d2904d	145	{
whismanoid	0:f7d706d2904d	146	// do nothing
whismanoid	0:f7d706d2904d	147	}
whismanoid	0:f7d706d2904d	148
whismanoid	0:f7d706d2904d	149	// CODE GENERATOR: spi_frequency setter definition
whismanoid	0:f7d706d2904d	150	// set SPI SCLK frequency
whismanoid	0:f7d706d2904d	151	void MAX11131::spi_frequency(int spi_sclk_Hz)
whismanoid	0:f7d706d2904d	152	{
whismanoid	0:f7d706d2904d	153	m_SPI_SCLK_Hz = spi_sclk_Hz;
whismanoid	0:f7d706d2904d	154	m_spi.frequency(m_SPI_SCLK_Hz);
whismanoid	0:f7d706d2904d	155	}
whismanoid	0:f7d706d2904d	156
whismanoid	0:f7d706d2904d	157	// CODE GENERATOR: omit global g_MAX11131_device
whismanoid	0:f7d706d2904d	158	// CODE GENERATOR: extern function declarations
whismanoid	0:f7d706d2904d	159	// CODE GENERATOR: extern function requirement MAX11131::SPIoutputCS
whismanoid	0:f7d706d2904d	160	// Assert SPI Chip Select
whismanoid	0:f7d706d2904d	161	// SPI chip-select for MAX11131
whismanoid	0:f7d706d2904d	162	//
whismanoid	0:f7d706d2904d	163	void MAX11131::SPIoutputCS(int isLogicHigh)
whismanoid	0:f7d706d2904d	164	{
whismanoid	0:f7d706d2904d	165	// CODE GENERATOR: extern function definition for function SPIoutputCS
whismanoid	0:f7d706d2904d	166	// CODE GENERATOR: extern function definition for standard SPI interface function SPIoutputCS(int isLogicHigh)
whismanoid	0:f7d706d2904d	167	m_SPI_cs_state = isLogicHigh;
whismanoid	0:f7d706d2904d	168	m_cs_pin = m_SPI_cs_state;
whismanoid	0:f7d706d2904d	169	}
whismanoid	0:f7d706d2904d	170
whismanoid	0:f7d706d2904d	171	// CODE GENERATOR: extern function requirement MAX11131::SPIwrite16bits
whismanoid	0:f7d706d2904d	172	// SPI write 16 bits
whismanoid	0:f7d706d2904d	173	// SPI interface to MAX11131 shift 16 bits mosiData16 into MAX11131 DIN
whismanoid	0:f7d706d2904d	174	// ignoring MAX11131 DOUT
whismanoid	0:f7d706d2904d	175	//
whismanoid	0:f7d706d2904d	176	void MAX11131::SPIwrite16bits(int16_t mosiData16)
whismanoid	0:f7d706d2904d	177	{
whismanoid	0:f7d706d2904d	178	// CODE GENERATOR: extern function definition for function SPIwrite16bits
whismanoid	0:f7d706d2904d	179	// TODO1: CODE GENERATOR: extern function definition for standard SPI interface function SPIwrite16bits(int16_t mosiData16)
whismanoid	0:f7d706d2904d	180	size_t byteCount = 2;
whismanoid	0:f7d706d2904d	181	static char mosiData[2];
whismanoid	0:f7d706d2904d	182	static char misoData[2];
whismanoid	0:f7d706d2904d	183	mosiData[0] = (char)((mosiData16 >> 8) & 0xFF); // MSByte
whismanoid	0:f7d706d2904d	184	mosiData[1] = (char)((mosiData16 >> 0) & 0xFF); // LSByte
whismanoid	0:f7d706d2904d	185	//
whismanoid	0:f7d706d2904d	186	// Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid	0:f7d706d2904d	187	//~ noInterrupts();
whismanoid	0:f7d706d2904d	188	//
whismanoid	0:f7d706d2904d	189	//~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid	0:f7d706d2904d	190	//
whismanoid	0:f7d706d2904d	191	unsigned int numBytesTransferred = m_spi.write(mosiData, byteCount, misoData, byteCount);
whismanoid	0:f7d706d2904d	192	//~ m_spi.transfer(mosiData8_FF0000);
whismanoid	0:f7d706d2904d	193	//~ m_spi.transfer(mosiData16_00FF00);
whismanoid	0:f7d706d2904d	194	//~ m_spi.transfer(mosiData16_0000FF);
whismanoid	0:f7d706d2904d	195	//
whismanoid	0:f7d706d2904d	196	//~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid	0:f7d706d2904d	197	//
whismanoid	0:f7d706d2904d	198	// Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid	0:f7d706d2904d	199	//~ interrupts();
whismanoid	0:f7d706d2904d	200	//
whismanoid	0:f7d706d2904d	201	// VERIFY: SPIwrite24bits print diagnostic information
whismanoid	0:f7d706d2904d	202	//cmdLine.serial().printf(" MOSI->"));
whismanoid	0:f7d706d2904d	203	//cmdLine.serial().printf(" 0x"));
whismanoid	0:f7d706d2904d	204	//Serial.print( (mosiData8_FF0000 & 0xFF), HEX);
whismanoid	0:f7d706d2904d	205	//cmdLine.serial().printf(" 0x"));
whismanoid	0:f7d706d2904d	206	//Serial.print( (mosiData16_00FF00 & 0xFF), HEX);
whismanoid	0:f7d706d2904d	207	//cmdLine.serial().printf(" 0x"));
whismanoid	0:f7d706d2904d	208	//Serial.print( (mosiData16_0000FF & 0xFF), HEX);
whismanoid	0:f7d706d2904d	209	// hex dump mosiData[0..byteCount-1]
whismanoid	0:f7d706d2904d	210	#if 0 // HAS_MICROUSBSERIAL
whismanoid	0:f7d706d2904d	211	cmdLine_microUSBserial.serial().printf("\r\nSPI");
whismanoid	0:f7d706d2904d	212	if (byteCount > 7) {
whismanoid	0:f7d706d2904d	213	cmdLine_microUSBserial.serial().printf(" byteCount:%d", byteCount);
whismanoid	0:f7d706d2904d	214	}
whismanoid	0:f7d706d2904d	215	cmdLine_microUSBserial.serial().printf(" MOSI->");
whismanoid	0:f7d706d2904d	216	for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid	0:f7d706d2904d	217	{
whismanoid	0:f7d706d2904d	218	cmdLine_microUSBserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid	0:f7d706d2904d	219	}
whismanoid	0:f7d706d2904d	220	// hex dump misoData[0..byteCount-1]
whismanoid	0:f7d706d2904d	221	cmdLine_microUSBserial.serial().printf(" MISO<-");
whismanoid	0:f7d706d2904d	222	for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid	0:f7d706d2904d	223	{
whismanoid	0:f7d706d2904d	224	cmdLine_microUSBserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid	0:f7d706d2904d	225	}
whismanoid	0:f7d706d2904d	226	cmdLine_microUSBserial.serial().printf(" ");
whismanoid	0:f7d706d2904d	227	#endif
whismanoid	0:f7d706d2904d	228	#if 0 // HAS_DAPLINK_SERIAL
whismanoid	0:f7d706d2904d	229	cmdLine_DAPLINKserial.serial().printf("\r\nSPI");
whismanoid	0:f7d706d2904d	230	if (byteCount > 7) {
whismanoid	0:f7d706d2904d	231	cmdLine_DAPLINKserial.serial().printf(" byteCount:%d", byteCount);
whismanoid	0:f7d706d2904d	232	}
whismanoid	0:f7d706d2904d	233	cmdLine_DAPLINKserial.serial().printf(" MOSI->");
whismanoid	0:f7d706d2904d	234	for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid	0:f7d706d2904d	235	{
whismanoid	0:f7d706d2904d	236	cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid	0:f7d706d2904d	237	}
whismanoid	0:f7d706d2904d	238	// hex dump misoData[0..byteCount-1]
whismanoid	0:f7d706d2904d	239	cmdLine_DAPLINKserial.serial().printf(" MISO<-");
whismanoid	0:f7d706d2904d	240	for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid	0:f7d706d2904d	241	{
whismanoid	0:f7d706d2904d	242	cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid	0:f7d706d2904d	243	}
whismanoid	0:f7d706d2904d	244	cmdLine_DAPLINKserial.serial().printf(" ");
whismanoid	0:f7d706d2904d	245	#endif
whismanoid	0:f7d706d2904d	246	// VERIFY: DIAGNOSTIC: print MAX5715 device register write
whismanoid	0:f7d706d2904d	247	// TODO: MAX5715_print_register_verbose(mosiData8_FF0000, mosiData16_00FFFF);
whismanoid	0:f7d706d2904d	248	// TODO: print_verbose_SPI_diagnostic(mosiData16_FF00, mosiData16_00FF, misoData16_FF00, misoData16_00FF);
whismanoid	0:f7d706d2904d	249	//
whismanoid	0:f7d706d2904d	250	// int misoData16 = (misoData16_FF00 << 8) \| misoData16_00FF;
whismanoid	0:f7d706d2904d	251	// return misoData16;
whismanoid	0:f7d706d2904d	252	}
whismanoid	0:f7d706d2904d	253
whismanoid	0:f7d706d2904d	254	// CODE GENERATOR: extern function requirement MAX11131::SPIwrite24bits
whismanoid	0:f7d706d2904d	255	// SPI write 17-24 bits
whismanoid	0:f7d706d2904d	256	// SPI interface to MAX11131 shift 16 bits mosiData16 into MAX11131 DIN
whismanoid	0:f7d706d2904d	257	// followed by one additional SCLK byte.
whismanoid	0:f7d706d2904d	258	// ignoring MAX11131 DOUT
whismanoid	0:f7d706d2904d	259	//
whismanoid	0:f7d706d2904d	260	void MAX11131::SPIwrite24bits(int16_t mosiData16_FFFF00, int8_t mosiData8_0000FF)
whismanoid	0:f7d706d2904d	261	{
whismanoid	0:f7d706d2904d	262	// CODE GENERATOR: extern function definition for function SPIwrite24bits
whismanoid	0:f7d706d2904d	263	// TODO1: CODE GENERATOR: extern function definition for standard SPI interface function SPIwrite24bits(int16_t mosiData16_FFFF00, int8_t mosiData8_0000FF)
whismanoid	0:f7d706d2904d	264	// TODO: implement SPIwrite24bits(int16_t mosiData16_FFFF00, int8_t mosiData8_0000FF)
whismanoid	0:f7d706d2904d	265	size_t byteCount = 3;
whismanoid	0:f7d706d2904d	266	static char mosiData[3];
whismanoid	0:f7d706d2904d	267	static char misoData[3];
whismanoid	0:f7d706d2904d	268	mosiData[0] = (char)((mosiData16_FFFF00 >> 8) & 0xFF); // MSByte
whismanoid	0:f7d706d2904d	269	mosiData[1] = (char)((mosiData16_FFFF00 >> 0) & 0xFF); // LSByte
whismanoid	0:f7d706d2904d	270	mosiData[2] = mosiData8_0000FF;
whismanoid	0:f7d706d2904d	271	//
whismanoid	0:f7d706d2904d	272	// Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid	0:f7d706d2904d	273	//~ noInterrupts();
whismanoid	0:f7d706d2904d	274	//
whismanoid	0:f7d706d2904d	275	//~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid	0:f7d706d2904d	276	//
whismanoid	0:f7d706d2904d	277	unsigned int numBytesTransferred = m_spi.write(mosiData, byteCount, misoData, byteCount);
whismanoid	0:f7d706d2904d	278	//~ m_spi.transfer(mosiData8_FF0000);
whismanoid	0:f7d706d2904d	279	//~ m_spi.transfer(mosiData16_00FF00);
whismanoid	0:f7d706d2904d	280	//~ m_spi.transfer(mosiData16_0000FF);
whismanoid	0:f7d706d2904d	281	//
whismanoid	0:f7d706d2904d	282	//~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid	0:f7d706d2904d	283	//
whismanoid	0:f7d706d2904d	284	// Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid	0:f7d706d2904d	285	//~ interrupts();
whismanoid	0:f7d706d2904d	286	//
whismanoid	0:f7d706d2904d	287	// VERIFY: SPIwrite24bits print diagnostic information
whismanoid	0:f7d706d2904d	288	//cmdLine.serial().printf(" MOSI->"));
whismanoid	0:f7d706d2904d	289	//cmdLine.serial().printf(" 0x"));
whismanoid	0:f7d706d2904d	290	//Serial.print( (mosiData8_FF0000 & 0xFF), HEX);
whismanoid	0:f7d706d2904d	291	//cmdLine.serial().printf(" 0x"));
whismanoid	0:f7d706d2904d	292	//Serial.print( (mosiData16_00FF00 & 0xFF), HEX);
whismanoid	0:f7d706d2904d	293	//cmdLine.serial().printf(" 0x"));
whismanoid	0:f7d706d2904d	294	//Serial.print( (mosiData16_0000FF & 0xFF), HEX);
whismanoid	0:f7d706d2904d	295	// hex dump mosiData[0..byteCount-1]
whismanoid	0:f7d706d2904d	296	#if 0 // HAS_MICROUSBSERIAL
whismanoid	0:f7d706d2904d	297	cmdLine_microUSBserial.serial().printf("\r\nSPI");
whismanoid	0:f7d706d2904d	298	if (byteCount > 7) {
whismanoid	0:f7d706d2904d	299	cmdLine_microUSBserial.serial().printf(" byteCount:%d", byteCount);
whismanoid	0:f7d706d2904d	300	}
whismanoid	0:f7d706d2904d	301	cmdLine_microUSBserial.serial().printf(" MOSI->");
whismanoid	0:f7d706d2904d	302	for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid	0:f7d706d2904d	303	{
whismanoid	0:f7d706d2904d	304	cmdLine_microUSBserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid	0:f7d706d2904d	305	}
whismanoid	0:f7d706d2904d	306	// hex dump misoData[0..byteCount-1]
whismanoid	0:f7d706d2904d	307	cmdLine_microUSBserial.serial().printf(" MISO<-");
whismanoid	0:f7d706d2904d	308	for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid	0:f7d706d2904d	309	{
whismanoid	0:f7d706d2904d	310	cmdLine_microUSBserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid	0:f7d706d2904d	311	}
whismanoid	0:f7d706d2904d	312	cmdLine_microUSBserial.serial().printf(" ");
whismanoid	0:f7d706d2904d	313	#endif
whismanoid	0:f7d706d2904d	314	#if 0 // HAS_DAPLINK_SERIAL
whismanoid	0:f7d706d2904d	315	cmdLine_DAPLINKserial.serial().printf("\r\nSPI");
whismanoid	0:f7d706d2904d	316	if (byteCount > 7) {
whismanoid	0:f7d706d2904d	317	cmdLine_DAPLINKserial.serial().printf(" byteCount:%d", byteCount);
whismanoid	0:f7d706d2904d	318	}
whismanoid	0:f7d706d2904d	319	cmdLine_DAPLINKserial.serial().printf(" MOSI->");
whismanoid	0:f7d706d2904d	320	for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid	0:f7d706d2904d	321	{
whismanoid	0:f7d706d2904d	322	cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid	0:f7d706d2904d	323	}
whismanoid	0:f7d706d2904d	324	// hex dump misoData[0..byteCount-1]
whismanoid	0:f7d706d2904d	325	cmdLine_DAPLINKserial.serial().printf(" MISO<-");
whismanoid	0:f7d706d2904d	326	for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid	0:f7d706d2904d	327	{
whismanoid	0:f7d706d2904d	328	cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid	0:f7d706d2904d	329	}
whismanoid	0:f7d706d2904d	330	cmdLine_DAPLINKserial.serial().printf(" ");
whismanoid	0:f7d706d2904d	331	#endif
whismanoid	0:f7d706d2904d	332	// VERIFY: DIAGNOSTIC: print MAX5715 device register write
whismanoid	0:f7d706d2904d	333	// TODO: MAX5715_print_register_verbose(mosiData8_FF0000, mosiData16_00FFFF);
whismanoid	0:f7d706d2904d	334	//
whismanoid	0:f7d706d2904d	335	// int misoData16 = (misoData16_FF00 << 8) \| misoData16_00FF;
whismanoid	0:f7d706d2904d	336	// return misoData16;
whismanoid	0:f7d706d2904d	337	}
whismanoid	0:f7d706d2904d	338
whismanoid	0:f7d706d2904d	339	// CODE GENERATOR: extern function requirement MAX11131::SPIread16bits
whismanoid	0:f7d706d2904d	340	// SPI read 16 bits while MOSI (MAX11131 DIN) is 0
whismanoid	0:f7d706d2904d	341	// SPI interface to capture 16 bits miso data from MAX11131 DOUT
whismanoid	0:f7d706d2904d	342	//
whismanoid	0:f7d706d2904d	343	int16_t MAX11131::SPIread16bits()
whismanoid	0:f7d706d2904d	344	{
whismanoid	0:f7d706d2904d	345	// CODE GENERATOR: extern function definition for function SPIread16bits
whismanoid	0:f7d706d2904d	346	// TODO1: CODE GENERATOR: extern function definition for standard SPI interface function int16_t SPIread16bits()
whismanoid	0:f7d706d2904d	347	int mosiData16 = 0;
whismanoid	0:f7d706d2904d	348	size_t byteCount = 2;
whismanoid	0:f7d706d2904d	349	static char mosiData[2];
whismanoid	0:f7d706d2904d	350	static char misoData[2];
whismanoid	0:f7d706d2904d	351	mosiData[0] = (char)((mosiData16 >> 8) & 0xFF); // MSByte
whismanoid	0:f7d706d2904d	352	mosiData[1] = (char)((mosiData16 >> 0) & 0xFF); // LSByte
whismanoid	0:f7d706d2904d	353	//
whismanoid	0:f7d706d2904d	354	// Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid	0:f7d706d2904d	355	//~ noInterrupts();
whismanoid	0:f7d706d2904d	356	//
whismanoid	0:f7d706d2904d	357	//~ digitalWrite(Scope_Trigger_Pin, LOW); // diagnostic Scope_Trigger_Pin
whismanoid	0:f7d706d2904d	358	//
whismanoid	0:f7d706d2904d	359	unsigned int numBytesTransferred = m_spi.write(mosiData, byteCount, misoData, byteCount);
whismanoid	0:f7d706d2904d	360	//~ m_spi.transfer(mosiData8_FF0000);
whismanoid	0:f7d706d2904d	361	//~ m_spi.transfer(mosiData16_00FF00);
whismanoid	0:f7d706d2904d	362	//~ m_spi.transfer(mosiData16_0000FF);
whismanoid	0:f7d706d2904d	363	//
whismanoid	0:f7d706d2904d	364	//~ digitalWrite(Scope_Trigger_Pin, HIGH); // diagnostic Scope_Trigger_Pin
whismanoid	0:f7d706d2904d	365	//
whismanoid	0:f7d706d2904d	366	// Arduino: begin critical section: noInterrupts() masks all interrupt sources; end critical section with interrupts()
whismanoid	0:f7d706d2904d	367	//~ interrupts();
whismanoid	0:f7d706d2904d	368	//
whismanoid	0:f7d706d2904d	369	// VERIFY: SPIwrite24bits print diagnostic information
whismanoid	0:f7d706d2904d	370	//cmdLine.serial().printf(" MOSI->"));
whismanoid	0:f7d706d2904d	371	//cmdLine.serial().printf(" 0x"));
whismanoid	0:f7d706d2904d	372	//Serial.print( (mosiData8_FF0000 & 0xFF), HEX);
whismanoid	0:f7d706d2904d	373	//cmdLine.serial().printf(" 0x"));
whismanoid	0:f7d706d2904d	374	//Serial.print( (mosiData16_00FF00 & 0xFF), HEX);
whismanoid	0:f7d706d2904d	375	//cmdLine.serial().printf(" 0x"));
whismanoid	0:f7d706d2904d	376	//Serial.print( (mosiData16_0000FF & 0xFF), HEX);
whismanoid	0:f7d706d2904d	377	// hex dump mosiData[0..byteCount-1]
whismanoid	0:f7d706d2904d	378	#if 0 // HAS_MICROUSBSERIAL
whismanoid	0:f7d706d2904d	379	cmdLine_microUSBserial.serial().printf("\r\nSPI");
whismanoid	0:f7d706d2904d	380	if (byteCount > 7) {
whismanoid	0:f7d706d2904d	381	cmdLine_microUSBserial.serial().printf(" byteCount:%d", byteCount);
whismanoid	0:f7d706d2904d	382	}
whismanoid	0:f7d706d2904d	383	cmdLine_microUSBserial.serial().printf(" MOSI->");
whismanoid	0:f7d706d2904d	384	for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid	0:f7d706d2904d	385	{
whismanoid	0:f7d706d2904d	386	cmdLine_microUSBserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid	0:f7d706d2904d	387	}
whismanoid	0:f7d706d2904d	388	// hex dump misoData[0..byteCount-1]
whismanoid	0:f7d706d2904d	389	cmdLine_microUSBserial.serial().printf(" MISO<-");
whismanoid	0:f7d706d2904d	390	for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid	0:f7d706d2904d	391	{
whismanoid	0:f7d706d2904d	392	cmdLine_microUSBserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid	0:f7d706d2904d	393	}
whismanoid	0:f7d706d2904d	394	cmdLine_microUSBserial.serial().printf(" ");
whismanoid	0:f7d706d2904d	395	#endif
whismanoid	0:f7d706d2904d	396	#if 0 // HAS_DAPLINK_SERIAL
whismanoid	0:f7d706d2904d	397	cmdLine_DAPLINKserial.serial().printf("\r\nSPI");
whismanoid	0:f7d706d2904d	398	if (byteCount > 7) {
whismanoid	0:f7d706d2904d	399	cmdLine_DAPLINKserial.serial().printf(" byteCount:%d", byteCount);
whismanoid	0:f7d706d2904d	400	}
whismanoid	0:f7d706d2904d	401	cmdLine_DAPLINKserial.serial().printf(" MOSI->");
whismanoid	0:f7d706d2904d	402	for (unsigned int byteIndex = 0; byteIndex < byteCount; byteIndex++)
whismanoid	0:f7d706d2904d	403	{
whismanoid	0:f7d706d2904d	404	cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", mosiData[byteIndex]);
whismanoid	0:f7d706d2904d	405	}
whismanoid	0:f7d706d2904d	406	// hex dump misoData[0..byteCount-1]
whismanoid	0:f7d706d2904d	407	cmdLine_DAPLINKserial.serial().printf(" MISO<-");
whismanoid	0:f7d706d2904d	408	for (unsigned int byteIndex = 0; byteIndex < numBytesTransferred; byteIndex++)
whismanoid	0:f7d706d2904d	409	{
whismanoid	0:f7d706d2904d	410	cmdLine_DAPLINKserial.serial().printf(" 0x%2.2X", misoData[byteIndex]);
whismanoid	0:f7d706d2904d	411	}
whismanoid	0:f7d706d2904d	412	cmdLine_DAPLINKserial.serial().printf(" ");
whismanoid	0:f7d706d2904d	413	#endif
whismanoid	0:f7d706d2904d	414	// VERIFY: DIAGNOSTIC: print MAX5715 device register write
whismanoid	0:f7d706d2904d	415	// TODO: MAX5715_print_register_verbose(mosiData8_FF0000, mosiData16_00FFFF);
whismanoid	0:f7d706d2904d	416	// TODO: print_verbose_SPI_diagnostic(mosiData16_FF00, mosiData16_00FF, misoData16_FF00, misoData16_00FF);
whismanoid	0:f7d706d2904d	417	//
whismanoid	0:f7d706d2904d	418	int misoData16 = (misoData[0] << 8) \| misoData[1];
whismanoid	0:f7d706d2904d	419	return misoData16;
whismanoid	0:f7d706d2904d	420	}
whismanoid	0:f7d706d2904d	421
whismanoid	0:f7d706d2904d	422	// CODE GENERATOR: extern function requirement MAX11131::CNVSToutputPulseLow
whismanoid	0:f7d706d2904d	423	// Assert MAX11131 CNVST convert start.
whismanoid	0:f7d706d2904d	424	// Required when using any of the InternalClock modes with SWCNV 0.
whismanoid	0:f7d706d2904d	425	// Trigger measurement by driving CNVST/AIN14 pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	0:f7d706d2904d	426	//
whismanoid	0:f7d706d2904d	427	void MAX11131::CNVSToutputPulseLow()
whismanoid	0:f7d706d2904d	428	{
whismanoid	0:f7d706d2904d	429	// CODE GENERATOR: extern function definition for function CNVSToutputPulseLow
whismanoid	0:f7d706d2904d	430	// TODO1: CODE GENERATOR: extern function definition for gpio interface function CNVSToutputPulseLow
whismanoid	0:f7d706d2904d	431	// TODO1: CODE GENERATOR: gpio pin CNVST assuming member function m_CNVST_pin
whismanoid	0:f7d706d2904d	432	// TODO1: CODE GENERATOR: gpio direction output
whismanoid	0:f7d706d2904d	433	// m_CNVST_pin.output(); // only applicable to DigitalInOut
whismanoid	0:f7d706d2904d	434	// TODO1: CODE GENERATOR: gpio function PulseLow
whismanoid	0:f7d706d2904d	435	m_CNVST_pin = 0; // output logic low
whismanoid	0:f7d706d2904d	436	wait(0.01); // pulse low delay time
whismanoid	0:f7d706d2904d	437	m_CNVST_pin = 1; // output logic high
whismanoid	0:f7d706d2904d	438	}
whismanoid	0:f7d706d2904d	439
whismanoid	0:f7d706d2904d	440	// CODE GENERATOR: extern function requirement MAX11131::EOCinputWaitUntilLow
whismanoid	0:f7d706d2904d	441	// Wait for MAX11131 EOC pin low, indicating end of conversion.
whismanoid	0:f7d706d2904d	442	// Required when using any of the InternalClock modes.
whismanoid	0:f7d706d2904d	443	//
whismanoid	0:f7d706d2904d	444	void MAX11131::EOCinputWaitUntilLow()
whismanoid	0:f7d706d2904d	445	{
whismanoid	0:f7d706d2904d	446	// CODE GENERATOR: extern function definition for function EOCinputWaitUntilLow
whismanoid	0:f7d706d2904d	447	// TODO1: CODE GENERATOR: extern function definition for gpio interface function EOCinputWaitUntilLow
whismanoid	0:f7d706d2904d	448	// TODO1: CODE GENERATOR: gpio pin EOC assuming member function m_EOC_pin
whismanoid	0:f7d706d2904d	449	// TODO1: CODE GENERATOR: gpio direction input
whismanoid	0:f7d706d2904d	450	// m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid	0:f7d706d2904d	451	// TODO1: CODE GENERATOR: gpio function WaitUntilLow
whismanoid	0:f7d706d2904d	452	while (m_EOC_pin != 0)
whismanoid	0:f7d706d2904d	453	{
whismanoid	0:f7d706d2904d	454	// spinlock waiting for logic low pin state
whismanoid	0:f7d706d2904d	455	}
whismanoid	0:f7d706d2904d	456	}
whismanoid	0:f7d706d2904d	457
whismanoid	0:f7d706d2904d	458	// CODE GENERATOR: extern function requirement MAX11131::EOCinputValue
whismanoid	0:f7d706d2904d	459	// Return the status of the MAX11131 EOC pin.
whismanoid	0:f7d706d2904d	460	//
whismanoid	0:f7d706d2904d	461	int MAX11131::EOCinputValue()
whismanoid	0:f7d706d2904d	462	{
whismanoid	0:f7d706d2904d	463	// CODE GENERATOR: extern function definition for function EOCinputValue
whismanoid	0:f7d706d2904d	464	// TODO1: CODE GENERATOR: extern function definition for gpio interface function EOCinputValue
whismanoid	0:f7d706d2904d	465	// TODO1: CODE GENERATOR: gpio pin EOC assuming member function m_EOC_pin
whismanoid	0:f7d706d2904d	466	// TODO1: CODE GENERATOR: gpio direction input
whismanoid	0:f7d706d2904d	467	// m_EOC_pin.input(); // only applicable to DigitalInOut
whismanoid	0:f7d706d2904d	468	// TODO1: CODE GENERATOR: gpio function Value
whismanoid	0:f7d706d2904d	469	return m_EOC_pin.read();
whismanoid	0:f7d706d2904d	470	}
whismanoid	0:f7d706d2904d	471
whismanoid	0:f7d706d2904d	472	// CODE GENERATOR: class member function definitions
whismanoid	0:f7d706d2904d	473	//----------------------------------------
whismanoid	0:f7d706d2904d	474	// Initialize device
whismanoid	0:f7d706d2904d	475	void MAX11131::Init(void)
whismanoid	0:f7d706d2904d	476	{
whismanoid	0:f7d706d2904d	477
whismanoid	0:f7d706d2904d	478	//----------------------------------------
whismanoid	0:f7d706d2904d	479	// Nominal Full-Scale Voltage Reference
whismanoid	0:f7d706d2904d	480	VRef = 2.500;
whismanoid	0:f7d706d2904d	481
whismanoid	0:f7d706d2904d	482	//----------------------------------------
whismanoid	0:f7d706d2904d	483	// define write-only register ADC_MODE_CONTROL
whismanoid	0:f7d706d2904d	484	ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid	0:f7d706d2904d	485	const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid	0:f7d706d2904d	486	const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid	0:f7d706d2904d	487	const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	488	const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid	0:f7d706d2904d	489	const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid	0:f7d706d2904d	490	const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid	0:f7d706d2904d	491
whismanoid	0:f7d706d2904d	492	//----------------------------------------
whismanoid	0:f7d706d2904d	493	// define write-only register ADC_CONFIGURATION
whismanoid	0:f7d706d2904d	494	ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid	0:f7d706d2904d	495	const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid	0:f7d706d2904d	496	const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid	0:f7d706d2904d	497	const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid	0:f7d706d2904d	498	const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid	0:f7d706d2904d	499	const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid	0:f7d706d2904d	500	const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid	0:f7d706d2904d	501
whismanoid	0:f7d706d2904d	502	//----------------------------------------
whismanoid	0:f7d706d2904d	503	// define write-only registers UNIPOLAR,BIPOLAR,RANGE
whismanoid	0:f7d706d2904d	504	UNIPOLAR = 0x8800; //!< mosiData16 0x8800..0x8FFF format: 1 0 0 0 1 UCH0/1 UCH2/3 UCH4/5 UCH6/7 UCH8/9 UCH10/11 UCH12/13 UCH14/15 PDIFF_COM x x
whismanoid	0:f7d706d2904d	505	BIPOLAR = 0x9000; //!< mosiData16 0x9000..0x97FF format: 1 0 0 1 0 BCH0/1 BCH2/3 BCH4/5 BCH6/7 BCH8/9 BCH10/11 BCH12/13 BCH14/15 x x x
whismanoid	0:f7d706d2904d	506	RANGE = 0x9800; //!< mosiData16 0x9800..0x9FFF format: 1 0 0 1 1 RANGE0/1 RANGE2/3 RANGE4/5 RANGE6/7 RANGE8/9 RANGE10/11 RANGE12/13 RANGE14/15 x x x
whismanoid	0:f7d706d2904d	507	const int AIN_0_1_LSB = 10; // UNIPOLAR.UCH0/1 BIPOLAR.BCH0/1 RANGE.RANGE0/1
whismanoid	0:f7d706d2904d	508	const int AIN_2_3_LSB = 9; // UNIPOLAR.UCH2/3 BIPOLAR.BCH2/3 RANGE.RANGE2/3
whismanoid	0:f7d706d2904d	509	const int AIN_4_5_LSB = 8; // UNIPOLAR.UCH4/5 BIPOLAR.BCH4/5 RANGE.RANGE4/5
whismanoid	0:f7d706d2904d	510	const int AIN_6_7_LSB = 7; // UNIPOLAR.UCH6/7 BIPOLAR.BCH6/7 RANGE.RANGE6/7
whismanoid	0:f7d706d2904d	511	const int AIN_8_9_LSB = 6; // UNIPOLAR.UCH8/9 BIPOLAR.BCH8/9 RANGE.RANGE8/9
whismanoid	0:f7d706d2904d	512	const int AIN_10_11_LSB = 5; // UNIPOLAR.UCH10/11 BIPOLAR.BCH10/11 RANGE.RANGE10/11
whismanoid	0:f7d706d2904d	513	const int AIN_12_13_LSB = 4; // UNIPOLAR.UCH12/13 BIPOLAR.BCH12/13 RANGE.RANGE12/13
whismanoid	0:f7d706d2904d	514	const int AIN_14_15_LSB = 3; // UNIPOLAR.UCH14/15 BIPOLAR.BCH14/15 RANGE.RANGE14/15
whismanoid	0:f7d706d2904d	515	const int PDIFF_COMM_LSB = 2; const int PDIFF_COMM_BITS = 0x01; // UNIPOLAR.PDIFF_COM
whismanoid	0:f7d706d2904d	516	// Summary of Table 8:
whismanoid	0:f7d706d2904d	517	// UCH0/1=0, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	518	// UCH0/1=1, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	519	// UCH0/1=0, BCH0/1=1, RANGE0/1=0: AIN0/AIN1 differential input pair ±½Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	520	// UCH0/1=1, BCH0/1=1, RANGE0/1=0: reserved do not use
whismanoid	0:f7d706d2904d	521	// UCH0/1=0, BCH0/1=0, RANGE0/1=1: reserved do not use
whismanoid	0:f7d706d2904d	522	// UCH0/1=1, BCH0/1=0, RANGE0/1=1: reserved do not use
whismanoid	0:f7d706d2904d	523	// UCH0/1=0, BCH0/1=1, RANGE0/1=1: AIN0/AIN1 differential input pair ±Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid	0:f7d706d2904d	524	// UCH0/1=1, BCH0/1=1, RANGE0/1=1: reserved do not use
whismanoid	0:f7d706d2904d	525	// Both channels of a differential pair must be within Input Voltage Range (dynamic signal range) 0..VREF.
whismanoid	0:f7d706d2904d	526
whismanoid	0:f7d706d2904d	527	//----------------------------------------
whismanoid	0:f7d706d2904d	528	// define write-only registers CSCAN0,CSCAN1
whismanoid	0:f7d706d2904d	529	CSCAN0 = 0xA000; //!< mosiData16 0xA000..0xA7FF format: 1 0 1 0 0 CHSCAN15 CHSCAN14 CHSCAN13 CHSCAN12 CHSCAN11 CHSCAN10 CHSCAN9 CHSCAN8 x x x
whismanoid	0:f7d706d2904d	530	const int CHSCAN15_LSB = 10; // CSCAN0.CHSCAN15
whismanoid	0:f7d706d2904d	531	const int CHSCAN14_LSB = 9; // CSCAN0.CHSCAN14
whismanoid	0:f7d706d2904d	532	const int CHSCAN13_LSB = 8; // CSCAN0.CHSCAN13
whismanoid	0:f7d706d2904d	533	const int CHSCAN12_LSB = 7; // CSCAN0.CHSCAN12
whismanoid	0:f7d706d2904d	534	const int CHSCAN11_LSB = 6; // CSCAN0.CHSCAN11
whismanoid	0:f7d706d2904d	535	const int CHSCAN10_LSB = 5; // CSCAN0.CHSCAN10
whismanoid	0:f7d706d2904d	536	const int CHSCAN9_LSB = 4; // CSCAN0.CHSCAN9
whismanoid	0:f7d706d2904d	537	const int CHSCAN8_LSB = 3; // CSCAN0.CHSCAN8
whismanoid	0:f7d706d2904d	538	CSCAN1 = 0xA800; //!< mosiData16 0xA800..0xAFFF format: 1 0 1 0 1 CHSCAN7 CHSCAN6 CHSCAN5 CHSCAN4 CHSCAN3 CHSCAN2 CHSCAN1 CHSCAN0 x x x
whismanoid	0:f7d706d2904d	539	const int CHSCAN7_LSB = 10; // CSCAN1.CHSCAN7
whismanoid	0:f7d706d2904d	540	const int CHSCAN6_LSB = 9; // CSCAN1.CHSCAN6
whismanoid	0:f7d706d2904d	541	const int CHSCAN5_LSB = 8; // CSCAN1.CHSCAN5
whismanoid	0:f7d706d2904d	542	const int CHSCAN4_LSB = 7; // CSCAN1.CHSCAN4
whismanoid	0:f7d706d2904d	543	const int CHSCAN3_LSB = 6; // CSCAN1.CHSCAN3
whismanoid	0:f7d706d2904d	544	const int CHSCAN2_LSB = 5; // CSCAN1.CHSCAN2
whismanoid	0:f7d706d2904d	545	const int CHSCAN1_LSB = 4; // CSCAN1.CHSCAN1
whismanoid	0:f7d706d2904d	546	const int CHSCAN0_LSB = 3; // CSCAN1.CHSCAN0
whismanoid	0:f7d706d2904d	547
whismanoid	0:f7d706d2904d	548	//----------------------------------------
whismanoid	0:f7d706d2904d	549	// Initialize shadow of write-only register SAMPLESET.
whismanoid	0:f7d706d2904d	550	// Do not write to SAMPLESET at this time.
whismanoid	0:f7d706d2904d	551	// A write to SAMPLESET must be followed by specified number of pattern entry words.
whismanoid	0:f7d706d2904d	552	// See ScanSampleSetExternalClock function for details.
whismanoid	0:f7d706d2904d	553	SAMPLESET = 0xB000; //!< mosiData16 0xB000..0xB7FF format: 1 0 1 1 0 SEQ_LENGTH[7:0] x x x
whismanoid	0:f7d706d2904d	554	const int SAMPLESET_LSB = 3; const int SAMPLESET_BITS = 0xFF; // SAMPLESET.SEQ_LENGTH[7:0]
whismanoid	0:f7d706d2904d	555
whismanoid	0:f7d706d2904d	556	//----------------------------------------
whismanoid	0:f7d706d2904d	557	// Reset all registers: ADC_MODE_CONTROL.RESET[1:0] = 2
whismanoid	0:f7d706d2904d	558	ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	559	ADC_MODE_CONTROL \|= ((2 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	560
whismanoid	0:f7d706d2904d	561	//----------------------------------------
whismanoid	0:f7d706d2904d	562	// SPI write ADC MODE CONTROL register
whismanoid	0:f7d706d2904d	563	// Send SPI configuration to device
whismanoid	0:f7d706d2904d	564	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	565	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	566	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	0:f7d706d2904d	567	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	568
whismanoid	0:f7d706d2904d	569	#if REFSEL_0
whismanoid	0:f7d706d2904d	570
whismanoid	0:f7d706d2904d	571	//----------------------------------------
whismanoid	0:f7d706d2904d	572	// Global setting for all channels: ADC_CONFIGURATION.REFSEL=0: external single-ended reference
whismanoid	0:f7d706d2904d	573	// SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL
whismanoid	0:f7d706d2904d	574	// SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL: EXTERNAL SINGLE-ENDED
whismanoid	0:f7d706d2904d	575	// SELECT ADC CONFIGURATION register set REFSEL BIT TO 0
whismanoid	0:f7d706d2904d	576	ADC_CONFIGURATION &= ~ (( REFSEL_BITS) << REFSEL_LSB); // ADC_CONFIGURATION.REFSEL=0: external single-ended reference. (For the 16-channel chips: channel AIN15 is available.)
whismanoid	0:f7d706d2904d	577	#endif // REFSEL_0
whismanoid	0:f7d706d2904d	578
whismanoid	0:f7d706d2904d	579	#if REFSEL_1
whismanoid	0:f7d706d2904d	580
whismanoid	0:f7d706d2904d	581	//----------------------------------------
whismanoid	0:f7d706d2904d	582	// Global setting for all channels: ADC_CONFIGURATION.REFSEL=1: external differential reference (For the 16-channel chips: channel AIN15 is unavailable, the pin is assigned to REF-.)
whismanoid	0:f7d706d2904d	583	// SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL
whismanoid	0:f7d706d2904d	584	// SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL: EXTERNAL DIFFERENTIAL
whismanoid	0:f7d706d2904d	585	// SELECT ADC CONFIGURATION register set REFSEL BIT TO 1
whismanoid	0:f7d706d2904d	586	ADC_CONFIGURATION \|= ((1 & REFSEL_BITS) << REFSEL_LSB); // ADC_CONFIGURATION.REFSEL=1: external differential reference. (For the 16-channel chips: channel AIN15 is unavailable, the pin is assigned to REF-.)
whismanoid	0:f7d706d2904d	587	#endif // REFSEL_1
whismanoid	0:f7d706d2904d	588
whismanoid	0:f7d706d2904d	589	#if PDIFF_COMM_0
whismanoid	0:f7d706d2904d	590
whismanoid	0:f7d706d2904d	591	//----------------------------------------
whismanoid	0:f7d706d2904d	592	// Global setting for all channels: PDIFF_COMM
whismanoid	0:f7d706d2904d	593	UNIPOLAR &= ~ (( PDIFF_COMM_BITS) << PDIFF_COMM_LSB); // UNIPOLAR.PDIFF_COMM=0: all single-ended channels use GND as common
whismanoid	0:f7d706d2904d	594	#endif // PDIFF_COMM_0
whismanoid	0:f7d706d2904d	595
whismanoid	0:f7d706d2904d	596	#if PDIFF_COMM_1
whismanoid	0:f7d706d2904d	597
whismanoid	0:f7d706d2904d	598	//----------------------------------------
whismanoid	0:f7d706d2904d	599	// Global setting for all channels: PDIFF_COMM
whismanoid	0:f7d706d2904d	600	// SELECT UNIPOLAR AND register set BIT PDIFF_COM TO 1 FOR PSEUDODIFFERENTIAL SELECTION
whismanoid	0:f7d706d2904d	601	UNIPOLAR \|= ((1 & PDIFF_COMM_BITS) << PDIFF_COMM_LSB); // UNIPOLAR.PDIFF_COMM=1: all single-ended channels are pseudo-differential with REF- as common
whismanoid	0:f7d706d2904d	602	#endif // PDIFF_COMM_1
whismanoid	0:f7d706d2904d	603
whismanoid	0:f7d706d2904d	604	#if AIN_0_1_SingleEnded
whismanoid	0:f7d706d2904d	605
whismanoid	0:f7d706d2904d	606	//----------------------------------------
whismanoid	0:f7d706d2904d	607	// ADC Channels AIN0, AIN1 = Both Single-Ended, Unipolar
whismanoid	0:f7d706d2904d	608	// Full Scale = VREF
whismanoid	0:f7d706d2904d	609	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	610	// AIN0 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	611	// AIN1 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	612	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	0:f7d706d2904d	613	// AIN0 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	614	// AIN1 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	615	//
whismanoid	0:f7d706d2904d	616	// SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid	0:f7d706d2904d	617	UNIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid	0:f7d706d2904d	618	BIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid	0:f7d706d2904d	619	RANGE &= ~ (1 << AIN_0_1_LSB);
whismanoid	0:f7d706d2904d	620	// UCH0/1=0, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	621	#endif // AIN_0_1_SingleEnded
whismanoid	0:f7d706d2904d	622
whismanoid	0:f7d706d2904d	623	#if AIN_0_1_DifferentialUnipolar
whismanoid	0:f7d706d2904d	624
whismanoid	0:f7d706d2904d	625	//----------------------------------------
whismanoid	0:f7d706d2904d	626	// ADC Channels AIN0, AIN1 = Differential Unipolar (AIN0 > AIN1)
whismanoid	0:f7d706d2904d	627	// Full Scale = VREF
whismanoid	0:f7d706d2904d	628	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	629	// AIN0, AIN1 are a Differential pair using Unipolar transfer function.
whismanoid	0:f7d706d2904d	630	// AIN0 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	631	// AIN1 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	632	//
whismanoid	0:f7d706d2904d	633	// SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid	0:f7d706d2904d	634	UNIPOLAR \|= (1 << AIN_0_1_LSB);
whismanoid	0:f7d706d2904d	635	BIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid	0:f7d706d2904d	636	RANGE &= ~ (1 << AIN_0_1_LSB);
whismanoid	0:f7d706d2904d	637	// UCH0/1=1, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	638	#endif // AIN_0_1_DifferentialUnipolar
whismanoid	0:f7d706d2904d	639
whismanoid	0:f7d706d2904d	640	#if AIN_0_1_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	641
whismanoid	0:f7d706d2904d	642	//----------------------------------------
whismanoid	0:f7d706d2904d	643	// ADC Channels AIN0, AIN1 = Differential Bipolar
whismanoid	0:f7d706d2904d	644	// Full Scale = VREF
whismanoid	0:f7d706d2904d	645	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	646	// AIN0, AIN1 are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid	0:f7d706d2904d	647	// AIN0 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	648	// AIN1 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	649	//
whismanoid	0:f7d706d2904d	650	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	0:f7d706d2904d	651	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid	0:f7d706d2904d	652	UNIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid	0:f7d706d2904d	653	BIPOLAR \|= (1 << AIN_0_1_LSB);
whismanoid	0:f7d706d2904d	654	RANGE &= ~ (1 << AIN_0_1_LSB);
whismanoid	0:f7d706d2904d	655	// UCH0/1=0, BCH0/1=1, RANGE0/1=0: AIN0/AIN1 differential input pair ±½Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	656	#endif // AIN_0_1_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	657
whismanoid	0:f7d706d2904d	658	#if AIN_0_1_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	659
whismanoid	0:f7d706d2904d	660	//----------------------------------------
whismanoid	0:f7d706d2904d	661	// ADC Channels AIN0, AIN1 = Differential Bipolar
whismanoid	0:f7d706d2904d	662	// Full Scale = 2 * VREF
whismanoid	0:f7d706d2904d	663	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	664	// AIN0, AIN1 are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid	0:f7d706d2904d	665	// AIN0 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	666	// AIN1 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	667	//
whismanoid	0:f7d706d2904d	668	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	0:f7d706d2904d	669	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid	0:f7d706d2904d	670	UNIPOLAR &= ~ (1 << AIN_0_1_LSB);
whismanoid	0:f7d706d2904d	671	BIPOLAR \|= (1 << AIN_0_1_LSB);
whismanoid	0:f7d706d2904d	672	RANGE \|= (1 << AIN_0_1_LSB);
whismanoid	0:f7d706d2904d	673	// UCH0/1=0, BCH0/1=1, RANGE0/1=1: AIN0/AIN1 differential input pair ±Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid	0:f7d706d2904d	674	#endif // AIN_0_1_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	675
whismanoid	0:f7d706d2904d	676	#if AIN_2_3_SingleEnded
whismanoid	0:f7d706d2904d	677
whismanoid	0:f7d706d2904d	678	//----------------------------------------
whismanoid	0:f7d706d2904d	679	// ADC Channels AIN2, AIN3 = Both Single-Ended, Unipolar
whismanoid	0:f7d706d2904d	680	// Full Scale = VREF
whismanoid	0:f7d706d2904d	681	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	682	// AIN2 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	683	// AIN3 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	684	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	0:f7d706d2904d	685	// AIN2 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	686	// AIN3 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	687	//
whismanoid	0:f7d706d2904d	688	// SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid	0:f7d706d2904d	689	UNIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid	0:f7d706d2904d	690	BIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid	0:f7d706d2904d	691	RANGE &= ~ (1 << AIN_2_3_LSB);
whismanoid	0:f7d706d2904d	692	// UCH2/3=0, BCH2/3=0, RANGE2/3=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	693	#endif // AIN_2_3_SingleEnded
whismanoid	0:f7d706d2904d	694
whismanoid	0:f7d706d2904d	695	#if AIN_2_3_DifferentialUnipolar
whismanoid	0:f7d706d2904d	696
whismanoid	0:f7d706d2904d	697	//----------------------------------------
whismanoid	0:f7d706d2904d	698	// ADC Channels AIN2, AIN3 = Differential Unipolar (AIN2 > AIN3)
whismanoid	0:f7d706d2904d	699	// Full Scale = VREF
whismanoid	0:f7d706d2904d	700	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	701	// AIN2, AIN3 are a Differential pair using Unipolar transfer function.
whismanoid	0:f7d706d2904d	702	// AIN2 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	703	// AIN3 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	704	//
whismanoid	0:f7d706d2904d	705	// SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid	0:f7d706d2904d	706	UNIPOLAR \|= (1 << AIN_2_3_LSB);
whismanoid	0:f7d706d2904d	707	BIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid	0:f7d706d2904d	708	RANGE &= ~ (1 << AIN_2_3_LSB);
whismanoid	0:f7d706d2904d	709	// UCH2/3=1, BCH2/3=0, RANGE2/3=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	710	#endif // AIN_2_3_DifferentialUnipolar
whismanoid	0:f7d706d2904d	711
whismanoid	0:f7d706d2904d	712	#if AIN_2_3_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	713
whismanoid	0:f7d706d2904d	714	//----------------------------------------
whismanoid	0:f7d706d2904d	715	// ADC Channels AIN2, AIN3 = Differential Bipolar
whismanoid	0:f7d706d2904d	716	// Full Scale = VREF
whismanoid	0:f7d706d2904d	717	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	718	// AIN2, AIN3 are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid	0:f7d706d2904d	719	// AIN2 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	720	// AIN3 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	721	//
whismanoid	0:f7d706d2904d	722	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	0:f7d706d2904d	723	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid	0:f7d706d2904d	724	UNIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid	0:f7d706d2904d	725	BIPOLAR \|= (1 << AIN_2_3_LSB);
whismanoid	0:f7d706d2904d	726	RANGE &= ~ (1 << AIN_2_3_LSB);
whismanoid	0:f7d706d2904d	727	// UCH2/3=0, BCH2/3=1, RANGE2/3=0: AIN0/AIN1 differential input pair ±½Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	728	#endif // AIN_2_3_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	729
whismanoid	0:f7d706d2904d	730	#if AIN_2_3_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	731
whismanoid	0:f7d706d2904d	732	//----------------------------------------
whismanoid	0:f7d706d2904d	733	// ADC Channels AIN2, AIN3 = Differential Bipolar
whismanoid	0:f7d706d2904d	734	// Full Scale = 2 * VREF
whismanoid	0:f7d706d2904d	735	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	736	// AIN2, AIN3 are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid	0:f7d706d2904d	737	// AIN2 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	738	// AIN3 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	739	//
whismanoid	0:f7d706d2904d	740	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	0:f7d706d2904d	741	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid	0:f7d706d2904d	742	UNIPOLAR &= ~ (1 << AIN_2_3_LSB);
whismanoid	0:f7d706d2904d	743	BIPOLAR \|= (1 << AIN_2_3_LSB);
whismanoid	0:f7d706d2904d	744	RANGE \|= (1 << AIN_2_3_LSB);
whismanoid	0:f7d706d2904d	745	// UCH2/3=0, BCH2/3=1, RANGE2/3=1: AIN0/AIN1 differential input pair ±Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid	0:f7d706d2904d	746	#endif // AIN_2_3_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	747
whismanoid	0:f7d706d2904d	748	#if AIN_4_5_SingleEnded
whismanoid	0:f7d706d2904d	749
whismanoid	0:f7d706d2904d	750	//----------------------------------------
whismanoid	0:f7d706d2904d	751	// ADC Channels AIN4, AIN5 = Both Single-Ended, Unipolar
whismanoid	0:f7d706d2904d	752	// Full Scale = VREF
whismanoid	0:f7d706d2904d	753	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	754	// AIN4 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	755	// AIN5 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	756	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	0:f7d706d2904d	757	// AIN4 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	758	// AIN5 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	759	//
whismanoid	0:f7d706d2904d	760	// SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid	0:f7d706d2904d	761	UNIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid	0:f7d706d2904d	762	BIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid	0:f7d706d2904d	763	RANGE &= ~ (1 << AIN_4_5_LSB);
whismanoid	0:f7d706d2904d	764	// UCH4/5=0, BCH4/5=0, RANGE4/5=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	765	#endif // AIN_4_5_SingleEnded
whismanoid	0:f7d706d2904d	766
whismanoid	0:f7d706d2904d	767	#if AIN_4_5_DifferentialUnipolar
whismanoid	0:f7d706d2904d	768
whismanoid	0:f7d706d2904d	769	//----------------------------------------
whismanoid	0:f7d706d2904d	770	// ADC Channels AIN4, AIN5 = Differential Unipolar (AIN4 > AIN5)
whismanoid	0:f7d706d2904d	771	// Full Scale = VREF
whismanoid	0:f7d706d2904d	772	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	773	// AIN4, AIN5 are a Differential pair using Unipolar transfer function.
whismanoid	0:f7d706d2904d	774	// AIN4 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	775	// AIN5 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	776	//
whismanoid	0:f7d706d2904d	777	// SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid	0:f7d706d2904d	778	UNIPOLAR \|= (1 << AIN_4_5_LSB);
whismanoid	0:f7d706d2904d	779	BIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid	0:f7d706d2904d	780	RANGE &= ~ (1 << AIN_4_5_LSB);
whismanoid	0:f7d706d2904d	781	// UCH4/5=1, BCH4/5=0, RANGE4/5=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	782	#endif // AIN_4_5_DifferentialUnipolar
whismanoid	0:f7d706d2904d	783
whismanoid	0:f7d706d2904d	784	#if AIN_4_5_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	785
whismanoid	0:f7d706d2904d	786	//----------------------------------------
whismanoid	0:f7d706d2904d	787	// ADC Channels AIN4, AIN5 = Differential Bipolar
whismanoid	0:f7d706d2904d	788	// Full Scale = VREF
whismanoid	0:f7d706d2904d	789	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	790	// AIN4, AIN5 are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid	0:f7d706d2904d	791	// AIN4 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	792	// AIN5 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	793	//
whismanoid	0:f7d706d2904d	794	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	0:f7d706d2904d	795	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid	0:f7d706d2904d	796	UNIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid	0:f7d706d2904d	797	BIPOLAR \|= (1 << AIN_4_5_LSB);
whismanoid	0:f7d706d2904d	798	RANGE &= ~ (1 << AIN_4_5_LSB);
whismanoid	0:f7d706d2904d	799	// UCH4/5=0, BCH4/5=1, RANGE4/5=0: AIN0/AIN1 differential input pair ±½Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	800	#endif // AIN_4_5_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	801
whismanoid	0:f7d706d2904d	802	#if AIN_4_5_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	803
whismanoid	0:f7d706d2904d	804	//----------------------------------------
whismanoid	0:f7d706d2904d	805	// ADC Channels AIN4, AIN5 = Differential Bipolar
whismanoid	0:f7d706d2904d	806	// Full Scale = 2 * VREF
whismanoid	0:f7d706d2904d	807	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	808	// AIN4, AIN5 are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid	0:f7d706d2904d	809	// AIN4 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	810	// AIN5 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	811	//
whismanoid	0:f7d706d2904d	812	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	0:f7d706d2904d	813	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid	0:f7d706d2904d	814	UNIPOLAR &= ~ (1 << AIN_4_5_LSB);
whismanoid	0:f7d706d2904d	815	BIPOLAR \|= (1 << AIN_4_5_LSB);
whismanoid	0:f7d706d2904d	816	RANGE \|= (1 << AIN_4_5_LSB);
whismanoid	0:f7d706d2904d	817	// UCH4/5=0, BCH4/5=1, RANGE4/5=1: AIN0/AIN1 differential input pair ±Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid	0:f7d706d2904d	818	#endif // AIN_4_5_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	819
whismanoid	0:f7d706d2904d	820	#if AIN_6_7_SingleEnded
whismanoid	0:f7d706d2904d	821
whismanoid	0:f7d706d2904d	822	//----------------------------------------
whismanoid	0:f7d706d2904d	823	// ADC Channels AIN6, AIN7 = Both Single-Ended, Unipolar
whismanoid	0:f7d706d2904d	824	// Full Scale = VREF
whismanoid	0:f7d706d2904d	825	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	826	// AIN6 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	827	// AIN7 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	828	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	0:f7d706d2904d	829	// AIN6 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	830	// AIN7 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	831	//
whismanoid	0:f7d706d2904d	832	// SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid	0:f7d706d2904d	833	UNIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid	0:f7d706d2904d	834	BIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid	0:f7d706d2904d	835	RANGE &= ~ (1 << AIN_6_7_LSB);
whismanoid	0:f7d706d2904d	836	// UCH6/7=0, BCH6/7=0, RANGE6/7=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	837	#endif // AIN_6_7_SingleEnded
whismanoid	0:f7d706d2904d	838
whismanoid	0:f7d706d2904d	839	#if AIN_6_7_DifferentialUnipolar
whismanoid	0:f7d706d2904d	840
whismanoid	0:f7d706d2904d	841	//----------------------------------------
whismanoid	0:f7d706d2904d	842	// ADC Channels AIN6, AIN7 = Differential Unipolar (AIN6 > AIN7)
whismanoid	0:f7d706d2904d	843	// Full Scale = VREF
whismanoid	0:f7d706d2904d	844	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	845	// AIN6, AIN7 are a Differential pair using Unipolar transfer function.
whismanoid	0:f7d706d2904d	846	// AIN6 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	847	// AIN7 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	848	//
whismanoid	0:f7d706d2904d	849	// SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid	0:f7d706d2904d	850	UNIPOLAR \|= (1 << AIN_6_7_LSB);
whismanoid	0:f7d706d2904d	851	BIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid	0:f7d706d2904d	852	RANGE &= ~ (1 << AIN_6_7_LSB);
whismanoid	0:f7d706d2904d	853	// UCH6/7=1, BCH6/7=0, RANGE6/7=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	854	#endif // AIN_6_7_DifferentialUnipolar
whismanoid	0:f7d706d2904d	855
whismanoid	0:f7d706d2904d	856	#if AIN_6_7_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	857
whismanoid	0:f7d706d2904d	858	//----------------------------------------
whismanoid	0:f7d706d2904d	859	// ADC Channels AIN6, AIN7 = Differential Bipolar
whismanoid	0:f7d706d2904d	860	// Full Scale = VREF
whismanoid	0:f7d706d2904d	861	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	862	// AIN6, AIN7 are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid	0:f7d706d2904d	863	// AIN6 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	864	// AIN7 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	865	//
whismanoid	0:f7d706d2904d	866	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	0:f7d706d2904d	867	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid	0:f7d706d2904d	868	UNIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid	0:f7d706d2904d	869	BIPOLAR \|= (1 << AIN_6_7_LSB);
whismanoid	0:f7d706d2904d	870	RANGE &= ~ (1 << AIN_6_7_LSB);
whismanoid	0:f7d706d2904d	871	// UCH6/7=0, BCH6/7=1, RANGE6/7=0: AIN0/AIN1 differential input pair ±½Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	872	#endif // AIN_6_7_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	873
whismanoid	0:f7d706d2904d	874	#if AIN_6_7_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	875
whismanoid	0:f7d706d2904d	876	//----------------------------------------
whismanoid	0:f7d706d2904d	877	// ADC Channels AIN6, AIN7 = Differential Bipolar
whismanoid	0:f7d706d2904d	878	// Full Scale = 2 * VREF
whismanoid	0:f7d706d2904d	879	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	880	// AIN6, AIN7 are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid	0:f7d706d2904d	881	// AIN6 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	882	// AIN7 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	883	//
whismanoid	0:f7d706d2904d	884	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	0:f7d706d2904d	885	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid	0:f7d706d2904d	886	UNIPOLAR &= ~ (1 << AIN_6_7_LSB);
whismanoid	0:f7d706d2904d	887	BIPOLAR \|= (1 << AIN_6_7_LSB);
whismanoid	0:f7d706d2904d	888	RANGE \|= (1 << AIN_6_7_LSB);
whismanoid	0:f7d706d2904d	889	// UCH6/7=0, BCH6/7=1, RANGE6/7=1: AIN0/AIN1 differential input pair ±Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid	0:f7d706d2904d	890	#endif // AIN_6_7_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	891
whismanoid	0:f7d706d2904d	892	#if AIN_8_9_SingleEnded
whismanoid	0:f7d706d2904d	893
whismanoid	0:f7d706d2904d	894	//----------------------------------------
whismanoid	0:f7d706d2904d	895	// ADC Channels AIN8, AIN9 = Both Single-Ended, Unipolar
whismanoid	0:f7d706d2904d	896	// Full Scale = VREF
whismanoid	0:f7d706d2904d	897	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	898	// AIN8 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	899	// AIN9 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	900	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	0:f7d706d2904d	901	// AIN8 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	902	// AIN9 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	903	//
whismanoid	0:f7d706d2904d	904	// SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid	0:f7d706d2904d	905	UNIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid	0:f7d706d2904d	906	BIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid	0:f7d706d2904d	907	RANGE &= ~ (1 << AIN_8_9_LSB);
whismanoid	0:f7d706d2904d	908	// UCH8/9=0, BCH8/9=0, RANGE8/9=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	909	#endif // AIN_8_9_SingleEnded
whismanoid	0:f7d706d2904d	910
whismanoid	0:f7d706d2904d	911	#if AIN_8_9_DifferentialUnipolar
whismanoid	0:f7d706d2904d	912
whismanoid	0:f7d706d2904d	913	//----------------------------------------
whismanoid	0:f7d706d2904d	914	// ADC Channels AIN8, AIN9 = Differential Unipolar (AIN8 > AIN9)
whismanoid	0:f7d706d2904d	915	// Full Scale = VREF
whismanoid	0:f7d706d2904d	916	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	917	// AIN8, AIN9 are a Differential pair using Unipolar transfer function.
whismanoid	0:f7d706d2904d	918	// AIN8 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	919	// AIN9 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	920	//
whismanoid	0:f7d706d2904d	921	// SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid	0:f7d706d2904d	922	UNIPOLAR \|= (1 << AIN_8_9_LSB);
whismanoid	0:f7d706d2904d	923	BIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid	0:f7d706d2904d	924	RANGE &= ~ (1 << AIN_8_9_LSB);
whismanoid	0:f7d706d2904d	925	// UCH8/9=1, BCH8/9=0, RANGE8/9=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	926	#endif // AIN_8_9_DifferentialUnipolar
whismanoid	0:f7d706d2904d	927
whismanoid	0:f7d706d2904d	928	#if AIN_8_9_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	929
whismanoid	0:f7d706d2904d	930	//----------------------------------------
whismanoid	0:f7d706d2904d	931	// ADC Channels AIN8, AIN9 = Differential Bipolar
whismanoid	0:f7d706d2904d	932	// Full Scale = VREF
whismanoid	0:f7d706d2904d	933	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	934	// AIN8, AIN9 are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid	0:f7d706d2904d	935	// AIN8 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	936	// AIN9 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	937	//
whismanoid	0:f7d706d2904d	938	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	0:f7d706d2904d	939	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid	0:f7d706d2904d	940	UNIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid	0:f7d706d2904d	941	BIPOLAR \|= (1 << AIN_8_9_LSB);
whismanoid	0:f7d706d2904d	942	RANGE &= ~ (1 << AIN_8_9_LSB);
whismanoid	0:f7d706d2904d	943	// UCH8/9=0, BCH8/9=1, RANGE8/9=0: AIN0/AIN1 differential input pair ±½Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	944	#endif // AIN_8_9_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	945
whismanoid	0:f7d706d2904d	946	#if AIN_8_9_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	947
whismanoid	0:f7d706d2904d	948	//----------------------------------------
whismanoid	0:f7d706d2904d	949	// ADC Channels AIN8, AIN9 = Differential Bipolar
whismanoid	0:f7d706d2904d	950	// Full Scale = 2 * VREF
whismanoid	0:f7d706d2904d	951	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	952	// AIN8, AIN9 are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid	0:f7d706d2904d	953	// AIN8 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	954	// AIN9 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	955	//
whismanoid	0:f7d706d2904d	956	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	0:f7d706d2904d	957	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid	0:f7d706d2904d	958	UNIPOLAR &= ~ (1 << AIN_8_9_LSB);
whismanoid	0:f7d706d2904d	959	BIPOLAR \|= (1 << AIN_8_9_LSB);
whismanoid	0:f7d706d2904d	960	RANGE \|= (1 << AIN_8_9_LSB);
whismanoid	0:f7d706d2904d	961	// UCH8/9=0, BCH8/9=1, RANGE8/9=1: AIN0/AIN1 differential input pair ±Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid	0:f7d706d2904d	962	#endif // AIN_8_9_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	963
whismanoid	0:f7d706d2904d	964	#if AIN_10_11_SingleEnded
whismanoid	0:f7d706d2904d	965
whismanoid	0:f7d706d2904d	966	//----------------------------------------
whismanoid	0:f7d706d2904d	967	// ADC Channels AIN10, AIN11 = Both Single-Ended, Unipolar
whismanoid	0:f7d706d2904d	968	// Full Scale = VREF
whismanoid	0:f7d706d2904d	969	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	970	// AIN10 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	971	// AIN11 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	972	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	0:f7d706d2904d	973	// AIN10 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	974	// AIN11 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	975	//
whismanoid	0:f7d706d2904d	976	// SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid	0:f7d706d2904d	977	UNIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid	0:f7d706d2904d	978	BIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid	0:f7d706d2904d	979	RANGE &= ~ (1 << AIN_10_11_LSB);
whismanoid	0:f7d706d2904d	980	// UCH10/11=0, BCH10/11=0, RANGE10/11=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	981	#endif // AIN_10_11_SingleEnded
whismanoid	0:f7d706d2904d	982
whismanoid	0:f7d706d2904d	983	#if AIN_10_11_DifferentialUnipolar
whismanoid	0:f7d706d2904d	984
whismanoid	0:f7d706d2904d	985	//----------------------------------------
whismanoid	0:f7d706d2904d	986	// ADC Channels AIN10, AIN11 = Differential Unipolar (AIN10 > AIN11)
whismanoid	0:f7d706d2904d	987	// Full Scale = VREF
whismanoid	0:f7d706d2904d	988	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	989	// AIN10, AIN11 are a Differential pair using Unipolar transfer function.
whismanoid	0:f7d706d2904d	990	// AIN10 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	991	// AIN11 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	992	//
whismanoid	0:f7d706d2904d	993	// SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid	0:f7d706d2904d	994	UNIPOLAR \|= (1 << AIN_10_11_LSB);
whismanoid	0:f7d706d2904d	995	BIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid	0:f7d706d2904d	996	RANGE &= ~ (1 << AIN_10_11_LSB);
whismanoid	0:f7d706d2904d	997	// UCH10/11=1, BCH10/11=0, RANGE10/11=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	998	#endif // AIN_10_11_DifferentialUnipolar
whismanoid	0:f7d706d2904d	999
whismanoid	0:f7d706d2904d	1000	#if AIN_10_11_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	1001
whismanoid	0:f7d706d2904d	1002	//----------------------------------------
whismanoid	0:f7d706d2904d	1003	// ADC Channels AIN10, AIN11 = Differential Bipolar
whismanoid	0:f7d706d2904d	1004	// Full Scale = VREF
whismanoid	0:f7d706d2904d	1005	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	1006	// AIN10, AIN11 are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid	0:f7d706d2904d	1007	// AIN10 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1008	// AIN11 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1009	//
whismanoid	0:f7d706d2904d	1010	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	0:f7d706d2904d	1011	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid	0:f7d706d2904d	1012	UNIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid	0:f7d706d2904d	1013	BIPOLAR \|= (1 << AIN_10_11_LSB);
whismanoid	0:f7d706d2904d	1014	RANGE &= ~ (1 << AIN_10_11_LSB);
whismanoid	0:f7d706d2904d	1015	// UCH10/11=0, BCH10/11=1, RANGE10/11=0: AIN0/AIN1 differential input pair ±½Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	1016	#endif // AIN_10_11_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	1017
whismanoid	0:f7d706d2904d	1018	#if AIN_10_11_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	1019
whismanoid	0:f7d706d2904d	1020	//----------------------------------------
whismanoid	0:f7d706d2904d	1021	// ADC Channels AIN10, AIN11 = Differential Bipolar
whismanoid	0:f7d706d2904d	1022	// Full Scale = 2 * VREF
whismanoid	0:f7d706d2904d	1023	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	1024	// AIN10, AIN11 are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid	0:f7d706d2904d	1025	// AIN10 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1026	// AIN11 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1027	//
whismanoid	0:f7d706d2904d	1028	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	0:f7d706d2904d	1029	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid	0:f7d706d2904d	1030	UNIPOLAR &= ~ (1 << AIN_10_11_LSB);
whismanoid	0:f7d706d2904d	1031	BIPOLAR \|= (1 << AIN_10_11_LSB);
whismanoid	0:f7d706d2904d	1032	RANGE \|= (1 << AIN_10_11_LSB);
whismanoid	0:f7d706d2904d	1033	// UCH10/11=0, BCH10/11=1, RANGE10/11=1: AIN0/AIN1 differential input pair ±Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid	0:f7d706d2904d	1034	#endif // AIN_10_11_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	1035
whismanoid	0:f7d706d2904d	1036	#if AIN_12_13_SingleEnded
whismanoid	0:f7d706d2904d	1037
whismanoid	0:f7d706d2904d	1038	//----------------------------------------
whismanoid	0:f7d706d2904d	1039	// ADC Channels AIN12, AIN13 = Both Single-Ended, Unipolar
whismanoid	0:f7d706d2904d	1040	// Full Scale = VREF
whismanoid	0:f7d706d2904d	1041	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	1042	// AIN12 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	1043	// AIN13 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	1044	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	0:f7d706d2904d	1045	// AIN12 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1046	// AIN13 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1047	//
whismanoid	0:f7d706d2904d	1048	// SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid	0:f7d706d2904d	1049	UNIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid	0:f7d706d2904d	1050	BIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid	0:f7d706d2904d	1051	RANGE &= ~ (1 << AIN_12_13_LSB);
whismanoid	0:f7d706d2904d	1052	// UCH12/13=0, BCH12/13=0, RANGE12/13=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	1053	#endif // AIN_12_13_SingleEnded
whismanoid	0:f7d706d2904d	1054
whismanoid	0:f7d706d2904d	1055	#if AIN_12_13_DifferentialUnipolar
whismanoid	0:f7d706d2904d	1056
whismanoid	0:f7d706d2904d	1057	//----------------------------------------
whismanoid	0:f7d706d2904d	1058	// ADC Channels AIN12, AIN13 = Differential Unipolar (AIN12 > AIN13)
whismanoid	0:f7d706d2904d	1059	// Full Scale = VREF
whismanoid	0:f7d706d2904d	1060	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	1061	// AIN12, AIN13 are a Differential pair using Unipolar transfer function.
whismanoid	0:f7d706d2904d	1062	// AIN12 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1063	// AIN13 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1064	//
whismanoid	0:f7d706d2904d	1065	// SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid	0:f7d706d2904d	1066	UNIPOLAR \|= (1 << AIN_12_13_LSB);
whismanoid	0:f7d706d2904d	1067	BIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid	0:f7d706d2904d	1068	RANGE &= ~ (1 << AIN_12_13_LSB);
whismanoid	0:f7d706d2904d	1069	// UCH12/13=1, BCH12/13=0, RANGE12/13=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	1070	#endif // AIN_12_13_DifferentialUnipolar
whismanoid	0:f7d706d2904d	1071
whismanoid	0:f7d706d2904d	1072	#if AIN_12_13_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	1073
whismanoid	0:f7d706d2904d	1074	//----------------------------------------
whismanoid	0:f7d706d2904d	1075	// ADC Channels AIN12, AIN13 = Differential Bipolar
whismanoid	0:f7d706d2904d	1076	// Full Scale = VREF
whismanoid	0:f7d706d2904d	1077	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	1078	// AIN12, AIN13 are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid	0:f7d706d2904d	1079	// AIN12 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1080	// AIN13 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1081	//
whismanoid	0:f7d706d2904d	1082	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	0:f7d706d2904d	1083	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid	0:f7d706d2904d	1084	UNIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid	0:f7d706d2904d	1085	BIPOLAR \|= (1 << AIN_12_13_LSB);
whismanoid	0:f7d706d2904d	1086	RANGE &= ~ (1 << AIN_12_13_LSB);
whismanoid	0:f7d706d2904d	1087	// UCH12/13=0, BCH12/13=1, RANGE12/13=0: AIN0/AIN1 differential input pair ±½Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	1088	#endif // AIN_12_13_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	1089
whismanoid	0:f7d706d2904d	1090	#if AIN_12_13_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	1091
whismanoid	0:f7d706d2904d	1092	//----------------------------------------
whismanoid	0:f7d706d2904d	1093	// ADC Channels AIN12, AIN13 = Differential Bipolar
whismanoid	0:f7d706d2904d	1094	// Full Scale = 2 * VREF
whismanoid	0:f7d706d2904d	1095	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	1096	// AIN12, AIN13 are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid	0:f7d706d2904d	1097	// AIN12 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1098	// AIN13 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1099	//
whismanoid	0:f7d706d2904d	1100	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	0:f7d706d2904d	1101	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid	0:f7d706d2904d	1102	UNIPOLAR &= ~ (1 << AIN_12_13_LSB);
whismanoid	0:f7d706d2904d	1103	BIPOLAR \|= (1 << AIN_12_13_LSB);
whismanoid	0:f7d706d2904d	1104	RANGE \|= (1 << AIN_12_13_LSB);
whismanoid	0:f7d706d2904d	1105	// UCH12/13=0, BCH12/13=1, RANGE12/13=1: AIN0/AIN1 differential input pair ±Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid	0:f7d706d2904d	1106	#endif // AIN_12_13_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	1107
whismanoid	0:f7d706d2904d	1108	#if AIN_14_15_SingleEnded
whismanoid	0:f7d706d2904d	1109
whismanoid	0:f7d706d2904d	1110	//----------------------------------------
whismanoid	0:f7d706d2904d	1111	// ADC Channels AIN14, AIN15 = Both Single-Ended, Unipolar
whismanoid	0:f7d706d2904d	1112	// Full Scale = VREF
whismanoid	0:f7d706d2904d	1113	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	1114	// AIN14 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	1115	// AIN15 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	1116	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	0:f7d706d2904d	1117	// AIN14 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1118	// AIN15 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1119	//
whismanoid	0:f7d706d2904d	1120	// SELECT UNIPOLAR AND BIPOLAR register set PER CHANNEL UCH(X)/(X+1) AND BCH(X)/(X+1) TO 0 FOR SINGLE-ENDED SELECTION
whismanoid	0:f7d706d2904d	1121	UNIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid	0:f7d706d2904d	1122	BIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid	0:f7d706d2904d	1123	RANGE &= ~ (1 << AIN_14_15_LSB);
whismanoid	0:f7d706d2904d	1124	// UCH14/15=0, BCH14/15=0, RANGE14/15=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	1125	#endif // AIN_14_15_SingleEnded
whismanoid	0:f7d706d2904d	1126
whismanoid	0:f7d706d2904d	1127	#if AIN_14_15_DifferentialUnipolar
whismanoid	0:f7d706d2904d	1128
whismanoid	0:f7d706d2904d	1129	//----------------------------------------
whismanoid	0:f7d706d2904d	1130	// ADC Channels AIN14, AIN15 = Differential Unipolar (AIN14 > AIN15)
whismanoid	0:f7d706d2904d	1131	// Full Scale = VREF
whismanoid	0:f7d706d2904d	1132	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	1133	// AIN14, AIN15 are a Differential pair using Unipolar transfer function.
whismanoid	0:f7d706d2904d	1134	// AIN14 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1135	// AIN15 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1136	//
whismanoid	0:f7d706d2904d	1137	// SELECT UNIPOLAR register set PER CHANNEL UCH(X)/(X+1) TO 1 FOR UNIPOLAR
whismanoid	0:f7d706d2904d	1138	UNIPOLAR \|= (1 << AIN_14_15_LSB);
whismanoid	0:f7d706d2904d	1139	BIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid	0:f7d706d2904d	1140	RANGE &= ~ (1 << AIN_14_15_LSB);
whismanoid	0:f7d706d2904d	1141	// UCH14/15=1, BCH14/15=0, RANGE14/15=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	1142	#endif // AIN_14_15_DifferentialUnipolar
whismanoid	0:f7d706d2904d	1143
whismanoid	0:f7d706d2904d	1144	#if AIN_14_15_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	1145
whismanoid	0:f7d706d2904d	1146	//----------------------------------------
whismanoid	0:f7d706d2904d	1147	// ADC Channels AIN14, AIN15 = Differential Bipolar
whismanoid	0:f7d706d2904d	1148	// Full Scale = VREF
whismanoid	0:f7d706d2904d	1149	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	1150	// AIN14, AIN15 are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid	0:f7d706d2904d	1151	// AIN14 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1152	// AIN15 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1153	//
whismanoid	0:f7d706d2904d	1154	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	0:f7d706d2904d	1155	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 0 +/-VREF+/2
whismanoid	0:f7d706d2904d	1156	UNIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid	0:f7d706d2904d	1157	BIPOLAR \|= (1 << AIN_14_15_LSB);
whismanoid	0:f7d706d2904d	1158	RANGE &= ~ (1 << AIN_14_15_LSB);
whismanoid	0:f7d706d2904d	1159	// UCH14/15=0, BCH14/15=1, RANGE14/15=0: AIN0/AIN1 differential input pair ±½Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	1160	#endif // AIN_14_15_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	1161
whismanoid	0:f7d706d2904d	1162	#if AIN_14_15_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	1163
whismanoid	0:f7d706d2904d	1164	//----------------------------------------
whismanoid	0:f7d706d2904d	1165	// ADC Channels AIN14, AIN15 = Differential Bipolar
whismanoid	0:f7d706d2904d	1166	// Full Scale = 2 * VREF
whismanoid	0:f7d706d2904d	1167	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	1168	// AIN14, AIN15 are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid	0:f7d706d2904d	1169	// AIN14 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1170	// AIN15 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1171	//
whismanoid	0:f7d706d2904d	1172	// SELECT BIPOLAR register set PER CHANNEL BCH(X)/(X+1) TO 1 FOR BIPOLAR FULLY DIFFERENTIAL
whismanoid	0:f7d706d2904d	1173	// SELECT RANGE register set PER CHANNEL PAIR RANGE(X)/(X+1) TO 1 +/-VREF+
whismanoid	0:f7d706d2904d	1174	UNIPOLAR &= ~ (1 << AIN_14_15_LSB);
whismanoid	0:f7d706d2904d	1175	BIPOLAR \|= (1 << AIN_14_15_LSB);
whismanoid	0:f7d706d2904d	1176	RANGE \|= (1 << AIN_14_15_LSB);
whismanoid	0:f7d706d2904d	1177	// UCH14/15=0, BCH14/15=1, RANGE14/15=1: AIN0/AIN1 differential input pair ±Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid	0:f7d706d2904d	1178	#endif // AIN_14_15_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	1179
whismanoid	0:f7d706d2904d	1180	//----------------------------------------
whismanoid	0:f7d706d2904d	1181	// SPI write ADC CONFIGURATION register
whismanoid	0:f7d706d2904d	1182	// Send SPI configuration to device
whismanoid	0:f7d706d2904d	1183	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	1184	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	1185	SPIwrite16bits(ADC_CONFIGURATION);
whismanoid	0:f7d706d2904d	1186	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	1187
whismanoid	0:f7d706d2904d	1188	//----------------------------------------
whismanoid	0:f7d706d2904d	1189	// SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid	0:f7d706d2904d	1190	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	1191	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	1192	SPIwrite16bits(UNIPOLAR);
whismanoid	0:f7d706d2904d	1193	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	1194	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	1195	SPIwrite16bits(BIPOLAR);
whismanoid	0:f7d706d2904d	1196	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	1197	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	1198	SPIwrite16bits(RANGE);
whismanoid	0:f7d706d2904d	1199	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	1200
whismanoid	0:f7d706d2904d	1201	//----------------------------------------
whismanoid	0:f7d706d2904d	1202	// SPI write CSCAN0 CSCAN1 registers
whismanoid	0:f7d706d2904d	1203	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	1204	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	1205	SPIwrite16bits(CSCAN0);
whismanoid	0:f7d706d2904d	1206	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	1207	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	1208	SPIwrite16bits(CSCAN1);
whismanoid	0:f7d706d2904d	1209	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	1210	}
whismanoid	0:f7d706d2904d	1211
whismanoid	0:f7d706d2904d	1212	//----------------------------------------
whismanoid	0:f7d706d2904d	1213	// ADC Channels AIN(channelId), AIN(channelId+1) = Both Single-Ended, Unipolar
whismanoid	0:f7d706d2904d	1214	// Full Scale = VREF
whismanoid	0:f7d706d2904d	1215	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	1216	// AIN(channelId) is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	1217	// AIN(channelId+1) is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	1218	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	0:f7d706d2904d	1219	// AIN(channelId) voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1220	// AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1221	//
whismanoid	0:f7d706d2904d	1222	void MAX11131::Reconfigure_SingleEnded(int channelNumber_0_15)
whismanoid	0:f7d706d2904d	1223	{
whismanoid	0:f7d706d2904d	1224
whismanoid	0:f7d706d2904d	1225	//----------------------------------------
whismanoid	0:f7d706d2904d	1226	// UCH(ch)/(ch+1)=0, BCH(ch)/(ch+1)=0, RANGE(ch)/(ch+1)=0:
whismanoid	0:f7d706d2904d	1227	// AIN(ch)/AIN(ch+1) two independent single-ended inputs,
whismanoid	0:f7d706d2904d	1228	// unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	1229	//
whismanoid	0:f7d706d2904d	1230	const int channelPairIndex = channelNumber_0_15 / 2;
whismanoid	0:f7d706d2904d	1231	const int bitmask = (1 << (10 - channelPairIndex));
whismanoid	0:f7d706d2904d	1232	UNIPOLAR &= ~ bitmask;
whismanoid	0:f7d706d2904d	1233	BIPOLAR &= ~ bitmask;
whismanoid	0:f7d706d2904d	1234	RANGE &= ~ bitmask;
whismanoid	0:f7d706d2904d	1235
whismanoid	0:f7d706d2904d	1236	//----------------------------------------
whismanoid	0:f7d706d2904d	1237	// SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid	0:f7d706d2904d	1238	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	1239	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	1240	SPIwrite16bits(UNIPOLAR);
whismanoid	0:f7d706d2904d	1241	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	1242	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	1243	SPIwrite16bits(BIPOLAR);
whismanoid	0:f7d706d2904d	1244	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	1245	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	1246	SPIwrite16bits(RANGE);
whismanoid	0:f7d706d2904d	1247	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	1248	}
whismanoid	0:f7d706d2904d	1249
whismanoid	0:f7d706d2904d	1250	//----------------------------------------
whismanoid	0:f7d706d2904d	1251	// ADC Channels AIN(channelId), AIN(channelId+1) = Differential Unipolar (AIN(channelId) > AIN(channelId+1))
whismanoid	0:f7d706d2904d	1252	// Full Scale = VREF
whismanoid	0:f7d706d2904d	1253	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	1254	// AIN(channelId), AIN(channelId+1) are a Differential pair using Unipolar transfer function.
whismanoid	0:f7d706d2904d	1255	// AIN(channelId) voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1256	// AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1257	//
whismanoid	0:f7d706d2904d	1258	void MAX11131::Reconfigure_DifferentialUnipolar(int channelNumber_0_15)
whismanoid	0:f7d706d2904d	1259	{
whismanoid	0:f7d706d2904d	1260
whismanoid	0:f7d706d2904d	1261	//----------------------------------------
whismanoid	0:f7d706d2904d	1262	// UCH(ch)/(ch+1)=1, BCH(ch)/(ch+1)=0, RANGE(ch)/(ch+1)=0:
whismanoid	0:f7d706d2904d	1263	// AIN(ch)/AIN(ch+1) differential input pair,
whismanoid	0:f7d706d2904d	1264	// unipolar code (AIN(ch)>AIN(ch+1)) (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	1265	//
whismanoid	0:f7d706d2904d	1266	const int channelPairIndex = channelNumber_0_15 / 2;
whismanoid	0:f7d706d2904d	1267	const int bitmask = (1 << (10 - channelPairIndex));
whismanoid	0:f7d706d2904d	1268	UNIPOLAR \|= bitmask;
whismanoid	0:f7d706d2904d	1269	BIPOLAR &= ~ bitmask;
whismanoid	0:f7d706d2904d	1270	RANGE &= ~ bitmask;
whismanoid	0:f7d706d2904d	1271	// UCH0/1=1, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	1272
whismanoid	0:f7d706d2904d	1273	//----------------------------------------
whismanoid	0:f7d706d2904d	1274	// SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid	0:f7d706d2904d	1275	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	1276	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	1277	SPIwrite16bits(UNIPOLAR);
whismanoid	0:f7d706d2904d	1278	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	1279	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	1280	SPIwrite16bits(BIPOLAR);
whismanoid	0:f7d706d2904d	1281	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	1282	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	1283	SPIwrite16bits(RANGE);
whismanoid	0:f7d706d2904d	1284	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	1285	}
whismanoid	0:f7d706d2904d	1286
whismanoid	0:f7d706d2904d	1287	//----------------------------------------
whismanoid	0:f7d706d2904d	1288	// ADC Channels AIN(channelId), AIN(channelId+1) = Differential Bipolar
whismanoid	0:f7d706d2904d	1289	// Full Scale = VREF
whismanoid	0:f7d706d2904d	1290	// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	1291	// AIN(channelId), AIN(channelId+1) are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid	0:f7d706d2904d	1292	// AIN(channelId) voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1293	// AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1294	//
whismanoid	0:f7d706d2904d	1295	void MAX11131::Reconfigure_DifferentialBipolarFSVref(int channelNumber_0_15)
whismanoid	0:f7d706d2904d	1296	{
whismanoid	0:f7d706d2904d	1297
whismanoid	0:f7d706d2904d	1298	//----------------------------------------
whismanoid	0:f7d706d2904d	1299	// UCH(ch)/(ch+1)=0, BCH(ch)/(ch+1)=1, RANGE(ch)/(ch+1)=0:
whismanoid	0:f7d706d2904d	1300	// AIN(ch)/AIN(ch+1) differential input pair ±½Vref,
whismanoid	0:f7d706d2904d	1301	// bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	1302	//
whismanoid	0:f7d706d2904d	1303	const int channelPairIndex = channelNumber_0_15 / 2;
whismanoid	0:f7d706d2904d	1304	const int bitmask = (1 << (10 - channelPairIndex));
whismanoid	0:f7d706d2904d	1305	UNIPOLAR &= ~ bitmask;
whismanoid	0:f7d706d2904d	1306	BIPOLAR \|= bitmask;
whismanoid	0:f7d706d2904d	1307	RANGE &= ~ bitmask;
whismanoid	0:f7d706d2904d	1308
whismanoid	0:f7d706d2904d	1309	//----------------------------------------
whismanoid	0:f7d706d2904d	1310	// SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid	0:f7d706d2904d	1311	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	1312	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	1313	SPIwrite16bits(UNIPOLAR);
whismanoid	0:f7d706d2904d	1314	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	1315	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	1316	SPIwrite16bits(BIPOLAR);
whismanoid	0:f7d706d2904d	1317	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	1318	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	1319	SPIwrite16bits(RANGE);
whismanoid	0:f7d706d2904d	1320	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	1321	}
whismanoid	0:f7d706d2904d	1322
whismanoid	0:f7d706d2904d	1323	//----------------------------------------
whismanoid	0:f7d706d2904d	1324	// ADC Channels AIN(channelId), AIN(channelId+1) = Differential Bipolar
whismanoid	0:f7d706d2904d	1325	// Full Scale = 2 * VREF
whismanoid	0:f7d706d2904d	1326	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	1327	// AIN(channelId), AIN(channelId+1) are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid	0:f7d706d2904d	1328	// AIN(channelId) voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1329	// AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1330	//
whismanoid	0:f7d706d2904d	1331	void MAX11131::Reconfigure_DifferentialBipolarFS2Vref(int channelNumber_0_15)
whismanoid	0:f7d706d2904d	1332	{
whismanoid	0:f7d706d2904d	1333
whismanoid	0:f7d706d2904d	1334	//----------------------------------------
whismanoid	0:f7d706d2904d	1335	// UCH(ch)/(ch+1)=0, BCH(ch)/(ch+1)=1, RANGE(ch)/(ch+1)=1:
whismanoid	0:f7d706d2904d	1336	// AIN(ch)/AIN(ch+1) differential input pair ±Vref,
whismanoid	0:f7d706d2904d	1337	// bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid	0:f7d706d2904d	1338	//
whismanoid	0:f7d706d2904d	1339	const int channelPairIndex = channelNumber_0_15 / 2;
whismanoid	0:f7d706d2904d	1340	const int bitmask = (1 << (10 - channelPairIndex));
whismanoid	0:f7d706d2904d	1341	UNIPOLAR &= ~ bitmask;
whismanoid	0:f7d706d2904d	1342	BIPOLAR \|= bitmask;
whismanoid	0:f7d706d2904d	1343	RANGE \|= bitmask;
whismanoid	0:f7d706d2904d	1344	// UCH0/1=0, BCH0/1=1, RANGE0/1=1: AIN0/AIN1 differential input pair ±Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid	0:f7d706d2904d	1345
whismanoid	0:f7d706d2904d	1346	//----------------------------------------
whismanoid	0:f7d706d2904d	1347	// SPI write UNIPOLAR BIPOLAR RANGE registers
whismanoid	0:f7d706d2904d	1348	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	1349	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	1350	SPIwrite16bits(UNIPOLAR);
whismanoid	0:f7d706d2904d	1351	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	1352	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	1353	SPIwrite16bits(BIPOLAR);
whismanoid	0:f7d706d2904d	1354	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	1355	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	1356	SPIwrite16bits(RANGE);
whismanoid	0:f7d706d2904d	1357	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	1358	}
whismanoid	0:f7d706d2904d	1359
whismanoid	0:f7d706d2904d	1360	//----------------------------------------
whismanoid	0:f7d706d2904d	1361	// SCAN_0000_NOP
whismanoid	0:f7d706d2904d	1362	//
whismanoid	0:f7d706d2904d	1363	// Shift 16 bits out of ADC, without changing configuration.
whismanoid	0:f7d706d2904d	1364	// Note: @return data format depends on CHAN_ID bit:
whismanoid	0:f7d706d2904d	1365	// "CH[3:0] DATA[11:0]" when CHAN_ID = 1, or
whismanoid	0:f7d706d2904d	1366	// "0 DATA[11:0] x x x" when CHAN_ID = 0.
whismanoid	0:f7d706d2904d	1367	int16_t MAX11131::ScanRead(void)
whismanoid	0:f7d706d2904d	1368	{
whismanoid	0:f7d706d2904d	1369
whismanoid	0:f7d706d2904d	1370	//----------------------------------------
whismanoid	0:f7d706d2904d	1371	// Read SPI data from device while MOSI (Maxim DIN) is 0. Effectively ADC_MODE_CONTROL SCAN[3:0] = SCAN_0000_NOP = 0
whismanoid	0:f7d706d2904d	1372	SPI_MOSI_Semantic = 0; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	1373	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	1374	int16_t misoData16 = SPIread16bits();
whismanoid	0:f7d706d2904d	1375	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	1376	// For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid	0:f7d706d2904d	1377	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	0:f7d706d2904d	1378	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1379	// For internal clock modes, the data format always includes the channel address.
whismanoid	0:f7d706d2904d	1380	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1381	return misoData16;
whismanoid	0:f7d706d2904d	1382	}
whismanoid	0:f7d706d2904d	1383
whismanoid	0:f7d706d2904d	1384	//----------------------------------------
whismanoid	0:f7d706d2904d	1385	// SCAN_0000_NOP
whismanoid	0:f7d706d2904d	1386	//
whismanoid	0:f7d706d2904d	1387	// Read raw ADC codes from device into AINcode[] and RAW_misoData16[].
whismanoid	0:f7d706d2904d	1388	// If internal clock mode with SWCNV=0, measurements will be triggered using CNVST pin.
whismanoid	0:f7d706d2904d	1389	//
whismanoid	0:f7d706d2904d	1390	// @pre one of the Scan functions was called, setting NumWords
whismanoid	0:f7d706d2904d	1391	// @post RAW_misoData16[index] contains the raw SPI Master-In,Slave-Out data
whismanoid	0:f7d706d2904d	1392	// @post AINcode[NUM_CHANNELS] contains the latest readings in LSBs
whismanoid	0:f7d706d2904d	1393	//
whismanoid	0:f7d706d2904d	1394	void MAX11131::ReadAINcode(void)
whismanoid	0:f7d706d2904d	1395	{
whismanoid	0:f7d706d2904d	1396
whismanoid	0:f7d706d2904d	1397	//----------------------------------------
whismanoid	0:f7d706d2904d	1398	// loop index for RAW_misoData16[SAMPLESET_MAX_ENTRIES];
whismanoid	0:f7d706d2904d	1399	int index;
whismanoid	0:f7d706d2904d	1400
whismanoid	0:f7d706d2904d	1401	//----------------------------------------
whismanoid	0:f7d706d2904d	1402	// If internal clock mode with SWCNV=0, trigger measurement using CNVST pin and wait for EOC pin.
whismanoid	0:f7d706d2904d	1403	if (isExternalClock == 0)
whismanoid	0:f7d706d2904d	1404	{
whismanoid	0:f7d706d2904d	1405	if (swcnv_0_1 == 0)
whismanoid	0:f7d706d2904d	1406	{
whismanoid	0:f7d706d2904d	1407	// SWCNV=0: trigger measurement by driving CNVST/AIN14 pin low
whismanoid	0:f7d706d2904d	1408	// for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	0:f7d706d2904d	1409	// One CNVST pulse scans all requested channels and stores the results in the FIFO.
whismanoid	0:f7d706d2904d	1410	CNVSToutputPulseLow();
whismanoid	0:f7d706d2904d	1411	}
whismanoid	0:f7d706d2904d	1412	// wait for EOC low (internal clock mode end of conversion)
whismanoid	0:f7d706d2904d	1413	EOCinputWaitUntilLow();
whismanoid	0:f7d706d2904d	1414	}
whismanoid	0:f7d706d2904d	1415
whismanoid	0:f7d706d2904d	1416	//----------------------------------------
whismanoid	0:f7d706d2904d	1417	// Read raw ADC codes from device into AINcode[] and RAW_misoData16[].
whismanoid	0:f7d706d2904d	1418	// For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid	0:f7d706d2904d	1419	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	0:f7d706d2904d	1420	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1421	// For internal clock modes, the data format always includes the channel address.
whismanoid	0:f7d706d2904d	1422	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1423	switch(ScanMode)
whismanoid	0:f7d706d2904d	1424	{
whismanoid	0:f7d706d2904d	1425	//----------------------------------------
whismanoid	0:f7d706d2904d	1426	// read data words
whismanoid	0:f7d706d2904d	1427	// For internal clock modes, the data format always includes the channel address.
whismanoid	0:f7d706d2904d	1428	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1429	case SCAN_0000_NOP:
whismanoid	0:f7d706d2904d	1430	case SCAN_0011_StandardInternalClock:
whismanoid	0:f7d706d2904d	1431	case SCAN_0101_UpperInternalClock:
whismanoid	0:f7d706d2904d	1432	case SCAN_0111_CustomInternalClock:
whismanoid	0:f7d706d2904d	1433	default:
whismanoid	0:f7d706d2904d	1434	for (index = 0; index < NumWords; index++) {
whismanoid	0:f7d706d2904d	1435	RAW_misoData16[index] = ScanRead();
whismanoid	0:f7d706d2904d	1436	// For internal clock modes, the data format always includes the channel address.
whismanoid	0:f7d706d2904d	1437	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1438	int16_t value_u12 = (RAW_misoData16[index] & 0x0FFF);
whismanoid	0:f7d706d2904d	1439	int channelId = ((RAW_misoData16[index] >> 12) & 0x000F);
whismanoid	0:f7d706d2904d	1440	AINcode[channelId] = value_u12;
whismanoid	0:f7d706d2904d	1441	}
whismanoid	0:f7d706d2904d	1442	break;
whismanoid	0:f7d706d2904d	1443	//----------------------------------------
whismanoid	0:f7d706d2904d	1444	// read data words
whismanoid	0:f7d706d2904d	1445	// For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid	0:f7d706d2904d	1446	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	0:f7d706d2904d	1447	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1448	// For internal clock modes, the data format always includes the channel address.
whismanoid	0:f7d706d2904d	1449	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1450	case SCAN_0001_Manual:
whismanoid	0:f7d706d2904d	1451	case SCAN_0100_StandardExternalClock:
whismanoid	0:f7d706d2904d	1452	case SCAN_0110_UpperExternalClock:
whismanoid	0:f7d706d2904d	1453	case SCAN_1000_CustomExternalClock:
whismanoid	0:f7d706d2904d	1454	case SCAN_1001_SampleSetExternalClock:
whismanoid	0:f7d706d2904d	1455	if (chan_id_0_1 != 0) {
whismanoid	0:f7d706d2904d	1456	for (index = 0; index < NumWords; index++) {
whismanoid	0:f7d706d2904d	1457	RAW_misoData16[index] = ScanRead();
whismanoid	0:f7d706d2904d	1458	// For internal clock modes, the data format always includes the channel address.
whismanoid	0:f7d706d2904d	1459	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1460	int16_t value_u12 = (RAW_misoData16[index] & 0x0FFF);
whismanoid	0:f7d706d2904d	1461	int channelId = ((RAW_misoData16[index] >> 12) & 0x000F);
whismanoid	0:f7d706d2904d	1462	AINcode[channelId] = value_u12;
whismanoid	0:f7d706d2904d	1463	}
whismanoid	0:f7d706d2904d	1464	} else {
whismanoid	0:f7d706d2904d	1465	for (index = 0; index < NumWords; index++) {
whismanoid	0:f7d706d2904d	1466	RAW_misoData16[index] = ScanRead();
whismanoid	0:f7d706d2904d	1467	int16_t value_u12 = ((RAW_misoData16[index] >> 3) & 0x0FFF);
whismanoid	0:f7d706d2904d	1468	int channelId = channelNumber_0_15;
whismanoid	0:f7d706d2904d	1469	AINcode[channelId] = value_u12;
whismanoid	0:f7d706d2904d	1470	}
whismanoid	0:f7d706d2904d	1471	}
whismanoid	0:f7d706d2904d	1472	break;
whismanoid	0:f7d706d2904d	1473	//----------------------------------------
whismanoid	0:f7d706d2904d	1474	// read data words and calculate mean, stddev
whismanoid	0:f7d706d2904d	1475	case SCAN_0010_Repeat:
whismanoid	0:f7d706d2904d	1476	// ScanRead_nWords_chanID_mean(NumWords); // TODO1: missing function
whismanoid	0:f7d706d2904d	1477	// was this function AINcode_print_value_chanID_mean(int nWords) in main?
whismanoid	0:f7d706d2904d	1478	// But this function prints to standard output so can't be inside the driver.
whismanoid	0:f7d706d2904d	1479	for (index = 0; index < NumWords; index++) {
whismanoid	0:f7d706d2904d	1480	RAW_misoData16[index] = ScanRead();
whismanoid	0:f7d706d2904d	1481	}
whismanoid	0:f7d706d2904d	1482	break;
whismanoid	0:f7d706d2904d	1483	}
whismanoid	0:f7d706d2904d	1484	}
whismanoid	0:f7d706d2904d	1485
whismanoid	0:f7d706d2904d	1486	//----------------------------------------
whismanoid	0:f7d706d2904d	1487	// Sign-Extend a right-aligned MAX11131 code into a signed 2's complement value.
whismanoid	0:f7d706d2904d	1488	// Supports the bipolar transfer functions.
whismanoid	0:f7d706d2904d	1489	// @param[in] value_u12: raw 12-bit MAX11131 code (right justified).
whismanoid	0:f7d706d2904d	1490	// @return sign-extended 2's complement value.
whismanoid	0:f7d706d2904d	1491	//
whismanoid	0:f7d706d2904d	1492	int32_t MAX11131::TwosComplementValue(uint32_t regValue)
whismanoid	0:f7d706d2904d	1493	{
whismanoid	0:f7d706d2904d	1494	const uint16_t SIGN_BIT_12BIT = 0x0800;
whismanoid	0:f7d706d2904d	1495	const uint16_t FULL_SCALE_CODE_12BIT = 0x0fff;
whismanoid	0:f7d706d2904d	1496	if (((regValue & SIGN_BIT_12BIT) != 0) && !((regValue & (SIGN_BIT_12BIT << 1)) != 0))
whismanoid	0:f7d706d2904d	1497	{
whismanoid	0:f7d706d2904d	1498	// (bSignBitNegative && !bExtendedSignBitNegative)
whismanoid	0:f7d706d2904d	1499	// Twos_Complement negative value
whismanoid	0:f7d706d2904d	1500	int32_t Offset_regValue = (int32_t)(regValue - (FULL_SCALE_CODE_12BIT + 1));
whismanoid	0:f7d706d2904d	1501	return Offset_regValue;
whismanoid	0:f7d706d2904d	1502	}
whismanoid	0:f7d706d2904d	1503	// Twos_Complement positive value or zero
whismanoid	0:f7d706d2904d	1504	return (int32_t)regValue;
whismanoid	0:f7d706d2904d	1505	}
whismanoid	0:f7d706d2904d	1506
whismanoid	0:f7d706d2904d	1507	//----------------------------------------
whismanoid	0:f7d706d2904d	1508	// Return the physical voltage corresponding to MAX11131 code.
whismanoid	0:f7d706d2904d	1509	// Does not perform any offset or gain correction.
whismanoid	0:f7d706d2904d	1510	// @pre VRef = Voltage of REF input, in Volts
whismanoid	0:f7d706d2904d	1511	// @param[in] value_u12: raw 12-bit MAX11131 code (right justified).
whismanoid	0:f7d706d2904d	1512	// @param[in] channelId: AIN channel number.
whismanoid	0:f7d706d2904d	1513	// @return physical voltage corresponding to MAX11131 code.
whismanoid	0:f7d706d2904d	1514	//
whismanoid	0:f7d706d2904d	1515	double MAX11131::VoltageOfCode(int16_t value_u12, int channelId)
whismanoid	0:f7d706d2904d	1516	{
whismanoid	0:f7d706d2904d	1517	int channelPairIndex = channelId / 2;
whismanoid	0:f7d706d2904d	1518	// format: 1 0 0 0 1 UCH0/1 UCH2/3 UCH4/5 UCH6/7 UCH8/9 UCH10/11 UCH12/13 UCH14/15 PDIFF_COM x x
whismanoid	0:f7d706d2904d	1519	int UCHn = (UNIPOLAR >> (10 - channelPairIndex)) & 0x01;
whismanoid	0:f7d706d2904d	1520	int BCHn = (BIPOLAR >> (10 - channelPairIndex)) & 0x01;
whismanoid	0:f7d706d2904d	1521	int RANGEn = (RANGE >> (10 - channelPairIndex)) & 0x01;
whismanoid	0:f7d706d2904d	1522	if (UCHn)
whismanoid	0:f7d706d2904d	1523	{
whismanoid	0:f7d706d2904d	1524	// UCH0/1=1, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 differential input pair, unipolar code (AIN0>AIN1) (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	1525	return (value_u12 * VRef / 4096);
whismanoid	0:f7d706d2904d	1526	}
whismanoid	0:f7d706d2904d	1527	else
whismanoid	0:f7d706d2904d	1528	{
whismanoid	0:f7d706d2904d	1529	if (BCHn)
whismanoid	0:f7d706d2904d	1530	{
whismanoid	0:f7d706d2904d	1531	if (RANGEn)
whismanoid	0:f7d706d2904d	1532	{
whismanoid	0:f7d706d2904d	1533	// UCH0/1=0, BCH0/1=1, RANGE0/1=1: AIN0/AIN1 differential input pair ±Vref, bipolar code (Full Scale = 2VREF, LSB = VREF/2048)
whismanoid	0:f7d706d2904d	1534	return (TwosComplementValue(value_u12) * VRef / 2048);
whismanoid	0:f7d706d2904d	1535	}
whismanoid	0:f7d706d2904d	1536	else
whismanoid	0:f7d706d2904d	1537	{
whismanoid	0:f7d706d2904d	1538	// UCH0/1=0, BCH0/1=1, RANGE0/1=0: AIN0/AIN1 differential input pair ±½Vref, bipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	1539	return (TwosComplementValue(value_u12) * VRef / 4096);
whismanoid	0:f7d706d2904d	1540	}
whismanoid	0:f7d706d2904d	1541	}
whismanoid	0:f7d706d2904d	1542	else
whismanoid	0:f7d706d2904d	1543	{
whismanoid	0:f7d706d2904d	1544	// UCH0/1=0, BCH0/1=0, RANGE0/1=0: AIN0/AIN1 two independent single-ended inputs, unipolar code (Full Scale = VREF, LSB = VREF/4096)
whismanoid	0:f7d706d2904d	1545	return (value_u12 * VRef / 4096);
whismanoid	0:f7d706d2904d	1546	}
whismanoid	0:f7d706d2904d	1547	}
whismanoid	0:f7d706d2904d	1548	}
whismanoid	0:f7d706d2904d	1549
whismanoid	0:f7d706d2904d	1550	//----------------------------------------
whismanoid	0:f7d706d2904d	1551	// SCAN_0001_Manual
whismanoid	0:f7d706d2904d	1552	//
whismanoid	0:f7d706d2904d	1553	// Measure ADC channel channelNumber_0_15 once.
whismanoid	0:f7d706d2904d	1554	// External clock mode.
whismanoid	0:f7d706d2904d	1555	// @param[in] channelNumber_0_15: AIN Channel Number
whismanoid	0:f7d706d2904d	1556	// @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	0:f7d706d2904d	1557	// @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid	0:f7d706d2904d	1558	// @return number of ScanRead() words needed to retrieve the data.
whismanoid	0:f7d706d2904d	1559	// For external clock modes, the data format depends on CHAN_ID.
whismanoid	0:f7d706d2904d	1560	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	0:f7d706d2904d	1561	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1562	//
whismanoid	0:f7d706d2904d	1563	int MAX11131::ScanManual(void)
whismanoid	0:f7d706d2904d	1564	{
whismanoid	0:f7d706d2904d	1565
whismanoid	0:f7d706d2904d	1566	//----------------------------------------
whismanoid	0:f7d706d2904d	1567	// number of words to read
whismanoid	0:f7d706d2904d	1568	NumWords = 1;
whismanoid	0:f7d706d2904d	1569
whismanoid	0:f7d706d2904d	1570	//----------------------------------------
whismanoid	0:f7d706d2904d	1571	// External Clock Mode
whismanoid	0:f7d706d2904d	1572	isExternalClock = 1;
whismanoid	0:f7d706d2904d	1573
whismanoid	0:f7d706d2904d	1574	//----------------------------------------
whismanoid	0:f7d706d2904d	1575	// update device driver global variable
whismanoid	0:f7d706d2904d	1576	ScanMode = SCAN_0001_Manual;
whismanoid	0:f7d706d2904d	1577
whismanoid	0:f7d706d2904d	1578	//----------------------------------------
whismanoid	0:f7d706d2904d	1579	// define write-only register ADC_MODE_CONTROL
whismanoid	0:f7d706d2904d	1580	ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid	0:f7d706d2904d	1581	const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid	0:f7d706d2904d	1582	const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid	0:f7d706d2904d	1583	const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	1584	const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid	0:f7d706d2904d	1585	const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid	0:f7d706d2904d	1586	const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid	0:f7d706d2904d	1587
whismanoid	0:f7d706d2904d	1588	//----------------------------------------
whismanoid	0:f7d706d2904d	1589	// Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid	0:f7d706d2904d	1590	ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	1591	ADC_MODE_CONTROL \|= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	1592
whismanoid	0:f7d706d2904d	1593	//----------------------------------------
whismanoid	0:f7d706d2904d	1594	// ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0001_Manual = 1
whismanoid	0:f7d706d2904d	1595	//~ const int SCAN_0001_Manual = 1; // replaced local const with enum
whismanoid	0:f7d706d2904d	1596	ADC_MODE_CONTROL \|= ((SCAN_0001_Manual & SCAN_BITS) << SCAN_LSB);
whismanoid	0:f7d706d2904d	1597
whismanoid	0:f7d706d2904d	1598	//----------------------------------------
whismanoid	0:f7d706d2904d	1599	// ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid	0:f7d706d2904d	1600	ADC_MODE_CONTROL \|= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid	0:f7d706d2904d	1601
whismanoid	0:f7d706d2904d	1602	//----------------------------------------
whismanoid	0:f7d706d2904d	1603	// ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid	0:f7d706d2904d	1604	ADC_MODE_CONTROL \|= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid	0:f7d706d2904d	1605
whismanoid	0:f7d706d2904d	1606	//----------------------------------------
whismanoid	0:f7d706d2904d	1607	// ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid	0:f7d706d2904d	1608	// (applicable to external clock mode only)
whismanoid	0:f7d706d2904d	1609	// For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid	0:f7d706d2904d	1610	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	0:f7d706d2904d	1611	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1612	// For internal clock modes, the data format always includes the channel address.
whismanoid	0:f7d706d2904d	1613	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1614	ADC_MODE_CONTROL \|= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid	0:f7d706d2904d	1615
whismanoid	0:f7d706d2904d	1616	//----------------------------------------
whismanoid	0:f7d706d2904d	1617	// SPI write ADC MODE CONTROL register
whismanoid	0:f7d706d2904d	1618	// Send SPI configuration to device
whismanoid	0:f7d706d2904d	1619	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	1620	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	1621	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	0:f7d706d2904d	1622	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	1623
whismanoid	0:f7d706d2904d	1624	//----------------------------------------
whismanoid	0:f7d706d2904d	1625	// return number of words to read
whismanoid	0:f7d706d2904d	1626	return NumWords;
whismanoid	0:f7d706d2904d	1627	}
whismanoid	0:f7d706d2904d	1628
whismanoid	0:f7d706d2904d	1629	//----------------------------------------
whismanoid	0:f7d706d2904d	1630	// SCAN_0010_Repeat
whismanoid	0:f7d706d2904d	1631	//
whismanoid	0:f7d706d2904d	1632	// Measure ADC channel channelNumber_0_15 repeatedly with averaging.
whismanoid	0:f7d706d2904d	1633	// Internal clock mode.
whismanoid	0:f7d706d2904d	1634	// @param[in] channelNumber_0_15: AIN Channel Number
whismanoid	0:f7d706d2904d	1635	// @param[in] average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid	0:f7d706d2904d	1636	// average_0_4_8_16_32=0 to disable averaging.
whismanoid	0:f7d706d2904d	1637	// @param[in] nscan_4_8_12_16: Number of ScanRead() words to report.
whismanoid	0:f7d706d2904d	1638	// @param[in] swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid	0:f7d706d2904d	1639	// SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid	0:f7d706d2904d	1640	// Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	0:f7d706d2904d	1641	// SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid	0:f7d706d2904d	1642	// CS must be held low for minimum of 17 SCLK cycles.
whismanoid	0:f7d706d2904d	1643	// CNVST pin is not used. (AIN14 is available)
whismanoid	0:f7d706d2904d	1644	// @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	0:f7d706d2904d	1645	// @return number of ScanRead() words needed to retrieve the data.
whismanoid	0:f7d706d2904d	1646	// For internal clock modes, the data format always includes the channel address.
whismanoid	0:f7d706d2904d	1647	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1648	//
whismanoid	0:f7d706d2904d	1649	int MAX11131::ScanRepeat(void)
whismanoid	0:f7d706d2904d	1650	{
whismanoid	0:f7d706d2904d	1651
whismanoid	0:f7d706d2904d	1652	//----------------------------------------
whismanoid	0:f7d706d2904d	1653	// number of words to read
whismanoid	0:f7d706d2904d	1654	NumWords = (nscan_4_8_12_16);
whismanoid	0:f7d706d2904d	1655
whismanoid	0:f7d706d2904d	1656	//----------------------------------------
whismanoid	0:f7d706d2904d	1657	// Internal Clock Mode
whismanoid	0:f7d706d2904d	1658	isExternalClock = 0;
whismanoid	0:f7d706d2904d	1659
whismanoid	0:f7d706d2904d	1660	//----------------------------------------
whismanoid	0:f7d706d2904d	1661	// update device driver global variable
whismanoid	0:f7d706d2904d	1662	ScanMode = SCAN_0010_Repeat;
whismanoid	0:f7d706d2904d	1663
whismanoid	0:f7d706d2904d	1664	//----------------------------------------
whismanoid	0:f7d706d2904d	1665	// define write-only register ADC_MODE_CONTROL
whismanoid	0:f7d706d2904d	1666	ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid	0:f7d706d2904d	1667	const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid	0:f7d706d2904d	1668	const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid	0:f7d706d2904d	1669	const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	1670	const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid	0:f7d706d2904d	1671	const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid	0:f7d706d2904d	1672	const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid	0:f7d706d2904d	1673
whismanoid	0:f7d706d2904d	1674	//----------------------------------------
whismanoid	0:f7d706d2904d	1675	// define write-only register ADC_CONFIGURATION
whismanoid	0:f7d706d2904d	1676	ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid	0:f7d706d2904d	1677	const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid	0:f7d706d2904d	1678	const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid	0:f7d706d2904d	1679	const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid	0:f7d706d2904d	1680	const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid	0:f7d706d2904d	1681	const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid	0:f7d706d2904d	1682	const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid	0:f7d706d2904d	1683
whismanoid	0:f7d706d2904d	1684	//----------------------------------------
whismanoid	0:f7d706d2904d	1685	// if average, ADC CONFIGURATION register set AVG and NAVG[1:0]
whismanoid	0:f7d706d2904d	1686	// (applicable to internal clock mode only)
whismanoid	0:f7d706d2904d	1687	// if average, ADC CONFIGURATION register set AVG ON BIT TO 1
whismanoid	0:f7d706d2904d	1688	// if average, ADC CONFIGURATION register set NAVG[1:0] TO N
whismanoid	0:f7d706d2904d	1689	if (average_0_4_8_16_32 == 4) {
whismanoid	0:f7d706d2904d	1690	// Enable Averaging of 4 samples (AVGON=1, NAVG[1:0]=0)
whismanoid	0:f7d706d2904d	1691	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	0:f7d706d2904d	1692	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	1693	ADC_CONFIGURATION \|= ((0 & NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	1694	} else if (average_0_4_8_16_32 == 8) {
whismanoid	0:f7d706d2904d	1695	// Enable Averaging of 8 samples (AVGON=1, NAVG[1:0]=1)
whismanoid	0:f7d706d2904d	1696	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	0:f7d706d2904d	1697	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	1698	ADC_CONFIGURATION \|= ((1 & NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	1699	} else if (average_0_4_8_16_32 == 16) {
whismanoid	0:f7d706d2904d	1700	// Enable Averaging of 16 samples (AVGON=1, NAVG[1:0]=2)
whismanoid	0:f7d706d2904d	1701	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	0:f7d706d2904d	1702	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	1703	ADC_CONFIGURATION \|= ((2 & NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	1704	} else if (average_0_4_8_16_32 == 32) {
whismanoid	0:f7d706d2904d	1705	// Enable Averaging of 32 samples (AVGON=1, NAVG[1:0]=3)
whismanoid	0:f7d706d2904d	1706	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	0:f7d706d2904d	1707	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	1708	ADC_CONFIGURATION \|= ((3 & NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	1709	} else {
whismanoid	0:f7d706d2904d	1710	// Disable Averaging (AVGON=0, NAVG[1:0]=0)
whismanoid	0:f7d706d2904d	1711	ADC_CONFIGURATION &= ~ (( AVGON_BITS) << AVGON_LSB);
whismanoid	0:f7d706d2904d	1712	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	1713	}
whismanoid	0:f7d706d2904d	1714
whismanoid	0:f7d706d2904d	1715	//----------------------------------------
whismanoid	0:f7d706d2904d	1716	// ADC CONFIGURATION register set NSCAN[1:0] for scan count
whismanoid	0:f7d706d2904d	1717	// (applicable to SCAN_0010_Repeat only)
whismanoid	0:f7d706d2904d	1718	if (nscan_4_8_12_16 == 4) {
whismanoid	0:f7d706d2904d	1719	// Set scan count 4
whismanoid	0:f7d706d2904d	1720	ADC_CONFIGURATION &= ~ (( NSCAN_BITS) << NSCAN_LSB);
whismanoid	0:f7d706d2904d	1721	ADC_CONFIGURATION \|= ((0 & NSCAN_BITS) << NSCAN_LSB);
whismanoid	0:f7d706d2904d	1722	} else if (nscan_4_8_12_16 == 8) {
whismanoid	0:f7d706d2904d	1723	// Set scan count 8
whismanoid	0:f7d706d2904d	1724	ADC_CONFIGURATION &= ~ (( NSCAN_BITS) << NSCAN_LSB);
whismanoid	0:f7d706d2904d	1725	ADC_CONFIGURATION \|= ((1 & NSCAN_BITS) << NSCAN_LSB);
whismanoid	0:f7d706d2904d	1726	} else if (nscan_4_8_12_16 == 12) {
whismanoid	0:f7d706d2904d	1727	// Set scan count 12
whismanoid	0:f7d706d2904d	1728	ADC_CONFIGURATION &= ~ (( NSCAN_BITS) << NSCAN_LSB);
whismanoid	0:f7d706d2904d	1729	ADC_CONFIGURATION \|= ((2 & NSCAN_BITS) << NSCAN_LSB);
whismanoid	0:f7d706d2904d	1730	} else if (nscan_4_8_12_16 == 16) {
whismanoid	0:f7d706d2904d	1731	// Set scan count 16
whismanoid	0:f7d706d2904d	1732	ADC_CONFIGURATION &= ~ (( NSCAN_BITS) << NSCAN_LSB);
whismanoid	0:f7d706d2904d	1733	ADC_CONFIGURATION \|= ((3 & NSCAN_BITS) << NSCAN_LSB);
whismanoid	0:f7d706d2904d	1734	}
whismanoid	0:f7d706d2904d	1735
whismanoid	0:f7d706d2904d	1736	//----------------------------------------
whismanoid	0:f7d706d2904d	1737	// SPI write ADC CONFIGURATION register
whismanoid	0:f7d706d2904d	1738	// Send SPI configuration to device
whismanoid	0:f7d706d2904d	1739	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	1740	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	1741	SPIwrite16bits(ADC_CONFIGURATION);
whismanoid	0:f7d706d2904d	1742	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	1743
whismanoid	0:f7d706d2904d	1744	//----------------------------------------
whismanoid	0:f7d706d2904d	1745	// Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid	0:f7d706d2904d	1746	ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	1747	ADC_MODE_CONTROL \|= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	1748
whismanoid	0:f7d706d2904d	1749	//----------------------------------------
whismanoid	0:f7d706d2904d	1750	// ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0010_Repeat = 2
whismanoid	0:f7d706d2904d	1751	//~ const int SCAN_0010_Repeat = 2; // replaced local const with enum
whismanoid	0:f7d706d2904d	1752	ADC_MODE_CONTROL \|= ((SCAN_0010_Repeat & SCAN_BITS) << SCAN_LSB);
whismanoid	0:f7d706d2904d	1753
whismanoid	0:f7d706d2904d	1754	//----------------------------------------
whismanoid	0:f7d706d2904d	1755	// ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid	0:f7d706d2904d	1756	ADC_MODE_CONTROL \|= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid	0:f7d706d2904d	1757
whismanoid	0:f7d706d2904d	1758	//----------------------------------------
whismanoid	0:f7d706d2904d	1759	// ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid	0:f7d706d2904d	1760	ADC_MODE_CONTROL \|= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid	0:f7d706d2904d	1761
whismanoid	0:f7d706d2904d	1762	//----------------------------------------
whismanoid	0:f7d706d2904d	1763	// ADC MODE CONTROL register set SWCNV if CNVST pin is not used
whismanoid	0:f7d706d2904d	1764	// ADC MODE CONTROL REGISTER SELECT THE RIGHT SWCNV BIT
whismanoid	0:f7d706d2904d	1765	// (applicable to internal clock mode only)
whismanoid	0:f7d706d2904d	1766	// SWCNV=1: trigger measurement on SPI CS rising edge; CNVST pin is not used. (AIN14 is available)
whismanoid	0:f7d706d2904d	1767	// SWCNV=0: trigger measurement by driving CNVST pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	0:f7d706d2904d	1768	if (swcnv_0_1) {
whismanoid	0:f7d706d2904d	1769	ADC_MODE_CONTROL \|= ((swcnv_0_1 & SWCNV_BITS) << SWCNV_LSB);
whismanoid	0:f7d706d2904d	1770	} else {
whismanoid	0:f7d706d2904d	1771	ADC_MODE_CONTROL &= ~ (( SWCNV_BITS) << SWCNV_LSB);
whismanoid	0:f7d706d2904d	1772	}
whismanoid	0:f7d706d2904d	1773
whismanoid	0:f7d706d2904d	1774	//----------------------------------------
whismanoid	0:f7d706d2904d	1775	// SPI write ADC MODE CONTROL register
whismanoid	0:f7d706d2904d	1776	// If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid	0:f7d706d2904d	1777	// Send SPI configuration to device
whismanoid	0:f7d706d2904d	1778	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	1779	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	1780	if (swcnv_0_1) {
whismanoid	0:f7d706d2904d	1781	// If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid	0:f7d706d2904d	1782	// NOTE: Figure 7 Internal Conversions with SWCNV=1 has an error, the 17th SCLK is mislabeled as "16" should be "17".
whismanoid	0:f7d706d2904d	1783	SPIwrite24bits(ADC_MODE_CONTROL, 0);
whismanoid	0:f7d706d2904d	1784	} else {
whismanoid	0:f7d706d2904d	1785	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	0:f7d706d2904d	1786	}
whismanoid	0:f7d706d2904d	1787	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	1788
whismanoid	0:f7d706d2904d	1789	//----------------------------------------
whismanoid	0:f7d706d2904d	1790	// return number of words to read
whismanoid	0:f7d706d2904d	1791	return NumWords;
whismanoid	0:f7d706d2904d	1792	}
whismanoid	0:f7d706d2904d	1793
whismanoid	0:f7d706d2904d	1794	//----------------------------------------
whismanoid	0:f7d706d2904d	1795	// SCAN_0011_StandardInternalClock
whismanoid	0:f7d706d2904d	1796	//
whismanoid	0:f7d706d2904d	1797	// Measure ADC channels in sequence from AIN0 to channelNumber_0_15.
whismanoid	0:f7d706d2904d	1798	// Internal clock mode.
whismanoid	0:f7d706d2904d	1799	// @param[in] channelNumber_0_15: AIN Channel Number
whismanoid	0:f7d706d2904d	1800	// @param[in] average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid	0:f7d706d2904d	1801	// average_0_4_8_16_32=0 to disable averaging.
whismanoid	0:f7d706d2904d	1802	// @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	0:f7d706d2904d	1803	// @param[in] swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid	0:f7d706d2904d	1804	// SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid	0:f7d706d2904d	1805	// Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	0:f7d706d2904d	1806	// SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid	0:f7d706d2904d	1807	// CS must be held low for minimum of 17 SCLK cycles.
whismanoid	0:f7d706d2904d	1808	// CNVST pin is not used. (AIN14 is available)
whismanoid	0:f7d706d2904d	1809	// @return number of ScanRead() words needed to retrieve the data.
whismanoid	0:f7d706d2904d	1810	// For internal clock modes, the data format always includes the channel address.
whismanoid	0:f7d706d2904d	1811	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1812	//
whismanoid	0:f7d706d2904d	1813	int MAX11131::ScanStandardInternalClock(void)
whismanoid	0:f7d706d2904d	1814	{
whismanoid	0:f7d706d2904d	1815
whismanoid	0:f7d706d2904d	1816	//----------------------------------------
whismanoid	0:f7d706d2904d	1817	// number of words to read
whismanoid	0:f7d706d2904d	1818	NumWords = (1 + channelNumber_0_15);
whismanoid	0:f7d706d2904d	1819
whismanoid	0:f7d706d2904d	1820	//----------------------------------------
whismanoid	0:f7d706d2904d	1821	// Internal Clock Mode
whismanoid	0:f7d706d2904d	1822	isExternalClock = 0;
whismanoid	0:f7d706d2904d	1823
whismanoid	0:f7d706d2904d	1824	//----------------------------------------
whismanoid	0:f7d706d2904d	1825	// update device driver global variable
whismanoid	0:f7d706d2904d	1826	ScanMode = SCAN_0011_StandardInternalClock;
whismanoid	0:f7d706d2904d	1827
whismanoid	0:f7d706d2904d	1828	//----------------------------------------
whismanoid	0:f7d706d2904d	1829	// define write-only register ADC_MODE_CONTROL
whismanoid	0:f7d706d2904d	1830	ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid	0:f7d706d2904d	1831	const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid	0:f7d706d2904d	1832	const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid	0:f7d706d2904d	1833	const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	1834	const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid	0:f7d706d2904d	1835	const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid	0:f7d706d2904d	1836	const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid	0:f7d706d2904d	1837
whismanoid	0:f7d706d2904d	1838	//----------------------------------------
whismanoid	0:f7d706d2904d	1839	// define write-only register ADC_CONFIGURATION
whismanoid	0:f7d706d2904d	1840	ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid	0:f7d706d2904d	1841	const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid	0:f7d706d2904d	1842	const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid	0:f7d706d2904d	1843	const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid	0:f7d706d2904d	1844	const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid	0:f7d706d2904d	1845	const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid	0:f7d706d2904d	1846	const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid	0:f7d706d2904d	1847
whismanoid	0:f7d706d2904d	1848	//----------------------------------------
whismanoid	0:f7d706d2904d	1849	// if average, ADC CONFIGURATION register set AVG and NAVG[1:0]
whismanoid	0:f7d706d2904d	1850	// (applicable to internal clock mode only)
whismanoid	0:f7d706d2904d	1851	// if average, ADC CONFIGURATION register set AVG ON BIT TO 1
whismanoid	0:f7d706d2904d	1852	// if average, ADC CONFIGURATION register set NAVG[1:0] TO N
whismanoid	0:f7d706d2904d	1853	if (average_0_4_8_16_32 == 4) {
whismanoid	0:f7d706d2904d	1854	// Enable Averaging of 4 samples (AVGON=1, NAVG[1:0]=0)
whismanoid	0:f7d706d2904d	1855	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	0:f7d706d2904d	1856	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	1857	ADC_CONFIGURATION \|= ((0 & NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	1858	} else if (average_0_4_8_16_32 == 8) {
whismanoid	0:f7d706d2904d	1859	// Enable Averaging of 8 samples (AVGON=1, NAVG[1:0]=1)
whismanoid	0:f7d706d2904d	1860	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	0:f7d706d2904d	1861	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	1862	ADC_CONFIGURATION \|= ((1 & NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	1863	} else if (average_0_4_8_16_32 == 16) {
whismanoid	0:f7d706d2904d	1864	// Enable Averaging of 16 samples (AVGON=1, NAVG[1:0]=2)
whismanoid	0:f7d706d2904d	1865	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	0:f7d706d2904d	1866	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	1867	ADC_CONFIGURATION \|= ((2 & NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	1868	} else if (average_0_4_8_16_32 == 32) {
whismanoid	0:f7d706d2904d	1869	// Enable Averaging of 32 samples (AVGON=1, NAVG[1:0]=3)
whismanoid	0:f7d706d2904d	1870	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	0:f7d706d2904d	1871	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	1872	ADC_CONFIGURATION \|= ((3 & NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	1873	} else {
whismanoid	0:f7d706d2904d	1874	// Disable Averaging (AVGON=0, NAVG[1:0]=0)
whismanoid	0:f7d706d2904d	1875	ADC_CONFIGURATION &= ~ (( AVGON_BITS) << AVGON_LSB);
whismanoid	0:f7d706d2904d	1876	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	1877	}
whismanoid	0:f7d706d2904d	1878
whismanoid	0:f7d706d2904d	1879	//----------------------------------------
whismanoid	0:f7d706d2904d	1880	// SPI write ADC CONFIGURATION register
whismanoid	0:f7d706d2904d	1881	// Send SPI configuration to device
whismanoid	0:f7d706d2904d	1882	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	1883	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	1884	SPIwrite16bits(ADC_CONFIGURATION);
whismanoid	0:f7d706d2904d	1885	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	1886
whismanoid	0:f7d706d2904d	1887	//----------------------------------------
whismanoid	0:f7d706d2904d	1888	// Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid	0:f7d706d2904d	1889	ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	1890	ADC_MODE_CONTROL \|= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	1891
whismanoid	0:f7d706d2904d	1892	//----------------------------------------
whismanoid	0:f7d706d2904d	1893	// ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0011_StandardInternalClock = 3
whismanoid	0:f7d706d2904d	1894	//~ const int SCAN_0011_StandardInternalClock = 3; // replaced local const with enum
whismanoid	0:f7d706d2904d	1895	ADC_MODE_CONTROL \|= ((SCAN_0011_StandardInternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid	0:f7d706d2904d	1896
whismanoid	0:f7d706d2904d	1897	//----------------------------------------
whismanoid	0:f7d706d2904d	1898	// ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid	0:f7d706d2904d	1899	ADC_MODE_CONTROL \|= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid	0:f7d706d2904d	1900
whismanoid	0:f7d706d2904d	1901	//----------------------------------------
whismanoid	0:f7d706d2904d	1902	// ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid	0:f7d706d2904d	1903	ADC_MODE_CONTROL \|= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid	0:f7d706d2904d	1904
whismanoid	0:f7d706d2904d	1905	//----------------------------------------
whismanoid	0:f7d706d2904d	1906	// ADC MODE CONTROL register set SWCNV if CNVST pin is not used
whismanoid	0:f7d706d2904d	1907	// ADC MODE CONTROL REGISTER SELECT THE RIGHT SWCNV BIT
whismanoid	0:f7d706d2904d	1908	// (applicable to internal clock mode only)
whismanoid	0:f7d706d2904d	1909	// SWCNV=1: trigger measurement on SPI CS rising edge; CNVST pin is not used. (AIN14 is available)
whismanoid	0:f7d706d2904d	1910	// SWCNV=0: trigger measurement by driving CNVST pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	0:f7d706d2904d	1911	if (swcnv_0_1) {
whismanoid	0:f7d706d2904d	1912	ADC_MODE_CONTROL \|= ((swcnv_0_1 & SWCNV_BITS) << SWCNV_LSB);
whismanoid	0:f7d706d2904d	1913	} else {
whismanoid	0:f7d706d2904d	1914	ADC_MODE_CONTROL &= ~ (( SWCNV_BITS) << SWCNV_LSB);
whismanoid	0:f7d706d2904d	1915	}
whismanoid	0:f7d706d2904d	1916
whismanoid	0:f7d706d2904d	1917	//----------------------------------------
whismanoid	0:f7d706d2904d	1918	// SPI write ADC MODE CONTROL register
whismanoid	0:f7d706d2904d	1919	// If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid	0:f7d706d2904d	1920	// Send SPI configuration to device
whismanoid	0:f7d706d2904d	1921	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	1922	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	1923	if (swcnv_0_1) {
whismanoid	0:f7d706d2904d	1924	// If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid	0:f7d706d2904d	1925	// NOTE: Figure 7 Internal Conversions with SWCNV=1 has an error, the 17th SCLK is mislabeled as "16" should be "17".
whismanoid	0:f7d706d2904d	1926	SPIwrite24bits(ADC_MODE_CONTROL, 0);
whismanoid	0:f7d706d2904d	1927	} else {
whismanoid	0:f7d706d2904d	1928	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	0:f7d706d2904d	1929	}
whismanoid	0:f7d706d2904d	1930	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	1931
whismanoid	0:f7d706d2904d	1932	//----------------------------------------
whismanoid	0:f7d706d2904d	1933	// return number of words to read
whismanoid	0:f7d706d2904d	1934	return NumWords;
whismanoid	0:f7d706d2904d	1935	}
whismanoid	0:f7d706d2904d	1936
whismanoid	0:f7d706d2904d	1937	//----------------------------------------
whismanoid	0:f7d706d2904d	1938	// SCAN_0100_StandardExternalClock
whismanoid	0:f7d706d2904d	1939	//
whismanoid	0:f7d706d2904d	1940	// Measure ADC channels in sequence from AIN0 to channelNumber_0_15.
whismanoid	0:f7d706d2904d	1941	// External clock mode.
whismanoid	0:f7d706d2904d	1942	// @param[in] channelNumber_0_15: AIN Channel Number
whismanoid	0:f7d706d2904d	1943	// @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	0:f7d706d2904d	1944	// @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid	0:f7d706d2904d	1945	// @return number of ScanRead() words needed to retrieve the data.
whismanoid	0:f7d706d2904d	1946	// For external clock modes, the data format depends on CHAN_ID.
whismanoid	0:f7d706d2904d	1947	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	0:f7d706d2904d	1948	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1949	//
whismanoid	0:f7d706d2904d	1950	int MAX11131::ScanStandardExternalClock(void)
whismanoid	0:f7d706d2904d	1951	{
whismanoid	0:f7d706d2904d	1952
whismanoid	0:f7d706d2904d	1953	//----------------------------------------
whismanoid	0:f7d706d2904d	1954	// number of words to read
whismanoid	0:f7d706d2904d	1955	NumWords = (1 + channelNumber_0_15);
whismanoid	0:f7d706d2904d	1956
whismanoid	0:f7d706d2904d	1957	//----------------------------------------
whismanoid	0:f7d706d2904d	1958	// External Clock Mode
whismanoid	0:f7d706d2904d	1959	isExternalClock = 1;
whismanoid	0:f7d706d2904d	1960
whismanoid	0:f7d706d2904d	1961	//----------------------------------------
whismanoid	0:f7d706d2904d	1962	// update device driver global variable
whismanoid	0:f7d706d2904d	1963	ScanMode = SCAN_0100_StandardExternalClock;
whismanoid	0:f7d706d2904d	1964
whismanoid	0:f7d706d2904d	1965	//----------------------------------------
whismanoid	0:f7d706d2904d	1966	// define write-only register ADC_MODE_CONTROL
whismanoid	0:f7d706d2904d	1967	ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid	0:f7d706d2904d	1968	const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid	0:f7d706d2904d	1969	const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid	0:f7d706d2904d	1970	const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	1971	const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid	0:f7d706d2904d	1972	const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid	0:f7d706d2904d	1973	const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid	0:f7d706d2904d	1974
whismanoid	0:f7d706d2904d	1975	//----------------------------------------
whismanoid	0:f7d706d2904d	1976	// Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid	0:f7d706d2904d	1977	ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	1978	ADC_MODE_CONTROL \|= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	1979
whismanoid	0:f7d706d2904d	1980	//----------------------------------------
whismanoid	0:f7d706d2904d	1981	// ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0100_StandardExternalClock = 4
whismanoid	0:f7d706d2904d	1982	//~ const int SCAN_0100_StandardExternalClock = 4; // replaced local const with enum
whismanoid	0:f7d706d2904d	1983	ADC_MODE_CONTROL \|= ((SCAN_0100_StandardExternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid	0:f7d706d2904d	1984
whismanoid	0:f7d706d2904d	1985	//----------------------------------------
whismanoid	0:f7d706d2904d	1986	// ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid	0:f7d706d2904d	1987	ADC_MODE_CONTROL \|= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid	0:f7d706d2904d	1988
whismanoid	0:f7d706d2904d	1989	//----------------------------------------
whismanoid	0:f7d706d2904d	1990	// ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid	0:f7d706d2904d	1991	ADC_MODE_CONTROL \|= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid	0:f7d706d2904d	1992
whismanoid	0:f7d706d2904d	1993	//----------------------------------------
whismanoid	0:f7d706d2904d	1994	// ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid	0:f7d706d2904d	1995	// (applicable to external clock mode only)
whismanoid	0:f7d706d2904d	1996	// For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid	0:f7d706d2904d	1997	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	0:f7d706d2904d	1998	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1999	// For internal clock modes, the data format always includes the channel address.
whismanoid	0:f7d706d2904d	2000	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	2001	ADC_MODE_CONTROL \|= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid	0:f7d706d2904d	2002
whismanoid	0:f7d706d2904d	2003	//----------------------------------------
whismanoid	0:f7d706d2904d	2004	// SPI write ADC MODE CONTROL register
whismanoid	0:f7d706d2904d	2005	// Send SPI configuration to device
whismanoid	0:f7d706d2904d	2006	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	2007	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	2008	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	0:f7d706d2904d	2009	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	2010
whismanoid	0:f7d706d2904d	2011	//----------------------------------------
whismanoid	0:f7d706d2904d	2012	// return number of words to read
whismanoid	0:f7d706d2904d	2013	return NumWords;
whismanoid	0:f7d706d2904d	2014	}
whismanoid	0:f7d706d2904d	2015
whismanoid	0:f7d706d2904d	2016	//----------------------------------------
whismanoid	0:f7d706d2904d	2017	// SCAN_0101_UpperInternalClock
whismanoid	0:f7d706d2904d	2018	//
whismanoid	0:f7d706d2904d	2019	// Measure ADC channels in sequence from channelNumber_0_15 to AIN15.
whismanoid	0:f7d706d2904d	2020	// Internal clock mode.
whismanoid	0:f7d706d2904d	2021	// @param[in] channelNumber_0_15: AIN Channel Number
whismanoid	0:f7d706d2904d	2022	// @param[in] average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid	0:f7d706d2904d	2023	// average_0_4_8_16_32=0 to disable averaging.
whismanoid	0:f7d706d2904d	2024	// @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	0:f7d706d2904d	2025	// @param[in] swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid	0:f7d706d2904d	2026	// SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid	0:f7d706d2904d	2027	// Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	0:f7d706d2904d	2028	// SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid	0:f7d706d2904d	2029	// CS must be held low for minimum of 17 SCLK cycles.
whismanoid	0:f7d706d2904d	2030	// CNVST pin is not used. (AIN14 is available)
whismanoid	0:f7d706d2904d	2031	// @return number of ScanRead() words needed to retrieve the data.
whismanoid	0:f7d706d2904d	2032	// For internal clock modes, the data format always includes the channel address.
whismanoid	0:f7d706d2904d	2033	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	2034	//
whismanoid	0:f7d706d2904d	2035	int MAX11131::ScanUpperInternalClock(void)
whismanoid	0:f7d706d2904d	2036	{
whismanoid	0:f7d706d2904d	2037
whismanoid	0:f7d706d2904d	2038	//----------------------------------------
whismanoid	0:f7d706d2904d	2039	// number of words to read
whismanoid	0:f7d706d2904d	2040	NumWords = (16 - channelNumber_0_15);
whismanoid	0:f7d706d2904d	2041
whismanoid	0:f7d706d2904d	2042	//----------------------------------------
whismanoid	0:f7d706d2904d	2043	// Internal Clock Mode
whismanoid	0:f7d706d2904d	2044	isExternalClock = 0;
whismanoid	0:f7d706d2904d	2045
whismanoid	0:f7d706d2904d	2046	//----------------------------------------
whismanoid	0:f7d706d2904d	2047	// update device driver global variable
whismanoid	0:f7d706d2904d	2048	ScanMode = SCAN_0101_UpperInternalClock;
whismanoid	0:f7d706d2904d	2049
whismanoid	0:f7d706d2904d	2050	//----------------------------------------
whismanoid	0:f7d706d2904d	2051	// define write-only register ADC_MODE_CONTROL
whismanoid	0:f7d706d2904d	2052	ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid	0:f7d706d2904d	2053	const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid	0:f7d706d2904d	2054	const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid	0:f7d706d2904d	2055	const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	2056	const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid	0:f7d706d2904d	2057	const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid	0:f7d706d2904d	2058	const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid	0:f7d706d2904d	2059
whismanoid	0:f7d706d2904d	2060	//----------------------------------------
whismanoid	0:f7d706d2904d	2061	// define write-only register ADC_CONFIGURATION
whismanoid	0:f7d706d2904d	2062	ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid	0:f7d706d2904d	2063	const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid	0:f7d706d2904d	2064	const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid	0:f7d706d2904d	2065	const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid	0:f7d706d2904d	2066	const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid	0:f7d706d2904d	2067	const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid	0:f7d706d2904d	2068	const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid	0:f7d706d2904d	2069
whismanoid	0:f7d706d2904d	2070	//----------------------------------------
whismanoid	0:f7d706d2904d	2071	// if average, ADC CONFIGURATION register set AVG and NAVG[1:0]
whismanoid	0:f7d706d2904d	2072	// (applicable to internal clock mode only)
whismanoid	0:f7d706d2904d	2073	// if average, ADC CONFIGURATION register set AVG ON BIT TO 1
whismanoid	0:f7d706d2904d	2074	// if average, ADC CONFIGURATION register set NAVG[1:0] TO N
whismanoid	0:f7d706d2904d	2075	if (average_0_4_8_16_32 == 4) {
whismanoid	0:f7d706d2904d	2076	// Enable Averaging of 4 samples (AVGON=1, NAVG[1:0]=0)
whismanoid	0:f7d706d2904d	2077	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	0:f7d706d2904d	2078	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	2079	ADC_CONFIGURATION \|= ((0 & NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	2080	} else if (average_0_4_8_16_32 == 8) {
whismanoid	0:f7d706d2904d	2081	// Enable Averaging of 8 samples (AVGON=1, NAVG[1:0]=1)
whismanoid	0:f7d706d2904d	2082	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	0:f7d706d2904d	2083	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	2084	ADC_CONFIGURATION \|= ((1 & NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	2085	} else if (average_0_4_8_16_32 == 16) {
whismanoid	0:f7d706d2904d	2086	// Enable Averaging of 16 samples (AVGON=1, NAVG[1:0]=2)
whismanoid	0:f7d706d2904d	2087	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	0:f7d706d2904d	2088	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	2089	ADC_CONFIGURATION \|= ((2 & NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	2090	} else if (average_0_4_8_16_32 == 32) {
whismanoid	0:f7d706d2904d	2091	// Enable Averaging of 32 samples (AVGON=1, NAVG[1:0]=3)
whismanoid	0:f7d706d2904d	2092	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	0:f7d706d2904d	2093	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	2094	ADC_CONFIGURATION \|= ((3 & NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	2095	} else {
whismanoid	0:f7d706d2904d	2096	// Disable Averaging (AVGON=0, NAVG[1:0]=0)
whismanoid	0:f7d706d2904d	2097	ADC_CONFIGURATION &= ~ (( AVGON_BITS) << AVGON_LSB);
whismanoid	0:f7d706d2904d	2098	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	2099	}
whismanoid	0:f7d706d2904d	2100
whismanoid	0:f7d706d2904d	2101	//----------------------------------------
whismanoid	0:f7d706d2904d	2102	// SPI write ADC CONFIGURATION register
whismanoid	0:f7d706d2904d	2103	// Send SPI configuration to device
whismanoid	0:f7d706d2904d	2104	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	2105	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	2106	SPIwrite16bits(ADC_CONFIGURATION);
whismanoid	0:f7d706d2904d	2107	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	2108
whismanoid	0:f7d706d2904d	2109	//----------------------------------------
whismanoid	0:f7d706d2904d	2110	// Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid	0:f7d706d2904d	2111	ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	2112	ADC_MODE_CONTROL \|= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	2113
whismanoid	0:f7d706d2904d	2114	//----------------------------------------
whismanoid	0:f7d706d2904d	2115	// ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0101_UpperInternalClock = 5
whismanoid	0:f7d706d2904d	2116	//~ const int SCAN_0101_UpperInternalClock = 5; // replaced local const with enum
whismanoid	0:f7d706d2904d	2117	ADC_MODE_CONTROL \|= ((SCAN_0101_UpperInternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid	0:f7d706d2904d	2118
whismanoid	0:f7d706d2904d	2119	//----------------------------------------
whismanoid	0:f7d706d2904d	2120	// ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid	0:f7d706d2904d	2121	ADC_MODE_CONTROL \|= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid	0:f7d706d2904d	2122
whismanoid	0:f7d706d2904d	2123	//----------------------------------------
whismanoid	0:f7d706d2904d	2124	// ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid	0:f7d706d2904d	2125	ADC_MODE_CONTROL \|= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid	0:f7d706d2904d	2126
whismanoid	0:f7d706d2904d	2127	//----------------------------------------
whismanoid	0:f7d706d2904d	2128	// ADC MODE CONTROL register set SWCNV if CNVST pin is not used
whismanoid	0:f7d706d2904d	2129	// ADC MODE CONTROL REGISTER SELECT THE RIGHT SWCNV BIT
whismanoid	0:f7d706d2904d	2130	// (applicable to internal clock mode only)
whismanoid	0:f7d706d2904d	2131	// SWCNV=1: trigger measurement on SPI CS rising edge; CNVST pin is not used. (AIN14 is available)
whismanoid	0:f7d706d2904d	2132	// SWCNV=0: trigger measurement by driving CNVST pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	0:f7d706d2904d	2133	if (swcnv_0_1) {
whismanoid	0:f7d706d2904d	2134	ADC_MODE_CONTROL \|= ((swcnv_0_1 & SWCNV_BITS) << SWCNV_LSB);
whismanoid	0:f7d706d2904d	2135	} else {
whismanoid	0:f7d706d2904d	2136	ADC_MODE_CONTROL &= ~ (( SWCNV_BITS) << SWCNV_LSB);
whismanoid	0:f7d706d2904d	2137	}
whismanoid	0:f7d706d2904d	2138
whismanoid	0:f7d706d2904d	2139	//----------------------------------------
whismanoid	0:f7d706d2904d	2140	// SPI write ADC MODE CONTROL register
whismanoid	0:f7d706d2904d	2141	// If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid	0:f7d706d2904d	2142	// Send SPI configuration to device
whismanoid	0:f7d706d2904d	2143	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	2144	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	2145	if (swcnv_0_1) {
whismanoid	0:f7d706d2904d	2146	// If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid	0:f7d706d2904d	2147	// NOTE: Figure 7 Internal Conversions with SWCNV=1 has an error, the 17th SCLK is mislabeled as "16" should be "17".
whismanoid	0:f7d706d2904d	2148	SPIwrite24bits(ADC_MODE_CONTROL, 0);
whismanoid	0:f7d706d2904d	2149	} else {
whismanoid	0:f7d706d2904d	2150	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	0:f7d706d2904d	2151	}
whismanoid	0:f7d706d2904d	2152	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	2153
whismanoid	0:f7d706d2904d	2154	//----------------------------------------
whismanoid	0:f7d706d2904d	2155	// return number of words to read
whismanoid	0:f7d706d2904d	2156	return NumWords;
whismanoid	0:f7d706d2904d	2157	}
whismanoid	0:f7d706d2904d	2158
whismanoid	0:f7d706d2904d	2159	//----------------------------------------
whismanoid	0:f7d706d2904d	2160	// SCAN_0110_UpperExternalClock
whismanoid	0:f7d706d2904d	2161	//
whismanoid	0:f7d706d2904d	2162	// Measure ADC channels in sequence from channelNumber_0_15 to AIN15.
whismanoid	0:f7d706d2904d	2163	// External clock mode.
whismanoid	0:f7d706d2904d	2164	// @param[in] channelNumber_0_15: AIN Channel Number
whismanoid	0:f7d706d2904d	2165	// @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	0:f7d706d2904d	2166	// @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid	0:f7d706d2904d	2167	// @return number of ScanRead() words needed to retrieve the data.
whismanoid	0:f7d706d2904d	2168	// For external clock modes, the data format depends on CHAN_ID.
whismanoid	0:f7d706d2904d	2169	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	0:f7d706d2904d	2170	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	2171	//
whismanoid	0:f7d706d2904d	2172	int MAX11131::ScanUpperExternalClock(void)
whismanoid	0:f7d706d2904d	2173	{
whismanoid	0:f7d706d2904d	2174
whismanoid	0:f7d706d2904d	2175	//----------------------------------------
whismanoid	0:f7d706d2904d	2176	// number of words to read
whismanoid	0:f7d706d2904d	2177	NumWords = (16 - channelNumber_0_15);
whismanoid	0:f7d706d2904d	2178
whismanoid	0:f7d706d2904d	2179	//----------------------------------------
whismanoid	0:f7d706d2904d	2180	// External Clock Mode
whismanoid	0:f7d706d2904d	2181	isExternalClock = 1;
whismanoid	0:f7d706d2904d	2182
whismanoid	0:f7d706d2904d	2183	//----------------------------------------
whismanoid	0:f7d706d2904d	2184	// update device driver global variable
whismanoid	0:f7d706d2904d	2185	ScanMode = SCAN_0110_UpperExternalClock;
whismanoid	0:f7d706d2904d	2186
whismanoid	0:f7d706d2904d	2187	//----------------------------------------
whismanoid	0:f7d706d2904d	2188	// define write-only register ADC_MODE_CONTROL
whismanoid	0:f7d706d2904d	2189	ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid	0:f7d706d2904d	2190	const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid	0:f7d706d2904d	2191	const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid	0:f7d706d2904d	2192	const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	2193	const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid	0:f7d706d2904d	2194	const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid	0:f7d706d2904d	2195	const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid	0:f7d706d2904d	2196
whismanoid	0:f7d706d2904d	2197	//----------------------------------------
whismanoid	0:f7d706d2904d	2198	// Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid	0:f7d706d2904d	2199	ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	2200	ADC_MODE_CONTROL \|= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	2201
whismanoid	0:f7d706d2904d	2202	//----------------------------------------
whismanoid	0:f7d706d2904d	2203	// ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0110_UpperExternalClock = 6
whismanoid	0:f7d706d2904d	2204	//~ const int SCAN_0110_UpperExternalClock = 6; // replaced local const with enum
whismanoid	0:f7d706d2904d	2205	ADC_MODE_CONTROL \|= ((SCAN_0110_UpperExternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid	0:f7d706d2904d	2206
whismanoid	0:f7d706d2904d	2207	//----------------------------------------
whismanoid	0:f7d706d2904d	2208	// ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid	0:f7d706d2904d	2209	ADC_MODE_CONTROL \|= ((channelNumber_0_15 & CHSEL_BITS) << CHSEL_LSB);
whismanoid	0:f7d706d2904d	2210
whismanoid	0:f7d706d2904d	2211	//----------------------------------------
whismanoid	0:f7d706d2904d	2212	// ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid	0:f7d706d2904d	2213	ADC_MODE_CONTROL \|= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid	0:f7d706d2904d	2214
whismanoid	0:f7d706d2904d	2215	//----------------------------------------
whismanoid	0:f7d706d2904d	2216	// ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid	0:f7d706d2904d	2217	// (applicable to external clock mode only)
whismanoid	0:f7d706d2904d	2218	// For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid	0:f7d706d2904d	2219	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	0:f7d706d2904d	2220	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	2221	// For internal clock modes, the data format always includes the channel address.
whismanoid	0:f7d706d2904d	2222	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	2223	ADC_MODE_CONTROL \|= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid	0:f7d706d2904d	2224
whismanoid	0:f7d706d2904d	2225	//----------------------------------------
whismanoid	0:f7d706d2904d	2226	// SPI write ADC MODE CONTROL register
whismanoid	0:f7d706d2904d	2227	// Send SPI configuration to device
whismanoid	0:f7d706d2904d	2228	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	2229	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	2230	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	0:f7d706d2904d	2231	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	2232
whismanoid	0:f7d706d2904d	2233	//----------------------------------------
whismanoid	0:f7d706d2904d	2234	// return number of words to read
whismanoid	0:f7d706d2904d	2235	return NumWords;
whismanoid	0:f7d706d2904d	2236	}
whismanoid	0:f7d706d2904d	2237
whismanoid	0:f7d706d2904d	2238	//----------------------------------------
whismanoid	0:f7d706d2904d	2239	// SCAN_0111_CustomInternalClock
whismanoid	0:f7d706d2904d	2240	//
whismanoid	0:f7d706d2904d	2241	// Measure selected ADC channels in sequence from AIN0 to AIN15,
whismanoid	0:f7d706d2904d	2242	// using only the channels enabled by enabledChannelsMask.
whismanoid	0:f7d706d2904d	2243	// Bit 0x0001 enables AIN0.
whismanoid	0:f7d706d2904d	2244	// Bit 0x0002 enables AIN1.
whismanoid	0:f7d706d2904d	2245	// Bit 0x0004 enables AIN2.
whismanoid	0:f7d706d2904d	2246	// Bit 0x0008 enables AIN3.
whismanoid	0:f7d706d2904d	2247	// Bit 0x0010 enables AIN4.
whismanoid	0:f7d706d2904d	2248	// Bit 0x0020 enables AIN5.
whismanoid	0:f7d706d2904d	2249	// Bit 0x0040 enables AIN6.
whismanoid	0:f7d706d2904d	2250	// Bit 0x0080 enables AIN7.
whismanoid	0:f7d706d2904d	2251	// Bit 0x0100 enables AIN8.
whismanoid	0:f7d706d2904d	2252	// Bit 0x0200 enables AIN9.
whismanoid	0:f7d706d2904d	2253	// Bit 0x0400 enables AIN10.
whismanoid	0:f7d706d2904d	2254	// Bit 0x0800 enables AIN11.
whismanoid	0:f7d706d2904d	2255	// Bit 0x1000 enables AIN12.
whismanoid	0:f7d706d2904d	2256	// Bit 0x2000 enables AIN13.
whismanoid	0:f7d706d2904d	2257	// Bit 0x4000 enables AIN14.
whismanoid	0:f7d706d2904d	2258	// Bit 0x8000 enables AIN15.
whismanoid	0:f7d706d2904d	2259	// Internal clock mode.
whismanoid	0:f7d706d2904d	2260	// @param[in] enabledChannelsMask: Bitmap of AIN Channels to scan.
whismanoid	0:f7d706d2904d	2261	// @param[in] average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid	0:f7d706d2904d	2262	// average_0_4_8_16_32=0 to disable averaging.
whismanoid	0:f7d706d2904d	2263	// @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	0:f7d706d2904d	2264	// @param[in] swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid	0:f7d706d2904d	2265	// SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid	0:f7d706d2904d	2266	// Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	0:f7d706d2904d	2267	// SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid	0:f7d706d2904d	2268	// CS must be held low for minimum of 17 SCLK cycles.
whismanoid	0:f7d706d2904d	2269	// CNVST pin is not used. (AIN14 is available)
whismanoid	0:f7d706d2904d	2270	// @return number of ScanRead() words needed to retrieve the data.
whismanoid	0:f7d706d2904d	2271	// For internal clock modes, the data format always includes the channel address.
whismanoid	0:f7d706d2904d	2272	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	2273	//
whismanoid	0:f7d706d2904d	2274	int MAX11131::ScanCustomInternalClock(void)
whismanoid	0:f7d706d2904d	2275	{
whismanoid	0:f7d706d2904d	2276
whismanoid	0:f7d706d2904d	2277	//----------------------------------------
whismanoid	0:f7d706d2904d	2278	// count nWords = number of set bits in enabledChannelsMask
whismanoid	0:f7d706d2904d	2279	uint16_t bitMask;
whismanoid	0:f7d706d2904d	2280	int nWords = 0;
whismanoid	0:f7d706d2904d	2281	for (bitMask = 0x8000; bitMask != 0; bitMask = bitMask / 2)
whismanoid	0:f7d706d2904d	2282	{
whismanoid	0:f7d706d2904d	2283	if (enabledChannelsMask & bitMask)
whismanoid	0:f7d706d2904d	2284	{
whismanoid	0:f7d706d2904d	2285	nWords++;
whismanoid	0:f7d706d2904d	2286	}
whismanoid	0:f7d706d2904d	2287	}
whismanoid	0:f7d706d2904d	2288
whismanoid	0:f7d706d2904d	2289	//----------------------------------------
whismanoid	0:f7d706d2904d	2290	// number of words to read
whismanoid	0:f7d706d2904d	2291	NumWords = nWords;
whismanoid	0:f7d706d2904d	2292
whismanoid	0:f7d706d2904d	2293	//----------------------------------------
whismanoid	0:f7d706d2904d	2294	// Internal Clock Mode
whismanoid	0:f7d706d2904d	2295	isExternalClock = 0;
whismanoid	0:f7d706d2904d	2296
whismanoid	0:f7d706d2904d	2297	//----------------------------------------
whismanoid	0:f7d706d2904d	2298	// update device driver global variable
whismanoid	0:f7d706d2904d	2299	ScanMode = SCAN_0111_CustomInternalClock;
whismanoid	0:f7d706d2904d	2300
whismanoid	0:f7d706d2904d	2301	//----------------------------------------
whismanoid	0:f7d706d2904d	2302	// define write-only register ADC_MODE_CONTROL
whismanoid	0:f7d706d2904d	2303	ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid	0:f7d706d2904d	2304	const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid	0:f7d706d2904d	2305	const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid	0:f7d706d2904d	2306	const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	2307	const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid	0:f7d706d2904d	2308	const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid	0:f7d706d2904d	2309	const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid	0:f7d706d2904d	2310
whismanoid	0:f7d706d2904d	2311	//----------------------------------------
whismanoid	0:f7d706d2904d	2312	// define write-only register ADC_CONFIGURATION
whismanoid	0:f7d706d2904d	2313	ADC_CONFIGURATION = 0x8000; //!< mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid	0:f7d706d2904d	2314	const int REFSEL_LSB = 10; const int REFSEL_BITS = 0x01; // ADC_CONFIGURATION.REFSEL
whismanoid	0:f7d706d2904d	2315	const int AVGON_LSB = 9; const int AVGON_BITS = 0x01; // ADC_CONFIGURATION.AVGON
whismanoid	0:f7d706d2904d	2316	const int NAVG_LSB = 7; const int NAVG_BITS = 0x03; // ADC_CONFIGURATION.NAVG[1:0]
whismanoid	0:f7d706d2904d	2317	const int NSCAN_LSB = 5; const int NSCAN_BITS = 0x03; // ADC_CONFIGURATION.NSCAN[1:0]
whismanoid	0:f7d706d2904d	2318	const int SPM_LSB = 3; const int SPM_BITS = 0x03; // ADC_CONFIGURATION.SPM[1:0]
whismanoid	0:f7d706d2904d	2319	const int ECHO_LSB = 2; const int ECHO_BITS = 0x01; // ADC_CONFIGURATION.ECHO
whismanoid	0:f7d706d2904d	2320
whismanoid	0:f7d706d2904d	2321	//----------------------------------------
whismanoid	0:f7d706d2904d	2322	// define write-only registers CSCAN0,CSCAN1
whismanoid	0:f7d706d2904d	2323	CSCAN0 = 0xA000; //!< mosiData16 0xA000..0xA7FF format: 1 0 1 0 0 CHSCAN15 CHSCAN14 CHSCAN13 CHSCAN12 CHSCAN11 CHSCAN10 CHSCAN9 CHSCAN8 x x x
whismanoid	0:f7d706d2904d	2324	const int CHSCAN15_LSB = 10; // CSCAN0.CHSCAN15
whismanoid	0:f7d706d2904d	2325	const int CHSCAN14_LSB = 9; // CSCAN0.CHSCAN14
whismanoid	0:f7d706d2904d	2326	const int CHSCAN13_LSB = 8; // CSCAN0.CHSCAN13
whismanoid	0:f7d706d2904d	2327	const int CHSCAN12_LSB = 7; // CSCAN0.CHSCAN12
whismanoid	0:f7d706d2904d	2328	const int CHSCAN11_LSB = 6; // CSCAN0.CHSCAN11
whismanoid	0:f7d706d2904d	2329	const int CHSCAN10_LSB = 5; // CSCAN0.CHSCAN10
whismanoid	0:f7d706d2904d	2330	const int CHSCAN9_LSB = 4; // CSCAN0.CHSCAN9
whismanoid	0:f7d706d2904d	2331	const int CHSCAN8_LSB = 3; // CSCAN0.CHSCAN8
whismanoid	0:f7d706d2904d	2332	CSCAN1 = 0xA800; //!< mosiData16 0xA800..0xAFFF format: 1 0 1 0 1 CHSCAN7 CHSCAN6 CHSCAN5 CHSCAN4 CHSCAN3 CHSCAN2 CHSCAN1 CHSCAN0 x x x
whismanoid	0:f7d706d2904d	2333	const int CHSCAN7_LSB = 10; // CSCAN1.CHSCAN7
whismanoid	0:f7d706d2904d	2334	const int CHSCAN6_LSB = 9; // CSCAN1.CHSCAN6
whismanoid	0:f7d706d2904d	2335	const int CHSCAN5_LSB = 8; // CSCAN1.CHSCAN5
whismanoid	0:f7d706d2904d	2336	const int CHSCAN4_LSB = 7; // CSCAN1.CHSCAN4
whismanoid	0:f7d706d2904d	2337	const int CHSCAN3_LSB = 6; // CSCAN1.CHSCAN3
whismanoid	0:f7d706d2904d	2338	const int CHSCAN2_LSB = 5; // CSCAN1.CHSCAN2
whismanoid	0:f7d706d2904d	2339	const int CHSCAN1_LSB = 4; // CSCAN1.CHSCAN1
whismanoid	0:f7d706d2904d	2340	const int CHSCAN0_LSB = 3; // CSCAN1.CHSCAN0
whismanoid	0:f7d706d2904d	2341
whismanoid	0:f7d706d2904d	2342	//----------------------------------------
whismanoid	0:f7d706d2904d	2343	// if average, ADC CONFIGURATION register set AVG and NAVG[1:0]
whismanoid	0:f7d706d2904d	2344	// (applicable to internal clock mode only)
whismanoid	0:f7d706d2904d	2345	// if average, ADC CONFIGURATION register set AVG ON BIT TO 1
whismanoid	0:f7d706d2904d	2346	// if average, ADC CONFIGURATION register set NAVG[1:0] TO N
whismanoid	0:f7d706d2904d	2347	if (average_0_4_8_16_32 == 4) {
whismanoid	0:f7d706d2904d	2348	// Enable Averaging of 4 samples (AVGON=1, NAVG[1:0]=0)
whismanoid	0:f7d706d2904d	2349	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	0:f7d706d2904d	2350	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	2351	ADC_CONFIGURATION \|= ((0 & NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	2352	} else if (average_0_4_8_16_32 == 8) {
whismanoid	0:f7d706d2904d	2353	// Enable Averaging of 8 samples (AVGON=1, NAVG[1:0]=1)
whismanoid	0:f7d706d2904d	2354	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	0:f7d706d2904d	2355	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	2356	ADC_CONFIGURATION \|= ((1 & NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	2357	} else if (average_0_4_8_16_32 == 16) {
whismanoid	0:f7d706d2904d	2358	// Enable Averaging of 16 samples (AVGON=1, NAVG[1:0]=2)
whismanoid	0:f7d706d2904d	2359	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	0:f7d706d2904d	2360	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	2361	ADC_CONFIGURATION \|= ((2 & NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	2362	} else if (average_0_4_8_16_32 == 32) {
whismanoid	0:f7d706d2904d	2363	// Enable Averaging of 32 samples (AVGON=1, NAVG[1:0]=3)
whismanoid	0:f7d706d2904d	2364	ADC_CONFIGURATION \|= ((1 & AVGON_BITS) << AVGON_LSB);
whismanoid	0:f7d706d2904d	2365	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	2366	ADC_CONFIGURATION \|= ((3 & NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	2367	} else {
whismanoid	0:f7d706d2904d	2368	// Disable Averaging (AVGON=0, NAVG[1:0]=0)
whismanoid	0:f7d706d2904d	2369	ADC_CONFIGURATION &= ~ (( AVGON_BITS) << AVGON_LSB);
whismanoid	0:f7d706d2904d	2370	ADC_CONFIGURATION &= ~ (( NAVG_BITS) << NAVG_LSB);
whismanoid	0:f7d706d2904d	2371	}
whismanoid	0:f7d706d2904d	2372
whismanoid	0:f7d706d2904d	2373	//----------------------------------------
whismanoid	0:f7d706d2904d	2374	// SPI write ADC CONFIGURATION register
whismanoid	0:f7d706d2904d	2375	// Send SPI configuration to device
whismanoid	0:f7d706d2904d	2376	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	2377	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	2378	SPIwrite16bits(ADC_CONFIGURATION);
whismanoid	0:f7d706d2904d	2379	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	2380
whismanoid	0:f7d706d2904d	2381	//----------------------------------------
whismanoid	0:f7d706d2904d	2382	// SET CSCAN0 CSCAN1 REGISTERS from enabledChannelsMask
whismanoid	0:f7d706d2904d	2383	CSCAN0 = 0xA000 \| (((enabledChannelsMask >> 8) & 0xFF) << 3); // CSCAN0.CHSCAN[15:8]
whismanoid	0:f7d706d2904d	2384	CSCAN1 = 0xA800 \| (((enabledChannelsMask) & 0xFF) << 3); // CSCAN1.CHSCAN[7:0]
whismanoid	0:f7d706d2904d	2385	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	2386	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	2387	SPIwrite16bits(CSCAN0);
whismanoid	0:f7d706d2904d	2388	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	2389	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	2390	SPIwrite16bits(CSCAN1);
whismanoid	0:f7d706d2904d	2391	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	2392
whismanoid	0:f7d706d2904d	2393	//----------------------------------------
whismanoid	0:f7d706d2904d	2394	// Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid	0:f7d706d2904d	2395	ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	2396	ADC_MODE_CONTROL \|= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	2397
whismanoid	0:f7d706d2904d	2398	//----------------------------------------
whismanoid	0:f7d706d2904d	2399	// ADC MODE CONTROL register set SCAN[3:0] TO SCAN_0111_CustomInternalClock = 7
whismanoid	0:f7d706d2904d	2400	//~ const int SCAN_0111_CustomInternalClock = 7; // replaced local const with enum
whismanoid	0:f7d706d2904d	2401	ADC_MODE_CONTROL \|= ((SCAN_0111_CustomInternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid	0:f7d706d2904d	2402
whismanoid	0:f7d706d2904d	2403	//----------------------------------------
whismanoid	0:f7d706d2904d	2404	// ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid	0:f7d706d2904d	2405	ADC_MODE_CONTROL \|= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid	0:f7d706d2904d	2406
whismanoid	0:f7d706d2904d	2407	//----------------------------------------
whismanoid	0:f7d706d2904d	2408	// ADC MODE CONTROL register set SWCNV if CNVST pin is not used
whismanoid	0:f7d706d2904d	2409	// ADC MODE CONTROL REGISTER SELECT THE RIGHT SWCNV BIT
whismanoid	0:f7d706d2904d	2410	// (applicable to internal clock mode only)
whismanoid	0:f7d706d2904d	2411	// SWCNV=1: trigger measurement on SPI CS rising edge; CNVST pin is not used. (AIN14 is available)
whismanoid	0:f7d706d2904d	2412	// SWCNV=0: trigger measurement by driving CNVST pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	0:f7d706d2904d	2413	if (swcnv_0_1) {
whismanoid	0:f7d706d2904d	2414	ADC_MODE_CONTROL \|= ((swcnv_0_1 & SWCNV_BITS) << SWCNV_LSB);
whismanoid	0:f7d706d2904d	2415	} else {
whismanoid	0:f7d706d2904d	2416	ADC_MODE_CONTROL &= ~ (( SWCNV_BITS) << SWCNV_LSB);
whismanoid	0:f7d706d2904d	2417	}
whismanoid	0:f7d706d2904d	2418
whismanoid	0:f7d706d2904d	2419	//----------------------------------------
whismanoid	0:f7d706d2904d	2420	// SPI write ADC MODE CONTROL register
whismanoid	0:f7d706d2904d	2421	// If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid	0:f7d706d2904d	2422	// Send SPI configuration to device
whismanoid	0:f7d706d2904d	2423	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	2424	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	2425	if (swcnv_0_1) {
whismanoid	0:f7d706d2904d	2426	// If SWCNV=1 then CS must be held low for at least 17 SCLK cycles.
whismanoid	0:f7d706d2904d	2427	// NOTE: Figure 7 Internal Conversions with SWCNV=1 has an error, the 17th SCLK is mislabeled as "16" should be "17".
whismanoid	0:f7d706d2904d	2428	SPIwrite24bits(ADC_MODE_CONTROL, 0);
whismanoid	0:f7d706d2904d	2429	} else {
whismanoid	0:f7d706d2904d	2430	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	0:f7d706d2904d	2431	}
whismanoid	0:f7d706d2904d	2432	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	2433
whismanoid	0:f7d706d2904d	2434	//----------------------------------------
whismanoid	0:f7d706d2904d	2435	// return number of words to read
whismanoid	0:f7d706d2904d	2436	return NumWords;
whismanoid	0:f7d706d2904d	2437	}
whismanoid	0:f7d706d2904d	2438
whismanoid	0:f7d706d2904d	2439	//----------------------------------------
whismanoid	0:f7d706d2904d	2440	// SCAN_1000_CustomExternalClock
whismanoid	0:f7d706d2904d	2441	//
whismanoid	0:f7d706d2904d	2442	// Measure selected ADC channels in sequence from AIN0 to AIN15,
whismanoid	0:f7d706d2904d	2443	// using only the channels enabled by enabledChannelsMask.
whismanoid	0:f7d706d2904d	2444	// Bit 0x0001 enables AIN0.
whismanoid	0:f7d706d2904d	2445	// Bit 0x0002 enables AIN1.
whismanoid	0:f7d706d2904d	2446	// Bit 0x0004 enables AIN2.
whismanoid	0:f7d706d2904d	2447	// Bit 0x0008 enables AIN3.
whismanoid	0:f7d706d2904d	2448	// Bit 0x0010 enables AIN4.
whismanoid	0:f7d706d2904d	2449	// Bit 0x0020 enables AIN5.
whismanoid	0:f7d706d2904d	2450	// Bit 0x0040 enables AIN6.
whismanoid	0:f7d706d2904d	2451	// Bit 0x0080 enables AIN7.
whismanoid	0:f7d706d2904d	2452	// Bit 0x0100 enables AIN8.
whismanoid	0:f7d706d2904d	2453	// Bit 0x0200 enables AIN9.
whismanoid	0:f7d706d2904d	2454	// Bit 0x0400 enables AIN10.
whismanoid	0:f7d706d2904d	2455	// Bit 0x0800 enables AIN11.
whismanoid	0:f7d706d2904d	2456	// Bit 0x1000 enables AIN12.
whismanoid	0:f7d706d2904d	2457	// Bit 0x2000 enables AIN13.
whismanoid	0:f7d706d2904d	2458	// Bit 0x4000 enables AIN14.
whismanoid	0:f7d706d2904d	2459	// Bit 0x8000 enables AIN15.
whismanoid	0:f7d706d2904d	2460	// External clock mode.
whismanoid	0:f7d706d2904d	2461	// @param[in] enabledChannelsMask: Bitmap of AIN Channels to scan.
whismanoid	0:f7d706d2904d	2462	// @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	0:f7d706d2904d	2463	// @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid	0:f7d706d2904d	2464	// @return number of ScanRead() words needed to retrieve the data.
whismanoid	0:f7d706d2904d	2465	// For external clock modes, the data format depends on CHAN_ID.
whismanoid	0:f7d706d2904d	2466	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	0:f7d706d2904d	2467	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	2468	//
whismanoid	0:f7d706d2904d	2469	int MAX11131::ScanCustomExternalClock(void)
whismanoid	0:f7d706d2904d	2470	{
whismanoid	0:f7d706d2904d	2471
whismanoid	0:f7d706d2904d	2472	//----------------------------------------
whismanoid	0:f7d706d2904d	2473	// count nWords = number of set bits in enabledChannelsMask
whismanoid	0:f7d706d2904d	2474	uint16_t bitMask;
whismanoid	0:f7d706d2904d	2475	int nWords = 0;
whismanoid	0:f7d706d2904d	2476	for (bitMask = 0x8000; bitMask != 0; bitMask = bitMask / 2)
whismanoid	0:f7d706d2904d	2477	{
whismanoid	0:f7d706d2904d	2478	if (enabledChannelsMask & bitMask)
whismanoid	0:f7d706d2904d	2479	{
whismanoid	0:f7d706d2904d	2480	nWords++;
whismanoid	0:f7d706d2904d	2481	}
whismanoid	0:f7d706d2904d	2482	}
whismanoid	0:f7d706d2904d	2483
whismanoid	0:f7d706d2904d	2484	//----------------------------------------
whismanoid	0:f7d706d2904d	2485	// number of words to read
whismanoid	0:f7d706d2904d	2486	NumWords = nWords;
whismanoid	0:f7d706d2904d	2487
whismanoid	0:f7d706d2904d	2488	//----------------------------------------
whismanoid	0:f7d706d2904d	2489	// External Clock Mode
whismanoid	0:f7d706d2904d	2490	isExternalClock = 1;
whismanoid	0:f7d706d2904d	2491
whismanoid	0:f7d706d2904d	2492	//----------------------------------------
whismanoid	0:f7d706d2904d	2493	// update device driver global variable
whismanoid	0:f7d706d2904d	2494	ScanMode = SCAN_1000_CustomExternalClock;
whismanoid	0:f7d706d2904d	2495
whismanoid	0:f7d706d2904d	2496	//----------------------------------------
whismanoid	0:f7d706d2904d	2497	// define write-only register ADC_MODE_CONTROL
whismanoid	0:f7d706d2904d	2498	ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid	0:f7d706d2904d	2499	const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid	0:f7d706d2904d	2500	const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid	0:f7d706d2904d	2501	const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	2502	const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid	0:f7d706d2904d	2503	const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid	0:f7d706d2904d	2504	const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid	0:f7d706d2904d	2505
whismanoid	0:f7d706d2904d	2506	//----------------------------------------
whismanoid	0:f7d706d2904d	2507	// define write-only registers CSCAN0,CSCAN1
whismanoid	0:f7d706d2904d	2508	CSCAN0 = 0xA000; //!< mosiData16 0xA000..0xA7FF format: 1 0 1 0 0 CHSCAN15 CHSCAN14 CHSCAN13 CHSCAN12 CHSCAN11 CHSCAN10 CHSCAN9 CHSCAN8 x x x
whismanoid	0:f7d706d2904d	2509	const int CHSCAN15_LSB = 10; // CSCAN0.CHSCAN15
whismanoid	0:f7d706d2904d	2510	const int CHSCAN14_LSB = 9; // CSCAN0.CHSCAN14
whismanoid	0:f7d706d2904d	2511	const int CHSCAN13_LSB = 8; // CSCAN0.CHSCAN13
whismanoid	0:f7d706d2904d	2512	const int CHSCAN12_LSB = 7; // CSCAN0.CHSCAN12
whismanoid	0:f7d706d2904d	2513	const int CHSCAN11_LSB = 6; // CSCAN0.CHSCAN11
whismanoid	0:f7d706d2904d	2514	const int CHSCAN10_LSB = 5; // CSCAN0.CHSCAN10
whismanoid	0:f7d706d2904d	2515	const int CHSCAN9_LSB = 4; // CSCAN0.CHSCAN9
whismanoid	0:f7d706d2904d	2516	const int CHSCAN8_LSB = 3; // CSCAN0.CHSCAN8
whismanoid	0:f7d706d2904d	2517	CSCAN1 = 0xA800; //!< mosiData16 0xA800..0xAFFF format: 1 0 1 0 1 CHSCAN7 CHSCAN6 CHSCAN5 CHSCAN4 CHSCAN3 CHSCAN2 CHSCAN1 CHSCAN0 x x x
whismanoid	0:f7d706d2904d	2518	const int CHSCAN7_LSB = 10; // CSCAN1.CHSCAN7
whismanoid	0:f7d706d2904d	2519	const int CHSCAN6_LSB = 9; // CSCAN1.CHSCAN6
whismanoid	0:f7d706d2904d	2520	const int CHSCAN5_LSB = 8; // CSCAN1.CHSCAN5
whismanoid	0:f7d706d2904d	2521	const int CHSCAN4_LSB = 7; // CSCAN1.CHSCAN4
whismanoid	0:f7d706d2904d	2522	const int CHSCAN3_LSB = 6; // CSCAN1.CHSCAN3
whismanoid	0:f7d706d2904d	2523	const int CHSCAN2_LSB = 5; // CSCAN1.CHSCAN2
whismanoid	0:f7d706d2904d	2524	const int CHSCAN1_LSB = 4; // CSCAN1.CHSCAN1
whismanoid	0:f7d706d2904d	2525	const int CHSCAN0_LSB = 3; // CSCAN1.CHSCAN0
whismanoid	0:f7d706d2904d	2526
whismanoid	0:f7d706d2904d	2527	//----------------------------------------
whismanoid	0:f7d706d2904d	2528	// SET CSCAN0 CSCAN1 REGISTERS from enabledChannelsMask
whismanoid	0:f7d706d2904d	2529	CSCAN0 = 0xA000 \| (((enabledChannelsMask >> 8) & 0xFF) << 3); // CSCAN0.CHSCAN[15:8]
whismanoid	0:f7d706d2904d	2530	CSCAN1 = 0xA800 \| (((enabledChannelsMask) & 0xFF) << 3); // CSCAN1.CHSCAN[7:0]
whismanoid	0:f7d706d2904d	2531	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	2532	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	2533	SPIwrite16bits(CSCAN0);
whismanoid	0:f7d706d2904d	2534	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	2535	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	2536	SPIwrite16bits(CSCAN1);
whismanoid	0:f7d706d2904d	2537	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	2538
whismanoid	0:f7d706d2904d	2539	//----------------------------------------
whismanoid	0:f7d706d2904d	2540	// Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid	0:f7d706d2904d	2541	ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	2542	ADC_MODE_CONTROL \|= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	2543
whismanoid	0:f7d706d2904d	2544	//----------------------------------------
whismanoid	0:f7d706d2904d	2545	// ADC MODE CONTROL register set SCAN[3:0] TO SCAN_1000_CustomExternalClock = 8
whismanoid	0:f7d706d2904d	2546	//~ const int SCAN_1000_CustomExternalClock = 8; // replaced local const with enum
whismanoid	0:f7d706d2904d	2547	ADC_MODE_CONTROL \|= ((SCAN_1000_CustomExternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid	0:f7d706d2904d	2548
whismanoid	0:f7d706d2904d	2549	//----------------------------------------
whismanoid	0:f7d706d2904d	2550	// ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid	0:f7d706d2904d	2551	ADC_MODE_CONTROL \|= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid	0:f7d706d2904d	2552
whismanoid	0:f7d706d2904d	2553	//----------------------------------------
whismanoid	0:f7d706d2904d	2554	// ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid	0:f7d706d2904d	2555	// (applicable to external clock mode only)
whismanoid	0:f7d706d2904d	2556	// For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid	0:f7d706d2904d	2557	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	0:f7d706d2904d	2558	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	2559	// For internal clock modes, the data format always includes the channel address.
whismanoid	0:f7d706d2904d	2560	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	2561	ADC_MODE_CONTROL \|= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid	0:f7d706d2904d	2562
whismanoid	0:f7d706d2904d	2563	//----------------------------------------
whismanoid	0:f7d706d2904d	2564	// SPI write ADC MODE CONTROL register
whismanoid	0:f7d706d2904d	2565	// Send SPI configuration to device
whismanoid	0:f7d706d2904d	2566	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	2567	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	2568	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	0:f7d706d2904d	2569	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	2570
whismanoid	0:f7d706d2904d	2571	//----------------------------------------
whismanoid	0:f7d706d2904d	2572	// return number of words to read
whismanoid	0:f7d706d2904d	2573	return NumWords;
whismanoid	0:f7d706d2904d	2574	}
whismanoid	0:f7d706d2904d	2575
whismanoid	0:f7d706d2904d	2576	//----------------------------------------
whismanoid	0:f7d706d2904d	2577	// SCAN_1001_SampleSetExternalClock
whismanoid	0:f7d706d2904d	2578	//
whismanoid	0:f7d706d2904d	2579	// Measure ADC channels in an arbitrary pattern.
whismanoid	0:f7d706d2904d	2580	// Channels can be visited in any order, with repetition allowed.
whismanoid	0:f7d706d2904d	2581	// External clock mode.
whismanoid	0:f7d706d2904d	2582	// @pre enabledChannelsPatternLength_1_256: number of channel selections
whismanoid	0:f7d706d2904d	2583	// @pre enabledChannelsPattern: array containing channel selection pattern
whismanoid	0:f7d706d2904d	2584	// In the array, one channel select per byte.
whismanoid	0:f7d706d2904d	2585	// In the SPI interface, immediately after SAMPLESET register is written,
whismanoid	0:f7d706d2904d	2586	// each byte encodes two channelNumber selections.
whismanoid	0:f7d706d2904d	2587	// The high 4 bits encode the first channelNumber.
whismanoid	0:f7d706d2904d	2588	// (((enabledChannelsPattern[0]) & 0x0F) << 4) \| ((enabledChannelsPattern[1]) & 0x0F)
whismanoid	0:f7d706d2904d	2589	// If it is an odd number of channels, additional nybbles will be ignored.
whismanoid	0:f7d706d2904d	2590	// CS will be asserted low during the entire SAMPLESET pattern selection.
whismanoid	0:f7d706d2904d	2591	// @param[in] PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	0:f7d706d2904d	2592	// @param[in] chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid	0:f7d706d2904d	2593	// @return number of ScanRead() words needed to retrieve the data.
whismanoid	0:f7d706d2904d	2594	// For external clock modes, the data format depends on CHAN_ID.
whismanoid	0:f7d706d2904d	2595	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	0:f7d706d2904d	2596	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	2597	//
whismanoid	0:f7d706d2904d	2598	int MAX11131::ScanSampleSetExternalClock(void)
whismanoid	0:f7d706d2904d	2599	{
whismanoid	0:f7d706d2904d	2600
whismanoid	0:f7d706d2904d	2601	//----------------------------------------
whismanoid	0:f7d706d2904d	2602	// number of words to read
whismanoid	0:f7d706d2904d	2603	NumWords = ((enabledChannelsPatternLength_1_256 != 0) ? enabledChannelsPatternLength_1_256 : 256 );
whismanoid	0:f7d706d2904d	2604
whismanoid	0:f7d706d2904d	2605	//----------------------------------------
whismanoid	0:f7d706d2904d	2606	// External Clock Mode
whismanoid	0:f7d706d2904d	2607	isExternalClock = 1;
whismanoid	0:f7d706d2904d	2608
whismanoid	0:f7d706d2904d	2609	//----------------------------------------
whismanoid	0:f7d706d2904d	2610	// update device driver global variable
whismanoid	0:f7d706d2904d	2611	ScanMode = SCAN_1001_SampleSetExternalClock;
whismanoid	0:f7d706d2904d	2612
whismanoid	0:f7d706d2904d	2613	//----------------------------------------
whismanoid	0:f7d706d2904d	2614	// define write-only register ADC_MODE_CONTROL
whismanoid	0:f7d706d2904d	2615	ADC_MODE_CONTROL = 0; //!< mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid	0:f7d706d2904d	2616	const int SCAN_LSB = 11; const int SCAN_BITS = 0x0F; //!< ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid	0:f7d706d2904d	2617	const int CHSEL_LSB = 7; const int CHSEL_BITS = 0x0F; //!< ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select AIN0..AIN15
whismanoid	0:f7d706d2904d	2618	const int RESET_LSB = 5; const int RESET_BITS = 0x03; //!< ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	2619	const int PM_LSB = 3; const int PM_BITS = 0x03; //!< ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid	0:f7d706d2904d	2620	const int CHAN_ID_LSB = 2; const int CHAN_ID_BITS = 0x01; //!< ADC_MODE_CONTROL.CHAN_ID
whismanoid	0:f7d706d2904d	2621	const int SWCNV_LSB = 1; const int SWCNV_BITS = 0x01; //!< ADC_MODE_CONTROL.SWCNV
whismanoid	0:f7d706d2904d	2622
whismanoid	0:f7d706d2904d	2623	//----------------------------------------
whismanoid	0:f7d706d2904d	2624	// Initialize shadow of write-only register SAMPLESET.
whismanoid	0:f7d706d2904d	2625	// Do not write to SAMPLESET at this time.
whismanoid	0:f7d706d2904d	2626	// A write to SAMPLESET must be followed by specified number of pattern entry words.
whismanoid	0:f7d706d2904d	2627	// See ScanSampleSetExternalClock function for details.
whismanoid	0:f7d706d2904d	2628	SAMPLESET = 0xB000; //!< mosiData16 0xB000..0xB7FF format: 1 0 1 1 0 SEQ_LENGTH[7:0] x x x
whismanoid	0:f7d706d2904d	2629	const int SAMPLESET_LSB = 3; const int SAMPLESET_BITS = 0xFF; // SAMPLESET.SEQ_LENGTH[7:0]
whismanoid	0:f7d706d2904d	2630
whismanoid	0:f7d706d2904d	2631	//----------------------------------------
whismanoid	0:f7d706d2904d	2632	// SampleSet register set SEQ_DEPTH[7:0] TO SET CHANNEL CAPTURE DEPTH; FOLLOW SampleSet REGISTER WITH CHANNEL PATTERN OF THE SAME SIZE AS SEQUENCE DEPTH
whismanoid	0:f7d706d2904d	2633	// NOTE: SAMPLESET.SEQ_LENGTH[7:0] is the number of channel entries in the pattern.
whismanoid	0:f7d706d2904d	2634	// NOTE: Each channel entry is 4 bits. The first 4 bits are the first channel in the sequence.
whismanoid	0:f7d706d2904d	2635	// NOTE: Channels can be repeated in any arbitrary order.
whismanoid	0:f7d706d2904d	2636	// NOTE: The channel entry pattern is sent immediately after writing SAMPLESET.
whismanoid	0:f7d706d2904d	2637	// NOTE: Keep CS low during the entire SAMPLESET pattern entry.
whismanoid	0:f7d706d2904d	2638	const int seq_length_minus_one_0_255 = enabledChannelsPatternLength_1_256 - 1;
whismanoid	0:f7d706d2904d	2639	SAMPLESET = 0xB000;
whismanoid	0:f7d706d2904d	2640	//SAMPLESET &= ~ (( SAMPLESET_BITS) << SAMPLESET_LSB);
whismanoid	0:f7d706d2904d	2641	SAMPLESET \|= ((seq_length_minus_one_0_255 & SAMPLESET_BITS) << SAMPLESET_LSB);
whismanoid	0:f7d706d2904d	2642	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	2643	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	2644	SPIwrite16bits(SAMPLESET); // SAMPLESET must be followed by several more bytes, length specified by SEQ_LENGTH[7:0]
whismanoid	0:f7d706d2904d	2645	// pack enabledChannelsPattern[index] into nybbles
whismanoid	0:f7d706d2904d	2646	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	2647	// NOTE: Send the sampleset pattern, with 4 entries packed into each 16-bit SPI word. Pad unused entries with 0.
whismanoid	0:f7d706d2904d	2648	SPI_MOSI_Semantic = 2; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	2649	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	2650	// NOTE: Keep CS low during the entire SAMPLESET pattern entry.
whismanoid	0:f7d706d2904d	2651	int entryIndex;
whismanoid	0:f7d706d2904d	2652	for (entryIndex = 0; entryIndex < enabledChannelsPatternLength_1_256; entryIndex += 4)
whismanoid	0:f7d706d2904d	2653	{
whismanoid	0:f7d706d2904d	2654	uint16_t pack4channels = 0;
whismanoid	0:f7d706d2904d	2655	pack4channels \|= (((enabledChannelsPattern[entryIndex + 0]) & 0x0F) << 12);
whismanoid	0:f7d706d2904d	2656	if ((entryIndex + 1) < enabledChannelsPatternLength_1_256) {
whismanoid	0:f7d706d2904d	2657	pack4channels \|= (((enabledChannelsPattern[entryIndex + 1]) & 0x0F) << 8);
whismanoid	0:f7d706d2904d	2658	}
whismanoid	0:f7d706d2904d	2659	if ((entryIndex + 2) < enabledChannelsPatternLength_1_256) {
whismanoid	0:f7d706d2904d	2660	pack4channels \|= (((enabledChannelsPattern[entryIndex + 2]) & 0x0F) << 4);
whismanoid	0:f7d706d2904d	2661	}
whismanoid	0:f7d706d2904d	2662	if ((entryIndex + 3) < enabledChannelsPatternLength_1_256) {
whismanoid	0:f7d706d2904d	2663	pack4channels \|= ((enabledChannelsPattern[entryIndex + 3]) & 0x0F);
whismanoid	0:f7d706d2904d	2664	}
whismanoid	0:f7d706d2904d	2665	SPIwrite16bits(pack4channels);
whismanoid	0:f7d706d2904d	2666	}
whismanoid	0:f7d706d2904d	2667	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	2668
whismanoid	0:f7d706d2904d	2669	//----------------------------------------
whismanoid	0:f7d706d2904d	2670	// Reset FIFO: ADC_MODE_CONTROL.RESET[1:0] = 1 Apply a soft reset when changing from internal to external clock mode.
whismanoid	0:f7d706d2904d	2671	ADC_MODE_CONTROL &= ~ (( RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	2672	ADC_MODE_CONTROL \|= ((1 & RESET_BITS) << RESET_LSB); // ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	2673
whismanoid	0:f7d706d2904d	2674	//----------------------------------------
whismanoid	0:f7d706d2904d	2675	// ADC MODE CONTROL register set SCAN[3:0] TO SCAN_1001_SampleSetExternalClock = 9
whismanoid	0:f7d706d2904d	2676	//~ const int SCAN_1001_SampleSetExternalClock = 9; // replaced local const with enum
whismanoid	0:f7d706d2904d	2677	ADC_MODE_CONTROL \|= ((SCAN_1001_SampleSetExternalClock & SCAN_BITS) << SCAN_LSB);
whismanoid	0:f7d706d2904d	2678
whismanoid	0:f7d706d2904d	2679	//----------------------------------------
whismanoid	0:f7d706d2904d	2680	// ADC MODE CONTROL register set CHSEL[3:0] TO channel number
whismanoid	0:f7d706d2904d	2681	ADC_MODE_CONTROL \|= ((0 & CHSEL_BITS) << CHSEL_LSB);
whismanoid	0:f7d706d2904d	2682
whismanoid	0:f7d706d2904d	2683	//----------------------------------------
whismanoid	0:f7d706d2904d	2684	// ADC MODE CONTROL REGISTER SELECT THE PM[1:0] BITS
whismanoid	0:f7d706d2904d	2685	ADC_MODE_CONTROL \|= ((PowerManagement_0_2 & PM_BITS) << PM_LSB);
whismanoid	0:f7d706d2904d	2686
whismanoid	0:f7d706d2904d	2687	//----------------------------------------
whismanoid	0:f7d706d2904d	2688	// ADC MODE CONTROL REGISTER SELECT THE CHAN_ID BIT
whismanoid	0:f7d706d2904d	2689	// (applicable to external clock mode only)
whismanoid	0:f7d706d2904d	2690	// For external clock modes, the data format returned depends on the CHAN_ID bit.
whismanoid	0:f7d706d2904d	2691	// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	0:f7d706d2904d	2692	// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	2693	// For internal clock modes, the data format always includes the channel address.
whismanoid	0:f7d706d2904d	2694	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	2695	ADC_MODE_CONTROL \|= ((chan_id_0_1 & CHAN_ID_BITS) << CHAN_ID_LSB);
whismanoid	0:f7d706d2904d	2696
whismanoid	0:f7d706d2904d	2697	//----------------------------------------
whismanoid	0:f7d706d2904d	2698	// SPI write ADC MODE CONTROL register
whismanoid	0:f7d706d2904d	2699	// Send SPI configuration to device
whismanoid	0:f7d706d2904d	2700	SPI_MOSI_Semantic = 1; // 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	2701	SPIoutputCS(0); // drive CS low
whismanoid	0:f7d706d2904d	2702	SPIwrite16bits(ADC_MODE_CONTROL);
whismanoid	0:f7d706d2904d	2703	SPIoutputCS(1); // drive CS high
whismanoid	0:f7d706d2904d	2704
whismanoid	0:f7d706d2904d	2705	//----------------------------------------
whismanoid	0:f7d706d2904d	2706	// return number of words to read
whismanoid	0:f7d706d2904d	2707	return NumWords;
whismanoid	0:f7d706d2904d	2708	}
whismanoid	0:f7d706d2904d	2709
whismanoid	0:f7d706d2904d	2710	//----------------------------------------
whismanoid	0:f7d706d2904d	2711	// Example configure and perform some measurements in ScanManual mode.
whismanoid	0:f7d706d2904d	2712	// @param[out] pd_mean = address for double mean (avearge)
whismanoid	0:f7d706d2904d	2713	// @param[out] pd_variance = address for double variance (variance)
whismanoid	0:f7d706d2904d	2714	// @param[out] pd_stddev = address for double stddev (standard deviation)
whismanoid	0:f7d706d2904d	2715	// @param[out] pd_Sx = address for double Sx (sum of all X)
whismanoid	0:f7d706d2904d	2716	// @param[out] pd_Sxx = address for double Sxx (sum of squares of each X)
whismanoid	0:f7d706d2904d	2717	void MAX11131::Example_ScanManual(int channelNumber_0_15, int nWords,
whismanoid	0:f7d706d2904d	2718	double* pd_mean, double* pd_variance, double* pd_stddev,
whismanoid	0:f7d706d2904d	2719	double* pd_Sx, double* pd_Sxx)
whismanoid	0:f7d706d2904d	2720	{
whismanoid	0:f7d706d2904d	2721
whismanoid	0:f7d706d2904d	2722	//----------------------------------------
whismanoid	0:f7d706d2904d	2723	// configure and perform some measurements in ScanManual mode
whismanoid	0:f7d706d2904d	2724	Init();
whismanoid	0:f7d706d2904d	2725	channelNumber_0_15 = channelNumber_0_15; // Analog Input Channel Select AIN0..
whismanoid	0:f7d706d2904d	2726	PowerManagement_0_2 = 0; // Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid	0:f7d706d2904d	2727	chan_id_0_1 = 1; // when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	0:f7d706d2904d	2728	// const int nWords = 100;
whismanoid	0:f7d706d2904d	2729	double Sx = 0;
whismanoid	0:f7d706d2904d	2730	double Sxx = 0;
whismanoid	0:f7d706d2904d	2731	int index;
whismanoid	0:f7d706d2904d	2732	ScanManual();
whismanoid	0:f7d706d2904d	2733	for (index = 0; index < nWords; index++)
whismanoid	0:f7d706d2904d	2734	{
whismanoid	0:f7d706d2904d	2735	int16_t misoData16 = ScanRead();
whismanoid	0:f7d706d2904d	2736	// For internal clock modes, the data format always includes the channel address.
whismanoid	0:f7d706d2904d	2737	// misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	2738	int16_t value_u12 = (misoData16 & 0x0FFF);
whismanoid	0:f7d706d2904d	2739	int channelId = ((misoData16 >> 12) & 0x000F);
whismanoid	0:f7d706d2904d	2740	Sx = Sx + value_u12;
whismanoid	0:f7d706d2904d	2741	Sxx = Sxx + ((double)value_u12 * value_u12);
whismanoid	0:f7d706d2904d	2742	}
whismanoid	0:f7d706d2904d	2743	if (pd_Sx != 0) {
whismanoid	0:f7d706d2904d	2744	*(pd_Sx) = Sx;
whismanoid	0:f7d706d2904d	2745	}
whismanoid	0:f7d706d2904d	2746	if (pd_Sxx != 0) {
whismanoid	0:f7d706d2904d	2747	*(pd_Sxx) = Sxx;
whismanoid	0:f7d706d2904d	2748	}
whismanoid	0:f7d706d2904d	2749	if (pd_mean != 0) {
whismanoid	0:f7d706d2904d	2750	*(pd_mean) = Sx / nWords;
whismanoid	0:f7d706d2904d	2751	}
whismanoid	0:f7d706d2904d	2752	if (nWords >= 2)
whismanoid	0:f7d706d2904d	2753	{
whismanoid	0:f7d706d2904d	2754	if (pd_variance != 0) {
whismanoid	0:f7d706d2904d	2755	// TODO1: is this variance calculation too naive to work reliably?
whismanoid	0:f7d706d2904d	2756	// see https://en.wikipedia.org/wiki/Algorithms_for_calculating_variance
whismanoid	0:f7d706d2904d	2757	(pd_variance) = (Sxx - ( Sx Sx / nWords) ) / (nWords - 1);
whismanoid	0:f7d706d2904d	2758	}
whismanoid	0:f7d706d2904d	2759	if (pd_stddev != 0) {
whismanoid	0:f7d706d2904d	2760	(pd_stddev) = sqrt( (pd_variance) );
whismanoid	0:f7d706d2904d	2761	}
whismanoid	0:f7d706d2904d	2762	}
whismanoid	0:f7d706d2904d	2763	}
whismanoid	0:f7d706d2904d	2764
whismanoid	0:f7d706d2904d	2765
whismanoid	0:f7d706d2904d	2766	// End of file
whismanoid	0:f7d706d2904d	2767

Repository toolbox

Export to desktop IDE

Repository details

Type:	Library
Created:	05 Jun 2019
Imports:	7
Forks:	0
Commits:	12
Dependents:	3
Dependencies:	0
Followers:	111

The code in this repository is Apache licensed.

Components

MAX11131BOB

MAX11131.cpp@0:f7d706d2904d, 2019-06-05 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Components

Important Information for this Arm website

Access Warning