MH / Mbed OS MAX30003WING_Demo_QRS_RK_MUX_05292021

3 channel_MUX

Dependencies:   BufferedSerial MAX30003 max32630fthr1 DS1307

main.cpp@13:3a49fb19b94b, 2021-05-26 (annotated)

Committer:
parthsagar2010
Date:
Wed May 26 00:06:00 2021 +0000
Revision:
13:3a49fb19b94b
Parent:
12:2f1730e0e638
Child:
14:2b140cea57b2
good_to_go_Ahmed

Who changed what in which revision?

UserRevisionLine numberNew contents of line
coreyharris 0:38c49bc37c7c 1 #include "mbed.h"
coreyharris 0:38c49bc37c7c 2 #include "max32630fthr.h"
parthsagar2010 10:3709e8f3d089 3 #include "MAX30003.h"
parthsagar2010 10:3709e8f3d089 4
coreyharris 0:38c49bc37c7c 5 MAX32630FTHR pegasus(MAX32630FTHR::VIO_3V3);
parthsagar2010 10:3709e8f3d089 6
coreyharris 0:38c49bc37c7c 7 void ecg_config(MAX30003 &ecgAFE);
parthsagar2010 12:2f1730e0e638 8 DigitalOut led1(P2_0,LED_ON);
parthsagar2010 12:2f1730e0e638 9
parthsagar2010 12:2f1730e0e638 10
parthsagar2010 12:2f1730e0e638 11
parthsagar2010 10:3709e8f3d089 12 /* ECG FIFO nearly full callback */
coreyharris 0:38c49bc37c7c 13 volatile bool ecgFIFOIntFlag = 0;
parthsagar2010 10:3709e8f3d089 14 void ecgFIFO_callback() {
coreyharris 0:38c49bc37c7c 15
coreyharris 0:38c49bc37c7c 16 ecgFIFOIntFlag = 1;
parthsagar2010 10:3709e8f3d089 17
coreyharris 0:38c49bc37c7c 18 }
parthsagar2010 12:2f1730e0e638 19 Timer timer1;
parthsagar2010 12:2f1730e0e638 20 //void MUX()
parthsagar2010 12:2f1730e0e638 21 //{
parthsagar2010 12:2f1730e0e638 22 DigitalOut EN(P1_7);
parthsagar2010 12:2f1730e0e638 23 DigitalOut A0(P1_4);
parthsagar2010 12:2f1730e0e638 24 DigitalOut A1(P7_2);
parthsagar2010 12:2f1730e0e638 25 //}
parthsagar2010 12:2f1730e0e638 26 bool mux1= false ;
parthsagar2010 12:2f1730e0e638 27 bool mux2= false ;
parthsagar2010 12:2f1730e0e638 28 bool mux3= false ;
parthsagar2010 12:2f1730e0e638 29
parthsagar2010 10:3709e8f3d089 30
coreyharris 0:38c49bc37c7c 31 int main()
coreyharris 3:420d5efbd967 32 {
parthsagar2010 12:2f1730e0e638 33
coreyharris 6:86ac850c718d 34 // Constants
coreyharris 4:06e258ff0b97 35 const int EINT_STATUS_MASK = 1 << 23;
coreyharris 6:86ac850c718d 36 const int FIFO_OVF_MASK = 0x7;
coreyharris 6:86ac850c718d 37 const int FIFO_VALID_SAMPLE_MASK = 0x0;
coreyharris 6:86ac850c718d 38 const int FIFO_FAST_SAMPLE_MASK = 0x1;
coreyharris 6:86ac850c718d 39 const int ETAG_BITS_MASK = 0x7;
coreyharris 3:420d5efbd967 40
parthsagar2010 13:3a49fb19b94b 41 int t=0;
parthsagar2010 12:2f1730e0e638 42
parthsagar2010 13:3a49fb19b94b 43 EN=0;
parthsagar2010 13:3a49fb19b94b 44 EN=1;
parthsagar2010 13:3a49fb19b94b 45 A0=0;
parthsagar2010 13:3a49fb19b94b 46 A1=1;
parthsagar2010 12:2f1730e0e638 47
parthsagar2010 10:3709e8f3d089 48 // Ports and serial connections
parthsagar2010 13:3a49fb19b94b 49 Serial pc(P0_1,P0_0); // Use USB debug probe for serial link
parthsagar2010 10:3709e8f3d089 50 pc.baud(230400); // Baud rate = 115200
parthsagar2010 12:2f1730e0e638 51 DigitalOut bLed(LED3, LED_ON);
parthsagar2010 13:3a49fb19b94b 52 // DigitalOut gLed(LED2, LED_ON);
parthsagar2010 13:3a49fb19b94b 53 // DigitalOut rLed(LED1, LED_ON);
parthsagar2010 12:2f1730e0e638 54 // Debug LEDs
coreyharris 1:86843c27cc81 55
coreyharris 1:86843c27cc81 56 InterruptIn ecgFIFO_int(P5_4); // Config P5_4 as int. in for the
parthsagar2010 10:3709e8f3d089 57 ecgFIFO_int.fall(&ecgFIFO_callback); // ecg FIFO almost full interrupt
coreyharris 0:38c49bc37c7c 58
parthsagar2010 11:1d4ecbca034e 59 //SPI spiBus(SPI2_MOSI, SPI2_MISO, SPI2_SCK); // SPI bus, P5_1 = MOSI,
coreyharris 1:86843c27cc81 60 // P5_2 = MISO, P5_0 = SCK
coreyharris 0:38c49bc37c7c 61
parthsagar2010 11:1d4ecbca034e 62
parthsagar2010 11:1d4ecbca034e 63 SPI spiBus(P5_1, P5_2, P5_0);
parthsagar2010 11:1d4ecbca034e 64
coreyharris 4:06e258ff0b97 65 MAX30003 ecgAFE(spiBus, P5_3); // New MAX30003 on spiBus, CS = P5_3
coreyharris 4:06e258ff0b97 66 ecg_config(ecgAFE); // Config ECG
coreyharris 1:86843c27cc81 67
coreyharris 0:38c49bc37c7c 68
coreyharris 4:06e258ff0b97 69 ecgAFE.writeRegister( MAX30003::SYNCH , 0);
coreyharris 0:38c49bc37c7c 70
coreyharris 4:06e258ff0b97 71 uint32_t ecgFIFO, readECGSamples, idx, ETAG[32], status;
coreyharris 1:86843c27cc81 72 int16_t ecgSample[32];
parthsagar2010 12:2f1730e0e638 73 int x=0;
parthsagar2010 10:3709e8f3d089 74 while(1) {
parthsagar2010 13:3a49fb19b94b 75 /*
parthsagar2010 12:2f1730e0e638 76 while (x<100 && mux1==false)
parthsagar2010 12:2f1730e0e638 77 {
parthsagar2010 12:2f1730e0e638 78 // if (0<x<=1000 && mux1==false)
parthsagar2010 12:2f1730e0e638 79 // {
parthsagar2010 12:2f1730e0e638 80
parthsagar2010 12:2f1730e0e638 81 EN = 0;
parthsagar2010 12:2f1730e0e638 82 EN = 1;
parthsagar2010 12:2f1730e0e638 83 A0 = 0;
parthsagar2010 12:2f1730e0e638 84 A1 = 0;
parthsagar2010 12:2f1730e0e638 85 mux1= true ;
parthsagar2010 12:2f1730e0e638 86 }
parthsagar2010 12:2f1730e0e638 87 while (101<x<=200 && mux2==false)
parthsagar2010 12:2f1730e0e638 88 {
parthsagar2010 12:2f1730e0e638 89 gLed = 1 ;
parthsagar2010 12:2f1730e0e638 90 EN = 0;
parthsagar2010 12:2f1730e0e638 91 EN = 1;
parthsagar2010 12:2f1730e0e638 92 A0 = 1;
parthsagar2010 12:2f1730e0e638 93 A1 = 0;
parthsagar2010 12:2f1730e0e638 94 mux2=true ;
parthsagar2010 12:2f1730e0e638 95 }
parthsagar2010 12:2f1730e0e638 96
parthsagar2010 12:2f1730e0e638 97 while (201<x<=300 && mux3==false)
parthsagar2010 12:2f1730e0e638 98 {
parthsagar2010 12:2f1730e0e638 99 rLed = 1 ;
parthsagar2010 12:2f1730e0e638 100 EN = 0 ;
parthsagar2010 12:2f1730e0e638 101 EN = 1;
parthsagar2010 12:2f1730e0e638 102 A0 = 0;
parthsagar2010 12:2f1730e0e638 103 A1 = 1;
parthsagar2010 12:2f1730e0e638 104 mux3=true;
parthsagar2010 12:2f1730e0e638 105 }
parthsagar2010 12:2f1730e0e638 106
parthsagar2010 13:3a49fb19b94b 107 */
coreyharris 4:06e258ff0b97 108 // Read back ECG samples from the FIFO
parthsagar2010 10:3709e8f3d089 109 if( ecgFIFOIntFlag ) {
parthsagar2010 12:2f1730e0e638 110 timer1.start();
parthsagar2010 13:3a49fb19b94b 111 // t=timer.read();
coreyharris 5:f8d1f651bef5 112 ecgFIFOIntFlag = 0;
parthsagar2010 13:3a49fb19b94b 113
coreyharris 4:06e258ff0b97 114 status = ecgAFE.readRegister( MAX30003::STATUS ); // Read the STATUS register
coreyharris 2:812d40f1853d 115
coreyharris 3:420d5efbd967 116 // Check if EINT interrupt asserted
parthsagar2010 10:3709e8f3d089 117 if ( ( status & EINT_STATUS_MASK ) == EINT_STATUS_MASK ) {
coreyharris 3:420d5efbd967 118
coreyharris 4:06e258ff0b97 119 readECGSamples = 0; // Reset sample counter
parthsagar2010 13:3a49fb19b94b 120
coreyharris 2:812d40f1853d 121 do {
coreyharris 6:86ac850c718d 122 ecgFIFO = ecgAFE.readRegister( MAX30003::ECG_FIFO ); // Read FIFO
coreyharris 4:06e258ff0b97 123 ecgSample[readECGSamples] = ecgFIFO >> 8; // Isolate voltage data
coreyharris 6:86ac850c718d 124 ETAG[readECGSamples] = ( ecgFIFO >> 3 ) & ETAG_BITS_MASK; // Isolate ETAG
coreyharris 4:06e258ff0b97 125 readECGSamples++; // Increment sample counter
coreyharris 3:420d5efbd967 126
coreyharris 3:420d5efbd967 127 // Check that sample is not last sample in FIFO
coreyharris 6:86ac850c718d 128 } while ( ETAG[readECGSamples-1] == FIFO_VALID_SAMPLE_MASK ||
coreyharris 6:86ac850c718d 129 ETAG[readECGSamples-1] == FIFO_FAST_SAMPLE_MASK );
coreyharris 2:812d40f1853d 130
coreyharris 3:420d5efbd967 131 // Check if FIFO has overflowed
parthsagar2010 10:3709e8f3d089 132 if( ETAG[readECGSamples - 1] == FIFO_OVF_MASK ){
coreyharris 3:420d5efbd967 133 ecgAFE.writeRegister( MAX30003::FIFO_RST , 0); // Reset FIFO
parthsagar2010 10:3709e8f3d089 134 bLed = 1;//notifies the user that an over flow occured
coreyharris 3:420d5efbd967 135 }
coreyharris 3:420d5efbd967 136
coreyharris 4:06e258ff0b97 137 // Print results
parthsagar2010 10:3709e8f3d089 138 for( idx = 0; idx < readECGSamples; idx++ ) {
parthsagar2010 10:3709e8f3d089 139 pc.printf("%6d\r\n", ecgSample[idx]);
parthsagar2010 13:3a49fb19b94b 140 // pc.printf("%d\n",t);
parthsagar2010 13:3a49fb19b94b 141
parthsagar2010 13:3a49fb19b94b 142 x++;
parthsagar2010 13:3a49fb19b94b 143 t++;
parthsagar2010 13:3a49fb19b94b 144
parthsagar2010 13:3a49fb19b94b 145 if (t>3000)
parthsagar2010 13:3a49fb19b94b 146 {
parthsagar2010 13:3a49fb19b94b 147 EN = 0;
parthsagar2010 13:3a49fb19b94b 148 EN = 1;
parthsagar2010 13:3a49fb19b94b 149 A0 = 0;
parthsagar2010 13:3a49fb19b94b 150 A1 = 0;
parthsagar2010 13:3a49fb19b94b 151 }
parthsagar2010 13:3a49fb19b94b 152 if (t>6000)
parthsagar2010 13:3a49fb19b94b 153
parthsagar2010 13:3a49fb19b94b 154 {
parthsagar2010 13:3a49fb19b94b 155 EN=0;
parthsagar2010 13:3a49fb19b94b 156 EN=1;
parthsagar2010 13:3a49fb19b94b 157 A0=0;
parthsagar2010 13:3a49fb19b94b 158 A1=1;
parthsagar2010 13:3a49fb19b94b 159
parthsagar2010 13:3a49fb19b94b 160 }
parthsagar2010 13:3a49fb19b94b 161
parthsagar2010 13:3a49fb19b94b 162 if (t>9000)
parthsagar2010 13:3a49fb19b94b 163
parthsagar2010 13:3a49fb19b94b 164 { t=0;}
parthsagar2010 13:3a49fb19b94b 165 }
parthsagar2010 12:2f1730e0e638 166 // bLed = ! bLed;
parthsagar2010 12:2f1730e0e638 167 // gLed = ! gLed;
parthsagar2010 12:2f1730e0e638 168 // rLed = ! rLed;
parthsagar2010 12:2f1730e0e638 169
parthsagar2010 12:2f1730e0e638 170
parthsagar2010 13:3a49fb19b94b 171
parthsagar2010 13:3a49fb19b94b 172 // if (x>300)
parthsagar2010 12:2f1730e0e638 173
parthsagar2010 13:3a49fb19b94b 174 // {x=0;}
parthsagar2010 13:3a49fb19b94b 175
parthsagar2010 13:3a49fb19b94b 176
parthsagar2010 13:3a49fb19b94b 177
coreyharris 0:38c49bc37c7c 178 }
parthsagar2010 13:3a49fb19b94b 179 }
parthsagar2010 12:2f1730e0e638 180
parthsagar2010 12:2f1730e0e638 181 }
coreyharris 0:38c49bc37c7c 182 }
parthsagar2010 10:3709e8f3d089 183
parthsagar2010 10:3709e8f3d089 184
parthsagar2010 10:3709e8f3d089 185
parthsagar2010 10:3709e8f3d089 186
coreyharris 0:38c49bc37c7c 187 void ecg_config(MAX30003& ecgAFE) {
parthsagar2010 10:3709e8f3d089 188
coreyharris 1:86843c27cc81 189 // Reset ECG to clear registers
coreyharris 1:86843c27cc81 190 ecgAFE.writeRegister( MAX30003::SW_RST , 0);
coreyharris 0:38c49bc37c7c 191
coreyharris 1:86843c27cc81 192 // General config register setting
coreyharris 1:86843c27cc81 193 MAX30003::GeneralConfiguration_u CNFG_GEN_r;
coreyharris 3:420d5efbd967 194 CNFG_GEN_r.bits.en_ecg = 1; // Enable ECG channel
coreyharris 3:420d5efbd967 195 CNFG_GEN_r.bits.rbiasn = 1; // Enable resistive bias on negative input
coreyharris 3:420d5efbd967 196 CNFG_GEN_r.bits.rbiasp = 1; // Enable resistive bias on positive input
coreyharris 3:420d5efbd967 197 CNFG_GEN_r.bits.en_rbias = 1; // Enable resistive bias
coreyharris 3:420d5efbd967 198 CNFG_GEN_r.bits.imag = 2; // Current magnitude = 10nA
coreyharris 3:420d5efbd967 199 CNFG_GEN_r.bits.en_dcloff = 1; // Enable DC lead-off detection
coreyharris 1:86843c27cc81 200 ecgAFE.writeRegister( MAX30003::CNFG_GEN , CNFG_GEN_r.all);
coreyharris 1:86843c27cc81 201
coreyharris 1:86843c27cc81 202
coreyharris 1:86843c27cc81 203 // ECG Config register setting
coreyharris 1:86843c27cc81 204 MAX30003::ECGConfiguration_u CNFG_ECG_r;
coreyharris 3:420d5efbd967 205 CNFG_ECG_r.bits.dlpf = 1; // Digital LPF cutoff = 40Hz
coreyharris 3:420d5efbd967 206 CNFG_ECG_r.bits.dhpf = 1; // Digital HPF cutoff = 0.5Hz
coreyharris 3:420d5efbd967 207 CNFG_ECG_r.bits.gain = 3; // ECG gain = 160V/V
coreyharris 3:420d5efbd967 208 CNFG_ECG_r.bits.rate = 2; // Sample rate = 128 sps
coreyharris 1:86843c27cc81 209 ecgAFE.writeRegister( MAX30003::CNFG_ECG , CNFG_ECG_r.all);
coreyharris 1:86843c27cc81 210
coreyharris 1:86843c27cc81 211
coreyharris 1:86843c27cc81 212 //R-to-R configuration
coreyharris 1:86843c27cc81 213 MAX30003::RtoR1Configuration_u CNFG_RTOR_r;
coreyharris 3:420d5efbd967 214 CNFG_RTOR_r.bits.en_rtor = 1; // Enable R-to-R detection
coreyharris 1:86843c27cc81 215 ecgAFE.writeRegister( MAX30003::CNFG_RTOR1 , CNFG_RTOR_r.all);
coreyharris 1:86843c27cc81 216
coreyharris 1:86843c27cc81 217
coreyharris 1:86843c27cc81 218 //Manage interrupts register setting
coreyharris 1:86843c27cc81 219 MAX30003::ManageInterrupts_u MNG_INT_r;
coreyharris 3:420d5efbd967 220 MNG_INT_r.bits.efit = 0b00011; // Assert EINT w/ 4 unread samples
coreyharris 3:420d5efbd967 221 MNG_INT_r.bits.clr_rrint = 0b01; // Clear R-to-R on RTOR reg. read back
coreyharris 1:86843c27cc81 222 ecgAFE.writeRegister( MAX30003::MNGR_INT , MNG_INT_r.all);
coreyharris 0:38c49bc37c7c 223
coreyharris 0:38c49bc37c7c 224
coreyharris 1:86843c27cc81 225 //Enable interrupts register setting
coreyharris 1:86843c27cc81 226 MAX30003::EnableInterrupts_u EN_INT_r;
coreyharris 5:f8d1f651bef5 227 EN_INT_r.all = 0;
coreyharris 3:420d5efbd967 228 EN_INT_r.bits.en_eint = 1; // Enable EINT interrupt
coreyharris 4:06e258ff0b97 229 EN_INT_r.bits.en_rrint = 0; // Disable R-to-R interrupt
coreyharris 3:420d5efbd967 230 EN_INT_r.bits.intb_type = 3; // Open-drain NMOS with internal pullup
coreyharris 1:86843c27cc81 231 ecgAFE.writeRegister( MAX30003::EN_INT , EN_INT_r.all);
coreyharris 1:86843c27cc81 232
coreyharris 1:86843c27cc81 233
coreyharris 1:86843c27cc81 234 //Dyanmic modes config
coreyharris 1:86843c27cc81 235 MAX30003::ManageDynamicModes_u MNG_DYN_r;
coreyharris 3:420d5efbd967 236 MNG_DYN_r.bits.fast = 0; // Fast recovery mode disabled
coreyharris 1:86843c27cc81 237 ecgAFE.writeRegister( MAX30003::MNGR_DYN , MNG_DYN_r.all);
coreyharris 5:f8d1f651bef5 238
coreyharris 5:f8d1f651bef5 239 // MUX Config
coreyharris 5:f8d1f651bef5 240 MAX30003::MuxConfiguration_u CNFG_MUX_r;
coreyharris 5:f8d1f651bef5 241 CNFG_MUX_r.bits.openn = 0; // Connect ECGN to AFE channel
coreyharris 5:f8d1f651bef5 242 CNFG_MUX_r.bits.openp = 0; // Connect ECGP to AFE channel
coreyharris 5:f8d1f651bef5 243 ecgAFE.writeRegister( MAX30003::CNFG_EMUX , CNFG_MUX_r.all);
coreyharris 1:86843c27cc81 244
coreyharris 1:86843c27cc81 245 return;
parthsagar2010 10:3709e8f3d089 246 }