MH / Mbed OS MAX30003WING_Demo_QRS_RK_MUX_05292021

3 channel_MUX

Dependencies:   BufferedSerial MAX30003 max32630fthr1 DS1307

main.cpp@14:2b140cea57b2, 2021-05-29 (annotated)

Committer:
kidecha_rahul
Date:
Sat May 29 19:50:35 2021 +0000
Revision:
14:2b140cea57b2
Parent:
13:3a49fb19b94b 
3 channal_MUX

Who changed what in which revision?

UserRevisionLine numberNew contents of line
coreyharris 0:38c49bc37c7c 1 #include "mbed.h"
coreyharris 0:38c49bc37c7c 2 #include "max32630fthr.h"
parthsagar2010 10:3709e8f3d089 3 #include "MAX30003.h"
parthsagar2010 10:3709e8f3d089 4
coreyharris 0:38c49bc37c7c 5 MAX32630FTHR pegasus(MAX32630FTHR::VIO_3V3);
parthsagar2010 10:3709e8f3d089 6
coreyharris 0:38c49bc37c7c 7 void ecg_config(MAX30003 &ecgAFE);
parthsagar2010 12:2f1730e0e638 8 DigitalOut led1(P2_0,LED_ON);
parthsagar2010 12:2f1730e0e638 9
parthsagar2010 12:2f1730e0e638 10
parthsagar2010 12:2f1730e0e638 11
parthsagar2010 10:3709e8f3d089 12 /* ECG FIFO nearly full callback */
coreyharris 0:38c49bc37c7c 13 volatile bool ecgFIFOIntFlag = 0;
parthsagar2010 10:3709e8f3d089 14 void ecgFIFO_callback() {
coreyharris 0:38c49bc37c7c 15
coreyharris 0:38c49bc37c7c 16 ecgFIFOIntFlag = 1;
parthsagar2010 10:3709e8f3d089 17
coreyharris 0:38c49bc37c7c 18 }
parthsagar2010 12:2f1730e0e638 19 Timer timer1;
kidecha_rahul 14:2b140cea57b2 20
parthsagar2010 12:2f1730e0e638 21 DigitalOut EN(P1_7);
parthsagar2010 12:2f1730e0e638 22 DigitalOut A0(P1_4);
parthsagar2010 12:2f1730e0e638 23 DigitalOut A1(P7_2);
parthsagar2010 10:3709e8f3d089 24
coreyharris 0:38c49bc37c7c 25 int main()
coreyharris 3:420d5efbd967 26 {
parthsagar2010 12:2f1730e0e638 27
coreyharris 6:86ac850c718d 28 // Constants
coreyharris 4:06e258ff0b97 29 const int EINT_STATUS_MASK = 1 << 23;
coreyharris 6:86ac850c718d 30 const int FIFO_OVF_MASK = 0x7;
coreyharris 6:86ac850c718d 31 const int FIFO_VALID_SAMPLE_MASK = 0x0;
coreyharris 6:86ac850c718d 32 const int FIFO_FAST_SAMPLE_MASK = 0x1;
coreyharris 6:86ac850c718d 33 const int ETAG_BITS_MASK = 0x7;
coreyharris 3:420d5efbd967 34
kidecha_rahul 14:2b140cea57b2 35 int t=0;
kidecha_rahul 14:2b140cea57b2 36 EN=0;
kidecha_rahul 14:2b140cea57b2 37 EN=1;
kidecha_rahul 14:2b140cea57b2 38 A0=0;
kidecha_rahul 14:2b140cea57b2 39 A1=1;
parthsagar2010 12:2f1730e0e638 40
parthsagar2010 10:3709e8f3d089 41 // Ports and serial connections
parthsagar2010 13:3a49fb19b94b 42 Serial pc(P0_1,P0_0); // Use USB debug probe for serial link
parthsagar2010 10:3709e8f3d089 43 pc.baud(230400); // Baud rate = 115200
parthsagar2010 12:2f1730e0e638 44 DigitalOut bLed(LED3, LED_ON);
parthsagar2010 13:3a49fb19b94b 45 // DigitalOut gLed(LED2, LED_ON);
parthsagar2010 13:3a49fb19b94b 46 // DigitalOut rLed(LED1, LED_ON);
coreyharris 1:86843c27cc81 47
coreyharris 1:86843c27cc81 48 InterruptIn ecgFIFO_int(P5_4); // Config P5_4 as int. in for the
parthsagar2010 10:3709e8f3d089 49 ecgFIFO_int.fall(&ecgFIFO_callback); // ecg FIFO almost full interrupt
coreyharris 0:38c49bc37c7c 50
parthsagar2010 11:1d4ecbca034e 51 //SPI spiBus(SPI2_MOSI, SPI2_MISO, SPI2_SCK); // SPI bus, P5_1 = MOSI,
kidecha_rahul 14:2b140cea57b2 52 // P5_2 = MISO, P5_0 = SCK
kidecha_rahul 14:2b140cea57b2 53 SPI spiBus(P5_1, P5_2, P5_0);
parthsagar2010 11:1d4ecbca034e 54
coreyharris 4:06e258ff0b97 55 MAX30003 ecgAFE(spiBus, P5_3); // New MAX30003 on spiBus, CS = P5_3
coreyharris 4:06e258ff0b97 56 ecg_config(ecgAFE); // Config ECG
coreyharris 1:86843c27cc81 57
coreyharris 0:38c49bc37c7c 58
kidecha_rahul 14:2b140cea57b2 59 ecgAFE.writeRegister( MAX30003::SYNCH ,0);
coreyharris 0:38c49bc37c7c 60
coreyharris 4:06e258ff0b97 61 uint32_t ecgFIFO, readECGSamples, idx, ETAG[32], status;
coreyharris 1:86843c27cc81 62 int16_t ecgSample[32];
kidecha_rahul 14:2b140cea57b2 63
parthsagar2010 10:3709e8f3d089 64 while(1) {
kidecha_rahul 14:2b140cea57b2 65
coreyharris 4:06e258ff0b97 66 // Read back ECG samples from the FIFO
parthsagar2010 10:3709e8f3d089 67 if( ecgFIFOIntFlag ) {
parthsagar2010 12:2f1730e0e638 68 timer1.start();
parthsagar2010 13:3a49fb19b94b 69 // t=timer.read();
coreyharris 5:f8d1f651bef5 70 ecgFIFOIntFlag = 0;
parthsagar2010 13:3a49fb19b94b 71
coreyharris 4:06e258ff0b97 72 status = ecgAFE.readRegister( MAX30003::STATUS ); // Read the STATUS register
coreyharris 2:812d40f1853d 73
coreyharris 3:420d5efbd967 74 // Check if EINT interrupt asserted
parthsagar2010 10:3709e8f3d089 75 if ( ( status & EINT_STATUS_MASK ) == EINT_STATUS_MASK ) {
coreyharris 3:420d5efbd967 76
coreyharris 4:06e258ff0b97 77 readECGSamples = 0; // Reset sample counter
parthsagar2010 13:3a49fb19b94b 78
coreyharris 2:812d40f1853d 79 do {
coreyharris 6:86ac850c718d 80 ecgFIFO = ecgAFE.readRegister( MAX30003::ECG_FIFO ); // Read FIFO
coreyharris 4:06e258ff0b97 81 ecgSample[readECGSamples] = ecgFIFO >> 8; // Isolate voltage data
coreyharris 6:86ac850c718d 82 ETAG[readECGSamples] = ( ecgFIFO >> 3 ) & ETAG_BITS_MASK; // Isolate ETAG
coreyharris 4:06e258ff0b97 83 readECGSamples++; // Increment sample counter
coreyharris 3:420d5efbd967 84
coreyharris 3:420d5efbd967 85 // Check that sample is not last sample in FIFO
coreyharris 6:86ac850c718d 86 } while ( ETAG[readECGSamples-1] == FIFO_VALID_SAMPLE_MASK ||
coreyharris 6:86ac850c718d 87 ETAG[readECGSamples-1] == FIFO_FAST_SAMPLE_MASK );
coreyharris 2:812d40f1853d 88
coreyharris 3:420d5efbd967 89 // Check if FIFO has overflowed
parthsagar2010 10:3709e8f3d089 90 if( ETAG[readECGSamples - 1] == FIFO_OVF_MASK ){
coreyharris 3:420d5efbd967 91 ecgAFE.writeRegister( MAX30003::FIFO_RST , 0); // Reset FIFO
parthsagar2010 10:3709e8f3d089 92 bLed = 1;//notifies the user that an over flow occured
coreyharris 3:420d5efbd967 93 }
coreyharris 3:420d5efbd967 94
coreyharris 4:06e258ff0b97 95 // Print results
parthsagar2010 10:3709e8f3d089 96 for( idx = 0; idx < readECGSamples; idx++ ) {
parthsagar2010 10:3709e8f3d089 97 pc.printf("%6d\r\n", ecgSample[idx]);
parthsagar2010 13:3a49fb19b94b 98 // pc.printf("%d\n",t);
kidecha_rahul 14:2b140cea57b2 99 //bLed = !bLed;
kidecha_rahul 14:2b140cea57b2 100 t++;
parthsagar2010 13:3a49fb19b94b 101
kidecha_rahul 14:2b140cea57b2 102 if (t>3000){
kidecha_rahul 14:2b140cea57b2 103 EN = 0;
kidecha_rahul 14:2b140cea57b2 104 EN = 1;
kidecha_rahul 14:2b140cea57b2 105 A0 = 0;
kidecha_rahul 14:2b140cea57b2 106 A1 = 0;
kidecha_rahul 14:2b140cea57b2 107 DigitalOut bLed(LED3, LED_OFF);
kidecha_rahul 14:2b140cea57b2 108 DigitalOut gLed(LED2, LED_ON);
kidecha_rahul 14:2b140cea57b2 109 }
kidecha_rahul 14:2b140cea57b2 110 if (t>6000){
kidecha_rahul 14:2b140cea57b2 111 EN=0;
kidecha_rahul 14:2b140cea57b2 112 EN=1;
kidecha_rahul 14:2b140cea57b2 113 A0=1;
kidecha_rahul 14:2b140cea57b2 114 A1=0;
kidecha_rahul 14:2b140cea57b2 115 DigitalOut gLed(LED2, LED_OFF);
kidecha_rahul 14:2b140cea57b2 116 DigitalOut rLed(LED1, LED_ON);
kidecha_rahul 14:2b140cea57b2 117 }
parthsagar2010 13:3a49fb19b94b 118
kidecha_rahul 14:2b140cea57b2 119 if (t>9000){
kidecha_rahul 14:2b140cea57b2 120 DigitalOut rLed(LED1, LED_OFF);
kidecha_rahul 14:2b140cea57b2 121 DigitalOut bLed(LED3, LED_ON);
kidecha_rahul 14:2b140cea57b2 122 t=0;
kidecha_rahul 14:2b140cea57b2 123 EN=0;
kidecha_rahul 14:2b140cea57b2 124 EN=1;
kidecha_rahul 14:2b140cea57b2 125 A0=0;
kidecha_rahul 14:2b140cea57b2 126 A1=1;
kidecha_rahul 14:2b140cea57b2 127 }
kidecha_rahul 14:2b140cea57b2 128 }
kidecha_rahul 14:2b140cea57b2 129 }
parthsagar2010 13:3a49fb19b94b 130 }
parthsagar2010 12:2f1730e0e638 131
kidecha_rahul 14:2b140cea57b2 132 }
coreyharris 0:38c49bc37c7c 133 }
parthsagar2010 10:3709e8f3d089 134
parthsagar2010 10:3709e8f3d089 135
parthsagar2010 10:3709e8f3d089 136
parthsagar2010 10:3709e8f3d089 137
coreyharris 0:38c49bc37c7c 138 void ecg_config(MAX30003& ecgAFE) {
parthsagar2010 10:3709e8f3d089 139
coreyharris 1:86843c27cc81 140 // Reset ECG to clear registers
coreyharris 1:86843c27cc81 141 ecgAFE.writeRegister( MAX30003::SW_RST , 0);
coreyharris 0:38c49bc37c7c 142
coreyharris 1:86843c27cc81 143 // General config register setting
coreyharris 1:86843c27cc81 144 MAX30003::GeneralConfiguration_u CNFG_GEN_r;
coreyharris 3:420d5efbd967 145 CNFG_GEN_r.bits.en_ecg = 1; // Enable ECG channel
coreyharris 3:420d5efbd967 146 CNFG_GEN_r.bits.rbiasn = 1; // Enable resistive bias on negative input
coreyharris 3:420d5efbd967 147 CNFG_GEN_r.bits.rbiasp = 1; // Enable resistive bias on positive input
coreyharris 3:420d5efbd967 148 CNFG_GEN_r.bits.en_rbias = 1; // Enable resistive bias
coreyharris 3:420d5efbd967 149 CNFG_GEN_r.bits.imag = 2; // Current magnitude = 10nA
coreyharris 3:420d5efbd967 150 CNFG_GEN_r.bits.en_dcloff = 1; // Enable DC lead-off detection
coreyharris 1:86843c27cc81 151 ecgAFE.writeRegister( MAX30003::CNFG_GEN , CNFG_GEN_r.all);
coreyharris 1:86843c27cc81 152
coreyharris 1:86843c27cc81 153
coreyharris 1:86843c27cc81 154 // ECG Config register setting
coreyharris 1:86843c27cc81 155 MAX30003::ECGConfiguration_u CNFG_ECG_r;
coreyharris 3:420d5efbd967 156 CNFG_ECG_r.bits.dlpf = 1; // Digital LPF cutoff = 40Hz
coreyharris 3:420d5efbd967 157 CNFG_ECG_r.bits.dhpf = 1; // Digital HPF cutoff = 0.5Hz
coreyharris 3:420d5efbd967 158 CNFG_ECG_r.bits.gain = 3; // ECG gain = 160V/V
coreyharris 3:420d5efbd967 159 CNFG_ECG_r.bits.rate = 2; // Sample rate = 128 sps
coreyharris 1:86843c27cc81 160 ecgAFE.writeRegister( MAX30003::CNFG_ECG , CNFG_ECG_r.all);
coreyharris 1:86843c27cc81 161
coreyharris 1:86843c27cc81 162
coreyharris 1:86843c27cc81 163 //R-to-R configuration
coreyharris 1:86843c27cc81 164 MAX30003::RtoR1Configuration_u CNFG_RTOR_r;
coreyharris 3:420d5efbd967 165 CNFG_RTOR_r.bits.en_rtor = 1; // Enable R-to-R detection
coreyharris 1:86843c27cc81 166 ecgAFE.writeRegister( MAX30003::CNFG_RTOR1 , CNFG_RTOR_r.all);
coreyharris 1:86843c27cc81 167
coreyharris 1:86843c27cc81 168
coreyharris 1:86843c27cc81 169 //Manage interrupts register setting
coreyharris 1:86843c27cc81 170 MAX30003::ManageInterrupts_u MNG_INT_r;
coreyharris 3:420d5efbd967 171 MNG_INT_r.bits.efit = 0b00011; // Assert EINT w/ 4 unread samples
coreyharris 3:420d5efbd967 172 MNG_INT_r.bits.clr_rrint = 0b01; // Clear R-to-R on RTOR reg. read back
coreyharris 1:86843c27cc81 173 ecgAFE.writeRegister( MAX30003::MNGR_INT , MNG_INT_r.all);
coreyharris 0:38c49bc37c7c 174
coreyharris 0:38c49bc37c7c 175
coreyharris 1:86843c27cc81 176 //Enable interrupts register setting
coreyharris 1:86843c27cc81 177 MAX30003::EnableInterrupts_u EN_INT_r;
coreyharris 5:f8d1f651bef5 178 EN_INT_r.all = 0;
coreyharris 3:420d5efbd967 179 EN_INT_r.bits.en_eint = 1; // Enable EINT interrupt
coreyharris 4:06e258ff0b97 180 EN_INT_r.bits.en_rrint = 0; // Disable R-to-R interrupt
coreyharris 3:420d5efbd967 181 EN_INT_r.bits.intb_type = 3; // Open-drain NMOS with internal pullup
coreyharris 1:86843c27cc81 182 ecgAFE.writeRegister( MAX30003::EN_INT , EN_INT_r.all);
coreyharris 1:86843c27cc81 183
coreyharris 1:86843c27cc81 184
coreyharris 1:86843c27cc81 185 //Dyanmic modes config
coreyharris 1:86843c27cc81 186 MAX30003::ManageDynamicModes_u MNG_DYN_r;
coreyharris 3:420d5efbd967 187 MNG_DYN_r.bits.fast = 0; // Fast recovery mode disabled
coreyharris 1:86843c27cc81 188 ecgAFE.writeRegister( MAX30003::MNGR_DYN , MNG_DYN_r.all);
coreyharris 5:f8d1f651bef5 189
coreyharris 5:f8d1f651bef5 190 // MUX Config
coreyharris 5:f8d1f651bef5 191 MAX30003::MuxConfiguration_u CNFG_MUX_r;
coreyharris 5:f8d1f651bef5 192 CNFG_MUX_r.bits.openn = 0; // Connect ECGN to AFE channel
coreyharris 5:f8d1f651bef5 193 CNFG_MUX_r.bits.openp = 0; // Connect ECGP to AFE channel
coreyharris 5:f8d1f651bef5 194 ecgAFE.writeRegister( MAX30003::CNFG_EMUX , CNFG_MUX_r.all);
coreyharris 1:86843c27cc81 195
coreyharris 1:86843c27cc81 196 return;
parthsagar2010 10:3709e8f3d089 197 }