MH / Mbed OS MAX30003WING_Demo_QRS_RK_MUX_05292021

3 channel_MUX

Dependencies:   BufferedSerial MAX30003 max32630fthr1 DS1307

main.cpp@9:24ecf16eab0f, 2020-08-19 (annotated)

Committer:
parthsagar2010
Date:
Wed Aug 19 19:38:17 2020 +0000
Revision:
9:24ecf16eab0f
Parent:
8:6b9359f81cc0
Child:
10:3709e8f3d089
Updated the code with 1 sec packets

Who changed what in which revision?

UserRevisionLine numberNew contents of line
coreyharris 6:86ac850c718d 1
parthsagar2010 8:6b9359f81cc0 2 #include "MAX30003.h"
coreyharris 0:38c49bc37c7c 3 #include "mbed.h"
coreyharris 0:38c49bc37c7c 4 #include "max32630fthr.h"
parthsagar2010 9:24ecf16eab0f 5 #include "ds1307.h"
parthsagar2010 8:6b9359f81cc0 6
parthsagar2010 9:24ecf16eab0f 7 Timer timer_fast;
coreyharris 0:38c49bc37c7c 8 MAX32630FTHR pegasus(MAX32630FTHR::VIO_3V3);
coreyharris 0:38c49bc37c7c 9
parthsagar2010 9:24ecf16eab0f 10 void task_fast(void);
parthsagar2010 9:24ecf16eab0f 11 DigitalOut ledA(LED2);
coreyharris 0:38c49bc37c7c 12 void ecg_config(MAX30003 &ecgAFE);
coreyharris 0:38c49bc37c7c 13
coreyharris 0:38c49bc37c7c 14 volatile bool ecgFIFOIntFlag = 0;
parthsagar2010 9:24ecf16eab0f 15 volatile int16_t onesec_counter = 0;
parthsagar2010 9:24ecf16eab0f 16 volatile bool timerflag = 0;
parthsagar2010 8:6b9359f81cc0 17 void ecgFIFO_callback_1() { // Triggered when the ECG FIFO is about to be full
coreyharris 0:38c49bc37c7c 18
coreyharris 0:38c49bc37c7c 19 ecgFIFOIntFlag = 1;
coreyharris 0:38c49bc37c7c 20
coreyharris 0:38c49bc37c7c 21 }
coreyharris 0:38c49bc37c7c 22
coreyharris 0:38c49bc37c7c 23 int main()
coreyharris 3:420d5efbd967 24 {
coreyharris 6:86ac850c718d 25
coreyharris 6:86ac850c718d 26 // Constants
coreyharris 4:06e258ff0b97 27 const int EINT_STATUS_MASK = 1 << 23;
coreyharris 6:86ac850c718d 28 const int FIFO_OVF_MASK = 0x7;
coreyharris 6:86ac850c718d 29 const int FIFO_VALID_SAMPLE_MASK = 0x0;
coreyharris 6:86ac850c718d 30 const int FIFO_FAST_SAMPLE_MASK = 0x1;
coreyharris 6:86ac850c718d 31 const int ETAG_BITS_MASK = 0x7;
parthsagar2010 9:24ecf16eab0f 32 timer_fast.start();
parthsagar2010 8:6b9359f81cc0 33 DigitalOut rLed(LED1, LED_OFF);
coreyharris 3:420d5efbd967 34
coreyharris 1:86843c27cc81 35 Serial pc(USBTX, USBRX); // Use USB debug probe for serial link
coreyharris 1:86843c27cc81 36 pc.baud(115200); // Baud rate = 115200
coreyharris 1:86843c27cc81 37
coreyharris 1:86843c27cc81 38 InterruptIn ecgFIFO_int(P5_4); // Config P5_4 as int. in for the
parthsagar2010 8:6b9359f81cc0 39 ecgFIFO_int.fall(&ecgFIFO_callback_1); // ecg FIFO interrupt at falling edge
coreyharris 0:38c49bc37c7c 40
coreyharris 1:86843c27cc81 41 SPI spiBus(SPI2_MOSI, SPI2_MISO, SPI2_SCK); // SPI bus, P5_1 = MOSI,
coreyharris 1:86843c27cc81 42 // P5_2 = MISO, P5_0 = SCK
coreyharris 0:38c49bc37c7c 43
coreyharris 4:06e258ff0b97 44 MAX30003 ecgAFE(spiBus, P5_3); // New MAX30003 on spiBus, CS = P5_3
parthsagar2010 8:6b9359f81cc0 45
coreyharris 4:06e258ff0b97 46 ecg_config(ecgAFE); // Config ECG
coreyharris 1:86843c27cc81 47
coreyharris 0:38c49bc37c7c 48
coreyharris 4:06e258ff0b97 49 ecgAFE.writeRegister( MAX30003::SYNCH , 0);
coreyharris 0:38c49bc37c7c 50
coreyharris 4:06e258ff0b97 51 uint32_t ecgFIFO, readECGSamples, idx, ETAG[32], status;
coreyharris 1:86843c27cc81 52 int16_t ecgSample[32];
parthsagar2010 9:24ecf16eab0f 53 //bool timerflag = false;
parthsagar2010 9:24ecf16eab0f 54 int16_t ecgSample_1sec[700];
parthsagar2010 9:24ecf16eab0f 55 int16_t onesec_counter = 0;
parthsagar2010 9:24ecf16eab0f 56 int16_t sample = 300;
coreyharris 2:812d40f1853d 57
parthsagar2010 9:24ecf16eab0f 58 while(1)
parthsagar2010 9:24ecf16eab0f 59 {
parthsagar2010 9:24ecf16eab0f 60
parthsagar2010 9:24ecf16eab0f 61 if (timer_fast.read() > 1)
parthsagar2010 9:24ecf16eab0f 62 {
parthsagar2010 9:24ecf16eab0f 63 //timerflag = 1;
parthsagar2010 9:24ecf16eab0f 64 ledA = !ledA;
parthsagar2010 9:24ecf16eab0f 65 timer_fast.reset();
parthsagar2010 9:24ecf16eab0f 66 int8_t header_device_id[3] = {0,0,210};
parthsagar2010 9:24ecf16eab0f 67 int8_t header_packet_type[2] = {0,2};
parthsagar2010 9:24ecf16eab0f 68 int8_t header_packet_id[4] = {0,0,0,0};
parthsagar2010 9:24ecf16eab0f 69 int8_t header_ecg_datalen[2] = {0,onesec_counter};
parthsagar2010 9:24ecf16eab0f 70 int8_t header_ecg_checksum[2] = {0,0};
parthsagar2010 9:24ecf16eab0f 71
parthsagar2010 9:24ecf16eab0f 72
parthsagar2010 9:24ecf16eab0f 73 //pc.printf("%6d\r\n", sample);
parthsagar2010 9:24ecf16eab0f 74 //pc.printf("%6d\r\n", onesec_counter);
parthsagar2010 9:24ecf16eab0f 75
parthsagar2010 9:24ecf16eab0f 76 onesec_counter = 0;
parthsagar2010 9:24ecf16eab0f 77 }
coreyharris 4:06e258ff0b97 78 // Read back ECG samples from the FIFO
parthsagar2010 9:24ecf16eab0f 79 else if( (ecgFIFOIntFlag==1))// && (timerflag == 0))
parthsagar2010 9:24ecf16eab0f 80 {
coreyharris 2:812d40f1853d 81
coreyharris 5:f8d1f651bef5 82 ecgFIFOIntFlag = 0;
coreyharris 4:06e258ff0b97 83 status = ecgAFE.readRegister( MAX30003::STATUS ); // Read the STATUS register
coreyharris 2:812d40f1853d 84
coreyharris 3:420d5efbd967 85 // Check if EINT interrupt asserted
parthsagar2010 9:24ecf16eab0f 86 if ( ( status & EINT_STATUS_MASK ) == EINT_STATUS_MASK )
parthsagar2010 9:24ecf16eab0f 87 {
coreyharris 3:420d5efbd967 88
coreyharris 4:06e258ff0b97 89 readECGSamples = 0; // Reset sample counter
coreyharris 3:420d5efbd967 90
coreyharris 2:812d40f1853d 91 do {
coreyharris 6:86ac850c718d 92 ecgFIFO = ecgAFE.readRegister( MAX30003::ECG_FIFO ); // Read FIFO
coreyharris 4:06e258ff0b97 93 ecgSample[readECGSamples] = ecgFIFO >> 8; // Isolate voltage data
coreyharris 6:86ac850c718d 94 ETAG[readECGSamples] = ( ecgFIFO >> 3 ) & ETAG_BITS_MASK; // Isolate ETAG
coreyharris 4:06e258ff0b97 95 readECGSamples++; // Increment sample counter
coreyharris 3:420d5efbd967 96
coreyharris 3:420d5efbd967 97 // Check that sample is not last sample in FIFO
coreyharris 6:86ac850c718d 98 } while ( ETAG[readECGSamples-1] == FIFO_VALID_SAMPLE_MASK ||
coreyharris 6:86ac850c718d 99 ETAG[readECGSamples-1] == FIFO_FAST_SAMPLE_MASK );
coreyharris 2:812d40f1853d 100
coreyharris 3:420d5efbd967 101 // Check if FIFO has overflowed
parthsagar2010 9:24ecf16eab0f 102 if( ETAG[readECGSamples - 1] == FIFO_OVF_MASK )
parthsagar2010 9:24ecf16eab0f 103 {
coreyharris 3:420d5efbd967 104 ecgAFE.writeRegister( MAX30003::FIFO_RST , 0); // Reset FIFO
johnGreeneMaxim 7:cf0855a0450a 105 rLed = 1;//notifies the user that an over flow occured
coreyharris 3:420d5efbd967 106 }
coreyharris 3:420d5efbd967 107
coreyharris 4:06e258ff0b97 108 // Print results
parthsagar2010 9:24ecf16eab0f 109 for( idx = 0; idx < readECGSamples; idx++ )
parthsagar2010 9:24ecf16eab0f 110 {
parthsagar2010 9:24ecf16eab0f 111 //pc.printf("%6d\r\n", ecgSample[idx]);
parthsagar2010 9:24ecf16eab0f 112 ecgSample_1sec[onesec_counter] = ecgSample[idx];
parthsagar2010 9:24ecf16eab0f 113 onesec_counter++;
coreyharris 6:86ac850c718d 114 }
coreyharris 6:86ac850c718d 115
coreyharris 0:38c49bc37c7c 116 }
parthsagar2010 9:24ecf16eab0f 117 // else
parthsagar2010 9:24ecf16eab0f 118 // {
parthsagar2010 9:24ecf16eab0f 119 // timerflag = 0;
parthsagar2010 9:24ecf16eab0f 120 // }
parthsagar2010 9:24ecf16eab0f 121 //else if (timerflag == 1)
parthsagar2010 9:24ecf16eab0f 122 //{
parthsagar2010 9:24ecf16eab0f 123 //timerflag = 0;
parthsagar2010 9:24ecf16eab0f 124 //pc.printf("1 sec ends :\n");
parthsagar2010 9:24ecf16eab0f 125 //onesec_counter = 0;
parthsagar2010 9:24ecf16eab0f 126 //timer_fast.reset();
parthsagar2010 9:24ecf16eab0f 127 //timer_fast.start();
parthsagar2010 9:24ecf16eab0f 128 //delete[] ecgSample_1sec;
parthsagar2010 9:24ecf16eab0f 129 //}
parthsagar2010 9:24ecf16eab0f 130
parthsagar2010 9:24ecf16eab0f 131
coreyharris 0:38c49bc37c7c 132 }
coreyharris 0:38c49bc37c7c 133 }
coreyharris 0:38c49bc37c7c 134 }
coreyharris 0:38c49bc37c7c 135
coreyharris 0:38c49bc37c7c 136
coreyharris 0:38c49bc37c7c 137
coreyharris 0:38c49bc37c7c 138
coreyharris 0:38c49bc37c7c 139 void ecg_config(MAX30003& ecgAFE) {
coreyharris 0:38c49bc37c7c 140
coreyharris 1:86843c27cc81 141 // Reset ECG to clear registers
coreyharris 1:86843c27cc81 142 ecgAFE.writeRegister( MAX30003::SW_RST , 0);
coreyharris 0:38c49bc37c7c 143
coreyharris 1:86843c27cc81 144 // General config register setting
coreyharris 1:86843c27cc81 145 MAX30003::GeneralConfiguration_u CNFG_GEN_r;
coreyharris 3:420d5efbd967 146 CNFG_GEN_r.bits.en_ecg = 1; // Enable ECG channel
coreyharris 3:420d5efbd967 147 CNFG_GEN_r.bits.rbiasn = 1; // Enable resistive bias on negative input
coreyharris 3:420d5efbd967 148 CNFG_GEN_r.bits.rbiasp = 1; // Enable resistive bias on positive input
coreyharris 3:420d5efbd967 149 CNFG_GEN_r.bits.en_rbias = 1; // Enable resistive bias
coreyharris 3:420d5efbd967 150 CNFG_GEN_r.bits.imag = 2; // Current magnitude = 10nA
coreyharris 3:420d5efbd967 151 CNFG_GEN_r.bits.en_dcloff = 1; // Enable DC lead-off detection
coreyharris 1:86843c27cc81 152 ecgAFE.writeRegister( MAX30003::CNFG_GEN , CNFG_GEN_r.all);
coreyharris 1:86843c27cc81 153
coreyharris 1:86843c27cc81 154
coreyharris 1:86843c27cc81 155 // ECG Config register setting
coreyharris 1:86843c27cc81 156 MAX30003::ECGConfiguration_u CNFG_ECG_r;
coreyharris 3:420d5efbd967 157 CNFG_ECG_r.bits.dlpf = 1; // Digital LPF cutoff = 40Hz
coreyharris 3:420d5efbd967 158 CNFG_ECG_r.bits.dhpf = 1; // Digital HPF cutoff = 0.5Hz
coreyharris 3:420d5efbd967 159 CNFG_ECG_r.bits.gain = 3; // ECG gain = 160V/V
coreyharris 3:420d5efbd967 160 CNFG_ECG_r.bits.rate = 2; // Sample rate = 128 sps
coreyharris 1:86843c27cc81 161 ecgAFE.writeRegister( MAX30003::CNFG_ECG , CNFG_ECG_r.all);
coreyharris 1:86843c27cc81 162
coreyharris 1:86843c27cc81 163
coreyharris 1:86843c27cc81 164 //R-to-R configuration
coreyharris 1:86843c27cc81 165 MAX30003::RtoR1Configuration_u CNFG_RTOR_r;
coreyharris 3:420d5efbd967 166 CNFG_RTOR_r.bits.en_rtor = 1; // Enable R-to-R detection
coreyharris 1:86843c27cc81 167 ecgAFE.writeRegister( MAX30003::CNFG_RTOR1 , CNFG_RTOR_r.all);
coreyharris 1:86843c27cc81 168
coreyharris 1:86843c27cc81 169
coreyharris 1:86843c27cc81 170 //Manage interrupts register setting
coreyharris 1:86843c27cc81 171 MAX30003::ManageInterrupts_u MNG_INT_r;
coreyharris 3:420d5efbd967 172 MNG_INT_r.bits.efit = 0b00011; // Assert EINT w/ 4 unread samples
coreyharris 3:420d5efbd967 173 MNG_INT_r.bits.clr_rrint = 0b01; // Clear R-to-R on RTOR reg. read back
coreyharris 1:86843c27cc81 174 ecgAFE.writeRegister( MAX30003::MNGR_INT , MNG_INT_r.all);
coreyharris 0:38c49bc37c7c 175
coreyharris 0:38c49bc37c7c 176
coreyharris 1:86843c27cc81 177 //Enable interrupts register setting
coreyharris 1:86843c27cc81 178 MAX30003::EnableInterrupts_u EN_INT_r;
coreyharris 5:f8d1f651bef5 179 EN_INT_r.all = 0;
coreyharris 3:420d5efbd967 180 EN_INT_r.bits.en_eint = 1; // Enable EINT interrupt
coreyharris 4:06e258ff0b97 181 EN_INT_r.bits.en_rrint = 0; // Disable R-to-R interrupt
coreyharris 3:420d5efbd967 182 EN_INT_r.bits.intb_type = 3; // Open-drain NMOS with internal pullup
coreyharris 1:86843c27cc81 183 ecgAFE.writeRegister( MAX30003::EN_INT , EN_INT_r.all);
coreyharris 1:86843c27cc81 184
coreyharris 1:86843c27cc81 185
coreyharris 1:86843c27cc81 186 //Dyanmic modes config
coreyharris 1:86843c27cc81 187 MAX30003::ManageDynamicModes_u MNG_DYN_r;
coreyharris 3:420d5efbd967 188 MNG_DYN_r.bits.fast = 0; // Fast recovery mode disabled
coreyharris 1:86843c27cc81 189 ecgAFE.writeRegister( MAX30003::MNGR_DYN , MNG_DYN_r.all);
coreyharris 5:f8d1f651bef5 190
coreyharris 5:f8d1f651bef5 191 // MUX Config
coreyharris 5:f8d1f651bef5 192 MAX30003::MuxConfiguration_u CNFG_MUX_r;
coreyharris 5:f8d1f651bef5 193 CNFG_MUX_r.bits.openn = 0; // Connect ECGN to AFE channel
coreyharris 5:f8d1f651bef5 194 CNFG_MUX_r.bits.openp = 0; // Connect ECGP to AFE channel
coreyharris 5:f8d1f651bef5 195 ecgAFE.writeRegister( MAX30003::CNFG_EMUX , CNFG_MUX_r.all);
coreyharris 1:86843c27cc81 196
coreyharris 1:86843c27cc81 197 return;
coreyharris 0:38c49bc37c7c 198 }
coreyharris 0:38c49bc37c7c 199