Girls BMS squad
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HighSide
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cpp/bq79606.cpp@2:9ca50d384b62, 2020-12-21 (annotated)
- Committer:
- dragica
- Date:
- Mon Dec 21 14:20:29 2020 +0000
- Revision:
- 2:9ca50d384b62
- Parent:
- 1:6231121f9e19
Commit with the following error:; Incompatible redefinition of macro "MBED_RAM_SIZE" "#define MBED_RAM_SIZE 0x00018000"
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| dragica | 1:6231121f9e19 | 1 | #include "bq79606.h" |
| dragica | 1:6231121f9e19 | 2 | |
| dragica | 1:6231121f9e19 | 3 | extern int UART_RX_RDY; |
| dragica | 1:6231121f9e19 | 4 | extern int RTI_TIMEOUT; |
| dragica | 2:9ca50d384b62 | 5 | |
| dragica | 2:9ca50d384b62 | 6 | |
| dragica | 2:9ca50d384b62 | 7 | static volatile struct g_sciTransfer |
| dragica | 2:9ca50d384b62 | 8 | { |
| dragica | 2:9ca50d384b62 | 9 | uint32_t mode; /* Used to check for TX interrupt Enable */ |
| dragica | 2:9ca50d384b62 | 10 | uint32_t tx_length; /* Transmit data length in number of Bytes */ |
| dragica | 2:9ca50d384b62 | 11 | uint32_t rx_length; /* Receive data length in number of Bytes */ |
| dragica | 2:9ca50d384b62 | 12 | uint8_t * tx_data; /* Transmit data pointer */ |
| dragica | 2:9ca50d384b62 | 13 | uint8_t * rx_data; /* Receive data pointer */ |
| dragica | 2:9ca50d384b62 | 14 | } g_sciTransfer_t; |
| dragica | 2:9ca50d384b62 | 15 | |
| dragica | 2:9ca50d384b62 | 16 | |
| dragica | 1:6231121f9e19 | 17 | |
| dragica | 1:6231121f9e19 | 18 | //****** |
| dragica | 1:6231121f9e19 | 19 | //PINGS |
| dragica | 1:6231121f9e19 | 20 | //****** |
| dragica | 1:6231121f9e19 | 21 | |
| dragica | 1:6231121f9e19 | 22 | void CommClear(void) { |
| dragica | 1:6231121f9e19 | 23 | int baudRate; |
| dragica | 1:6231121f9e19 | 24 | baudRate = scilinREG->BRS; |
| dragica | 1:6231121f9e19 | 25 | |
| dragica | 1:6231121f9e19 | 26 | scilinREG->GCR1 &= ~(1U << 7U); // put SCI into reset |
| dragica | 1:6231121f9e19 | 27 | scilinREG->PIO0 &= ~(1U << 2U); // disable transmit function - now a GPIO |
| dragica | 1:6231121f9e19 | 28 | scilinREG->PIO3 &= ~(1U << 2U); // set output to low |
| dragica | 1:6231121f9e19 | 29 | |
| dragica | 2:9ca50d384b62 | 30 | wait_us(baudRate * 2); // ~= 1/BAUDRATE/16*(155+1)*1.01 |
| dragica | 1:6231121f9e19 | 31 | sciInit(); |
| dragica | 1:6231121f9e19 | 32 | sciSetBaudrate(scilinREG, BAUDRATE); |
| dragica | 1:6231121f9e19 | 33 | } |
| dragica | 1:6231121f9e19 | 34 | |
| dragica | 1:6231121f9e19 | 35 | void CommSleepToWake(void) { |
| dragica | 1:6231121f9e19 | 36 | scilinREG->GCR1 &= ~(1U << 7U); // put SCI into reset |
| dragica | 1:6231121f9e19 | 37 | scilinREG->PIO0 &= ~(1U << 2U); // disable transmit function - now a GPIO |
| dragica | 1:6231121f9e19 | 38 | scilinREG->PIO3 &= ~(1U << 2U); // set output to low |
| dragica | 1:6231121f9e19 | 39 | |
| dragica | 2:9ca50d384b62 | 40 | wait_us(250); // 250us to 300us, same as wake |
| dragica | 1:6231121f9e19 | 41 | sciInit(); |
| dragica | 1:6231121f9e19 | 42 | sciSetBaudrate(scilinREG, BAUDRATE); |
| dragica | 1:6231121f9e19 | 43 | } |
| dragica | 1:6231121f9e19 | 44 | |
| dragica | 1:6231121f9e19 | 45 | |
| dragica | 1:6231121f9e19 | 46 | void CommReset(void) { |
| dragica | 1:6231121f9e19 | 47 | scilinREG->GCR1 &= ~(1U << 7U); // put SCI into reset |
| dragica | 1:6231121f9e19 | 48 | scilinREG->PIO0 &= ~(1U << 2U); // disable transmit function - now a GPIO |
| dragica | 1:6231121f9e19 | 49 | scilinREG->PIO3 &= ~(1U << 2U); // set output to low |
| dragica | 1:6231121f9e19 | 50 | |
| dragica | 2:9ca50d384b62 | 51 | wait_us(500); // should cover any possible baud rate |
| dragica | 1:6231121f9e19 | 52 | sciInit(); |
| dragica | 1:6231121f9e19 | 53 | |
| dragica | 1:6231121f9e19 | 54 | //BASE DEVICE NOW AT 250K BAUDRATE, STACK DEVICES ARE WHATEVER BAUDRATE THEY WERE BEFORE |
| dragica | 1:6231121f9e19 | 55 | |
| dragica | 1:6231121f9e19 | 56 | //wait a bit just to make sure the microcontroller is ready |
| dragica | 2:9ca50d384b62 | 57 | wait_us(100); |
| dragica | 1:6231121f9e19 | 58 | |
| dragica | 1:6231121f9e19 | 59 | //set microcontroller to 250k to talk to base |
| dragica | 1:6231121f9e19 | 60 | sciSetBaudrate(scilinREG, 250000); |
| dragica | 1:6231121f9e19 | 61 | |
| dragica | 1:6231121f9e19 | 62 | //tell the base device to set its baudrate to the chosen BAUDRATE, and propagate to the rest of the stack |
| dragica | 1:6231121f9e19 | 63 | //then set the microcontroller to the appropriate baudrate to match |
| dragica | 1:6231121f9e19 | 64 | if(BAUDRATE == 1000000) |
| dragica | 1:6231121f9e19 | 65 | { |
| dragica | 1:6231121f9e19 | 66 | //set COMM_CTRL and DAISY_CHAIN_CTRL registers |
| dragica | 1:6231121f9e19 | 67 | WriteReg(0, COMM_CTRL, 0x3C3C, 2, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 68 | |
| dragica | 1:6231121f9e19 | 69 | //ALL 606 DEVICES ARE NOW AT 1M BAUDRATE |
| dragica | 1:6231121f9e19 | 70 | |
| dragica | 1:6231121f9e19 | 71 | //set the microcontroller to 1M baudrate |
| dragica | 1:6231121f9e19 | 72 | sciSetBaudrate(scilinREG, 1000000); |
| dragica | 1:6231121f9e19 | 73 | } |
| dragica | 1:6231121f9e19 | 74 | else if(BAUDRATE == 500000) |
| dragica | 1:6231121f9e19 | 75 | { |
| dragica | 1:6231121f9e19 | 76 | WriteReg(0, COMM_CTRL, 0x383C, 2, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 77 | sciSetBaudrate(scilinREG, 500000); |
| dragica | 1:6231121f9e19 | 78 | } |
| dragica | 1:6231121f9e19 | 79 | else if(BAUDRATE == 250000) |
| dragica | 1:6231121f9e19 | 80 | { |
| dragica | 1:6231121f9e19 | 81 | WriteReg(0, COMM_CTRL, 0x343C, 2, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 82 | sciSetBaudrate(scilinREG, 250000); |
| dragica | 1:6231121f9e19 | 83 | } |
| dragica | 1:6231121f9e19 | 84 | else if(BAUDRATE == 125000) |
| dragica | 1:6231121f9e19 | 85 | { |
| dragica | 1:6231121f9e19 | 86 | WriteReg(0, COMM_CTRL, 0x303C, 2, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 87 | sciSetBaudrate(scilinREG, 125000); |
| dragica | 1:6231121f9e19 | 88 | } |
| dragica | 1:6231121f9e19 | 89 | else |
| dragica | 1:6231121f9e19 | 90 | { |
| dragica | 1:6231121f9e19 | 91 | printf("ERROR: INVALID BAUDRATE CHOSEN IN BQ79606.h FILE. Choosing default 1M baudrate:\n\n"); |
| dragica | 1:6231121f9e19 | 92 | WriteReg(0, COMM_CTRL, 0x3C3C, 2, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 93 | sciSetBaudrate(scilinREG, 1000000); |
| dragica | 1:6231121f9e19 | 94 | } |
| dragica | 1:6231121f9e19 | 95 | |
| dragica | 2:9ca50d384b62 | 96 | wait_us(100); |
| dragica | 1:6231121f9e19 | 97 | } |
| dragica | 1:6231121f9e19 | 98 | //********** |
| dragica | 1:6231121f9e19 | 99 | //END PINGS |
| dragica | 1:6231121f9e19 | 100 | //********** |
| dragica | 1:6231121f9e19 | 101 | |
| dragica | 1:6231121f9e19 | 102 | |
| dragica | 1:6231121f9e19 | 103 | //********************** |
| dragica | 1:6231121f9e19 | 104 | //AUTO ADDRESS SEQUENCE |
| dragica | 1:6231121f9e19 | 105 | //********************** |
| dragica | 1:6231121f9e19 | 106 | void AutoAddress() |
| dragica | 1:6231121f9e19 | 107 | { |
| dragica | 1:6231121f9e19 | 108 | memset(response_frame2,0,sizeof(response_frame2)); //clear out the response frame buffer |
| dragica | 1:6231121f9e19 | 109 | |
| dragica | 1:6231121f9e19 | 110 | //dummy write to ECC_TEST (sync DLL) |
| dragica | 1:6231121f9e19 | 111 | WriteReg(0, ECC_TEST, 0x00, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 112 | |
| dragica | 1:6231121f9e19 | 113 | //clear CONFIG in case it is set |
| dragica | 1:6231121f9e19 | 114 | WriteReg(0, CONFIG, 0x00, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 115 | |
| dragica | 1:6231121f9e19 | 116 | //enter auto addressing mode |
| dragica | 1:6231121f9e19 | 117 | WriteReg(0, CONTROL1, 0x01, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 118 | |
| dragica | 1:6231121f9e19 | 119 | //set addresses for all boards in daisy-chain |
| dragica | 1:6231121f9e19 | 120 | for (nCurrentBoard = 0; nCurrentBoard < TOTALBOARDS; nCurrentBoard++) |
| dragica | 1:6231121f9e19 | 121 | { |
| dragica | 1:6231121f9e19 | 122 | WriteReg(nCurrentBoard, DEVADD_USR, nCurrentBoard, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 123 | } |
| dragica | 1:6231121f9e19 | 124 | |
| dragica | 1:6231121f9e19 | 125 | //set all devices as a stack device |
| dragica | 1:6231121f9e19 | 126 | WriteReg(0, CONFIG, 0x02, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 127 | |
| dragica | 1:6231121f9e19 | 128 | //if there's only 1 board, it's the base AND the top of stack, so change it to those |
| dragica | 1:6231121f9e19 | 129 | if(TOTALBOARDS==1) |
| dragica | 1:6231121f9e19 | 130 | { |
| dragica | 1:6231121f9e19 | 131 | WriteReg(0, CONFIG, 0x01, 1, FRMWRT_SGL_NR); |
| dragica | 1:6231121f9e19 | 132 | } |
| dragica | 1:6231121f9e19 | 133 | //otherwise set the base and top of stack individually |
| dragica | 1:6231121f9e19 | 134 | else |
| dragica | 1:6231121f9e19 | 135 | { |
| dragica | 1:6231121f9e19 | 136 | WriteReg(0, CONFIG, 0x00, 1, FRMWRT_SGL_NR); //base |
| dragica | 1:6231121f9e19 | 137 | WriteReg(TOTALBOARDS-1, CONFIG, 0x03, 1, FRMWRT_SGL_NR); //top of stack |
| dragica | 1:6231121f9e19 | 138 | } |
| dragica | 1:6231121f9e19 | 139 | |
| dragica | 1:6231121f9e19 | 140 | //dummy read from ECC_TEST (sync DLL) |
| dragica | 1:6231121f9e19 | 141 | ReadReg(TOTALBOARDS-1, ECC_TEST, response_frame2, 1, 0, FRMWRT_ALL_R); |
| dragica | 1:6231121f9e19 | 142 | |
| dragica | 1:6231121f9e19 | 143 | // //OPTIONAL: read back all device addresses |
| dragica | 1:6231121f9e19 | 144 | // WriteReg(0, COMM_TO, 0x00, 1, FRMWRT_ALL_NR); //Disable communication timeout because printf takes a long time |
| dragica | 1:6231121f9e19 | 145 | // for (nCurrentBoard = 0; nCurrentBoard < TOTALBOARDS; nCurrentBoard++) { |
| dragica | 1:6231121f9e19 | 146 | // memset(response_frame2, 0, sizeof(response_frame2)); |
| dragica | 1:6231121f9e19 | 147 | // ReadReg(nCurrentBoard, DEVADD_USR, response_frame2, 1, 0, FRMWRT_SGL_R); |
| dragica | 1:6231121f9e19 | 148 | // printf("Board %d=%02x\n",nCurrentBoard,response_frame2[4]); |
| dragica | 1:6231121f9e19 | 149 | // } |
| dragica | 1:6231121f9e19 | 150 | } |
| dragica | 1:6231121f9e19 | 151 | //************************** |
| dragica | 1:6231121f9e19 | 152 | //END AUTO ADDRESS SEQUENCE |
| dragica | 1:6231121f9e19 | 153 | //************************** |
| dragica | 1:6231121f9e19 | 154 | |
| dragica | 1:6231121f9e19 | 155 | |
| dragica | 1:6231121f9e19 | 156 | //************************ |
| dragica | 1:6231121f9e19 | 157 | //WRITE AND READ FUNCTIONS |
| dragica | 1:6231121f9e19 | 158 | //************************ |
| dragica | 2:9ca50d384b62 | 159 | int WriteReg(BYTE bID, uint16_t wAddr, uint64_t dwData, BYTE bLen, BYTE bWriteType) { |
| dragica | 1:6231121f9e19 | 160 | // device address, register start address, data bytes, data length, write type (single, broadcast, stack) |
| dragica | 1:6231121f9e19 | 161 | bRes = 0; |
| dragica | 1:6231121f9e19 | 162 | memset(bBuf,0,sizeof(bBuf)); |
| dragica | 1:6231121f9e19 | 163 | switch (bLen) { |
| dragica | 1:6231121f9e19 | 164 | case 1: |
| dragica | 1:6231121f9e19 | 165 | bBuf[0] = dwData & 0x00000000000000FF; |
| dragica | 1:6231121f9e19 | 166 | bRes = WriteFrame(bID, wAddr, bBuf, 1, bWriteType); |
| dragica | 1:6231121f9e19 | 167 | break; |
| dragica | 1:6231121f9e19 | 168 | case 2: |
| dragica | 1:6231121f9e19 | 169 | bBuf[0] = (dwData & 0x000000000000FF00) >> 8; |
| dragica | 1:6231121f9e19 | 170 | bBuf[1] = dwData & 0x00000000000000FF; |
| dragica | 1:6231121f9e19 | 171 | bRes = WriteFrame(bID, wAddr, bBuf, 2, bWriteType); |
| dragica | 1:6231121f9e19 | 172 | break; |
| dragica | 1:6231121f9e19 | 173 | case 3: |
| dragica | 1:6231121f9e19 | 174 | bBuf[0] = (dwData & 0x0000000000FF0000) >> 16; |
| dragica | 1:6231121f9e19 | 175 | bBuf[1] = (dwData & 0x000000000000FF00) >> 8; |
| dragica | 1:6231121f9e19 | 176 | bBuf[2] = dwData & 0x00000000000000FF; |
| dragica | 1:6231121f9e19 | 177 | bRes = WriteFrame(bID, wAddr, bBuf, 3, bWriteType); |
| dragica | 1:6231121f9e19 | 178 | break; |
| dragica | 1:6231121f9e19 | 179 | case 4: |
| dragica | 1:6231121f9e19 | 180 | bBuf[0] = (dwData & 0x00000000FF000000) >> 24; |
| dragica | 1:6231121f9e19 | 181 | bBuf[1] = (dwData & 0x0000000000FF0000) >> 16; |
| dragica | 1:6231121f9e19 | 182 | bBuf[2] = (dwData & 0x000000000000FF00) >> 8; |
| dragica | 1:6231121f9e19 | 183 | bBuf[3] = dwData & 0x00000000000000FF; |
| dragica | 1:6231121f9e19 | 184 | bRes = WriteFrame(bID, wAddr, bBuf, 4, bWriteType); |
| dragica | 1:6231121f9e19 | 185 | break; |
| dragica | 1:6231121f9e19 | 186 | case 5: |
| dragica | 1:6231121f9e19 | 187 | bBuf[0] = (dwData & 0x000000FF00000000) >> 32; |
| dragica | 1:6231121f9e19 | 188 | bBuf[1] = (dwData & 0x00000000FF000000) >> 24; |
| dragica | 1:6231121f9e19 | 189 | bBuf[2] = (dwData & 0x0000000000FF0000) >> 16; |
| dragica | 1:6231121f9e19 | 190 | bBuf[3] = (dwData & 0x000000000000FF00) >> 8; |
| dragica | 1:6231121f9e19 | 191 | bBuf[4] = dwData & 0x00000000000000FF; |
| dragica | 1:6231121f9e19 | 192 | bRes = WriteFrame(bID, wAddr, bBuf, 5, bWriteType); |
| dragica | 1:6231121f9e19 | 193 | break; |
| dragica | 1:6231121f9e19 | 194 | case 6: |
| dragica | 1:6231121f9e19 | 195 | bBuf[0] = (dwData & 0x0000FF0000000000) >> 40; |
| dragica | 1:6231121f9e19 | 196 | bBuf[1] = (dwData & 0x000000FF00000000) >> 32; |
| dragica | 1:6231121f9e19 | 197 | bBuf[2] = (dwData & 0x00000000FF000000) >> 24; |
| dragica | 1:6231121f9e19 | 198 | bBuf[3] = (dwData & 0x0000000000FF0000) >> 16; |
| dragica | 1:6231121f9e19 | 199 | bBuf[4] = (dwData & 0x000000000000FF00) >> 8; |
| dragica | 1:6231121f9e19 | 200 | bBuf[5] = dwData & 0x00000000000000FF; |
| dragica | 1:6231121f9e19 | 201 | bRes = WriteFrame(bID, wAddr, bBuf, 6, bWriteType); |
| dragica | 1:6231121f9e19 | 202 | break; |
| dragica | 1:6231121f9e19 | 203 | case 7: |
| dragica | 1:6231121f9e19 | 204 | bBuf[0] = (dwData & 0x00FF000000000000) >> 48; |
| dragica | 1:6231121f9e19 | 205 | bBuf[1] = (dwData & 0x0000FF0000000000) >> 40; |
| dragica | 1:6231121f9e19 | 206 | bBuf[2] = (dwData & 0x000000FF00000000) >> 32; |
| dragica | 1:6231121f9e19 | 207 | bBuf[3] = (dwData & 0x00000000FF000000) >> 24; |
| dragica | 1:6231121f9e19 | 208 | bBuf[4] = (dwData & 0x0000000000FF0000) >> 16; |
| dragica | 1:6231121f9e19 | 209 | bBuf[5] = (dwData & 0x000000000000FF00) >> 8; |
| dragica | 1:6231121f9e19 | 210 | bBuf[6] = dwData & 0x00000000000000FF; |
| dragica | 1:6231121f9e19 | 211 | bRes = WriteFrame(bID, wAddr, bBuf, 7, bWriteType); |
| dragica | 1:6231121f9e19 | 212 | break; |
| dragica | 1:6231121f9e19 | 213 | case 8: |
| dragica | 1:6231121f9e19 | 214 | bBuf[0] = (dwData & 0xFF00000000000000) >> 56; |
| dragica | 1:6231121f9e19 | 215 | bBuf[1] = (dwData & 0x00FF000000000000) >> 48; |
| dragica | 1:6231121f9e19 | 216 | bBuf[2] = (dwData & 0x0000FF0000000000) >> 40; |
| dragica | 1:6231121f9e19 | 217 | bBuf[3] = (dwData & 0x000000FF00000000) >> 32; |
| dragica | 1:6231121f9e19 | 218 | bBuf[4] = (dwData & 0x00000000FF000000) >> 24; |
| dragica | 1:6231121f9e19 | 219 | bBuf[5] = (dwData & 0x0000000000FF0000) >> 16; |
| dragica | 1:6231121f9e19 | 220 | bBuf[6] = (dwData & 0x000000000000FF00) >> 8; |
| dragica | 1:6231121f9e19 | 221 | bBuf[7] = dwData & 0x00000000000000FF; |
| dragica | 1:6231121f9e19 | 222 | bRes = WriteFrame(bID, wAddr, bBuf, 8, bWriteType); |
| dragica | 1:6231121f9e19 | 223 | break; |
| dragica | 1:6231121f9e19 | 224 | default: |
| dragica | 1:6231121f9e19 | 225 | break; |
| dragica | 1:6231121f9e19 | 226 | } |
| dragica | 1:6231121f9e19 | 227 | return bRes; |
| dragica | 1:6231121f9e19 | 228 | } |
| dragica | 1:6231121f9e19 | 229 | |
| dragica | 2:9ca50d384b62 | 230 | int WriteFrame(BYTE bID, uint16_t wAddr, BYTE * pData, BYTE bLen, BYTE bWriteType) { |
| dragica | 1:6231121f9e19 | 231 | int bPktLen = 0; |
| dragica | 2:9ca50d384b62 | 232 | uint8_t * pBuf = pFrame; |
| dragica | 2:9ca50d384b62 | 233 | uint16_t wCRC; |
| dragica | 1:6231121f9e19 | 234 | memset(pFrame, 0x7F, sizeof(pFrame)); |
| dragica | 1:6231121f9e19 | 235 | *pBuf++ = 0x80 | (bWriteType) | ((bWriteType & 0x10) ? bLen - 0x01 : 0x00); //Only include blen if it is a write; Writes are 0x90, 0xB0, 0xD0 |
| dragica | 1:6231121f9e19 | 236 | if (bWriteType == FRMWRT_SGL_R || bWriteType == FRMWRT_SGL_NR) |
| dragica | 1:6231121f9e19 | 237 | { |
| dragica | 1:6231121f9e19 | 238 | *pBuf++ = (bID & 0x00FF); |
| dragica | 1:6231121f9e19 | 239 | } |
| dragica | 1:6231121f9e19 | 240 | *pBuf++ = (wAddr & 0xFF00) >> 8; |
| dragica | 1:6231121f9e19 | 241 | *pBuf++ = wAddr & 0x00FF; |
| dragica | 1:6231121f9e19 | 242 | |
| dragica | 1:6231121f9e19 | 243 | while (bLen--) |
| dragica | 1:6231121f9e19 | 244 | *pBuf++ = *pData++; |
| dragica | 1:6231121f9e19 | 245 | |
| dragica | 1:6231121f9e19 | 246 | bPktLen = pBuf - pFrame; |
| dragica | 1:6231121f9e19 | 247 | |
| dragica | 1:6231121f9e19 | 248 | wCRC = CRC16(pFrame, bPktLen); |
| dragica | 1:6231121f9e19 | 249 | *pBuf++ = wCRC & 0x00FF; |
| dragica | 1:6231121f9e19 | 250 | *pBuf++ = (wCRC & 0xFF00) >> 8; |
| dragica | 1:6231121f9e19 | 251 | bPktLen += 2; |
| dragica | 1:6231121f9e19 | 252 | |
| dragica | 1:6231121f9e19 | 253 | return bPktLen; |
| dragica | 1:6231121f9e19 | 254 | } |
| dragica | 1:6231121f9e19 | 255 | |
| dragica | 2:9ca50d384b62 | 256 | /*int ReadReg(BYTE bID, uint16_t wAddr, BYTE * pData, BYTE bLen, uint32_t dwTimeOut, |
| dragica | 1:6231121f9e19 | 257 | BYTE bWriteType) { |
| dragica | 1:6231121f9e19 | 258 | bRes = 0; |
| dragica | 2:9ca50d384b62 | 259 | int count = 100000; |
| dragica | 1:6231121f9e19 | 260 | if (bWriteType == FRMWRT_SGL_R) { |
| dragica | 1:6231121f9e19 | 261 | ReadFrameReq(bID, wAddr, bLen, bWriteType); |
| dragica | 1:6231121f9e19 | 262 | memset(pData, 0, sizeof(pData)); |
| dragica | 1:6231121f9e19 | 263 | sciEnableNotification(scilinREG, SCI_RX_INT); |
| dragica | 1:6231121f9e19 | 264 | sciReceive(scilinREG, bLen + 6, pData); |
| dragica | 2:9ca50d384b62 | 265 | while(UART_RX_RDY == 0U && count>0) count--; //wait |
| dragica | 1:6231121f9e19 | 266 | //if(count == 0) printf("COUNT REACHED 0\n"); |
| dragica | 1:6231121f9e19 | 267 | UART_RX_RDY = 0; |
| dragica | 1:6231121f9e19 | 268 | bRes = bLen + 6; |
| dragica | 1:6231121f9e19 | 269 | } else if (bWriteType == FRMWRT_STK_R) { |
| dragica | 1:6231121f9e19 | 270 | bRes = ReadFrameReq(bID, wAddr, bLen, bWriteType); |
| dragica | 1:6231121f9e19 | 271 | memset(pData, 0, sizeof(pData)); |
| dragica | 1:6231121f9e19 | 272 | sciEnableNotification(scilinREG, SCI_RX_INT); |
| dragica | 1:6231121f9e19 | 273 | sciReceive(scilinREG, (bLen + 6) * (TOTALBOARDS - 1), pData); |
| dragica | 2:9ca50d384b62 | 274 | while(UART_RX_RDY == 0U && count>0) count--; //wait |
| dragica | 1:6231121f9e19 | 275 | UART_RX_RDY = 0; |
| dragica | 1:6231121f9e19 | 276 | bRes = (bLen + 6) * (TOTALBOARDS - 1); |
| dragica | 1:6231121f9e19 | 277 | } else if (bWriteType == FRMWRT_ALL_R) { |
| dragica | 1:6231121f9e19 | 278 | bRes = ReadFrameReq(bID, wAddr, bLen, bWriteType); |
| dragica | 1:6231121f9e19 | 279 | memset(pData, 0, sizeof(pData)); |
| dragica | 1:6231121f9e19 | 280 | sciEnableNotification(scilinREG, SCI_RX_INT); |
| dragica | 1:6231121f9e19 | 281 | sciReceive(scilinREG, (bLen + 6) * TOTALBOARDS, pData); |
| dragica | 2:9ca50d384b62 | 282 | while(UART_RX_RDY == 0U && count>0) count--; //wait |
| dragica | 1:6231121f9e19 | 283 | UART_RX_RDY = 0; |
| dragica | 1:6231121f9e19 | 284 | bRes = (bLen + 6) * TOTALBOARDS; |
| dragica | 1:6231121f9e19 | 285 | } else { |
| dragica | 1:6231121f9e19 | 286 | bRes = 0; |
| dragica | 1:6231121f9e19 | 287 | } |
| dragica | 1:6231121f9e19 | 288 | return bRes; |
| dragica | 2:9ca50d384b62 | 289 | }*/ |
| dragica | 1:6231121f9e19 | 290 | |
| dragica | 2:9ca50d384b62 | 291 | int ReadFrameReq(BYTE bID, uint16_t wAddr, BYTE bByteToReturn, BYTE bWriteType) { |
| dragica | 1:6231121f9e19 | 292 | bReturn = bByteToReturn - 1; |
| dragica | 1:6231121f9e19 | 293 | |
| dragica | 1:6231121f9e19 | 294 | if (bReturn > 127) |
| dragica | 1:6231121f9e19 | 295 | return 0; |
| dragica | 1:6231121f9e19 | 296 | |
| dragica | 1:6231121f9e19 | 297 | return WriteFrame(bID, wAddr, &bReturn, 1, bWriteType); |
| dragica | 1:6231121f9e19 | 298 | } |
| dragica | 1:6231121f9e19 | 299 | |
| dragica | 1:6231121f9e19 | 300 | // CRC16 TABLE |
| dragica | 1:6231121f9e19 | 301 | // ITU_T polynomial: x^16 + x^15 + x^2 + 1 |
| dragica | 2:9ca50d384b62 | 302 | const uint16_t crc16_table[256] = { 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, |
| dragica | 1:6231121f9e19 | 303 | 0x03C0, 0x0280, 0xC241, 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, |
| dragica | 1:6231121f9e19 | 304 | 0xC481, 0x0440, 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, |
| dragica | 1:6231121f9e19 | 305 | 0x0E40, 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841, |
| dragica | 1:6231121f9e19 | 306 | 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40, 0x1E00, |
| dragica | 1:6231121f9e19 | 307 | 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41, 0x1400, 0xD4C1, |
| dragica | 1:6231121f9e19 | 308 | 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641, 0xD201, 0x12C0, 0x1380, |
| dragica | 1:6231121f9e19 | 309 | 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040, 0xF001, 0x30C0, 0x3180, 0xF141, |
| dragica | 1:6231121f9e19 | 310 | 0x3300, 0xF3C1, 0xF281, 0x3240, 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, |
| dragica | 1:6231121f9e19 | 311 | 0x35C0, 0x3480, 0xF441, 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, |
| dragica | 1:6231121f9e19 | 312 | 0x3E80, 0xFE41, 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, |
| dragica | 1:6231121f9e19 | 313 | 0x3840, 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41, |
| dragica | 1:6231121f9e19 | 314 | 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40, 0xE401, |
| dragica | 1:6231121f9e19 | 315 | 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640, 0x2200, 0xE2C1, |
| dragica | 1:6231121f9e19 | 316 | 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041, 0xA001, 0x60C0, 0x6180, |
| dragica | 1:6231121f9e19 | 317 | 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240, 0x6600, 0xA6C1, 0xA781, 0x6740, |
| dragica | 1:6231121f9e19 | 318 | 0xA501, 0x65C0, 0x6480, 0xA441, 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, |
| dragica | 1:6231121f9e19 | 319 | 0x6FC0, 0x6E80, 0xAE41, 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, |
| dragica | 1:6231121f9e19 | 320 | 0xA881, 0x6840, 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, |
| dragica | 1:6231121f9e19 | 321 | 0xBA41, 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40, |
| dragica | 1:6231121f9e19 | 322 | 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640, 0x7200, |
| dragica | 1:6231121f9e19 | 323 | 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041, 0x5000, 0x90C1, |
| dragica | 1:6231121f9e19 | 324 | 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241, 0x9601, 0x56C0, 0x5780, |
| dragica | 1:6231121f9e19 | 325 | 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440, 0x9C01, 0x5CC0, 0x5D80, 0x9D41, |
| dragica | 1:6231121f9e19 | 326 | 0x5F00, 0x9FC1, 0x9E81, 0x5E40, 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, |
| dragica | 1:6231121f9e19 | 327 | 0x59C0, 0x5880, 0x9841, 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, |
| dragica | 1:6231121f9e19 | 328 | 0x8A81, 0x4A40, 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, |
| dragica | 1:6231121f9e19 | 329 | 0x8C41, 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641, |
| dragica | 1:6231121f9e19 | 330 | 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040 }; |
| dragica | 1:6231121f9e19 | 331 | |
| dragica | 2:9ca50d384b62 | 332 | uint16_t CRC16(BYTE *pBuf, int nLen) { |
| dragica | 2:9ca50d384b62 | 333 | uint16_t wCRC = 0xFFFF; |
| dragica | 1:6231121f9e19 | 334 | int i; |
| dragica | 1:6231121f9e19 | 335 | |
| dragica | 1:6231121f9e19 | 336 | for (i = 0; i < nLen; i++) { |
| dragica | 1:6231121f9e19 | 337 | wCRC ^= (*pBuf++) & 0x00FF; |
| dragica | 1:6231121f9e19 | 338 | wCRC = crc16_table[wCRC & 0x00FF] ^ (wCRC >> 8); |
| dragica | 1:6231121f9e19 | 339 | } |
| dragica | 1:6231121f9e19 | 340 | |
| dragica | 1:6231121f9e19 | 341 | return wCRC; |
| dragica | 1:6231121f9e19 | 342 | } |
| dragica | 1:6231121f9e19 | 343 | //**************************** |
| dragica | 1:6231121f9e19 | 344 | //END WRITE AND READ FUNCTIONS |
| dragica | 1:6231121f9e19 | 345 | //**************************** |
| dragica | 1:6231121f9e19 | 346 | |
| dragica | 1:6231121f9e19 | 347 | //************************ |
| dragica | 1:6231121f9e19 | 348 | //MISCELLANEOUS FUNCTIONS |
| dragica | 1:6231121f9e19 | 349 | //************************ |
| dragica | 2:9ca50d384b62 | 350 | /*void wait_us(uint16_t us) { |
| dragica | 1:6231121f9e19 | 351 | if (us == 0) |
| dragica | 1:6231121f9e19 | 352 | return; |
| dragica | 1:6231121f9e19 | 353 | else |
| dragica | 1:6231121f9e19 | 354 | { |
| dragica | 1:6231121f9e19 | 355 | //CHANGE THE INTERRUPT COMPARE VALUES (PERIOD OF INTERRUPT) |
| dragica | 1:6231121f9e19 | 356 | //Setup compare 0 value. |
| dragica | 1:6231121f9e19 | 357 | rtiREG1->CMP[0U].COMPx = 10*us; //10 ticks of clock per microsecond, so multiply by 10 |
| dragica | 1:6231121f9e19 | 358 | //Setup update compare 0 value. |
| dragica | 1:6231121f9e19 | 359 | rtiREG1->CMP[0U].UDCPx = 10*us; |
| dragica | 1:6231121f9e19 | 360 | |
| dragica | 1:6231121f9e19 | 361 | //ENABLE THE NOTIFICATION FOR THE PERIOD WE SET |
| dragica | 1:6231121f9e19 | 362 | rtiEnableNotification(rtiNOTIFICATION_COMPARE0); |
| dragica | 1:6231121f9e19 | 363 | |
| dragica | 1:6231121f9e19 | 364 | //START THE COUNTER |
| dragica | 1:6231121f9e19 | 365 | rtiStartCounter(rtiCOUNTER_BLOCK0); |
| dragica | 1:6231121f9e19 | 366 | |
| dragica | 1:6231121f9e19 | 367 | //WAIT IN LOOP UNTIL THE INTERRUPT HAPPENS (HAPPENS AFTER THE PERIOD WE SET) |
| dragica | 1:6231121f9e19 | 368 | //WHEN INTERRUPT HAPPENS, RTI_NOTIFICATION GETS SET TO 1 IN THAT INTERRUPT |
| dragica | 1:6231121f9e19 | 369 | //GO TO notification.c -> rtiNotification() to see where RTI_TIMEOUT is set to 1 |
| dragica | 1:6231121f9e19 | 370 | while(RTI_TIMEOUT==0); |
| dragica | 1:6231121f9e19 | 371 | |
| dragica | 1:6231121f9e19 | 372 | //RESET THE VARIABLE TO 0, FOR THE NEXT TIME WE DO A DELAY |
| dragica | 1:6231121f9e19 | 373 | RTI_TIMEOUT = 0; |
| dragica | 1:6231121f9e19 | 374 | |
| dragica | 1:6231121f9e19 | 375 | //DISABLE THE INTERRUPT NOTIFICATION |
| dragica | 1:6231121f9e19 | 376 | rtiDisableNotification(rtiNOTIFICATION_COMPARE0); |
| dragica | 1:6231121f9e19 | 377 | |
| dragica | 1:6231121f9e19 | 378 | //STOP THE COUNTER |
| dragica | 1:6231121f9e19 | 379 | rtiStopCounter(rtiCOUNTER_BLOCK0); |
| dragica | 1:6231121f9e19 | 380 | |
| dragica | 1:6231121f9e19 | 381 | //RESET COUNTER FOR THE NEXT TIME WE DO A DELAY |
| dragica | 1:6231121f9e19 | 382 | rtiResetCounter(rtiCOUNTER_BLOCK0); |
| dragica | 1:6231121f9e19 | 383 | } |
| dragica | 2:9ca50d384b62 | 384 | }*/ |
| dragica | 1:6231121f9e19 | 385 | |
| dragica | 2:9ca50d384b62 | 386 | /*void delayms(uint16_t ms) { |
| dragica | 1:6231121f9e19 | 387 | if (ms == 0) |
| dragica | 1:6231121f9e19 | 388 | return; |
| dragica | 1:6231121f9e19 | 389 | else |
| dragica | 1:6231121f9e19 | 390 | { |
| dragica | 1:6231121f9e19 | 391 | rtiREG1->CMP[0U].COMPx = 10000*ms; |
| dragica | 1:6231121f9e19 | 392 | rtiREG1->CMP[0U].UDCPx = 10000*ms; |
| dragica | 1:6231121f9e19 | 393 | rtiEnableNotification(rtiNOTIFICATION_COMPARE0); |
| dragica | 1:6231121f9e19 | 394 | rtiStartCounter(rtiCOUNTER_BLOCK0); |
| dragica | 1:6231121f9e19 | 395 | while(RTI_TIMEOUT==0); |
| dragica | 1:6231121f9e19 | 396 | RTI_TIMEOUT = 0; |
| dragica | 1:6231121f9e19 | 397 | rtiDisableNotification(rtiNOTIFICATION_COMPARE0); |
| dragica | 1:6231121f9e19 | 398 | rtiStopCounter(rtiCOUNTER_BLOCK0); |
| dragica | 1:6231121f9e19 | 399 | rtiResetCounter(rtiCOUNTER_BLOCK0); |
| dragica | 1:6231121f9e19 | 400 | } |
| dragica | 2:9ca50d384b62 | 401 | }*/ |
| dragica | 2:9ca50d384b62 | 402 | /* |
| dragica | 1:6231121f9e19 | 403 | float Complement(uint16 rawData, float multiplier) |
| dragica | 1:6231121f9e19 | 404 | { |
| dragica | 1:6231121f9e19 | 405 | return -1*(~rawData+1)*multiplier; |
| dragica | 1:6231121f9e19 | 406 | } |
| dragica | 1:6231121f9e19 | 407 | |
| dragica | 1:6231121f9e19 | 408 | BOOL GetFaultStat() { |
| dragica | 1:6231121f9e19 | 409 | |
| dragica | 1:6231121f9e19 | 410 | if (!gioGetBit(gioPORTA, 1)) |
| dragica | 1:6231121f9e19 | 411 | return 0; |
| dragica | 1:6231121f9e19 | 412 | return 1; |
| dragica | 2:9ca50d384b62 | 413 | }*/ |
| dragica | 2:9ca50d384b62 | 414 | |
| dragica | 2:9ca50d384b62 | 415 | void sciInit(void) |
| dragica | 2:9ca50d384b62 | 416 | { |
| dragica | 2:9ca50d384b62 | 417 | /* USER CODE BEGIN (2) */ |
| dragica | 2:9ca50d384b62 | 418 | /* USER CODE END */ |
| dragica | 2:9ca50d384b62 | 419 | |
| dragica | 2:9ca50d384b62 | 420 | /** @b initialize @b SCILIN */ |
| dragica | 2:9ca50d384b62 | 421 | |
| dragica | 2:9ca50d384b62 | 422 | /** - bring SCI out of reset */ |
| dragica | 2:9ca50d384b62 | 423 | scilinREG->GCR0 = 0U; |
| dragica | 2:9ca50d384b62 | 424 | scilinREG->GCR0 = 1U; |
| dragica | 2:9ca50d384b62 | 425 | |
| dragica | 2:9ca50d384b62 | 426 | /** - Disable all interrupts */ |
| dragica | 2:9ca50d384b62 | 427 | scilinREG->CLEARINT = 0xFFFFFFFFU; |
| dragica | 2:9ca50d384b62 | 428 | scilinREG->CLEARINTLVL = 0xFFFFFFFFU; |
| dragica | 2:9ca50d384b62 | 429 | |
| dragica | 2:9ca50d384b62 | 430 | /** - global control 1 */ |
| dragica | 2:9ca50d384b62 | 431 | scilinREG->GCR1 = (uint32_t)((uint32_t)1U << 25U) /* enable transmit */ |
| dragica | 2:9ca50d384b62 | 432 | | (uint32_t)((uint32_t)1U << 24U) /* enable receive */ |
| dragica | 2:9ca50d384b62 | 433 | | (uint32_t)((uint32_t)1U << 5U) /* internal clock (device has no clock pin) */ |
| dragica | 2:9ca50d384b62 | 434 | | (uint32_t)((uint32_t)(2U-1U) << 4U) /* number of stop bits */ |
| dragica | 2:9ca50d384b62 | 435 | | (uint32_t)((uint32_t)0U << 3U) /* even parity, otherwise odd */ |
| dragica | 2:9ca50d384b62 | 436 | | (uint32_t)((uint32_t)0U << 2U) /* enable parity */ |
| dragica | 2:9ca50d384b62 | 437 | | (uint32_t)((uint32_t)1U << 1U); /* asynchronous timing mode */ |
| dragica | 2:9ca50d384b62 | 438 | |
| dragica | 2:9ca50d384b62 | 439 | /** - set baudrate */ |
| dragica | 2:9ca50d384b62 | 440 | scilinREG->BRS = 4U; /* baudrate */ |
| dragica | 2:9ca50d384b62 | 441 | |
| dragica | 2:9ca50d384b62 | 442 | /** - transmission length */ |
| dragica | 2:9ca50d384b62 | 443 | scilinREG->FORMAT = 8U - 1U; /* length */ |
| dragica | 2:9ca50d384b62 | 444 | |
| dragica | 2:9ca50d384b62 | 445 | /** - set SCI pins functional mode */ |
| dragica | 2:9ca50d384b62 | 446 | scilinREG->PIO0 = (uint32_t)((uint32_t)1U << 2U) /* tx pin */ |
| dragica | 2:9ca50d384b62 | 447 | | (uint32_t)((uint32_t)1U << 1U); /* rx pin */ |
| dragica | 2:9ca50d384b62 | 448 | |
| dragica | 2:9ca50d384b62 | 449 | |
| dragica | 2:9ca50d384b62 | 450 | /** - set SCI pins default output value */ |
| dragica | 2:9ca50d384b62 | 451 | scilinREG->PIO3 = (uint32_t)((uint32_t)1U << 2U) /* tx pin */ |
| dragica | 2:9ca50d384b62 | 452 | | (uint32_t)((uint32_t)1U << 1U); /* rx pin */ |
| dragica | 2:9ca50d384b62 | 453 | |
| dragica | 2:9ca50d384b62 | 454 | |
| dragica | 2:9ca50d384b62 | 455 | /** - set SCI pins output direction */ |
| dragica | 2:9ca50d384b62 | 456 | scilinREG->PIO1 = (uint32_t)((uint32_t)1U << 2U) /* tx pin */ |
| dragica | 2:9ca50d384b62 | 457 | | (uint32_t)((uint32_t)0U << 1U); /* rx pin */ |
| dragica | 2:9ca50d384b62 | 458 | |
| dragica | 2:9ca50d384b62 | 459 | |
| dragica | 2:9ca50d384b62 | 460 | /** - set SCI pins open drain enable */ |
| dragica | 2:9ca50d384b62 | 461 | scilinREG->PIO6 = (uint32_t)((uint32_t)0U << 2U) /* tx pin */ |
| dragica | 2:9ca50d384b62 | 462 | | (uint32_t)((uint32_t)0U << 1U); /* rx pin */ |
| dragica | 2:9ca50d384b62 | 463 | |
| dragica | 2:9ca50d384b62 | 464 | |
| dragica | 2:9ca50d384b62 | 465 | /** - set SCI pins pullup/pulldown enable */ |
| dragica | 2:9ca50d384b62 | 466 | scilinREG->PIO7 = (uint32_t)((uint32_t)0U << 2U) /* tx pin */ |
| dragica | 2:9ca50d384b62 | 467 | | (uint32_t)((uint32_t)0U << 1U); /* rx pin */ |
| dragica | 2:9ca50d384b62 | 468 | |
| dragica | 2:9ca50d384b62 | 469 | |
| dragica | 2:9ca50d384b62 | 470 | /** - set SCI pins pullup/pulldown select */ |
| dragica | 2:9ca50d384b62 | 471 | scilinREG->PIO8 = (uint32_t)((uint32_t)1U << 2U) /* tx pin */ |
| dragica | 2:9ca50d384b62 | 472 | | (uint32_t)((uint32_t)1U << 1U); /* rx pin */ |
| dragica | 2:9ca50d384b62 | 473 | |
| dragica | 2:9ca50d384b62 | 474 | |
| dragica | 2:9ca50d384b62 | 475 | /** - set interrupt level */ |
| dragica | 2:9ca50d384b62 | 476 | scilinREG->SETINTLVL = (uint32_t)((uint32_t)0U << 26U) /* Framing error */ |
| dragica | 2:9ca50d384b62 | 477 | | (uint32_t)((uint32_t)0U << 25U) /* Overrun error */ |
| dragica | 2:9ca50d384b62 | 478 | | (uint32_t)((uint32_t)0U << 24U) /* Parity error */ |
| dragica | 2:9ca50d384b62 | 479 | | (uint32_t)((uint32_t)1U << 9U) /* Receive */ |
| dragica | 2:9ca50d384b62 | 480 | | (uint32_t)((uint32_t)1U << 8U) /* Transmit */ |
| dragica | 2:9ca50d384b62 | 481 | | (uint32_t)((uint32_t)0U << 1U) /* Wakeup */ |
| dragica | 2:9ca50d384b62 | 482 | | (uint32_t)((uint32_t)0U << 0U); /* Break detect */ |
| dragica | 2:9ca50d384b62 | 483 | |
| dragica | 2:9ca50d384b62 | 484 | /** - set interrupt enable */ |
| dragica | 2:9ca50d384b62 | 485 | scilinREG->SETINT = (uint32_t)((uint32_t)0U << 26U) /* Framing error */ |
| dragica | 2:9ca50d384b62 | 486 | | (uint32_t)((uint32_t)0U << 25U) /* Overrun error */ |
| dragica | 2:9ca50d384b62 | 487 | | (uint32_t)((uint32_t)0U << 24U) /* Parity error */ |
| dragica | 2:9ca50d384b62 | 488 | | (uint32_t)((uint32_t)1U << 9U) /* Receive */ |
| dragica | 2:9ca50d384b62 | 489 | | (uint32_t)((uint32_t)0U << 1U) /* Wakeup */ |
| dragica | 2:9ca50d384b62 | 490 | | (uint32_t)((uint32_t)0U); /* Break detect */ |
| dragica | 2:9ca50d384b62 | 491 | |
| dragica | 2:9ca50d384b62 | 492 | /** - initialize global transfer variables */ |
| dragica | 2:9ca50d384b62 | 493 | g_sciTransfer_t.mode = (uint32_t)0U << 8U; |
| dragica | 2:9ca50d384b62 | 494 | g_sciTransfer_t.tx_length = 0U; |
| dragica | 2:9ca50d384b62 | 495 | g_sciTransfer_t.rx_length = 0U; |
| dragica | 2:9ca50d384b62 | 496 | |
| dragica | 2:9ca50d384b62 | 497 | /** - Finaly start SCILIN */ |
| dragica | 2:9ca50d384b62 | 498 | scilinREG->GCR1 |= 0x80U; |
| dragica | 2:9ca50d384b62 | 499 | |
| dragica | 2:9ca50d384b62 | 500 | /* USER CODE BEGIN (3) */ |
| dragica | 2:9ca50d384b62 | 501 | /* USER CODE END */ |
| dragica | 1:6231121f9e19 | 502 | } |
| dragica | 1:6231121f9e19 | 503 | |
| dragica | 1:6231121f9e19 | 504 | void InitDevices() { |
| dragica | 1:6231121f9e19 | 505 | /*******Optional examples of some initialization functions*****/ |
| dragica | 1:6231121f9e19 | 506 | |
| dragica | 2:9ca50d384b62 | 507 | wait_ms(1); |
| dragica | 1:6231121f9e19 | 508 | WriteReg(0, COMM_TO, 0x00, 1, FRMWRT_ALL_NR); //Communication timeout disabled |
| dragica | 1:6231121f9e19 | 509 | WriteReg(0, TX_HOLD_OFF, 0x00, 1, FRMWRT_ALL_NR); //no transmit delay after stop bit |
| dragica | 1:6231121f9e19 | 510 | |
| dragica | 1:6231121f9e19 | 511 | /* mask all low level faults... user should unmask necessary faults */ |
| dragica | 1:6231121f9e19 | 512 | WriteReg(0, GPIO_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); //mask GPIO faults |
| dragica | 1:6231121f9e19 | 513 | WriteReg(0, UV_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); //mask UV faults |
| dragica | 1:6231121f9e19 | 514 | WriteReg(0, OV_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); //mask OV faults |
| dragica | 1:6231121f9e19 | 515 | WriteReg(0, UT_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); //mask UT faults |
| dragica | 1:6231121f9e19 | 516 | WriteReg(0, OT_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); //mask OT faults |
| dragica | 1:6231121f9e19 | 517 | WriteReg(0, TONE_FLT_MSK, 0x07, 1, FRMWRT_ALL_NR); //mask all tone faults |
| dragica | 1:6231121f9e19 | 518 | WriteReg(0, COMM_UART_FLT_MSK, 0x07, 1, FRMWRT_ALL_NR); //mask UART faults |
| dragica | 1:6231121f9e19 | 519 | WriteReg(0, COMM_UART_RC_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); //mask UART fault contd |
| dragica | 1:6231121f9e19 | 520 | WriteReg(0, COMM_UART_RR_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 521 | WriteReg(0, COMM_UART_TR_FLT_MSK, 0x03, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 522 | WriteReg(0, COMM_COMH_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 523 | WriteReg(0, COMM_COMH_RC_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 524 | WriteReg(0, COMM_COMH_RR_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 525 | WriteReg(0, COMM_COMH_TR_FLT_MSK, 0x03, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 526 | WriteReg(0, COMM_COML_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 527 | WriteReg(0, COMM_COML_RC_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 528 | WriteReg(0, COMM_COML_RR_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 529 | WriteReg(0, COMM_COML_TR_FLT_MSK, 0x03, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 530 | WriteReg(0, OTP_FLT_MSK, 0x07, 1, FRMWRT_ALL_NR); // mask otp faults |
| dragica | 1:6231121f9e19 | 531 | WriteReg(0, RAIL_FLT_MSK, 0xFF, 1, FRMWRT_ALL_NR); //mask power rail faults |
| dragica | 1:6231121f9e19 | 532 | WriteReg(0, SYSFLT1_FLT_MSK, 0x7F, 1, FRMWRT_ALL_NR); //sys fault mask 1 |
| dragica | 1:6231121f9e19 | 533 | WriteReg(0, SYSFLT2_FLT_MSK, 0xFF, 1, FRMWRT_ALL_NR); //sys fault mask 2 |
| dragica | 1:6231121f9e19 | 534 | WriteReg(0, SYSFLT3_FLT_MSK, 0x7F, 1, FRMWRT_ALL_NR); //sys fault mask 3 |
| dragica | 1:6231121f9e19 | 535 | WriteReg(0, OVUV_BIST_FLT_MSK, 0x03, 1, FRMWRT_ALL_NR); //mask ov/uv bist faults |
| dragica | 1:6231121f9e19 | 536 | WriteReg(0, OTUT_BIST_FLT_MSK, 0xFF, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 537 | |
| dragica | 1:6231121f9e19 | 538 | WriteReg(0, CELL_ADC_CTRL, 0x3F, 1, FRMWRT_ALL_NR); //enables ADC for all 6 cell channels |
| dragica | 1:6231121f9e19 | 539 | WriteReg(0, OVUV_CTRL, 0x3F, 1, FRMWRT_ALL_NR); //enable all cell ov/uv |
| dragica | 1:6231121f9e19 | 540 | WriteReg(0, UV_THRESH, 0x53, 1, FRMWRT_ALL_NR); //sets cell UV to 2.8V |
| dragica | 1:6231121f9e19 | 541 | WriteReg(0, OV_THRESH, 0x5B, 1, FRMWRT_ALL_NR); //sets cell OV to 4.3V |
| dragica | 1:6231121f9e19 | 542 | //WriteReg(0, OTUT_CTRL, 0x3F, 1, FRMWRT_ALL_NR); //enable GPIO OT/UT |
| dragica | 1:6231121f9e19 | 543 | //WriteReg(0, OTUT_THRESH, 0xFF, 1, FRMWRT_ALL_NR); //sets OT to 35% TSREF, UT to 75%, programmabe in 1% increment |
| dragica | 1:6231121f9e19 | 544 | WriteReg(0, GPIO_ADC_CONF, 0x3F, 1, FRMWRT_ALL_NR); //configure GPIO as AUX voltage (absolute voltage, set to 0 for ratiometric) |
| dragica | 1:6231121f9e19 | 545 | for (nCurrentBoard = 0; nCurrentBoard < TOTALBOARDS; nCurrentBoard++) { |
| dragica | 1:6231121f9e19 | 546 | //set adc delay for each device |
| dragica | 1:6231121f9e19 | 547 | WriteReg(nCurrentBoard, ADC_DELAY, 0x00, 1, FRMWRT_SGL_NR); |
| dragica | 1:6231121f9e19 | 548 | } |
| dragica | 1:6231121f9e19 | 549 | WriteReg(0, AUX_ADC_CONF, 0x08, 1, FRMWRT_ALL_NR); //1MHz AUX sample rate, 128 decimation ratio |
| dragica | 1:6231121f9e19 | 550 | WriteReg(0, CELL_ADC_CONF1, 0x67, 1, FRMWRT_ALL_NR); //256 decimation ratio, 1MHz sample. 1.2 Hz LPF |
| dragica | 1:6231121f9e19 | 551 | WriteReg(0, CELL_ADC_CONF2, 0x00, 1, FRMWRT_ALL_NR); //single conversion |
| dragica | 1:6231121f9e19 | 552 | //enable continuous sampling. Otherwise, single conversions with CONTROL2[CELL_ADC_GO] |
| dragica | 1:6231121f9e19 | 553 | //WriteReg(0,CELL_ADC_CONF2, 0x0A,1,FRMWRT_ALL_NR);//continuous sampling with 5ms interval |
| dragica | 1:6231121f9e19 | 554 | WriteReg(0, CONTROL2, 0x10, 1, FRMWRT_ALL_NR);// enable TSREF to give enough settling time |
| dragica | 2:9ca50d384b62 | 555 | wait_ms(2); // provides settling time for TSREF |
| dragica | 1:6231121f9e19 | 556 | |
| dragica | 1:6231121f9e19 | 557 | for (nCurrentBoard = 0; nCurrentBoard < TOTALBOARDS; nCurrentBoard++) { |
| dragica | 1:6231121f9e19 | 558 | //read PARTID |
| dragica | 1:6231121f9e19 | 559 | ReadReg(nCurrentBoard, PARTID, bFrame, 1, 0, FRMWRT_SGL_R); |
| dragica | 2:9ca50d384b62 | 560 | wait_us(500); |
| dragica | 1:6231121f9e19 | 561 | } |
| dragica | 1:6231121f9e19 | 562 | for (nCurrentBoard = 0; nCurrentBoard < TOTALBOARDS; nCurrentBoard++) { |
| dragica | 1:6231121f9e19 | 563 | //read DEV_STAT |
| dragica | 1:6231121f9e19 | 564 | ReadReg(nCurrentBoard, DEV_STAT, bFrame, 1, 0, FRMWRT_SGL_R); |
| dragica | 2:9ca50d384b62 | 565 | wait_us(500); |
| dragica | 1:6231121f9e19 | 566 | } |
| dragica | 1:6231121f9e19 | 567 | for (nCurrentBoard = 0; nCurrentBoard < TOTALBOARDS; nCurrentBoard++) { |
| dragica | 1:6231121f9e19 | 568 | //read LOOP_STAT |
| dragica | 1:6231121f9e19 | 569 | ReadReg(nCurrentBoard, LOOP_STAT, bFrame, 1, 0, FRMWRT_SGL_R); |
| dragica | 2:9ca50d384b62 | 570 | wait_us(500); |
| dragica | 1:6231121f9e19 | 571 | } |
| dragica | 2:9ca50d384b62 | 572 | wait_us(100); |
| dragica | 1:6231121f9e19 | 573 | for (nCurrentBoard = 0; nCurrentBoard < TOTALBOARDS; nCurrentBoard++) { |
| dragica | 1:6231121f9e19 | 574 | //read FAULT_SUM |
| dragica | 1:6231121f9e19 | 575 | ReadReg(nCurrentBoard, FAULT_SUM, bFrame, 1, 0, FRMWRT_SGL_R); |
| dragica | 2:9ca50d384b62 | 576 | wait_us(500); |
| dragica | 1:6231121f9e19 | 577 | } |
| dragica | 2:9ca50d384b62 | 578 | wait_us(100); |
| dragica | 1:6231121f9e19 | 579 | for (nCurrentBoard = 0; nCurrentBoard < TOTALBOARDS; nCurrentBoard++) { |
| dragica | 1:6231121f9e19 | 580 | //read cust_crc_rslt high and low byte |
| dragica | 1:6231121f9e19 | 581 | ReadReg(nCurrentBoard, CUST_CRC_RSLTH, bFrame, 2, 0, FRMWRT_SGL_R); //read Customer CRC result and update |
| dragica | 2:9ca50d384b62 | 582 | wait_ms(1); |
| dragica | 1:6231121f9e19 | 583 | WriteReg(nCurrentBoard, CUST_CRCH, bFrame[5], 1, FRMWRT_SGL_NR); //update high byte |
| dragica | 1:6231121f9e19 | 584 | WriteReg(nCurrentBoard, CUST_CRCL, bFrame[6], 1, FRMWRT_SGL_NR); //update low byte |
| dragica | 1:6231121f9e19 | 585 | } |
| dragica | 1:6231121f9e19 | 586 | // WriteReg(0, CONTROL2, 0x1D, 1, FRMWRT_ALL_NR); // OTUT EN, OVUV EN, Sample all cells |
| dragica | 1:6231121f9e19 | 587 | |
| dragica | 1:6231121f9e19 | 588 | WriteReg(0, AUX_ADC_CTRL1, 0x01, 1, FRMWRT_ALL_NR); //convert BAT with AUX ADC |
| dragica | 1:6231121f9e19 | 589 | WriteReg(0, AUX_ADC_CTRL2, 0x00, 1, FRMWRT_ALL_NR); //No AUX ADC measurements from this register |
| dragica | 1:6231121f9e19 | 590 | WriteReg(0, AUX_ADC_CTRL3, 0x00, 1, FRMWRT_ALL_NR); //No AUX ADC measurements from this register |
| dragica | 2:9ca50d384b62 | 591 | wait_us(100); |
| dragica | 1:6231121f9e19 | 592 | for (nCurrentBoard = 0; nCurrentBoard < TOTALBOARDS; nCurrentBoard++) { |
| dragica | 1:6231121f9e19 | 593 | //read CB_SW_STAT |
| dragica | 1:6231121f9e19 | 594 | ReadReg(nCurrentBoard, CB_SW_STAT, bFrame, 1, 0, FRMWRT_SGL_R); |
| dragica | 2:9ca50d384b62 | 595 | wait_us(500); |
| dragica | 1:6231121f9e19 | 596 | } |
| dragica | 2:9ca50d384b62 | 597 | wait_us(100); |
| dragica | 1:6231121f9e19 | 598 | WriteReg(0, DIAG_CTRL2, 0x41, 1, FRMWRT_ALL_NR); //set AUX ADC to measure cell 1 |
| dragica | 1:6231121f9e19 | 599 | |
| dragica | 1:6231121f9e19 | 600 | //configure cell balancing |
| dragica | 1:6231121f9e19 | 601 | WriteReg(0, CB_CONFIG, 0x0A, 1, FRMWRT_ALL_NR); // 2 minutes duty cycle, continue on fault, odds then even |
| dragica | 1:6231121f9e19 | 602 | //configure cell balancing timers |
| dragica | 1:6231121f9e19 | 603 | WriteReg(0, CB_CELL1_CTRL, 0x03, 1, FRMWRT_ALL_NR); // 3 minute balance timer to all but base device |
| dragica | 1:6231121f9e19 | 604 | WriteReg(0, CB_CELL2_CTRL, 0x03, 1, FRMWRT_ALL_NR); // 3 minute balance timer to all but base device |
| dragica | 1:6231121f9e19 | 605 | WriteReg(0, CB_CELL3_CTRL, 0x03, 1, FRMWRT_ALL_NR); // 3 minute balance timer to all but base device |
| dragica | 1:6231121f9e19 | 606 | WriteReg(0, CB_CELL4_CTRL, 0x03, 1, FRMWRT_ALL_NR); // 3 minute balance timer to all but base device |
| dragica | 1:6231121f9e19 | 607 | WriteReg(0, CB_CELL5_CTRL, 0x03, 1, FRMWRT_ALL_NR); // 3 minute balance timer to all but base device |
| dragica | 1:6231121f9e19 | 608 | WriteReg(0, CB_CELL6_CTRL, 0x03, 1, FRMWRT_ALL_NR); // 3 minute balance timer to all but base device |
| dragica | 1:6231121f9e19 | 609 | |
| dragica | 2:9ca50d384b62 | 610 | wait_ms(2); |
| dragica | 1:6231121f9e19 | 611 | //end init sequence |
| dragica | 1:6231121f9e19 | 612 | } |
| dragica | 1:6231121f9e19 | 613 | //*************************** |
| dragica | 1:6231121f9e19 | 614 | //END MISCELLANEOUS FUNCTIONS |
| dragica | 1:6231121f9e19 | 615 | //*************************** |
| dragica | 1:6231121f9e19 | 616 | //EOF |
| dragica | 1:6231121f9e19 | 617 |