Girls BMS squad
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HighSide
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cpp/bq79606.cpp@1:6231121f9e19, 2020-12-21 (annotated)
- Committer:
- dragica
- Date:
- Mon Dec 21 10:34:18 2020 +0000
- Revision:
- 1:6231121f9e19
- Child:
- 2:9ca50d384b62
Update BMS LV SW;
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| dragica | 1:6231121f9e19 | 1 | /* |
| dragica | 1:6231121f9e19 | 2 | * @file bq79606.c |
| dragica | 1:6231121f9e19 | 3 | * |
| dragica | 1:6231121f9e19 | 4 | * @author Vince Toledo - Texas Instruments Inc. |
| dragica | 1:6231121f9e19 | 5 | * @date August 2019 |
| dragica | 1:6231121f9e19 | 6 | * @version 2.0 |
| dragica | 1:6231121f9e19 | 7 | * @note Built with CCS for Hercules Version: 8.1.0.00011 |
| dragica | 1:6231121f9e19 | 8 | */ |
| dragica | 1:6231121f9e19 | 9 | |
| dragica | 1:6231121f9e19 | 10 | /***************************************************************************** |
| dragica | 1:6231121f9e19 | 11 | ** |
| dragica | 1:6231121f9e19 | 12 | ** Copyright (c) 2011-2017 Texas Instruments |
| dragica | 1:6231121f9e19 | 13 | ** |
| dragica | 1:6231121f9e19 | 14 | ******************************************************************************/ |
| dragica | 1:6231121f9e19 | 15 | #include "bq79606.h" |
| dragica | 1:6231121f9e19 | 16 | |
| dragica | 1:6231121f9e19 | 17 | extern int UART_RX_RDY; |
| dragica | 1:6231121f9e19 | 18 | extern int RTI_TIMEOUT; |
| dragica | 1:6231121f9e19 | 19 | int bRes = 0; |
| dragica | 1:6231121f9e19 | 20 | int count = 10000; |
| dragica | 1:6231121f9e19 | 21 | uint8 pFrame[(MAXBYTES+6)*TOTALBOARDS]; |
| dragica | 1:6231121f9e19 | 22 | BYTE bBuf[8]; |
| dragica | 1:6231121f9e19 | 23 | BYTE bReturn = 0; |
| dragica | 1:6231121f9e19 | 24 | BYTE response_frame2[(MAXBYTES+6)*TOTALBOARDS]; |
| dragica | 1:6231121f9e19 | 25 | BYTE bFrame[(2+6)*TOTALBOARDS]; |
| dragica | 1:6231121f9e19 | 26 | int nCurrentBoard = 0; |
| dragica | 1:6231121f9e19 | 27 | |
| dragica | 1:6231121f9e19 | 28 | //****** |
| dragica | 1:6231121f9e19 | 29 | //PINGS |
| dragica | 1:6231121f9e19 | 30 | //****** |
| dragica | 1:6231121f9e19 | 31 | void WakeUp() { |
| dragica | 1:6231121f9e19 | 32 | bmsLVWakeUp=0;//active low |
| dragica | 1:6231121f9e19 | 33 | delayus(250);//wait min 250us |
| dragica | 1:6231121f9e19 | 34 | bmsLVWakeUp=1;//de-assert, done with toggle in code example |
| dragica | 1:6231121f9e19 | 35 | delayms(7); //tsu(wake) 7ms delay PER BOARD before beginning communication |
| dragica | 1:6231121f9e19 | 36 | |
| dragica | 1:6231121f9e19 | 37 | void CommClear(void) { |
| dragica | 1:6231121f9e19 | 38 | int baudRate; |
| dragica | 1:6231121f9e19 | 39 | baudRate = scilinREG->BRS; |
| dragica | 1:6231121f9e19 | 40 | |
| dragica | 1:6231121f9e19 | 41 | scilinREG->GCR1 &= ~(1U << 7U); // put SCI into reset |
| dragica | 1:6231121f9e19 | 42 | scilinREG->PIO0 &= ~(1U << 2U); // disable transmit function - now a GPIO |
| dragica | 1:6231121f9e19 | 43 | scilinREG->PIO3 &= ~(1U << 2U); // set output to low |
| dragica | 1:6231121f9e19 | 44 | |
| dragica | 1:6231121f9e19 | 45 | delayus(baudRate * 2); // ~= 1/BAUDRATE/16*(155+1)*1.01 |
| dragica | 1:6231121f9e19 | 46 | sciInit(); |
| dragica | 1:6231121f9e19 | 47 | sciSetBaudrate(scilinREG, BAUDRATE); |
| dragica | 1:6231121f9e19 | 48 | } |
| dragica | 1:6231121f9e19 | 49 | |
| dragica | 1:6231121f9e19 | 50 | void CommSleepToWake(void) { |
| dragica | 1:6231121f9e19 | 51 | scilinREG->GCR1 &= ~(1U << 7U); // put SCI into reset |
| dragica | 1:6231121f9e19 | 52 | scilinREG->PIO0 &= ~(1U << 2U); // disable transmit function - now a GPIO |
| dragica | 1:6231121f9e19 | 53 | scilinREG->PIO3 &= ~(1U << 2U); // set output to low |
| dragica | 1:6231121f9e19 | 54 | |
| dragica | 1:6231121f9e19 | 55 | delayus(250); // 250us to 300us, same as wake |
| dragica | 1:6231121f9e19 | 56 | sciInit(); |
| dragica | 1:6231121f9e19 | 57 | sciSetBaudrate(scilinREG, BAUDRATE); |
| dragica | 1:6231121f9e19 | 58 | } |
| dragica | 1:6231121f9e19 | 59 | |
| dragica | 1:6231121f9e19 | 60 | |
| dragica | 1:6231121f9e19 | 61 | void CommReset(void) { |
| dragica | 1:6231121f9e19 | 62 | scilinREG->GCR1 &= ~(1U << 7U); // put SCI into reset |
| dragica | 1:6231121f9e19 | 63 | scilinREG->PIO0 &= ~(1U << 2U); // disable transmit function - now a GPIO |
| dragica | 1:6231121f9e19 | 64 | scilinREG->PIO3 &= ~(1U << 2U); // set output to low |
| dragica | 1:6231121f9e19 | 65 | |
| dragica | 1:6231121f9e19 | 66 | delayus(500); // should cover any possible baud rate |
| dragica | 1:6231121f9e19 | 67 | sciInit(); |
| dragica | 1:6231121f9e19 | 68 | |
| dragica | 1:6231121f9e19 | 69 | //BASE DEVICE NOW AT 250K BAUDRATE, STACK DEVICES ARE WHATEVER BAUDRATE THEY WERE BEFORE |
| dragica | 1:6231121f9e19 | 70 | |
| dragica | 1:6231121f9e19 | 71 | //wait a bit just to make sure the microcontroller is ready |
| dragica | 1:6231121f9e19 | 72 | delayus(100); |
| dragica | 1:6231121f9e19 | 73 | |
| dragica | 1:6231121f9e19 | 74 | //set microcontroller to 250k to talk to base |
| dragica | 1:6231121f9e19 | 75 | sciSetBaudrate(scilinREG, 250000); |
| dragica | 1:6231121f9e19 | 76 | |
| dragica | 1:6231121f9e19 | 77 | //tell the base device to set its baudrate to the chosen BAUDRATE, and propagate to the rest of the stack |
| dragica | 1:6231121f9e19 | 78 | //then set the microcontroller to the appropriate baudrate to match |
| dragica | 1:6231121f9e19 | 79 | if(BAUDRATE == 1000000) |
| dragica | 1:6231121f9e19 | 80 | { |
| dragica | 1:6231121f9e19 | 81 | //set COMM_CTRL and DAISY_CHAIN_CTRL registers |
| dragica | 1:6231121f9e19 | 82 | WriteReg(0, COMM_CTRL, 0x3C3C, 2, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 83 | |
| dragica | 1:6231121f9e19 | 84 | //ALL 606 DEVICES ARE NOW AT 1M BAUDRATE |
| dragica | 1:6231121f9e19 | 85 | |
| dragica | 1:6231121f9e19 | 86 | //set the microcontroller to 1M baudrate |
| dragica | 1:6231121f9e19 | 87 | sciSetBaudrate(scilinREG, 1000000); |
| dragica | 1:6231121f9e19 | 88 | } |
| dragica | 1:6231121f9e19 | 89 | else if(BAUDRATE == 500000) |
| dragica | 1:6231121f9e19 | 90 | { |
| dragica | 1:6231121f9e19 | 91 | WriteReg(0, COMM_CTRL, 0x383C, 2, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 92 | sciSetBaudrate(scilinREG, 500000); |
| dragica | 1:6231121f9e19 | 93 | } |
| dragica | 1:6231121f9e19 | 94 | else if(BAUDRATE == 250000) |
| dragica | 1:6231121f9e19 | 95 | { |
| dragica | 1:6231121f9e19 | 96 | WriteReg(0, COMM_CTRL, 0x343C, 2, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 97 | sciSetBaudrate(scilinREG, 250000); |
| dragica | 1:6231121f9e19 | 98 | } |
| dragica | 1:6231121f9e19 | 99 | else if(BAUDRATE == 125000) |
| dragica | 1:6231121f9e19 | 100 | { |
| dragica | 1:6231121f9e19 | 101 | WriteReg(0, COMM_CTRL, 0x303C, 2, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 102 | sciSetBaudrate(scilinREG, 125000); |
| dragica | 1:6231121f9e19 | 103 | } |
| dragica | 1:6231121f9e19 | 104 | else |
| dragica | 1:6231121f9e19 | 105 | { |
| dragica | 1:6231121f9e19 | 106 | printf("ERROR: INVALID BAUDRATE CHOSEN IN BQ79606.h FILE. Choosing default 1M baudrate:\n\n"); |
| dragica | 1:6231121f9e19 | 107 | WriteReg(0, COMM_CTRL, 0x3C3C, 2, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 108 | sciSetBaudrate(scilinREG, 1000000); |
| dragica | 1:6231121f9e19 | 109 | } |
| dragica | 1:6231121f9e19 | 110 | |
| dragica | 1:6231121f9e19 | 111 | delayus(100); |
| dragica | 1:6231121f9e19 | 112 | } |
| dragica | 1:6231121f9e19 | 113 | //********** |
| dragica | 1:6231121f9e19 | 114 | //END PINGS |
| dragica | 1:6231121f9e19 | 115 | //********** |
| dragica | 1:6231121f9e19 | 116 | |
| dragica | 1:6231121f9e19 | 117 | |
| dragica | 1:6231121f9e19 | 118 | //********************** |
| dragica | 1:6231121f9e19 | 119 | //AUTO ADDRESS SEQUENCE |
| dragica | 1:6231121f9e19 | 120 | //********************** |
| dragica | 1:6231121f9e19 | 121 | void AutoAddress() |
| dragica | 1:6231121f9e19 | 122 | { |
| dragica | 1:6231121f9e19 | 123 | memset(response_frame2,0,sizeof(response_frame2)); //clear out the response frame buffer |
| dragica | 1:6231121f9e19 | 124 | |
| dragica | 1:6231121f9e19 | 125 | //dummy write to ECC_TEST (sync DLL) |
| dragica | 1:6231121f9e19 | 126 | WriteReg(0, ECC_TEST, 0x00, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 127 | |
| dragica | 1:6231121f9e19 | 128 | //clear CONFIG in case it is set |
| dragica | 1:6231121f9e19 | 129 | WriteReg(0, CONFIG, 0x00, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 130 | |
| dragica | 1:6231121f9e19 | 131 | //enter auto addressing mode |
| dragica | 1:6231121f9e19 | 132 | WriteReg(0, CONTROL1, 0x01, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 133 | |
| dragica | 1:6231121f9e19 | 134 | //set addresses for all boards in daisy-chain |
| dragica | 1:6231121f9e19 | 135 | for (nCurrentBoard = 0; nCurrentBoard < TOTALBOARDS; nCurrentBoard++) |
| dragica | 1:6231121f9e19 | 136 | { |
| dragica | 1:6231121f9e19 | 137 | WriteReg(nCurrentBoard, DEVADD_USR, nCurrentBoard, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 138 | } |
| dragica | 1:6231121f9e19 | 139 | |
| dragica | 1:6231121f9e19 | 140 | //set all devices as a stack device |
| dragica | 1:6231121f9e19 | 141 | WriteReg(0, CONFIG, 0x02, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 142 | |
| dragica | 1:6231121f9e19 | 143 | //if there's only 1 board, it's the base AND the top of stack, so change it to those |
| dragica | 1:6231121f9e19 | 144 | if(TOTALBOARDS==1) |
| dragica | 1:6231121f9e19 | 145 | { |
| dragica | 1:6231121f9e19 | 146 | WriteReg(0, CONFIG, 0x01, 1, FRMWRT_SGL_NR); |
| dragica | 1:6231121f9e19 | 147 | } |
| dragica | 1:6231121f9e19 | 148 | //otherwise set the base and top of stack individually |
| dragica | 1:6231121f9e19 | 149 | else |
| dragica | 1:6231121f9e19 | 150 | { |
| dragica | 1:6231121f9e19 | 151 | WriteReg(0, CONFIG, 0x00, 1, FRMWRT_SGL_NR); //base |
| dragica | 1:6231121f9e19 | 152 | WriteReg(TOTALBOARDS-1, CONFIG, 0x03, 1, FRMWRT_SGL_NR); //top of stack |
| dragica | 1:6231121f9e19 | 153 | } |
| dragica | 1:6231121f9e19 | 154 | |
| dragica | 1:6231121f9e19 | 155 | //dummy read from ECC_TEST (sync DLL) |
| dragica | 1:6231121f9e19 | 156 | ReadReg(TOTALBOARDS-1, ECC_TEST, response_frame2, 1, 0, FRMWRT_ALL_R); |
| dragica | 1:6231121f9e19 | 157 | |
| dragica | 1:6231121f9e19 | 158 | // //OPTIONAL: read back all device addresses |
| dragica | 1:6231121f9e19 | 159 | // WriteReg(0, COMM_TO, 0x00, 1, FRMWRT_ALL_NR); //Disable communication timeout because printf takes a long time |
| dragica | 1:6231121f9e19 | 160 | // for (nCurrentBoard = 0; nCurrentBoard < TOTALBOARDS; nCurrentBoard++) { |
| dragica | 1:6231121f9e19 | 161 | // memset(response_frame2, 0, sizeof(response_frame2)); |
| dragica | 1:6231121f9e19 | 162 | // ReadReg(nCurrentBoard, DEVADD_USR, response_frame2, 1, 0, FRMWRT_SGL_R); |
| dragica | 1:6231121f9e19 | 163 | // printf("Board %d=%02x\n",nCurrentBoard,response_frame2[4]); |
| dragica | 1:6231121f9e19 | 164 | // } |
| dragica | 1:6231121f9e19 | 165 | } |
| dragica | 1:6231121f9e19 | 166 | //************************** |
| dragica | 1:6231121f9e19 | 167 | //END AUTO ADDRESS SEQUENCE |
| dragica | 1:6231121f9e19 | 168 | //************************** |
| dragica | 1:6231121f9e19 | 169 | |
| dragica | 1:6231121f9e19 | 170 | |
| dragica | 1:6231121f9e19 | 171 | //************************ |
| dragica | 1:6231121f9e19 | 172 | //WRITE AND READ FUNCTIONS |
| dragica | 1:6231121f9e19 | 173 | //************************ |
| dragica | 1:6231121f9e19 | 174 | int WriteReg(BYTE bID, uint16 wAddr, uint64 dwData, BYTE bLen, BYTE bWriteType) { |
| dragica | 1:6231121f9e19 | 175 | // device address, register start address, data bytes, data length, write type (single, broadcast, stack) |
| dragica | 1:6231121f9e19 | 176 | bRes = 0; |
| dragica | 1:6231121f9e19 | 177 | memset(bBuf,0,sizeof(bBuf)); |
| dragica | 1:6231121f9e19 | 178 | switch (bLen) { |
| dragica | 1:6231121f9e19 | 179 | case 1: |
| dragica | 1:6231121f9e19 | 180 | bBuf[0] = dwData & 0x00000000000000FF; |
| dragica | 1:6231121f9e19 | 181 | bRes = WriteFrame(bID, wAddr, bBuf, 1, bWriteType); |
| dragica | 1:6231121f9e19 | 182 | break; |
| dragica | 1:6231121f9e19 | 183 | case 2: |
| dragica | 1:6231121f9e19 | 184 | bBuf[0] = (dwData & 0x000000000000FF00) >> 8; |
| dragica | 1:6231121f9e19 | 185 | bBuf[1] = dwData & 0x00000000000000FF; |
| dragica | 1:6231121f9e19 | 186 | bRes = WriteFrame(bID, wAddr, bBuf, 2, bWriteType); |
| dragica | 1:6231121f9e19 | 187 | break; |
| dragica | 1:6231121f9e19 | 188 | case 3: |
| dragica | 1:6231121f9e19 | 189 | bBuf[0] = (dwData & 0x0000000000FF0000) >> 16; |
| dragica | 1:6231121f9e19 | 190 | bBuf[1] = (dwData & 0x000000000000FF00) >> 8; |
| dragica | 1:6231121f9e19 | 191 | bBuf[2] = dwData & 0x00000000000000FF; |
| dragica | 1:6231121f9e19 | 192 | bRes = WriteFrame(bID, wAddr, bBuf, 3, bWriteType); |
| dragica | 1:6231121f9e19 | 193 | break; |
| dragica | 1:6231121f9e19 | 194 | case 4: |
| dragica | 1:6231121f9e19 | 195 | bBuf[0] = (dwData & 0x00000000FF000000) >> 24; |
| dragica | 1:6231121f9e19 | 196 | bBuf[1] = (dwData & 0x0000000000FF0000) >> 16; |
| dragica | 1:6231121f9e19 | 197 | bBuf[2] = (dwData & 0x000000000000FF00) >> 8; |
| dragica | 1:6231121f9e19 | 198 | bBuf[3] = dwData & 0x00000000000000FF; |
| dragica | 1:6231121f9e19 | 199 | bRes = WriteFrame(bID, wAddr, bBuf, 4, bWriteType); |
| dragica | 1:6231121f9e19 | 200 | break; |
| dragica | 1:6231121f9e19 | 201 | case 5: |
| dragica | 1:6231121f9e19 | 202 | bBuf[0] = (dwData & 0x000000FF00000000) >> 32; |
| dragica | 1:6231121f9e19 | 203 | bBuf[1] = (dwData & 0x00000000FF000000) >> 24; |
| dragica | 1:6231121f9e19 | 204 | bBuf[2] = (dwData & 0x0000000000FF0000) >> 16; |
| dragica | 1:6231121f9e19 | 205 | bBuf[3] = (dwData & 0x000000000000FF00) >> 8; |
| dragica | 1:6231121f9e19 | 206 | bBuf[4] = dwData & 0x00000000000000FF; |
| dragica | 1:6231121f9e19 | 207 | bRes = WriteFrame(bID, wAddr, bBuf, 5, bWriteType); |
| dragica | 1:6231121f9e19 | 208 | break; |
| dragica | 1:6231121f9e19 | 209 | case 6: |
| dragica | 1:6231121f9e19 | 210 | bBuf[0] = (dwData & 0x0000FF0000000000) >> 40; |
| dragica | 1:6231121f9e19 | 211 | bBuf[1] = (dwData & 0x000000FF00000000) >> 32; |
| dragica | 1:6231121f9e19 | 212 | bBuf[2] = (dwData & 0x00000000FF000000) >> 24; |
| dragica | 1:6231121f9e19 | 213 | bBuf[3] = (dwData & 0x0000000000FF0000) >> 16; |
| dragica | 1:6231121f9e19 | 214 | bBuf[4] = (dwData & 0x000000000000FF00) >> 8; |
| dragica | 1:6231121f9e19 | 215 | bBuf[5] = dwData & 0x00000000000000FF; |
| dragica | 1:6231121f9e19 | 216 | bRes = WriteFrame(bID, wAddr, bBuf, 6, bWriteType); |
| dragica | 1:6231121f9e19 | 217 | break; |
| dragica | 1:6231121f9e19 | 218 | case 7: |
| dragica | 1:6231121f9e19 | 219 | bBuf[0] = (dwData & 0x00FF000000000000) >> 48; |
| dragica | 1:6231121f9e19 | 220 | bBuf[1] = (dwData & 0x0000FF0000000000) >> 40; |
| dragica | 1:6231121f9e19 | 221 | bBuf[2] = (dwData & 0x000000FF00000000) >> 32; |
| dragica | 1:6231121f9e19 | 222 | bBuf[3] = (dwData & 0x00000000FF000000) >> 24; |
| dragica | 1:6231121f9e19 | 223 | bBuf[4] = (dwData & 0x0000000000FF0000) >> 16; |
| dragica | 1:6231121f9e19 | 224 | bBuf[5] = (dwData & 0x000000000000FF00) >> 8; |
| dragica | 1:6231121f9e19 | 225 | bBuf[6] = dwData & 0x00000000000000FF; |
| dragica | 1:6231121f9e19 | 226 | bRes = WriteFrame(bID, wAddr, bBuf, 7, bWriteType); |
| dragica | 1:6231121f9e19 | 227 | break; |
| dragica | 1:6231121f9e19 | 228 | case 8: |
| dragica | 1:6231121f9e19 | 229 | bBuf[0] = (dwData & 0xFF00000000000000) >> 56; |
| dragica | 1:6231121f9e19 | 230 | bBuf[1] = (dwData & 0x00FF000000000000) >> 48; |
| dragica | 1:6231121f9e19 | 231 | bBuf[2] = (dwData & 0x0000FF0000000000) >> 40; |
| dragica | 1:6231121f9e19 | 232 | bBuf[3] = (dwData & 0x000000FF00000000) >> 32; |
| dragica | 1:6231121f9e19 | 233 | bBuf[4] = (dwData & 0x00000000FF000000) >> 24; |
| dragica | 1:6231121f9e19 | 234 | bBuf[5] = (dwData & 0x0000000000FF0000) >> 16; |
| dragica | 1:6231121f9e19 | 235 | bBuf[6] = (dwData & 0x000000000000FF00) >> 8; |
| dragica | 1:6231121f9e19 | 236 | bBuf[7] = dwData & 0x00000000000000FF; |
| dragica | 1:6231121f9e19 | 237 | bRes = WriteFrame(bID, wAddr, bBuf, 8, bWriteType); |
| dragica | 1:6231121f9e19 | 238 | break; |
| dragica | 1:6231121f9e19 | 239 | default: |
| dragica | 1:6231121f9e19 | 240 | break; |
| dragica | 1:6231121f9e19 | 241 | } |
| dragica | 1:6231121f9e19 | 242 | return bRes; |
| dragica | 1:6231121f9e19 | 243 | } |
| dragica | 1:6231121f9e19 | 244 | |
| dragica | 1:6231121f9e19 | 245 | int WriteFrame(BYTE bID, uint16 wAddr, BYTE * pData, BYTE bLen, BYTE bWriteType) { |
| dragica | 1:6231121f9e19 | 246 | int bPktLen = 0; |
| dragica | 1:6231121f9e19 | 247 | uint8 * pBuf = pFrame; |
| dragica | 1:6231121f9e19 | 248 | uint16 wCRC; |
| dragica | 1:6231121f9e19 | 249 | memset(pFrame, 0x7F, sizeof(pFrame)); |
| dragica | 1:6231121f9e19 | 250 | *pBuf++ = 0x80 | (bWriteType) | ((bWriteType & 0x10) ? bLen - 0x01 : 0x00); //Only include blen if it is a write; Writes are 0x90, 0xB0, 0xD0 |
| dragica | 1:6231121f9e19 | 251 | if (bWriteType == FRMWRT_SGL_R || bWriteType == FRMWRT_SGL_NR) |
| dragica | 1:6231121f9e19 | 252 | { |
| dragica | 1:6231121f9e19 | 253 | *pBuf++ = (bID & 0x00FF); |
| dragica | 1:6231121f9e19 | 254 | } |
| dragica | 1:6231121f9e19 | 255 | *pBuf++ = (wAddr & 0xFF00) >> 8; |
| dragica | 1:6231121f9e19 | 256 | *pBuf++ = wAddr & 0x00FF; |
| dragica | 1:6231121f9e19 | 257 | |
| dragica | 1:6231121f9e19 | 258 | while (bLen--) |
| dragica | 1:6231121f9e19 | 259 | *pBuf++ = *pData++; |
| dragica | 1:6231121f9e19 | 260 | |
| dragica | 1:6231121f9e19 | 261 | bPktLen = pBuf - pFrame; |
| dragica | 1:6231121f9e19 | 262 | |
| dragica | 1:6231121f9e19 | 263 | wCRC = CRC16(pFrame, bPktLen); |
| dragica | 1:6231121f9e19 | 264 | *pBuf++ = wCRC & 0x00FF; |
| dragica | 1:6231121f9e19 | 265 | *pBuf++ = (wCRC & 0xFF00) >> 8; |
| dragica | 1:6231121f9e19 | 266 | bPktLen += 2; |
| dragica | 1:6231121f9e19 | 267 | //THIS SEEMS to occasionally drop bytes from the frame. Sometimes is not sending the last frame of the CRC. |
| dragica | 1:6231121f9e19 | 268 | //(Seems to be caused by stack overflow, so take precautions to reduce stack usage in function calls) |
| dragica | 1:6231121f9e19 | 269 | sciSend(scilinREG, bPktLen, pFrame); |
| dragica | 1:6231121f9e19 | 270 | |
| dragica | 1:6231121f9e19 | 271 | return bPktLen; |
| dragica | 1:6231121f9e19 | 272 | } |
| dragica | 1:6231121f9e19 | 273 | |
| dragica | 1:6231121f9e19 | 274 | int ReadReg(BYTE bID, uint16 wAddr, BYTE * pData, BYTE bLen, uint32 dwTimeOut, |
| dragica | 1:6231121f9e19 | 275 | BYTE bWriteType) { |
| dragica | 1:6231121f9e19 | 276 | bRes = 0; |
| dragica | 1:6231121f9e19 | 277 | count = 100000; |
| dragica | 1:6231121f9e19 | 278 | if (bWriteType == FRMWRT_SGL_R) { |
| dragica | 1:6231121f9e19 | 279 | ReadFrameReq(bID, wAddr, bLen, bWriteType); |
| dragica | 1:6231121f9e19 | 280 | memset(pData, 0, sizeof(pData)); |
| dragica | 1:6231121f9e19 | 281 | sciEnableNotification(scilinREG, SCI_RX_INT); |
| dragica | 1:6231121f9e19 | 282 | sciReceive(scilinREG, bLen + 6, pData); |
| dragica | 1:6231121f9e19 | 283 | while(UART_RX_RDY == 0U && count>0) count--; /*wait*/ |
| dragica | 1:6231121f9e19 | 284 | //if(count == 0) printf("COUNT REACHED 0\n"); |
| dragica | 1:6231121f9e19 | 285 | UART_RX_RDY = 0; |
| dragica | 1:6231121f9e19 | 286 | bRes = bLen + 6; |
| dragica | 1:6231121f9e19 | 287 | } else if (bWriteType == FRMWRT_STK_R) { |
| dragica | 1:6231121f9e19 | 288 | bRes = ReadFrameReq(bID, wAddr, bLen, bWriteType); |
| dragica | 1:6231121f9e19 | 289 | memset(pData, 0, sizeof(pData)); |
| dragica | 1:6231121f9e19 | 290 | sciEnableNotification(scilinREG, SCI_RX_INT); |
| dragica | 1:6231121f9e19 | 291 | sciReceive(scilinREG, (bLen + 6) * (TOTALBOARDS - 1), pData); |
| dragica | 1:6231121f9e19 | 292 | while(UART_RX_RDY == 0U && count>0) count--; /*wait*/ |
| dragica | 1:6231121f9e19 | 293 | UART_RX_RDY = 0; |
| dragica | 1:6231121f9e19 | 294 | bRes = (bLen + 6) * (TOTALBOARDS - 1); |
| dragica | 1:6231121f9e19 | 295 | } else if (bWriteType == FRMWRT_ALL_R) { |
| dragica | 1:6231121f9e19 | 296 | bRes = ReadFrameReq(bID, wAddr, bLen, bWriteType); |
| dragica | 1:6231121f9e19 | 297 | memset(pData, 0, sizeof(pData)); |
| dragica | 1:6231121f9e19 | 298 | sciEnableNotification(scilinREG, SCI_RX_INT); |
| dragica | 1:6231121f9e19 | 299 | sciReceive(scilinREG, (bLen + 6) * TOTALBOARDS, pData); |
| dragica | 1:6231121f9e19 | 300 | while(UART_RX_RDY == 0U && count>0) count--; /*wait*/ |
| dragica | 1:6231121f9e19 | 301 | UART_RX_RDY = 0; |
| dragica | 1:6231121f9e19 | 302 | bRes = (bLen + 6) * TOTALBOARDS; |
| dragica | 1:6231121f9e19 | 303 | } else { |
| dragica | 1:6231121f9e19 | 304 | bRes = 0; |
| dragica | 1:6231121f9e19 | 305 | } |
| dragica | 1:6231121f9e19 | 306 | return bRes; |
| dragica | 1:6231121f9e19 | 307 | } |
| dragica | 1:6231121f9e19 | 308 | |
| dragica | 1:6231121f9e19 | 309 | int ReadFrameReq(BYTE bID, uint16 wAddr, BYTE bByteToReturn, BYTE bWriteType) { |
| dragica | 1:6231121f9e19 | 310 | bReturn = bByteToReturn - 1; |
| dragica | 1:6231121f9e19 | 311 | |
| dragica | 1:6231121f9e19 | 312 | if (bReturn > 127) |
| dragica | 1:6231121f9e19 | 313 | return 0; |
| dragica | 1:6231121f9e19 | 314 | |
| dragica | 1:6231121f9e19 | 315 | return WriteFrame(bID, wAddr, &bReturn, 1, bWriteType); |
| dragica | 1:6231121f9e19 | 316 | } |
| dragica | 1:6231121f9e19 | 317 | |
| dragica | 1:6231121f9e19 | 318 | // CRC16 TABLE |
| dragica | 1:6231121f9e19 | 319 | // ITU_T polynomial: x^16 + x^15 + x^2 + 1 |
| dragica | 1:6231121f9e19 | 320 | const uint16 crc16_table[256] = { 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, |
| dragica | 1:6231121f9e19 | 321 | 0x03C0, 0x0280, 0xC241, 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, |
| dragica | 1:6231121f9e19 | 322 | 0xC481, 0x0440, 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, |
| dragica | 1:6231121f9e19 | 323 | 0x0E40, 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841, |
| dragica | 1:6231121f9e19 | 324 | 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40, 0x1E00, |
| dragica | 1:6231121f9e19 | 325 | 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41, 0x1400, 0xD4C1, |
| dragica | 1:6231121f9e19 | 326 | 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641, 0xD201, 0x12C0, 0x1380, |
| dragica | 1:6231121f9e19 | 327 | 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040, 0xF001, 0x30C0, 0x3180, 0xF141, |
| dragica | 1:6231121f9e19 | 328 | 0x3300, 0xF3C1, 0xF281, 0x3240, 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, |
| dragica | 1:6231121f9e19 | 329 | 0x35C0, 0x3480, 0xF441, 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, |
| dragica | 1:6231121f9e19 | 330 | 0x3E80, 0xFE41, 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, |
| dragica | 1:6231121f9e19 | 331 | 0x3840, 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41, |
| dragica | 1:6231121f9e19 | 332 | 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40, 0xE401, |
| dragica | 1:6231121f9e19 | 333 | 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640, 0x2200, 0xE2C1, |
| dragica | 1:6231121f9e19 | 334 | 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041, 0xA001, 0x60C0, 0x6180, |
| dragica | 1:6231121f9e19 | 335 | 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240, 0x6600, 0xA6C1, 0xA781, 0x6740, |
| dragica | 1:6231121f9e19 | 336 | 0xA501, 0x65C0, 0x6480, 0xA441, 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, |
| dragica | 1:6231121f9e19 | 337 | 0x6FC0, 0x6E80, 0xAE41, 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, |
| dragica | 1:6231121f9e19 | 338 | 0xA881, 0x6840, 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, |
| dragica | 1:6231121f9e19 | 339 | 0xBA41, 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40, |
| dragica | 1:6231121f9e19 | 340 | 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640, 0x7200, |
| dragica | 1:6231121f9e19 | 341 | 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041, 0x5000, 0x90C1, |
| dragica | 1:6231121f9e19 | 342 | 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241, 0x9601, 0x56C0, 0x5780, |
| dragica | 1:6231121f9e19 | 343 | 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440, 0x9C01, 0x5CC0, 0x5D80, 0x9D41, |
| dragica | 1:6231121f9e19 | 344 | 0x5F00, 0x9FC1, 0x9E81, 0x5E40, 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, |
| dragica | 1:6231121f9e19 | 345 | 0x59C0, 0x5880, 0x9841, 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, |
| dragica | 1:6231121f9e19 | 346 | 0x8A81, 0x4A40, 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, |
| dragica | 1:6231121f9e19 | 347 | 0x8C41, 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641, |
| dragica | 1:6231121f9e19 | 348 | 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040 }; |
| dragica | 1:6231121f9e19 | 349 | |
| dragica | 1:6231121f9e19 | 350 | uint16 CRC16(BYTE *pBuf, int nLen) { |
| dragica | 1:6231121f9e19 | 351 | uint16 wCRC = 0xFFFF; |
| dragica | 1:6231121f9e19 | 352 | int i; |
| dragica | 1:6231121f9e19 | 353 | |
| dragica | 1:6231121f9e19 | 354 | for (i = 0; i < nLen; i++) { |
| dragica | 1:6231121f9e19 | 355 | wCRC ^= (*pBuf++) & 0x00FF; |
| dragica | 1:6231121f9e19 | 356 | wCRC = crc16_table[wCRC & 0x00FF] ^ (wCRC >> 8); |
| dragica | 1:6231121f9e19 | 357 | } |
| dragica | 1:6231121f9e19 | 358 | |
| dragica | 1:6231121f9e19 | 359 | return wCRC; |
| dragica | 1:6231121f9e19 | 360 | } |
| dragica | 1:6231121f9e19 | 361 | //**************************** |
| dragica | 1:6231121f9e19 | 362 | //END WRITE AND READ FUNCTIONS |
| dragica | 1:6231121f9e19 | 363 | //**************************** |
| dragica | 1:6231121f9e19 | 364 | |
| dragica | 1:6231121f9e19 | 365 | //************************ |
| dragica | 1:6231121f9e19 | 366 | //MISCELLANEOUS FUNCTIONS |
| dragica | 1:6231121f9e19 | 367 | //************************ |
| dragica | 1:6231121f9e19 | 368 | void delayus(uint16 us) { |
| dragica | 1:6231121f9e19 | 369 | if (us == 0) |
| dragica | 1:6231121f9e19 | 370 | return; |
| dragica | 1:6231121f9e19 | 371 | else |
| dragica | 1:6231121f9e19 | 372 | { |
| dragica | 1:6231121f9e19 | 373 | //CHANGE THE INTERRUPT COMPARE VALUES (PERIOD OF INTERRUPT) |
| dragica | 1:6231121f9e19 | 374 | //Setup compare 0 value. |
| dragica | 1:6231121f9e19 | 375 | rtiREG1->CMP[0U].COMPx = 10*us; //10 ticks of clock per microsecond, so multiply by 10 |
| dragica | 1:6231121f9e19 | 376 | //Setup update compare 0 value. |
| dragica | 1:6231121f9e19 | 377 | rtiREG1->CMP[0U].UDCPx = 10*us; |
| dragica | 1:6231121f9e19 | 378 | |
| dragica | 1:6231121f9e19 | 379 | //ENABLE THE NOTIFICATION FOR THE PERIOD WE SET |
| dragica | 1:6231121f9e19 | 380 | rtiEnableNotification(rtiNOTIFICATION_COMPARE0); |
| dragica | 1:6231121f9e19 | 381 | |
| dragica | 1:6231121f9e19 | 382 | //START THE COUNTER |
| dragica | 1:6231121f9e19 | 383 | rtiStartCounter(rtiCOUNTER_BLOCK0); |
| dragica | 1:6231121f9e19 | 384 | |
| dragica | 1:6231121f9e19 | 385 | //WAIT IN LOOP UNTIL THE INTERRUPT HAPPENS (HAPPENS AFTER THE PERIOD WE SET) |
| dragica | 1:6231121f9e19 | 386 | //WHEN INTERRUPT HAPPENS, RTI_NOTIFICATION GETS SET TO 1 IN THAT INTERRUPT |
| dragica | 1:6231121f9e19 | 387 | //GO TO notification.c -> rtiNotification() to see where RTI_TIMEOUT is set to 1 |
| dragica | 1:6231121f9e19 | 388 | while(RTI_TIMEOUT==0); |
| dragica | 1:6231121f9e19 | 389 | |
| dragica | 1:6231121f9e19 | 390 | //RESET THE VARIABLE TO 0, FOR THE NEXT TIME WE DO A DELAY |
| dragica | 1:6231121f9e19 | 391 | RTI_TIMEOUT = 0; |
| dragica | 1:6231121f9e19 | 392 | |
| dragica | 1:6231121f9e19 | 393 | //DISABLE THE INTERRUPT NOTIFICATION |
| dragica | 1:6231121f9e19 | 394 | rtiDisableNotification(rtiNOTIFICATION_COMPARE0); |
| dragica | 1:6231121f9e19 | 395 | |
| dragica | 1:6231121f9e19 | 396 | //STOP THE COUNTER |
| dragica | 1:6231121f9e19 | 397 | rtiStopCounter(rtiCOUNTER_BLOCK0); |
| dragica | 1:6231121f9e19 | 398 | |
| dragica | 1:6231121f9e19 | 399 | //RESET COUNTER FOR THE NEXT TIME WE DO A DELAY |
| dragica | 1:6231121f9e19 | 400 | rtiResetCounter(rtiCOUNTER_BLOCK0); |
| dragica | 1:6231121f9e19 | 401 | } |
| dragica | 1:6231121f9e19 | 402 | } |
| dragica | 1:6231121f9e19 | 403 | |
| dragica | 1:6231121f9e19 | 404 | void delayms(uint16 ms) { |
| dragica | 1:6231121f9e19 | 405 | if (ms == 0) |
| dragica | 1:6231121f9e19 | 406 | return; |
| dragica | 1:6231121f9e19 | 407 | else |
| dragica | 1:6231121f9e19 | 408 | { |
| dragica | 1:6231121f9e19 | 409 | rtiREG1->CMP[0U].COMPx = 10000*ms; |
| dragica | 1:6231121f9e19 | 410 | rtiREG1->CMP[0U].UDCPx = 10000*ms; |
| dragica | 1:6231121f9e19 | 411 | rtiEnableNotification(rtiNOTIFICATION_COMPARE0); |
| dragica | 1:6231121f9e19 | 412 | rtiStartCounter(rtiCOUNTER_BLOCK0); |
| dragica | 1:6231121f9e19 | 413 | while(RTI_TIMEOUT==0); |
| dragica | 1:6231121f9e19 | 414 | RTI_TIMEOUT = 0; |
| dragica | 1:6231121f9e19 | 415 | rtiDisableNotification(rtiNOTIFICATION_COMPARE0); |
| dragica | 1:6231121f9e19 | 416 | rtiStopCounter(rtiCOUNTER_BLOCK0); |
| dragica | 1:6231121f9e19 | 417 | rtiResetCounter(rtiCOUNTER_BLOCK0); |
| dragica | 1:6231121f9e19 | 418 | } |
| dragica | 1:6231121f9e19 | 419 | } |
| dragica | 1:6231121f9e19 | 420 | |
| dragica | 1:6231121f9e19 | 421 | float Complement(uint16 rawData, float multiplier) |
| dragica | 1:6231121f9e19 | 422 | { |
| dragica | 1:6231121f9e19 | 423 | return -1*(~rawData+1)*multiplier; |
| dragica | 1:6231121f9e19 | 424 | } |
| dragica | 1:6231121f9e19 | 425 | |
| dragica | 1:6231121f9e19 | 426 | BOOL GetFaultStat() { |
| dragica | 1:6231121f9e19 | 427 | |
| dragica | 1:6231121f9e19 | 428 | if (!gioGetBit(gioPORTA, 1)) |
| dragica | 1:6231121f9e19 | 429 | return 0; |
| dragica | 1:6231121f9e19 | 430 | return 1; |
| dragica | 1:6231121f9e19 | 431 | } |
| dragica | 1:6231121f9e19 | 432 | |
| dragica | 1:6231121f9e19 | 433 | void InitDevices() { |
| dragica | 1:6231121f9e19 | 434 | /*******Optional examples of some initialization functions*****/ |
| dragica | 1:6231121f9e19 | 435 | |
| dragica | 1:6231121f9e19 | 436 | delayms(1); |
| dragica | 1:6231121f9e19 | 437 | WriteReg(0, COMM_TO, 0x00, 1, FRMWRT_ALL_NR); //Communication timeout disabled |
| dragica | 1:6231121f9e19 | 438 | WriteReg(0, TX_HOLD_OFF, 0x00, 1, FRMWRT_ALL_NR); //no transmit delay after stop bit |
| dragica | 1:6231121f9e19 | 439 | |
| dragica | 1:6231121f9e19 | 440 | /* mask all low level faults... user should unmask necessary faults */ |
| dragica | 1:6231121f9e19 | 441 | WriteReg(0, GPIO_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); //mask GPIO faults |
| dragica | 1:6231121f9e19 | 442 | WriteReg(0, UV_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); //mask UV faults |
| dragica | 1:6231121f9e19 | 443 | WriteReg(0, OV_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); //mask OV faults |
| dragica | 1:6231121f9e19 | 444 | WriteReg(0, UT_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); //mask UT faults |
| dragica | 1:6231121f9e19 | 445 | WriteReg(0, OT_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); //mask OT faults |
| dragica | 1:6231121f9e19 | 446 | WriteReg(0, TONE_FLT_MSK, 0x07, 1, FRMWRT_ALL_NR); //mask all tone faults |
| dragica | 1:6231121f9e19 | 447 | WriteReg(0, COMM_UART_FLT_MSK, 0x07, 1, FRMWRT_ALL_NR); //mask UART faults |
| dragica | 1:6231121f9e19 | 448 | WriteReg(0, COMM_UART_RC_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); //mask UART fault contd |
| dragica | 1:6231121f9e19 | 449 | WriteReg(0, COMM_UART_RR_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 450 | WriteReg(0, COMM_UART_TR_FLT_MSK, 0x03, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 451 | WriteReg(0, COMM_COMH_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 452 | WriteReg(0, COMM_COMH_RC_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 453 | WriteReg(0, COMM_COMH_RR_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 454 | WriteReg(0, COMM_COMH_TR_FLT_MSK, 0x03, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 455 | WriteReg(0, COMM_COML_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 456 | WriteReg(0, COMM_COML_RC_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 457 | WriteReg(0, COMM_COML_RR_FLT_MSK, 0x3F, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 458 | WriteReg(0, COMM_COML_TR_FLT_MSK, 0x03, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 459 | WriteReg(0, OTP_FLT_MSK, 0x07, 1, FRMWRT_ALL_NR); // mask otp faults |
| dragica | 1:6231121f9e19 | 460 | WriteReg(0, RAIL_FLT_MSK, 0xFF, 1, FRMWRT_ALL_NR); //mask power rail faults |
| dragica | 1:6231121f9e19 | 461 | WriteReg(0, SYSFLT1_FLT_MSK, 0x7F, 1, FRMWRT_ALL_NR); //sys fault mask 1 |
| dragica | 1:6231121f9e19 | 462 | WriteReg(0, SYSFLT2_FLT_MSK, 0xFF, 1, FRMWRT_ALL_NR); //sys fault mask 2 |
| dragica | 1:6231121f9e19 | 463 | WriteReg(0, SYSFLT3_FLT_MSK, 0x7F, 1, FRMWRT_ALL_NR); //sys fault mask 3 |
| dragica | 1:6231121f9e19 | 464 | WriteReg(0, OVUV_BIST_FLT_MSK, 0x03, 1, FRMWRT_ALL_NR); //mask ov/uv bist faults |
| dragica | 1:6231121f9e19 | 465 | WriteReg(0, OTUT_BIST_FLT_MSK, 0xFF, 1, FRMWRT_ALL_NR); |
| dragica | 1:6231121f9e19 | 466 | |
| dragica | 1:6231121f9e19 | 467 | WriteReg(0, CELL_ADC_CTRL, 0x3F, 1, FRMWRT_ALL_NR); //enables ADC for all 6 cell channels |
| dragica | 1:6231121f9e19 | 468 | WriteReg(0, OVUV_CTRL, 0x3F, 1, FRMWRT_ALL_NR); //enable all cell ov/uv |
| dragica | 1:6231121f9e19 | 469 | WriteReg(0, UV_THRESH, 0x53, 1, FRMWRT_ALL_NR); //sets cell UV to 2.8V |
| dragica | 1:6231121f9e19 | 470 | WriteReg(0, OV_THRESH, 0x5B, 1, FRMWRT_ALL_NR); //sets cell OV to 4.3V |
| dragica | 1:6231121f9e19 | 471 | //WriteReg(0, OTUT_CTRL, 0x3F, 1, FRMWRT_ALL_NR); //enable GPIO OT/UT |
| dragica | 1:6231121f9e19 | 472 | //WriteReg(0, OTUT_THRESH, 0xFF, 1, FRMWRT_ALL_NR); //sets OT to 35% TSREF, UT to 75%, programmabe in 1% increment |
| dragica | 1:6231121f9e19 | 473 | WriteReg(0, GPIO_ADC_CONF, 0x3F, 1, FRMWRT_ALL_NR); //configure GPIO as AUX voltage (absolute voltage, set to 0 for ratiometric) |
| dragica | 1:6231121f9e19 | 474 | for (nCurrentBoard = 0; nCurrentBoard < TOTALBOARDS; nCurrentBoard++) { |
| dragica | 1:6231121f9e19 | 475 | //set adc delay for each device |
| dragica | 1:6231121f9e19 | 476 | WriteReg(nCurrentBoard, ADC_DELAY, 0x00, 1, FRMWRT_SGL_NR); |
| dragica | 1:6231121f9e19 | 477 | } |
| dragica | 1:6231121f9e19 | 478 | WriteReg(0, AUX_ADC_CONF, 0x08, 1, FRMWRT_ALL_NR); //1MHz AUX sample rate, 128 decimation ratio |
| dragica | 1:6231121f9e19 | 479 | WriteReg(0, CELL_ADC_CONF1, 0x67, 1, FRMWRT_ALL_NR); //256 decimation ratio, 1MHz sample. 1.2 Hz LPF |
| dragica | 1:6231121f9e19 | 480 | WriteReg(0, CELL_ADC_CONF2, 0x00, 1, FRMWRT_ALL_NR); //single conversion |
| dragica | 1:6231121f9e19 | 481 | //enable continuous sampling. Otherwise, single conversions with CONTROL2[CELL_ADC_GO] |
| dragica | 1:6231121f9e19 | 482 | //WriteReg(0,CELL_ADC_CONF2, 0x0A,1,FRMWRT_ALL_NR);//continuous sampling with 5ms interval |
| dragica | 1:6231121f9e19 | 483 | WriteReg(0, CONTROL2, 0x10, 1, FRMWRT_ALL_NR);// enable TSREF to give enough settling time |
| dragica | 1:6231121f9e19 | 484 | delayms(2); // provides settling time for TSREF |
| dragica | 1:6231121f9e19 | 485 | |
| dragica | 1:6231121f9e19 | 486 | for (nCurrentBoard = 0; nCurrentBoard < TOTALBOARDS; nCurrentBoard++) { |
| dragica | 1:6231121f9e19 | 487 | //read PARTID |
| dragica | 1:6231121f9e19 | 488 | ReadReg(nCurrentBoard, PARTID, bFrame, 1, 0, FRMWRT_SGL_R); |
| dragica | 1:6231121f9e19 | 489 | delayus(500); |
| dragica | 1:6231121f9e19 | 490 | } |
| dragica | 1:6231121f9e19 | 491 | for (nCurrentBoard = 0; nCurrentBoard < TOTALBOARDS; nCurrentBoard++) { |
| dragica | 1:6231121f9e19 | 492 | //read DEV_STAT |
| dragica | 1:6231121f9e19 | 493 | ReadReg(nCurrentBoard, DEV_STAT, bFrame, 1, 0, FRMWRT_SGL_R); |
| dragica | 1:6231121f9e19 | 494 | delayus(500); |
| dragica | 1:6231121f9e19 | 495 | } |
| dragica | 1:6231121f9e19 | 496 | for (nCurrentBoard = 0; nCurrentBoard < TOTALBOARDS; nCurrentBoard++) { |
| dragica | 1:6231121f9e19 | 497 | //read LOOP_STAT |
| dragica | 1:6231121f9e19 | 498 | ReadReg(nCurrentBoard, LOOP_STAT, bFrame, 1, 0, FRMWRT_SGL_R); |
| dragica | 1:6231121f9e19 | 499 | delayus(500); |
| dragica | 1:6231121f9e19 | 500 | } |
| dragica | 1:6231121f9e19 | 501 | delayus(100); |
| dragica | 1:6231121f9e19 | 502 | for (nCurrentBoard = 0; nCurrentBoard < TOTALBOARDS; nCurrentBoard++) { |
| dragica | 1:6231121f9e19 | 503 | //read FAULT_SUM |
| dragica | 1:6231121f9e19 | 504 | ReadReg(nCurrentBoard, FAULT_SUM, bFrame, 1, 0, FRMWRT_SGL_R); |
| dragica | 1:6231121f9e19 | 505 | delayus(500); |
| dragica | 1:6231121f9e19 | 506 | } |
| dragica | 1:6231121f9e19 | 507 | delayus(100); |
| dragica | 1:6231121f9e19 | 508 | for (nCurrentBoard = 0; nCurrentBoard < TOTALBOARDS; nCurrentBoard++) { |
| dragica | 1:6231121f9e19 | 509 | //read cust_crc_rslt high and low byte |
| dragica | 1:6231121f9e19 | 510 | ReadReg(nCurrentBoard, CUST_CRC_RSLTH, bFrame, 2, 0, FRMWRT_SGL_R); //read Customer CRC result and update |
| dragica | 1:6231121f9e19 | 511 | delayms(1); |
| dragica | 1:6231121f9e19 | 512 | WriteReg(nCurrentBoard, CUST_CRCH, bFrame[5], 1, FRMWRT_SGL_NR); //update high byte |
| dragica | 1:6231121f9e19 | 513 | WriteReg(nCurrentBoard, CUST_CRCL, bFrame[6], 1, FRMWRT_SGL_NR); //update low byte |
| dragica | 1:6231121f9e19 | 514 | } |
| dragica | 1:6231121f9e19 | 515 | // WriteReg(0, CONTROL2, 0x1D, 1, FRMWRT_ALL_NR); // OTUT EN, OVUV EN, Sample all cells |
| dragica | 1:6231121f9e19 | 516 | |
| dragica | 1:6231121f9e19 | 517 | WriteReg(0, AUX_ADC_CTRL1, 0x01, 1, FRMWRT_ALL_NR); //convert BAT with AUX ADC |
| dragica | 1:6231121f9e19 | 518 | WriteReg(0, AUX_ADC_CTRL2, 0x00, 1, FRMWRT_ALL_NR); //No AUX ADC measurements from this register |
| dragica | 1:6231121f9e19 | 519 | WriteReg(0, AUX_ADC_CTRL3, 0x00, 1, FRMWRT_ALL_NR); //No AUX ADC measurements from this register |
| dragica | 1:6231121f9e19 | 520 | delayus(100); |
| dragica | 1:6231121f9e19 | 521 | for (nCurrentBoard = 0; nCurrentBoard < TOTALBOARDS; nCurrentBoard++) { |
| dragica | 1:6231121f9e19 | 522 | //read CB_SW_STAT |
| dragica | 1:6231121f9e19 | 523 | ReadReg(nCurrentBoard, CB_SW_STAT, bFrame, 1, 0, FRMWRT_SGL_R); |
| dragica | 1:6231121f9e19 | 524 | delayus(500); |
| dragica | 1:6231121f9e19 | 525 | } |
| dragica | 1:6231121f9e19 | 526 | delayus(100); |
| dragica | 1:6231121f9e19 | 527 | WriteReg(0, DIAG_CTRL2, 0x41, 1, FRMWRT_ALL_NR); //set AUX ADC to measure cell 1 |
| dragica | 1:6231121f9e19 | 528 | |
| dragica | 1:6231121f9e19 | 529 | //configure cell balancing |
| dragica | 1:6231121f9e19 | 530 | WriteReg(0, CB_CONFIG, 0x0A, 1, FRMWRT_ALL_NR); // 2 minutes duty cycle, continue on fault, odds then even |
| dragica | 1:6231121f9e19 | 531 | //configure cell balancing timers |
| dragica | 1:6231121f9e19 | 532 | WriteReg(0, CB_CELL1_CTRL, 0x03, 1, FRMWRT_ALL_NR); // 3 minute balance timer to all but base device |
| dragica | 1:6231121f9e19 | 533 | WriteReg(0, CB_CELL2_CTRL, 0x03, 1, FRMWRT_ALL_NR); // 3 minute balance timer to all but base device |
| dragica | 1:6231121f9e19 | 534 | WriteReg(0, CB_CELL3_CTRL, 0x03, 1, FRMWRT_ALL_NR); // 3 minute balance timer to all but base device |
| dragica | 1:6231121f9e19 | 535 | WriteReg(0, CB_CELL4_CTRL, 0x03, 1, FRMWRT_ALL_NR); // 3 minute balance timer to all but base device |
| dragica | 1:6231121f9e19 | 536 | WriteReg(0, CB_CELL5_CTRL, 0x03, 1, FRMWRT_ALL_NR); // 3 minute balance timer to all but base device |
| dragica | 1:6231121f9e19 | 537 | WriteReg(0, CB_CELL6_CTRL, 0x03, 1, FRMWRT_ALL_NR); // 3 minute balance timer to all but base device |
| dragica | 1:6231121f9e19 | 538 | |
| dragica | 1:6231121f9e19 | 539 | delayms(2); |
| dragica | 1:6231121f9e19 | 540 | //end init sequence |
| dragica | 1:6231121f9e19 | 541 | } |
| dragica | 1:6231121f9e19 | 542 | //*************************** |
| dragica | 1:6231121f9e19 | 543 | //END MISCELLANEOUS FUNCTIONS |
| dragica | 1:6231121f9e19 | 544 | //*************************** |
| dragica | 1:6231121f9e19 | 545 | //EOF |
| dragica | 1:6231121f9e19 | 546 |