Capstone / SX1276Lib_modtronix

SX1276 library for modtronix inair9. Edited for use with NRF51DK board.

Dependents:   InAir9_PingPong

Fork of SX1276Lib_modtronix by modtronix H

sx1276/sx1276.cpp@26:ad32782125eb, 2017-11-19 (annotated)

Committer:
AMNoll
Date:
Sun Nov 19 18:19:55 2017 +0000
Revision:
26:ad32782125eb
Parent:
25:72381be1b0ce 
latest version of pingpong on inair9

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
GregCr 8:0fe3e0e8007b 7 ( C )2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: Actual implementation of a SX1276 radio, inherits Radio
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
GregCr 0:e6ceb13d2d05 14 */
GregCr 0:e6ceb13d2d05 15 #include "sx1276.h"
GregCr 0:e6ceb13d2d05 16
AMNoll 26:ad32782125eb 17 Serial pc1(USBTX, USBRX);
AMNoll 26:ad32782125eb 18
GregCr 0:e6ceb13d2d05 19 const FskBandwidth_t SX1276::FskBandwidths[] =
GregCr 0:e6ceb13d2d05 20 {
GregCr 0:e6ceb13d2d05 21 { 2600 , 0x17 },
GregCr 0:e6ceb13d2d05 22 { 3100 , 0x0F },
GregCr 0:e6ceb13d2d05 23 { 3900 , 0x07 },
GregCr 0:e6ceb13d2d05 24 { 5200 , 0x16 },
GregCr 0:e6ceb13d2d05 25 { 6300 , 0x0E },
GregCr 0:e6ceb13d2d05 26 { 7800 , 0x06 },
GregCr 0:e6ceb13d2d05 27 { 10400 , 0x15 },
GregCr 0:e6ceb13d2d05 28 { 12500 , 0x0D },
GregCr 0:e6ceb13d2d05 29 { 15600 , 0x05 },
GregCr 0:e6ceb13d2d05 30 { 20800 , 0x14 },
GregCr 0:e6ceb13d2d05 31 { 25000 , 0x0C },
GregCr 0:e6ceb13d2d05 32 { 31300 , 0x04 },
GregCr 0:e6ceb13d2d05 33 { 41700 , 0x13 },
GregCr 0:e6ceb13d2d05 34 { 50000 , 0x0B },
GregCr 0:e6ceb13d2d05 35 { 62500 , 0x03 },
GregCr 0:e6ceb13d2d05 36 { 83333 , 0x12 },
GregCr 0:e6ceb13d2d05 37 { 100000, 0x0A },
GregCr 0:e6ceb13d2d05 38 { 125000, 0x02 },
GregCr 0:e6ceb13d2d05 39 { 166700, 0x11 },
GregCr 0:e6ceb13d2d05 40 { 200000, 0x09 },
mluis 15:04374b1c33fa 41 { 250000, 0x01 },
modtronix 20:7cf7c08f0088 42 { 300000, 0x00 }, // Invalid Badwidth
GregCr 0:e6ceb13d2d05 43 };
GregCr 0:e6ceb13d2d05 44
GregCr 0:e6ceb13d2d05 45
GregCr 7:2b555111463f 46 SX1276::SX1276( void ( *txDone )( ), void ( *txTimeout ) ( ), void ( *rxDone ) ( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr ),
mluis 13:618826a997e2 47 void ( *rxTimeout ) ( ), void ( *rxError ) ( ), void ( *fhssChangeChannel ) ( uint8_t channelIndex ), void ( *cadDone ) ( bool channelActivityDetected ),
mluis 13:618826a997e2 48 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
modtronix 25:72381be1b0ce 49 PinName dio0, PinName dio1, PinName dio2, PinName dio3/*, PinName dio4, PinName dio5*/)
mluis 13:618826a997e2 50 : Radio( txDone, txTimeout, rxDone, rxTimeout, rxError, fhssChangeChannel, cadDone ),
mluis 13:618826a997e2 51 spi( mosi, miso, sclk ),
mluis 13:618826a997e2 52 nss( nss ),
mluis 13:618826a997e2 53 reset( reset ),
modtronix 25:72381be1b0ce 54 dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), /*dio4( dio4 ), dio5( dio5 ),*/
mluis 13:618826a997e2 55 isRadioActive( false )
GregCr 0:e6ceb13d2d05 56 {
mluis 13:618826a997e2 57 wait_ms( 10 );
mluis 13:618826a997e2 58 this->rxTx = 0;
mluis 13:618826a997e2 59 this->rxBuffer = new uint8_t[RX_BUFFER_SIZE];
mluis 13:618826a997e2 60 previousOpMode = RF_OPMODE_STANDBY;
mluis 13:618826a997e2 61
mluis 13:618826a997e2 62 this->dioIrq = new DioIrqHandler[6];
GregCr 0:e6ceb13d2d05 63
mluis 13:618826a997e2 64 this->dioIrq[0] = &SX1276::OnDio0Irq;
mluis 13:618826a997e2 65 this->dioIrq[1] = &SX1276::OnDio1Irq;
mluis 13:618826a997e2 66 this->dioIrq[2] = &SX1276::OnDio2Irq;
modtronix 22:20db480143c9 67 //For SHD3I with BOARD_INAIR4 in imod3, on FRDM-KL25Z board. It uses A4 on FRDM-KL25Z board, which does not have interrupt
modtronix 18:cdb08d710838 68 #if( defined ( TARGET_KL25Z ) && defined(SHIELD_SHD3I_INAIR9) )
modtronix 18:cdb08d710838 69 this->dioIrq[3] = NULL;
modtronix 18:cdb08d710838 70 #else
mluis 13:618826a997e2 71 this->dioIrq[3] = &SX1276::OnDio3Irq;
modtronix 18:cdb08d710838 72 #endif
modtronix 25:72381be1b0ce 73 //this->dioIrq[4] = &SX1276::OnDio4Irq;
modtronix 25:72381be1b0ce 74 //this->dioIrq[5] = NULL;
mluis 13:618826a997e2 75
mluis 13:618826a997e2 76 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 77 }
GregCr 0:e6ceb13d2d05 78
GregCr 0:e6ceb13d2d05 79 SX1276::~SX1276( )
GregCr 0:e6ceb13d2d05 80 {
mluis 13:618826a997e2 81 delete this->rxBuffer;
mluis 13:618826a997e2 82 delete this->dioIrq;
GregCr 0:e6ceb13d2d05 83 }
GregCr 0:e6ceb13d2d05 84
modtronix 22:20db480143c9 85 uint8_t SX1276::GetBoardType( void )
modtronix 22:20db480143c9 86 {
modtronix 22:20db480143c9 87 return boardConnected;
modtronix 22:20db480143c9 88 }
modtronix 22:20db480143c9 89
modtronix 22:20db480143c9 90 void SX1276::SetBoardType( uint8_t boardType)
modtronix 22:20db480143c9 91 {
modtronix 22:20db480143c9 92 boardConnected = boardType;
modtronix 22:20db480143c9 93 }
modtronix 22:20db480143c9 94
GregCr 0:e6ceb13d2d05 95 void SX1276::RxChainCalibration( void )
GregCr 0:e6ceb13d2d05 96 {
GregCr 0:e6ceb13d2d05 97 uint8_t regPaConfigInitVal;
GregCr 0:e6ceb13d2d05 98 uint32_t initialFreq;
GregCr 0:e6ceb13d2d05 99
GregCr 0:e6ceb13d2d05 100 // Save context
GregCr 0:e6ceb13d2d05 101 regPaConfigInitVal = this->Read( REG_PACONFIG );
GregCr 0:e6ceb13d2d05 102 initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) |
GregCr 0:e6ceb13d2d05 103 ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) |
GregCr 0:e6ceb13d2d05 104 ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
GregCr 0:e6ceb13d2d05 105
GregCr 0:e6ceb13d2d05 106 // Cut the PA just in case, RFO output, power = -1 dBm
GregCr 0:e6ceb13d2d05 107 this->Write( REG_PACONFIG, 0x00 );
GregCr 0:e6ceb13d2d05 108
GregCr 0:e6ceb13d2d05 109 // Launch Rx chain calibration for LF band
GregCr 0:e6ceb13d2d05 110 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
GregCr 0:e6ceb13d2d05 111 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
GregCr 0:e6ceb13d2d05 112 {
GregCr 0:e6ceb13d2d05 113 }
GregCr 0:e6ceb13d2d05 114
GregCr 0:e6ceb13d2d05 115 // Sets a Frequency in HF band
GregCr 0:e6ceb13d2d05 116 settings.Channel= 868000000 ;
GregCr 0:e6ceb13d2d05 117
GregCr 0:e6ceb13d2d05 118 // Launch Rx chain calibration for HF band
GregCr 0:e6ceb13d2d05 119 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
GregCr 0:e6ceb13d2d05 120 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
GregCr 0:e6ceb13d2d05 121 {
GregCr 0:e6ceb13d2d05 122 }
GregCr 0:e6ceb13d2d05 123
GregCr 0:e6ceb13d2d05 124 // Restore context
GregCr 0:e6ceb13d2d05 125 this->Write( REG_PACONFIG, regPaConfigInitVal );
GregCr 0:e6ceb13d2d05 126 SetChannel( initialFreq );
GregCr 0:e6ceb13d2d05 127 }
GregCr 0:e6ceb13d2d05 128
GregCr 0:e6ceb13d2d05 129 RadioState SX1276::GetState( void )
GregCr 0:e6ceb13d2d05 130 {
GregCr 0:e6ceb13d2d05 131 return this->settings.State;
GregCr 0:e6ceb13d2d05 132 }
GregCr 0:e6ceb13d2d05 133
GregCr 0:e6ceb13d2d05 134 void SX1276::SetChannel( uint32_t freq )
GregCr 0:e6ceb13d2d05 135 {
GregCr 0:e6ceb13d2d05 136 this->settings.Channel = freq;
GregCr 0:e6ceb13d2d05 137 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 138 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 139 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 140 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
GregCr 0:e6ceb13d2d05 141 }
GregCr 0:e6ceb13d2d05 142
GregCr 0:e6ceb13d2d05 143 bool SX1276::IsChannelFree( ModemType modem, uint32_t freq, int8_t rssiThresh )
GregCr 0:e6ceb13d2d05 144 {
GregCr 7:2b555111463f 145 int16_t rssi = 0;
GregCr 0:e6ceb13d2d05 146
GregCr 0:e6ceb13d2d05 147 SetModem( modem );
GregCr 0:e6ceb13d2d05 148
GregCr 0:e6ceb13d2d05 149 SetChannel( freq );
GregCr 0:e6ceb13d2d05 150
GregCr 0:e6ceb13d2d05 151 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 152
GregCr 4:f0ce52e94d3f 153 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 154
GregCr 0:e6ceb13d2d05 155 rssi = GetRssi( modem );
GregCr 0:e6ceb13d2d05 156
GregCr 0:e6ceb13d2d05 157 Sleep( );
GregCr 0:e6ceb13d2d05 158
GregCr 7:2b555111463f 159 if( rssi > ( int16_t )rssiThresh )
GregCr 0:e6ceb13d2d05 160 {
GregCr 0:e6ceb13d2d05 161 return false;
GregCr 0:e6ceb13d2d05 162 }
GregCr 0:e6ceb13d2d05 163 return true;
GregCr 0:e6ceb13d2d05 164 }
GregCr 0:e6ceb13d2d05 165
GregCr 0:e6ceb13d2d05 166 uint32_t SX1276::Random( void )
GregCr 0:e6ceb13d2d05 167 {
GregCr 0:e6ceb13d2d05 168 uint8_t i;
GregCr 0:e6ceb13d2d05 169 uint32_t rnd = 0;
GregCr 0:e6ceb13d2d05 170
GregCr 0:e6ceb13d2d05 171 /*
GregCr 0:e6ceb13d2d05 172 * Radio setup for random number generation
GregCr 0:e6ceb13d2d05 173 */
GregCr 0:e6ceb13d2d05 174 // Set LoRa modem ON
GregCr 0:e6ceb13d2d05 175 SetModem( MODEM_LORA );
GregCr 0:e6ceb13d2d05 176
GregCr 0:e6ceb13d2d05 177 // Disable LoRa modem interrupts
GregCr 0:e6ceb13d2d05 178 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 179 RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 180 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 0:e6ceb13d2d05 181 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 182 RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 183 RFLR_IRQFLAGS_CADDONE |
GregCr 0:e6ceb13d2d05 184 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 185 RFLR_IRQFLAGS_CADDETECTED );
GregCr 0:e6ceb13d2d05 186
GregCr 0:e6ceb13d2d05 187 // Set radio in continuous reception
GregCr 0:e6ceb13d2d05 188 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 189
GregCr 0:e6ceb13d2d05 190 for( i = 0; i < 32; i++ )
GregCr 0:e6ceb13d2d05 191 {
GregCr 4:f0ce52e94d3f 192 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 193 // Unfiltered RSSI value reading. Only takes the LSB value
GregCr 0:e6ceb13d2d05 194 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
GregCr 0:e6ceb13d2d05 195 }
GregCr 0:e6ceb13d2d05 196
GregCr 0:e6ceb13d2d05 197 Sleep( );
GregCr 0:e6ceb13d2d05 198
GregCr 0:e6ceb13d2d05 199 return rnd;
GregCr 0:e6ceb13d2d05 200 }
GregCr 0:e6ceb13d2d05 201
GregCr 0:e6ceb13d2d05 202 /*!
GregCr 0:e6ceb13d2d05 203 * Returns the known FSK bandwidth registers value
GregCr 0:e6ceb13d2d05 204 *
GregCr 0:e6ceb13d2d05 205 * \param [IN] bandwidth Bandwidth value in Hz
GregCr 0:e6ceb13d2d05 206 * \retval regValue Bandwidth register value.
GregCr 0:e6ceb13d2d05 207 */
GregCr 0:e6ceb13d2d05 208 uint8_t SX1276::GetFskBandwidthRegValue( uint32_t bandwidth )
GregCr 0:e6ceb13d2d05 209 {
GregCr 0:e6ceb13d2d05 210 uint8_t i;
GregCr 0:e6ceb13d2d05 211
GregCr 0:e6ceb13d2d05 212 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
GregCr 0:e6ceb13d2d05 213 {
GregCr 0:e6ceb13d2d05 214 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
GregCr 0:e6ceb13d2d05 215 {
GregCr 0:e6ceb13d2d05 216 return FskBandwidths[i].RegValue;
GregCr 0:e6ceb13d2d05 217 }
GregCr 0:e6ceb13d2d05 218 }
GregCr 0:e6ceb13d2d05 219 // ERROR: Value not found
GregCr 0:e6ceb13d2d05 220 while( 1 );
GregCr 0:e6ceb13d2d05 221 }
GregCr 0:e6ceb13d2d05 222
GregCr 0:e6ceb13d2d05 223 void SX1276::SetRxConfig( ModemType modem, uint32_t bandwidth,
GregCr 0:e6ceb13d2d05 224 uint32_t datarate, uint8_t coderate,
GregCr 0:e6ceb13d2d05 225 uint32_t bandwidthAfc, uint16_t preambleLen,
GregCr 0:e6ceb13d2d05 226 uint16_t symbTimeout, bool fixLen,
mluis 13:618826a997e2 227 uint8_t payloadLen,
mluis 13:618826a997e2 228 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
GregCr 6:e7f02929cd3d 229 bool iqInverted, bool rxContinuous )
GregCr 0:e6ceb13d2d05 230 {
GregCr 0:e6ceb13d2d05 231 SetModem( modem );
GregCr 0:e6ceb13d2d05 232
GregCr 0:e6ceb13d2d05 233 switch( modem )
GregCr 0:e6ceb13d2d05 234 {
GregCr 0:e6ceb13d2d05 235 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 236 {
GregCr 0:e6ceb13d2d05 237 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 238 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 239 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
GregCr 0:e6ceb13d2d05 240 this->settings.Fsk.FixLen = fixLen;
mluis 13:618826a997e2 241 this->settings.Fsk.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 242 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 243 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 244 this->settings.Fsk.RxContinuous = rxContinuous;
GregCr 0:e6ceb13d2d05 245 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 246
GregCr 0:e6ceb13d2d05 247 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 248 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 249 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 250
GregCr 0:e6ceb13d2d05 251 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
GregCr 0:e6ceb13d2d05 252 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
GregCr 0:e6ceb13d2d05 253
mluis 14:8552d0b840be 254 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
mluis 14:8552d0b840be 255 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
GregCr 0:e6ceb13d2d05 256
GregCr 0:e6ceb13d2d05 257 Write( REG_PACKETCONFIG1,
GregCr 0:e6ceb13d2d05 258 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 259 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 260 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 261 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 262 ( crcOn << 4 ) );
mluis 13:618826a997e2 263 if( fixLen == 1 )
mluis 13:618826a997e2 264 {
mluis 13:618826a997e2 265 Write( REG_PAYLOADLENGTH, payloadLen );
mluis 13:618826a997e2 266 }
GregCr 0:e6ceb13d2d05 267 }
GregCr 0:e6ceb13d2d05 268 break;
GregCr 0:e6ceb13d2d05 269 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 270 {
modtronix 16:0927c093fd82 271 if( bandwidth > 9 )
GregCr 0:e6ceb13d2d05 272 {
modtronix 16:0927c093fd82 273 // Fatal error: Bandwidth must be 0-9 (7.8 - 500khz)
GregCr 0:e6ceb13d2d05 274 while( 1 );
GregCr 0:e6ceb13d2d05 275 }
modtronix 16:0927c093fd82 276 //bandwidth += 7; //Changed bandwidth from 0-2 to 0-10
GregCr 0:e6ceb13d2d05 277 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 278 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 279 this->settings.LoRa.Coderate = coderate;
GregCr 0:e6ceb13d2d05 280 this->settings.LoRa.FixLen = fixLen;
mluis 13:618826a997e2 281 this->settings.LoRa.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 282 this->settings.LoRa.CrcOn = crcOn;
mluis 13:618826a997e2 283 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 284 this->settings.LoRa.HopPeriod = hopPeriod;
GregCr 0:e6ceb13d2d05 285 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 286 this->settings.LoRa.RxContinuous = rxContinuous;
mluis 13:618826a997e2 287
GregCr 0:e6ceb13d2d05 288 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 289 {
GregCr 0:e6ceb13d2d05 290 datarate = 12;
GregCr 0:e6ceb13d2d05 291 }
GregCr 0:e6ceb13d2d05 292 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 293 {
GregCr 0:e6ceb13d2d05 294 datarate = 6;
GregCr 0:e6ceb13d2d05 295 }
GregCr 0:e6ceb13d2d05 296
modtronix 20:7cf7c08f0088 297 //bandwidth 6=62.5, 7=125, 8=250, 9=500, datarate=SF. LowDatarateOptimize is mandatory when symbol length > 16ms
modtronix 20:7cf7c08f0088 298 //LowDatarateOptimize = 0 when (BW=500) or (BW=250 and SF=12), else it is ON (Tsym > 16ms)
modtronix 20:7cf7c08f0088 299 if( ( ( bandwidth == 8 ) && ( datarate == 12 ) ) ||
modtronix 20:7cf7c08f0088 300 ( ( bandwidth == 7 ) && ( datarate > 10 ) ) ||
modtronix 20:7cf7c08f0088 301 ( ( bandwidth == 6 ) && ( datarate > 9 ) ) ||
modtronix 20:7cf7c08f0088 302 ( ( bandwidth == 5 ) && ( datarate > 9 ) ) ||
modtronix 20:7cf7c08f0088 303 ( ( bandwidth == 4 ) && ( datarate > 8 ) ) || ( bandwidth < 4 )
modtronix 20:7cf7c08f0088 304 //The below is actually correct method, but assume BW = 20.8 and lower will always have SF > 8
modtronix 20:7cf7c08f0088 305 // ( ( bandwidth == 3 ) && ( datarate > 8 ) ) ||
modtronix 20:7cf7c08f0088 306 // ( ( bandwidth == 2 ) && ( datarate > 7 ) ) ||
modtronix 20:7cf7c08f0088 307 // ( ( bandwidth == 1 ) && ( datarate > 7 ) ) ||
modtronix 20:7cf7c08f0088 308 // ( ( bandwidth == 0 ) && ( datarate > 6 ) )
modtronix 20:7cf7c08f0088 309 )
GregCr 0:e6ceb13d2d05 310 {
GregCr 0:e6ceb13d2d05 311 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 312 }
GregCr 0:e6ceb13d2d05 313 else
GregCr 0:e6ceb13d2d05 314 {
GregCr 0:e6ceb13d2d05 315 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 316 }
GregCr 0:e6ceb13d2d05 317
GregCr 0:e6ceb13d2d05 318 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 319 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 320 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 321 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 322 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
GregCr 0:e6ceb13d2d05 323 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 324 fixLen );
GregCr 0:e6ceb13d2d05 325
GregCr 0:e6ceb13d2d05 326 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 327 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 328 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 329 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
GregCr 0:e6ceb13d2d05 330 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
GregCr 0:e6ceb13d2d05 331 ( datarate << 4 ) | ( crcOn << 2 ) |
GregCr 0:e6ceb13d2d05 332 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
GregCr 0:e6ceb13d2d05 333
GregCr 0:e6ceb13d2d05 334 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 335 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 336 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 337 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
GregCr 0:e6ceb13d2d05 338
GregCr 0:e6ceb13d2d05 339 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
GregCr 0:e6ceb13d2d05 340
GregCr 0:e6ceb13d2d05 341 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 342 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
GregCr 0:e6ceb13d2d05 343
mluis 13:618826a997e2 344 if( fixLen == 1 )
mluis 13:618826a997e2 345 {
mluis 13:618826a997e2 346 Write( REG_LR_PAYLOADLENGTH, payloadLen );
mluis 13:618826a997e2 347 }
mluis 13:618826a997e2 348
GregCr 6:e7f02929cd3d 349 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 350 {
GregCr 6:e7f02929cd3d 351 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 352 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 353 }
GregCr 6:e7f02929cd3d 354
GregCr 0:e6ceb13d2d05 355 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 356 {
GregCr 0:e6ceb13d2d05 357 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 358 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 359 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 360 RFLR_DETECTIONOPTIMIZE_SF6 );
GregCr 0:e6ceb13d2d05 361 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 362 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 363 }
GregCr 0:e6ceb13d2d05 364 else
GregCr 0:e6ceb13d2d05 365 {
GregCr 0:e6ceb13d2d05 366 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 367 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 368 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 369 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 370 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 371 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 372 }
GregCr 0:e6ceb13d2d05 373 }
GregCr 0:e6ceb13d2d05 374 break;
GregCr 0:e6ceb13d2d05 375 }
GregCr 0:e6ceb13d2d05 376 }
GregCr 0:e6ceb13d2d05 377
GregCr 0:e6ceb13d2d05 378 void SX1276::SetTxConfig( ModemType modem, int8_t power, uint32_t fdev,
GregCr 0:e6ceb13d2d05 379 uint32_t bandwidth, uint32_t datarate,
GregCr 0:e6ceb13d2d05 380 uint8_t coderate, uint16_t preambleLen,
mluis 13:618826a997e2 381 bool fixLen, bool crcOn, bool freqHopOn,
mluis 13:618826a997e2 382 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
GregCr 0:e6ceb13d2d05 383 {
GregCr 0:e6ceb13d2d05 384 uint8_t paConfig = 0;
GregCr 0:e6ceb13d2d05 385 uint8_t paDac = 0;
GregCr 0:e6ceb13d2d05 386
GregCr 0:e6ceb13d2d05 387 SetModem( modem );
GregCr 0:e6ceb13d2d05 388
GregCr 0:e6ceb13d2d05 389 paConfig = Read( REG_PACONFIG );
GregCr 0:e6ceb13d2d05 390 paDac = Read( REG_PADAC );
GregCr 0:e6ceb13d2d05 391
GregCr 0:e6ceb13d2d05 392 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
GregCr 0:e6ceb13d2d05 393 paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
GregCr 0:e6ceb13d2d05 394
GregCr 0:e6ceb13d2d05 395 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
GregCr 0:e6ceb13d2d05 396 {
GregCr 0:e6ceb13d2d05 397 if( power > 17 )
GregCr 0:e6ceb13d2d05 398 {
GregCr 0:e6ceb13d2d05 399 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
GregCr 0:e6ceb13d2d05 400 }
GregCr 0:e6ceb13d2d05 401 else
GregCr 0:e6ceb13d2d05 402 {
GregCr 0:e6ceb13d2d05 403 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
GregCr 0:e6ceb13d2d05 404 }
GregCr 0:e6ceb13d2d05 405 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
GregCr 0:e6ceb13d2d05 406 {
GregCr 0:e6ceb13d2d05 407 if( power < 5 )
GregCr 0:e6ceb13d2d05 408 {
GregCr 0:e6ceb13d2d05 409 power = 5;
GregCr 0:e6ceb13d2d05 410 }
GregCr 0:e6ceb13d2d05 411 if( power > 20 )
GregCr 0:e6ceb13d2d05 412 {
GregCr 0:e6ceb13d2d05 413 power = 20;
GregCr 0:e6ceb13d2d05 414 }
GregCr 0:e6ceb13d2d05 415 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
GregCr 0:e6ceb13d2d05 416 }
GregCr 0:e6ceb13d2d05 417 else
GregCr 0:e6ceb13d2d05 418 {
GregCr 0:e6ceb13d2d05 419 if( power < 2 )
GregCr 0:e6ceb13d2d05 420 {
GregCr 0:e6ceb13d2d05 421 power = 2;
GregCr 0:e6ceb13d2d05 422 }
GregCr 0:e6ceb13d2d05 423 if( power > 17 )
GregCr 0:e6ceb13d2d05 424 {
GregCr 0:e6ceb13d2d05 425 power = 17;
GregCr 0:e6ceb13d2d05 426 }
GregCr 0:e6ceb13d2d05 427 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
GregCr 0:e6ceb13d2d05 428 }
GregCr 0:e6ceb13d2d05 429 }
GregCr 0:e6ceb13d2d05 430 else
GregCr 0:e6ceb13d2d05 431 {
GregCr 0:e6ceb13d2d05 432 if( power < -1 )
GregCr 0:e6ceb13d2d05 433 {
GregCr 0:e6ceb13d2d05 434 power = -1;
GregCr 0:e6ceb13d2d05 435 }
GregCr 0:e6ceb13d2d05 436 if( power > 14 )
GregCr 0:e6ceb13d2d05 437 {
GregCr 0:e6ceb13d2d05 438 power = 14;
GregCr 0:e6ceb13d2d05 439 }
GregCr 0:e6ceb13d2d05 440 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
GregCr 0:e6ceb13d2d05 441 }
GregCr 0:e6ceb13d2d05 442 Write( REG_PACONFIG, paConfig );
GregCr 0:e6ceb13d2d05 443 Write( REG_PADAC, paDac );
GregCr 0:e6ceb13d2d05 444
GregCr 0:e6ceb13d2d05 445 switch( modem )
GregCr 0:e6ceb13d2d05 446 {
GregCr 0:e6ceb13d2d05 447 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 448 {
GregCr 0:e6ceb13d2d05 449 this->settings.Fsk.Power = power;
GregCr 0:e6ceb13d2d05 450 this->settings.Fsk.Fdev = fdev;
GregCr 0:e6ceb13d2d05 451 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 452 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 453 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 454 this->settings.Fsk.FixLen = fixLen;
GregCr 0:e6ceb13d2d05 455 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 456 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 457 this->settings.Fsk.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 458
GregCr 0:e6ceb13d2d05 459 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 460 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
GregCr 0:e6ceb13d2d05 461 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
GregCr 0:e6ceb13d2d05 462
GregCr 0:e6ceb13d2d05 463 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 464 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 465 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 466
GregCr 0:e6ceb13d2d05 467 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 468 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 469
GregCr 0:e6ceb13d2d05 470 Write( REG_PACKETCONFIG1,
GregCr 0:e6ceb13d2d05 471 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 472 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 473 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 474 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 475 ( crcOn << 4 ) );
GregCr 0:e6ceb13d2d05 476 }
GregCr 0:e6ceb13d2d05 477 break;
GregCr 0:e6ceb13d2d05 478 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 479 {
GregCr 0:e6ceb13d2d05 480 this->settings.LoRa.Power = power;
modtronix 16:0927c093fd82 481 if( bandwidth > 9 )
GregCr 0:e6ceb13d2d05 482 {
modtronix 16:0927c093fd82 483 // Fatal error: Bandwidth must be 0-9 (7.8 - 500khz)
GregCr 0:e6ceb13d2d05 484 while( 1 );
GregCr 0:e6ceb13d2d05 485 }
modtronix 16:0927c093fd82 486 //bandwidth += 7;
GregCr 0:e6ceb13d2d05 487 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 488 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 489 this->settings.LoRa.Coderate = coderate;
GregCr 0:e6ceb13d2d05 490 this->settings.LoRa.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 491 this->settings.LoRa.FixLen = fixLen;
GregCr 0:e6ceb13d2d05 492 this->settings.LoRa.CrcOn = crcOn;
mluis 13:618826a997e2 493 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 494 this->settings.LoRa.HopPeriod = hopPeriod;
GregCr 0:e6ceb13d2d05 495 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 496 this->settings.LoRa.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 497
GregCr 0:e6ceb13d2d05 498 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 499 {
GregCr 0:e6ceb13d2d05 500 datarate = 12;
GregCr 0:e6ceb13d2d05 501 }
GregCr 0:e6ceb13d2d05 502 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 503 {
GregCr 0:e6ceb13d2d05 504 datarate = 6;
GregCr 0:e6ceb13d2d05 505 }
modtronix 20:7cf7c08f0088 506 //bandwidth 6=62.5, 7=125, 8=250, 9=500, datarate=SF. LowDatarateOptimize is mandatory when symbol length > 16ms
modtronix 20:7cf7c08f0088 507 //LowDatarateOptimize = 0 when (BW=500) or (BW=250 and SF=12), else it is ON (Tsym > 16ms)
modtronix 20:7cf7c08f0088 508 if( ( ( bandwidth == 8 ) && ( datarate == 12 ) ) ||
modtronix 20:7cf7c08f0088 509 ( ( bandwidth == 7 ) && ( datarate > 10 ) ) ||
modtronix 20:7cf7c08f0088 510 ( ( bandwidth == 6 ) && ( datarate > 9 ) ) ||
modtronix 20:7cf7c08f0088 511 ( ( bandwidth == 5 ) && ( datarate > 9 ) ) ||
modtronix 20:7cf7c08f0088 512 ( ( bandwidth == 4 ) && ( datarate > 8 ) ) || ( bandwidth < 4 )
modtronix 20:7cf7c08f0088 513 //The below is actually correct method, but assume BW = 20.8 and lower will always have SF > 8
modtronix 20:7cf7c08f0088 514 // ( ( bandwidth == 3 ) && ( datarate > 8 ) ) ||
modtronix 20:7cf7c08f0088 515 // ( ( bandwidth == 2 ) && ( datarate > 7 ) ) ||
modtronix 20:7cf7c08f0088 516 // ( ( bandwidth == 1 ) && ( datarate > 7 ) ) ||
modtronix 20:7cf7c08f0088 517 // ( ( bandwidth == 0 ) && ( datarate > 6 ) )
modtronix 20:7cf7c08f0088 518 )
GregCr 0:e6ceb13d2d05 519 {
GregCr 0:e6ceb13d2d05 520 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 521 }
GregCr 0:e6ceb13d2d05 522 else
GregCr 0:e6ceb13d2d05 523 {
GregCr 0:e6ceb13d2d05 524 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 525 }
GregCr 6:e7f02929cd3d 526
GregCr 6:e7f02929cd3d 527 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 528 {
GregCr 6:e7f02929cd3d 529 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 530 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 531 }
GregCr 6:e7f02929cd3d 532
GregCr 0:e6ceb13d2d05 533 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 534 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 535 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 536 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 537 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
GregCr 0:e6ceb13d2d05 538 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 539 fixLen );
GregCr 0:e6ceb13d2d05 540
GregCr 0:e6ceb13d2d05 541 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 542 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 543 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 544 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) |
GregCr 0:e6ceb13d2d05 545 ( datarate << 4 ) | ( crcOn << 2 ) );
GregCr 0:e6ceb13d2d05 546
GregCr 0:e6ceb13d2d05 547 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 548 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 549 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 550 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
GregCr 0:e6ceb13d2d05 551
GregCr 0:e6ceb13d2d05 552 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 553 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 554
GregCr 0:e6ceb13d2d05 555 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 556 {
GregCr 0:e6ceb13d2d05 557 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 558 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 559 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 560 RFLR_DETECTIONOPTIMIZE_SF6 );
GregCr 0:e6ceb13d2d05 561 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 562 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 563 }
GregCr 0:e6ceb13d2d05 564 else
GregCr 0:e6ceb13d2d05 565 {
GregCr 0:e6ceb13d2d05 566 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 567 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 568 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 569 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 570 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 571 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 572 }
GregCr 0:e6ceb13d2d05 573 }
GregCr 0:e6ceb13d2d05 574 break;
GregCr 0:e6ceb13d2d05 575 }
GregCr 0:e6ceb13d2d05 576 }
GregCr 0:e6ceb13d2d05 577
GregCr 0:e6ceb13d2d05 578 double SX1276::TimeOnAir( ModemType modem, uint8_t pktLen )
GregCr 0:e6ceb13d2d05 579 {
GregCr 0:e6ceb13d2d05 580 double airTime = 0.0;
GregCr 0:e6ceb13d2d05 581
GregCr 0:e6ceb13d2d05 582 switch( modem )
GregCr 0:e6ceb13d2d05 583 {
GregCr 0:e6ceb13d2d05 584 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 585 {
GregCr 4:f0ce52e94d3f 586 airTime = ceil( ( 8 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 587 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
GregCr 0:e6ceb13d2d05 588 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
GregCr 0:e6ceb13d2d05 589 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
GregCr 0:e6ceb13d2d05 590 pktLen +
GregCr 0:e6ceb13d2d05 591 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
GregCr 0:e6ceb13d2d05 592 this->settings.Fsk.Datarate ) * 1e6 );
GregCr 0:e6ceb13d2d05 593 }
GregCr 0:e6ceb13d2d05 594 break;
GregCr 0:e6ceb13d2d05 595 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 596 {
GregCr 0:e6ceb13d2d05 597 double bw = 0.0;
GregCr 0:e6ceb13d2d05 598 switch( this->settings.LoRa.Bandwidth )
GregCr 0:e6ceb13d2d05 599 {
modtronix 16:0927c093fd82 600 case 0: // 7.8 kHz
modtronix 16:0927c093fd82 601 bw = 78e2;
modtronix 16:0927c093fd82 602 break;
modtronix 16:0927c093fd82 603 case 1: // 10.4 kHz
modtronix 16:0927c093fd82 604 bw = 104e2;
modtronix 16:0927c093fd82 605 break;
modtronix 16:0927c093fd82 606 case 2: // 15.6 kHz
modtronix 16:0927c093fd82 607 bw = 156e2;
modtronix 16:0927c093fd82 608 break;
modtronix 16:0927c093fd82 609 case 3: // 20.8 kHz
modtronix 16:0927c093fd82 610 bw = 208e2;
modtronix 16:0927c093fd82 611 break;
modtronix 16:0927c093fd82 612 case 4: // 31.2 kHz
modtronix 16:0927c093fd82 613 bw = 312e2;
modtronix 16:0927c093fd82 614 break;
modtronix 16:0927c093fd82 615 case 5: // 41.4 kHz
modtronix 16:0927c093fd82 616 bw = 414e2;
modtronix 16:0927c093fd82 617 break;
modtronix 16:0927c093fd82 618 case 6: // 62.5 kHz
modtronix 16:0927c093fd82 619 bw = 625e2;
modtronix 16:0927c093fd82 620 break;
GregCr 0:e6ceb13d2d05 621 case 7: // 125 kHz
GregCr 0:e6ceb13d2d05 622 bw = 125e3;
GregCr 0:e6ceb13d2d05 623 break;
GregCr 0:e6ceb13d2d05 624 case 8: // 250 kHz
GregCr 0:e6ceb13d2d05 625 bw = 250e3;
GregCr 0:e6ceb13d2d05 626 break;
GregCr 0:e6ceb13d2d05 627 case 9: // 500 kHz
GregCr 0:e6ceb13d2d05 628 bw = 500e3;
GregCr 0:e6ceb13d2d05 629 break;
GregCr 0:e6ceb13d2d05 630 }
GregCr 0:e6ceb13d2d05 631
GregCr 0:e6ceb13d2d05 632 // Symbol rate : time for one symbol (secs)
GregCr 0:e6ceb13d2d05 633 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
GregCr 0:e6ceb13d2d05 634 double ts = 1 / rs;
GregCr 0:e6ceb13d2d05 635 // time of preamble
GregCr 0:e6ceb13d2d05 636 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
GregCr 0:e6ceb13d2d05 637 // Symbol length of payload and time
GregCr 0:e6ceb13d2d05 638 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
GregCr 0:e6ceb13d2d05 639 28 + 16 * this->settings.LoRa.CrcOn -
GregCr 0:e6ceb13d2d05 640 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
GregCr 0:e6ceb13d2d05 641 ( double )( 4 * this->settings.LoRa.Datarate -
GregCr 0:e6ceb13d2d05 642 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 8 : 0 ) ) ) *
GregCr 0:e6ceb13d2d05 643 ( this->settings.LoRa.Coderate + 4 );
GregCr 0:e6ceb13d2d05 644 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
GregCr 0:e6ceb13d2d05 645 double tPayload = nPayload * ts;
GregCr 0:e6ceb13d2d05 646 // Time on air
GregCr 0:e6ceb13d2d05 647 double tOnAir = tPreamble + tPayload;
GregCr 0:e6ceb13d2d05 648 // return us secs
GregCr 0:e6ceb13d2d05 649 airTime = floor( tOnAir * 1e6 + 0.999 );
GregCr 0:e6ceb13d2d05 650 }
GregCr 0:e6ceb13d2d05 651 break;
GregCr 0:e6ceb13d2d05 652 }
GregCr 0:e6ceb13d2d05 653 return airTime;
GregCr 0:e6ceb13d2d05 654 }
GregCr 0:e6ceb13d2d05 655
GregCr 0:e6ceb13d2d05 656 void SX1276::Send( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 657 {
GregCr 0:e6ceb13d2d05 658 uint32_t txTimeout = 0;
GregCr 0:e6ceb13d2d05 659
GregCr 5:11ec8a6ba4f0 660 this->settings.State = IDLE;
GregCr 5:11ec8a6ba4f0 661
GregCr 0:e6ceb13d2d05 662 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 663 {
GregCr 0:e6ceb13d2d05 664 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 665 {
GregCr 0:e6ceb13d2d05 666 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 667 this->settings.FskPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 668
GregCr 0:e6ceb13d2d05 669 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 670 {
GregCr 0:e6ceb13d2d05 671 WriteFifo( ( uint8_t* )&size, 1 );
GregCr 0:e6ceb13d2d05 672 }
GregCr 0:e6ceb13d2d05 673 else
GregCr 0:e6ceb13d2d05 674 {
GregCr 0:e6ceb13d2d05 675 Write( REG_PAYLOADLENGTH, size );
GregCr 0:e6ceb13d2d05 676 }
GregCr 0:e6ceb13d2d05 677
GregCr 0:e6ceb13d2d05 678 if( ( size > 0 ) && ( size <= 64 ) )
GregCr 0:e6ceb13d2d05 679 {
GregCr 0:e6ceb13d2d05 680 this->settings.FskPacketHandler.ChunkSize = size;
GregCr 0:e6ceb13d2d05 681 }
GregCr 0:e6ceb13d2d05 682 else
GregCr 0:e6ceb13d2d05 683 {
GregCr 0:e6ceb13d2d05 684 this->settings.FskPacketHandler.ChunkSize = 32;
GregCr 0:e6ceb13d2d05 685 }
GregCr 0:e6ceb13d2d05 686
GregCr 0:e6ceb13d2d05 687 // Write payload buffer
GregCr 0:e6ceb13d2d05 688 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 689 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 690 txTimeout = this->settings.Fsk.TxTimeout;
GregCr 0:e6ceb13d2d05 691 }
GregCr 0:e6ceb13d2d05 692 break;
GregCr 0:e6ceb13d2d05 693 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 694 {
GregCr 0:e6ceb13d2d05 695 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 696 {
GregCr 0:e6ceb13d2d05 697 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
GregCr 0:e6ceb13d2d05 698 }
GregCr 0:e6ceb13d2d05 699 else
GregCr 0:e6ceb13d2d05 700 {
GregCr 0:e6ceb13d2d05 701 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
GregCr 0:e6ceb13d2d05 702 }
GregCr 0:e6ceb13d2d05 703
GregCr 0:e6ceb13d2d05 704 this->settings.LoRaPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 705
GregCr 0:e6ceb13d2d05 706 // Initializes the payload size
GregCr 0:e6ceb13d2d05 707 Write( REG_LR_PAYLOADLENGTH, size );
GregCr 0:e6ceb13d2d05 708
GregCr 0:e6ceb13d2d05 709 // Full buffer used for Tx
GregCr 0:e6ceb13d2d05 710 Write( REG_LR_FIFOTXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 711 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 712
GregCr 0:e6ceb13d2d05 713 // FIFO operations can not take place in Sleep mode
GregCr 0:e6ceb13d2d05 714 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 715 {
GregCr 0:e6ceb13d2d05 716 Standby( );
GregCr 4:f0ce52e94d3f 717 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 718 }
GregCr 0:e6ceb13d2d05 719 // Write payload buffer
GregCr 0:e6ceb13d2d05 720 WriteFifo( buffer, size );
GregCr 0:e6ceb13d2d05 721 txTimeout = this->settings.LoRa.TxTimeout;
GregCr 0:e6ceb13d2d05 722 }
GregCr 0:e6ceb13d2d05 723 break;
GregCr 0:e6ceb13d2d05 724 }
GregCr 0:e6ceb13d2d05 725
GregCr 0:e6ceb13d2d05 726 Tx( txTimeout );
GregCr 0:e6ceb13d2d05 727 }
GregCr 0:e6ceb13d2d05 728
GregCr 0:e6ceb13d2d05 729 void SX1276::Sleep( void )
GregCr 0:e6ceb13d2d05 730 {
mluis 13:618826a997e2 731 // Initialize driver timeout timers
mluis 13:618826a997e2 732 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 733 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 734 SetOpMode( RF_OPMODE_SLEEP );
GregCr 0:e6ceb13d2d05 735 }
GregCr 0:e6ceb13d2d05 736
GregCr 0:e6ceb13d2d05 737 void SX1276::Standby( void )
GregCr 0:e6ceb13d2d05 738 {
GregCr 0:e6ceb13d2d05 739 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 740 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 741 SetOpMode( RF_OPMODE_STANDBY );
GregCr 0:e6ceb13d2d05 742 }
GregCr 0:e6ceb13d2d05 743
GregCr 0:e6ceb13d2d05 744 void SX1276::Rx( uint32_t timeout )
GregCr 0:e6ceb13d2d05 745 {
AMNoll 26:ad32782125eb 746 // configure uart port
AMNoll 26:ad32782125eb 747 pc1.baud(9600);
AMNoll 26:ad32782125eb 748 pc1.format(8, SerialBase::None, 1);
AMNoll 26:ad32782125eb 749 pc1.printf("PC printing enabled\n\r");
AMNoll 26:ad32782125eb 750 wait(2);
AMNoll 26:ad32782125eb 751
GregCr 0:e6ceb13d2d05 752 bool rxContinuous = false;
GregCr 6:e7f02929cd3d 753
GregCr 0:e6ceb13d2d05 754 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 755 {
GregCr 0:e6ceb13d2d05 756 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 757 {
GregCr 0:e6ceb13d2d05 758 rxContinuous = this->settings.Fsk.RxContinuous;
GregCr 0:e6ceb13d2d05 759
GregCr 0:e6ceb13d2d05 760 // DIO0=PayloadReady
GregCr 0:e6ceb13d2d05 761 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 762 // DIO2=SyncAddr
GregCr 0:e6ceb13d2d05 763 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 764 // DIO4=Preamble
GregCr 0:e6ceb13d2d05 765 // DIO5=ModeReady
GregCr 5:11ec8a6ba4f0 766 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & RF_DIOMAPPING1_DIO1_MASK &
GregCr 0:e6ceb13d2d05 767 RF_DIOMAPPING1_DIO2_MASK ) |
GregCr 0:e6ceb13d2d05 768 RF_DIOMAPPING1_DIO0_00 |
GregCr 0:e6ceb13d2d05 769 RF_DIOMAPPING1_DIO2_11 );
GregCr 0:e6ceb13d2d05 770
GregCr 0:e6ceb13d2d05 771 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 772 RF_DIOMAPPING2_MAP_MASK ) |
GregCr 0:e6ceb13d2d05 773 RF_DIOMAPPING2_DIO4_11 |
GregCr 0:e6ceb13d2d05 774 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
GregCr 0:e6ceb13d2d05 775
GregCr 0:e6ceb13d2d05 776 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 777
GregCr 0:e6ceb13d2d05 778 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 779 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 780 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 781 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 782 }
GregCr 0:e6ceb13d2d05 783 break;
GregCr 0:e6ceb13d2d05 784 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 785 {
AMNoll 26:ad32782125eb 786
AMNoll 26:ad32782125eb 787 pc1.printf("MODEM_LORA enabled \n\r");
AMNoll 26:ad32782125eb 788
GregCr 0:e6ceb13d2d05 789 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 790 {
GregCr 0:e6ceb13d2d05 791 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
GregCr 0:e6ceb13d2d05 792 }
GregCr 0:e6ceb13d2d05 793 else
GregCr 0:e6ceb13d2d05 794 {
GregCr 0:e6ceb13d2d05 795 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
GregCr 0:e6ceb13d2d05 796 }
GregCr 0:e6ceb13d2d05 797
GregCr 0:e6ceb13d2d05 798 rxContinuous = this->settings.LoRa.RxContinuous;
GregCr 0:e6ceb13d2d05 799
GregCr 6:e7f02929cd3d 800 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 801 {
GregCr 6:e7f02929cd3d 802 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 803 //RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 804 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 4:f0ce52e94d3f 805 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 806 RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 807 RFLR_IRQFLAGS_CADDONE |
GregCr 6:e7f02929cd3d 808 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 809 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 810
mluis 13:618826a997e2 811 // DIO0=RxDone, DIO2=FhssChangeChannel
mluis 13:618826a997e2 812 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 813 }
GregCr 6:e7f02929cd3d 814 else
GregCr 6:e7f02929cd3d 815 {
GregCr 6:e7f02929cd3d 816 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 6:e7f02929cd3d 817 //RFLR_IRQFLAGS_RXDONE |
GregCr 6:e7f02929cd3d 818 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 6:e7f02929cd3d 819 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 6:e7f02929cd3d 820 RFLR_IRQFLAGS_TXDONE |
GregCr 6:e7f02929cd3d 821 RFLR_IRQFLAGS_CADDONE |
GregCr 8:0fe3e0e8007b 822 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 6:e7f02929cd3d 823 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 824
GregCr 6:e7f02929cd3d 825 // DIO0=RxDone
GregCr 6:e7f02929cd3d 826 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 6:e7f02929cd3d 827 }
GregCr 0:e6ceb13d2d05 828
GregCr 0:e6ceb13d2d05 829 Write( REG_LR_FIFORXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 830 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 831 }
GregCr 0:e6ceb13d2d05 832 break;
GregCr 0:e6ceb13d2d05 833 }
GregCr 0:e6ceb13d2d05 834
AMNoll 26:ad32782125eb 835 //this->settings.State
AMNoll 26:ad32782125eb 836 pc1.printf("got to memset and setting RX_DONE\n\r");
AMNoll 26:ad32782125eb 837
GregCr 0:e6ceb13d2d05 838 memset( rxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
GregCr 0:e6ceb13d2d05 839
modtronix 25:72381be1b0ce 840 this->settings.State = RX_DONE;
AMNoll 26:ad32782125eb 841
GregCr 0:e6ceb13d2d05 842 if( timeout != 0 )
GregCr 0:e6ceb13d2d05 843 {
GregCr 0:e6ceb13d2d05 844 rxTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 845 }
GregCr 0:e6ceb13d2d05 846
GregCr 0:e6ceb13d2d05 847 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 848 {
GregCr 0:e6ceb13d2d05 849 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 850
GregCr 0:e6ceb13d2d05 851 if( rxContinuous == false )
GregCr 0:e6ceb13d2d05 852 {
GregCr 0:e6ceb13d2d05 853 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 854 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 855 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
GregCr 0:e6ceb13d2d05 856 1.0 ) + 1.0 ) /
GregCr 0:e6ceb13d2d05 857 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 858 }
GregCr 0:e6ceb13d2d05 859 }
GregCr 0:e6ceb13d2d05 860 else
GregCr 0:e6ceb13d2d05 861 {
GregCr 0:e6ceb13d2d05 862 if( rxContinuous == true )
GregCr 0:e6ceb13d2d05 863 {
GregCr 0:e6ceb13d2d05 864 SetOpMode( RFLR_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 865 }
GregCr 0:e6ceb13d2d05 866 else
GregCr 0:e6ceb13d2d05 867 {
GregCr 0:e6ceb13d2d05 868 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
GregCr 0:e6ceb13d2d05 869 }
GregCr 0:e6ceb13d2d05 870 }
GregCr 0:e6ceb13d2d05 871 }
GregCr 0:e6ceb13d2d05 872
GregCr 0:e6ceb13d2d05 873 void SX1276::Tx( uint32_t timeout )
GregCr 0:e6ceb13d2d05 874 {
GregCr 0:e6ceb13d2d05 875 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 876 {
GregCr 0:e6ceb13d2d05 877 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 878 {
GregCr 0:e6ceb13d2d05 879 // DIO0=PacketSent
GregCr 0:e6ceb13d2d05 880 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 881 // DIO2=FifoFull
GregCr 0:e6ceb13d2d05 882 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 883 // DIO4=LowBat
GregCr 0:e6ceb13d2d05 884 // DIO5=ModeReady
GregCr 5:11ec8a6ba4f0 885 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & RF_DIOMAPPING1_DIO1_MASK &
GregCr 0:e6ceb13d2d05 886 RF_DIOMAPPING1_DIO2_MASK ) );
GregCr 0:e6ceb13d2d05 887
GregCr 0:e6ceb13d2d05 888 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 889 RF_DIOMAPPING2_MAP_MASK ) );
GregCr 0:e6ceb13d2d05 890 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 891 }
GregCr 0:e6ceb13d2d05 892 break;
GregCr 0:e6ceb13d2d05 893 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 894 {
GregCr 6:e7f02929cd3d 895
GregCr 6:e7f02929cd3d 896 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 897 {
GregCr 6:e7f02929cd3d 898 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 6:e7f02929cd3d 899 RFLR_IRQFLAGS_RXDONE |
GregCr 6:e7f02929cd3d 900 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 6:e7f02929cd3d 901 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 6:e7f02929cd3d 902 //RFLR_IRQFLAGS_TXDONE |
GregCr 6:e7f02929cd3d 903 RFLR_IRQFLAGS_CADDONE |
GregCr 6:e7f02929cd3d 904 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 6:e7f02929cd3d 905 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 906
GregCr 6:e7f02929cd3d 907 // DIO0=TxDone
GregCr 8:0fe3e0e8007b 908 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
GregCr 6:e7f02929cd3d 909 // DIO2=FhssChangeChannel
GregCr 6:e7f02929cd3d 910 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 911 }
GregCr 6:e7f02929cd3d 912 else
GregCr 6:e7f02929cd3d 913 {
GregCr 6:e7f02929cd3d 914 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 915 RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 916 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 0:e6ceb13d2d05 917 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 918 //RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 919 RFLR_IRQFLAGS_CADDONE |
GregCr 0:e6ceb13d2d05 920 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 921 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 922
GregCr 6:e7f02929cd3d 923 // DIO0=TxDone
GregCr 6:e7f02929cd3d 924 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
GregCr 6:e7f02929cd3d 925 }
GregCr 0:e6ceb13d2d05 926 }
GregCr 0:e6ceb13d2d05 927 break;
GregCr 0:e6ceb13d2d05 928 }
GregCr 0:e6ceb13d2d05 929
modtronix 25:72381be1b0ce 930 this->settings.State = TX_DONE;
mluis 13:618826a997e2 931 txTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 932 SetOpMode( RF_OPMODE_TRANSMITTER );
GregCr 0:e6ceb13d2d05 933 }
GregCr 0:e6ceb13d2d05 934
GregCr 7:2b555111463f 935 void SX1276::StartCad( void )
GregCr 0:e6ceb13d2d05 936 {
GregCr 7:2b555111463f 937 switch( this->settings.Modem )
GregCr 7:2b555111463f 938 {
GregCr 7:2b555111463f 939 case MODEM_FSK:
GregCr 7:2b555111463f 940 {
GregCr 7:2b555111463f 941
GregCr 7:2b555111463f 942 }
GregCr 7:2b555111463f 943 break;
GregCr 7:2b555111463f 944 case MODEM_LORA:
GregCr 7:2b555111463f 945 {
GregCr 7:2b555111463f 946 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 7:2b555111463f 947 RFLR_IRQFLAGS_RXDONE |
GregCr 7:2b555111463f 948 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 7:2b555111463f 949 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 7:2b555111463f 950 RFLR_IRQFLAGS_TXDONE |
GregCr 7:2b555111463f 951 //RFLR_IRQFLAGS_CADDONE |
GregCr 12:aa5b3bf7fdf4 952 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
GregCr 12:aa5b3bf7fdf4 953 //RFLR_IRQFLAGS_CADDETECTED
GregCr 12:aa5b3bf7fdf4 954 );
GregCr 7:2b555111463f 955
GregCr 7:2b555111463f 956 // DIO3=CADDone
GregCr 7:2b555111463f 957 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 7:2b555111463f 958
GregCr 7:2b555111463f 959 this->settings.State = CAD;
GregCr 7:2b555111463f 960 SetOpMode( RFLR_OPMODE_CAD );
GregCr 7:2b555111463f 961 }
GregCr 7:2b555111463f 962 break;
GregCr 7:2b555111463f 963 default:
GregCr 7:2b555111463f 964 break;
GregCr 7:2b555111463f 965 }
GregCr 7:2b555111463f 966 }
GregCr 7:2b555111463f 967
GregCr 7:2b555111463f 968 int16_t SX1276::GetRssi( ModemType modem )
GregCr 7:2b555111463f 969 {
GregCr 7:2b555111463f 970 int16_t rssi = 0;
GregCr 0:e6ceb13d2d05 971
GregCr 0:e6ceb13d2d05 972 switch( modem )
GregCr 0:e6ceb13d2d05 973 {
GregCr 0:e6ceb13d2d05 974 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 975 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 976 break;
GregCr 0:e6ceb13d2d05 977 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 978 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 979 {
GregCr 0:e6ceb13d2d05 980 rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 981 }
GregCr 0:e6ceb13d2d05 982 else
GregCr 0:e6ceb13d2d05 983 {
GregCr 0:e6ceb13d2d05 984 rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 985 }
GregCr 0:e6ceb13d2d05 986 break;
GregCr 0:e6ceb13d2d05 987 default:
GregCr 0:e6ceb13d2d05 988 rssi = -1;
GregCr 0:e6ceb13d2d05 989 break;
GregCr 0:e6ceb13d2d05 990 }
GregCr 0:e6ceb13d2d05 991 return rssi;
GregCr 0:e6ceb13d2d05 992 }
GregCr 0:e6ceb13d2d05 993
GregCr 0:e6ceb13d2d05 994 void SX1276::SetOpMode( uint8_t opMode )
GregCr 0:e6ceb13d2d05 995 {
GregCr 0:e6ceb13d2d05 996 if( opMode != previousOpMode )
GregCr 0:e6ceb13d2d05 997 {
GregCr 0:e6ceb13d2d05 998 previousOpMode = opMode;
GregCr 0:e6ceb13d2d05 999 if( opMode == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 1000 {
GregCr 0:e6ceb13d2d05 1001 SetAntSwLowPower( true );
GregCr 0:e6ceb13d2d05 1002 }
GregCr 0:e6ceb13d2d05 1003 else
GregCr 0:e6ceb13d2d05 1004 {
GregCr 0:e6ceb13d2d05 1005 SetAntSwLowPower( false );
GregCr 0:e6ceb13d2d05 1006 if( opMode == RF_OPMODE_TRANSMITTER )
GregCr 0:e6ceb13d2d05 1007 {
GregCr 0:e6ceb13d2d05 1008 SetAntSw( 1 );
GregCr 0:e6ceb13d2d05 1009 }
GregCr 0:e6ceb13d2d05 1010 else
GregCr 0:e6ceb13d2d05 1011 {
GregCr 0:e6ceb13d2d05 1012 SetAntSw( 0 );
GregCr 0:e6ceb13d2d05 1013 }
GregCr 0:e6ceb13d2d05 1014 }
GregCr 0:e6ceb13d2d05 1015 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
GregCr 0:e6ceb13d2d05 1016 }
GregCr 0:e6ceb13d2d05 1017 }
GregCr 0:e6ceb13d2d05 1018
GregCr 0:e6ceb13d2d05 1019 void SX1276::SetModem( ModemType modem )
GregCr 0:e6ceb13d2d05 1020 {
GregCr 4:f0ce52e94d3f 1021 if( this->settings.Modem != modem )
GregCr 0:e6ceb13d2d05 1022 {
mluis 13:618826a997e2 1023 this->settings.Modem = modem;
mluis 13:618826a997e2 1024 switch( this->settings.Modem )
mluis 13:618826a997e2 1025 {
mluis 13:618826a997e2 1026 default:
mluis 13:618826a997e2 1027 case MODEM_FSK:
mluis 13:618826a997e2 1028 SetOpMode( RF_OPMODE_SLEEP );
mluis 13:618826a997e2 1029 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
mluis 13:618826a997e2 1030
mluis 13:618826a997e2 1031 Write( REG_DIOMAPPING1, 0x00 );
mluis 13:618826a997e2 1032 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
mluis 13:618826a997e2 1033 break;
mluis 13:618826a997e2 1034 case MODEM_LORA:
mluis 13:618826a997e2 1035 SetOpMode( RF_OPMODE_SLEEP );
mluis 13:618826a997e2 1036 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
mluis 13:618826a997e2 1037 Write( 0x30, 0x00 ); // IF = 0
mluis 13:618826a997e2 1038 Write( REG_LR_DETECTOPTIMIZE, ( Read( REG_LR_DETECTOPTIMIZE ) & 0x7F ) ); // Manual IF
mluis 13:618826a997e2 1039 Write( REG_DIOMAPPING1, 0x00 );
mluis 13:618826a997e2 1040 Write( REG_DIOMAPPING2, 0x00 );
mluis 13:618826a997e2 1041 break;
mluis 13:618826a997e2 1042 }
GregCr 0:e6ceb13d2d05 1043 }
GregCr 0:e6ceb13d2d05 1044 }
GregCr 0:e6ceb13d2d05 1045
GregCr 0:e6ceb13d2d05 1046 void SX1276::OnTimeoutIrq( void )
GregCr 0:e6ceb13d2d05 1047 {
GregCr 0:e6ceb13d2d05 1048 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1049 {
modtronix 25:72381be1b0ce 1050 case RX_DONE:
GregCr 0:e6ceb13d2d05 1051 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 1052 {
GregCr 0:e6ceb13d2d05 1053 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1054 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1055 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1056 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1057
GregCr 0:e6ceb13d2d05 1058 // Clear Irqs
GregCr 0:e6ceb13d2d05 1059 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 0:e6ceb13d2d05 1060 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 0:e6ceb13d2d05 1061 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 0:e6ceb13d2d05 1062 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 0:e6ceb13d2d05 1063
GregCr 0:e6ceb13d2d05 1064 if( this->settings.Fsk.RxContinuous == true )
GregCr 0:e6ceb13d2d05 1065 {
GregCr 0:e6ceb13d2d05 1066 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1067 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1068 }
GregCr 0:e6ceb13d2d05 1069 else
GregCr 0:e6ceb13d2d05 1070 {
GregCr 5:11ec8a6ba4f0 1071 this->settings.State = IDLE;
GregCr 5:11ec8a6ba4f0 1072 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 1073 }
GregCr 0:e6ceb13d2d05 1074 }
GregCr 0:e6ceb13d2d05 1075 if( ( rxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1076 {
GregCr 0:e6ceb13d2d05 1077 rxTimeout( );
GregCr 0:e6ceb13d2d05 1078 }
GregCr 0:e6ceb13d2d05 1079 break;
modtronix 25:72381be1b0ce 1080 case TX_DONE:
mluis 13:618826a997e2 1081 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1082 if( ( txTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1083 {
GregCr 0:e6ceb13d2d05 1084 txTimeout( );
GregCr 0:e6ceb13d2d05 1085 }
GregCr 0:e6ceb13d2d05 1086 break;
GregCr 0:e6ceb13d2d05 1087 default:
GregCr 0:e6ceb13d2d05 1088 break;
GregCr 0:e6ceb13d2d05 1089 }
GregCr 0:e6ceb13d2d05 1090 }
GregCr 0:e6ceb13d2d05 1091
GregCr 0:e6ceb13d2d05 1092 void SX1276::OnDio0Irq( void )
GregCr 0:e6ceb13d2d05 1093 {
GregCr 0:e6ceb13d2d05 1094 __IO uint8_t irqFlags = 0;
modtronix 20:7cf7c08f0088 1095
GregCr 0:e6ceb13d2d05 1096 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1097 {
modtronix 25:72381be1b0ce 1098 case RX_DONE:
GregCr 0:e6ceb13d2d05 1099 //TimerStop( &RxTimeoutTimer );
GregCr 0:e6ceb13d2d05 1100 // RxDone interrupt
GregCr 0:e6ceb13d2d05 1101 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1102 {
GregCr 0:e6ceb13d2d05 1103 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1104 irqFlags = Read( REG_IRQFLAGS2 );
GregCr 0:e6ceb13d2d05 1105 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
GregCr 0:e6ceb13d2d05 1106 {
GregCr 0:e6ceb13d2d05 1107 // Clear Irqs
GregCr 0:e6ceb13d2d05 1108 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 0:e6ceb13d2d05 1109 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 0:e6ceb13d2d05 1110 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 0:e6ceb13d2d05 1111 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 0:e6ceb13d2d05 1112
GregCr 0:e6ceb13d2d05 1113 if( this->settings.Fsk.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1114 {
GregCr 0:e6ceb13d2d05 1115 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1116 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 1117 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 1118 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
GregCr 0:e6ceb13d2d05 1119 1.0 ) + 1.0 ) /
GregCr 0:e6ceb13d2d05 1120 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 1121 }
GregCr 0:e6ceb13d2d05 1122 else
GregCr 0:e6ceb13d2d05 1123 {
GregCr 0:e6ceb13d2d05 1124 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1125 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1126 }
GregCr 0:e6ceb13d2d05 1127 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1128
GregCr 0:e6ceb13d2d05 1129 if( ( rxError != NULL ) )
GregCr 0:e6ceb13d2d05 1130 {
GregCr 0:e6ceb13d2d05 1131 rxError( );
GregCr 0:e6ceb13d2d05 1132 }
GregCr 0:e6ceb13d2d05 1133 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1134 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1135 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1136 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1137 break;
GregCr 0:e6ceb13d2d05 1138 }
GregCr 0:e6ceb13d2d05 1139
GregCr 0:e6ceb13d2d05 1140 // Read received packet size
GregCr 0:e6ceb13d2d05 1141 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1142 {
GregCr 0:e6ceb13d2d05 1143 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1144 {
GregCr 0:e6ceb13d2d05 1145 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1146 }
GregCr 0:e6ceb13d2d05 1147 else
GregCr 0:e6ceb13d2d05 1148 {
GregCr 0:e6ceb13d2d05 1149 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1150 }
GregCr 0:e6ceb13d2d05 1151 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1152 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1153 }
GregCr 0:e6ceb13d2d05 1154 else
GregCr 0:e6ceb13d2d05 1155 {
GregCr 0:e6ceb13d2d05 1156 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1157 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1158 }
GregCr 0:e6ceb13d2d05 1159
GregCr 0:e6ceb13d2d05 1160 if( this->settings.Fsk.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1161 {
GregCr 0:e6ceb13d2d05 1162 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1163 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 1164 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 1165 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
GregCr 0:e6ceb13d2d05 1166 1.0 ) + 1.0 ) /
GregCr 0:e6ceb13d2d05 1167 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 1168 }
GregCr 0:e6ceb13d2d05 1169 else
GregCr 0:e6ceb13d2d05 1170 {
GregCr 0:e6ceb13d2d05 1171 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1172 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1173 }
GregCr 0:e6ceb13d2d05 1174 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1175
GregCr 0:e6ceb13d2d05 1176 if( (rxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1177 {
GregCr 0:e6ceb13d2d05 1178 rxDone( rxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
GregCr 0:e6ceb13d2d05 1179 }
GregCr 0:e6ceb13d2d05 1180 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1181 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1182 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1183 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1184 break;
GregCr 0:e6ceb13d2d05 1185 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1186 {
GregCr 0:e6ceb13d2d05 1187 uint8_t snr = 0;
GregCr 0:e6ceb13d2d05 1188
GregCr 0:e6ceb13d2d05 1189 // Clear Irq
GregCr 0:e6ceb13d2d05 1190 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
GregCr 0:e6ceb13d2d05 1191
GregCr 0:e6ceb13d2d05 1192 irqFlags = Read( REG_LR_IRQFLAGS );
GregCr 0:e6ceb13d2d05 1193 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
GregCr 0:e6ceb13d2d05 1194 {
GregCr 0:e6ceb13d2d05 1195 // Clear Irq
GregCr 0:e6ceb13d2d05 1196 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
GregCr 0:e6ceb13d2d05 1197
GregCr 0:e6ceb13d2d05 1198 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1199 {
GregCr 0:e6ceb13d2d05 1200 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1201 }
GregCr 0:e6ceb13d2d05 1202 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1203
GregCr 4:f0ce52e94d3f 1204 if( ( rxError != NULL ) )
GregCr 0:e6ceb13d2d05 1205 {
GregCr 0:e6ceb13d2d05 1206 rxError( );
GregCr 0:e6ceb13d2d05 1207 }
GregCr 0:e6ceb13d2d05 1208 break;
GregCr 0:e6ceb13d2d05 1209 }
GregCr 0:e6ceb13d2d05 1210
GregCr 0:e6ceb13d2d05 1211 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
GregCr 0:e6ceb13d2d05 1212 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
GregCr 0:e6ceb13d2d05 1213 {
GregCr 0:e6ceb13d2d05 1214 // Invert and divide by 4
GregCr 0:e6ceb13d2d05 1215 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1216 snr = -snr;
GregCr 0:e6ceb13d2d05 1217 }
GregCr 0:e6ceb13d2d05 1218 else
GregCr 0:e6ceb13d2d05 1219 {
GregCr 0:e6ceb13d2d05 1220 // Divide by 4
GregCr 0:e6ceb13d2d05 1221 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1222 }
GregCr 0:e6ceb13d2d05 1223
GregCr 7:2b555111463f 1224 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
GregCr 0:e6ceb13d2d05 1225 if( this->settings.LoRaPacketHandler.SnrValue < 0 )
GregCr 0:e6ceb13d2d05 1226 {
GregCr 0:e6ceb13d2d05 1227 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1228 {
GregCr 0:e6ceb13d2d05 1229 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1230 snr;
GregCr 0:e6ceb13d2d05 1231 }
GregCr 0:e6ceb13d2d05 1232 else
GregCr 0:e6ceb13d2d05 1233 {
GregCr 0:e6ceb13d2d05 1234 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1235 snr;
GregCr 0:e6ceb13d2d05 1236 }
GregCr 0:e6ceb13d2d05 1237 }
GregCr 0:e6ceb13d2d05 1238 else
GregCr 0:e6ceb13d2d05 1239 {
GregCr 0:e6ceb13d2d05 1240 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1241 {
GregCr 0:e6ceb13d2d05 1242 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1243 }
GregCr 0:e6ceb13d2d05 1244 else
GregCr 0:e6ceb13d2d05 1245 {
GregCr 0:e6ceb13d2d05 1246 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1247 }
GregCr 0:e6ceb13d2d05 1248 }
GregCr 0:e6ceb13d2d05 1249
GregCr 0:e6ceb13d2d05 1250 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
GregCr 0:e6ceb13d2d05 1251 ReadFifo( rxBuffer, this->settings.LoRaPacketHandler.Size );
GregCr 0:e6ceb13d2d05 1252
GregCr 0:e6ceb13d2d05 1253 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1254 {
GregCr 0:e6ceb13d2d05 1255 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1256 }
GregCr 0:e6ceb13d2d05 1257 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1258
GregCr 0:e6ceb13d2d05 1259 if( ( rxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1260 {
GregCr 0:e6ceb13d2d05 1261 rxDone( rxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
GregCr 0:e6ceb13d2d05 1262 }
GregCr 0:e6ceb13d2d05 1263 }
GregCr 0:e6ceb13d2d05 1264 break;
GregCr 0:e6ceb13d2d05 1265 default:
GregCr 0:e6ceb13d2d05 1266 break;
GregCr 0:e6ceb13d2d05 1267 }
GregCr 0:e6ceb13d2d05 1268 break;
modtronix 25:72381be1b0ce 1269 case TX_DONE:
GregCr 0:e6ceb13d2d05 1270 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1271 // TxDone interrupt
GregCr 0:e6ceb13d2d05 1272 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1273 {
GregCr 0:e6ceb13d2d05 1274 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1275 // Clear Irq
GregCr 0:e6ceb13d2d05 1276 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
GregCr 0:e6ceb13d2d05 1277 // Intentional fall through
GregCr 0:e6ceb13d2d05 1278 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1279 default:
GregCr 0:e6ceb13d2d05 1280 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1281 if( ( txDone != NULL ) )
GregCr 0:e6ceb13d2d05 1282 {
GregCr 0:e6ceb13d2d05 1283 txDone( );
GregCr 0:e6ceb13d2d05 1284 }
GregCr 0:e6ceb13d2d05 1285 break;
GregCr 0:e6ceb13d2d05 1286 }
GregCr 0:e6ceb13d2d05 1287 break;
GregCr 0:e6ceb13d2d05 1288 default:
GregCr 0:e6ceb13d2d05 1289 break;
GregCr 0:e6ceb13d2d05 1290 }
GregCr 0:e6ceb13d2d05 1291 }
GregCr 0:e6ceb13d2d05 1292
GregCr 0:e6ceb13d2d05 1293 void SX1276::OnDio1Irq( void )
GregCr 0:e6ceb13d2d05 1294 {
GregCr 0:e6ceb13d2d05 1295 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1296 {
modtronix 25:72381be1b0ce 1297 case RX_DONE:
GregCr 0:e6ceb13d2d05 1298 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1299 {
GregCr 0:e6ceb13d2d05 1300 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1301 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1302 // Read received packet size
GregCr 0:e6ceb13d2d05 1303 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1304 {
GregCr 0:e6ceb13d2d05 1305 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1306 {
GregCr 0:e6ceb13d2d05 1307 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1308 }
GregCr 0:e6ceb13d2d05 1309 else
GregCr 0:e6ceb13d2d05 1310 {
GregCr 0:e6ceb13d2d05 1311 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1312 }
GregCr 0:e6ceb13d2d05 1313 }
GregCr 0:e6ceb13d2d05 1314
GregCr 0:e6ceb13d2d05 1315 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
GregCr 0:e6ceb13d2d05 1316 {
GregCr 0:e6ceb13d2d05 1317 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
GregCr 0:e6ceb13d2d05 1318 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
GregCr 0:e6ceb13d2d05 1319 }
GregCr 0:e6ceb13d2d05 1320 else
GregCr 0:e6ceb13d2d05 1321 {
GregCr 0:e6ceb13d2d05 1322 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1323 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1324 }
GregCr 0:e6ceb13d2d05 1325 break;
GregCr 0:e6ceb13d2d05 1326 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1327 // Sync time out
GregCr 0:e6ceb13d2d05 1328 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1329 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1330 if( ( rxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1331 {
GregCr 0:e6ceb13d2d05 1332 rxTimeout( );
GregCr 0:e6ceb13d2d05 1333 }
GregCr 0:e6ceb13d2d05 1334 break;
GregCr 0:e6ceb13d2d05 1335 default:
GregCr 0:e6ceb13d2d05 1336 break;
GregCr 0:e6ceb13d2d05 1337 }
GregCr 0:e6ceb13d2d05 1338 break;
modtronix 25:72381be1b0ce 1339 case TX_DONE:
GregCr 0:e6ceb13d2d05 1340 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1341 {
GregCr 0:e6ceb13d2d05 1342 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1343 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1344 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
GregCr 0:e6ceb13d2d05 1345 {
GregCr 0:e6ceb13d2d05 1346 WriteFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 1347 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 1348 }
GregCr 0:e6ceb13d2d05 1349 else
GregCr 0:e6ceb13d2d05 1350 {
GregCr 0:e6ceb13d2d05 1351 // Write the last chunk of data
GregCr 0:e6ceb13d2d05 1352 WriteFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1353 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
GregCr 0:e6ceb13d2d05 1354 }
GregCr 0:e6ceb13d2d05 1355 break;
GregCr 0:e6ceb13d2d05 1356 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1357 break;
GregCr 0:e6ceb13d2d05 1358 default:
GregCr 0:e6ceb13d2d05 1359 break;
GregCr 0:e6ceb13d2d05 1360 }
GregCr 0:e6ceb13d2d05 1361 break;
GregCr 0:e6ceb13d2d05 1362 default:
GregCr 0:e6ceb13d2d05 1363 break;
GregCr 0:e6ceb13d2d05 1364 }
GregCr 0:e6ceb13d2d05 1365 }
GregCr 0:e6ceb13d2d05 1366
GregCr 0:e6ceb13d2d05 1367 void SX1276::OnDio2Irq( void )
GregCr 0:e6ceb13d2d05 1368 {
GregCr 0:e6ceb13d2d05 1369 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1370 {
modtronix 25:72381be1b0ce 1371 case RX_DONE:
GregCr 0:e6ceb13d2d05 1372 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1373 {
GregCr 0:e6ceb13d2d05 1374 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1375 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
GregCr 0:e6ceb13d2d05 1376 {
GregCr 0:e6ceb13d2d05 1377 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 1378
GregCr 0:e6ceb13d2d05 1379 this->settings.FskPacketHandler.SyncWordDetected = true;
GregCr 0:e6ceb13d2d05 1380
GregCr 0:e6ceb13d2d05 1381 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 1382
GregCr 0:e6ceb13d2d05 1383 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
GregCr 0:e6ceb13d2d05 1384 ( uint16_t )Read( REG_AFCLSB ) ) *
GregCr 0:e6ceb13d2d05 1385 ( double )FREQ_STEP;
GregCr 0:e6ceb13d2d05 1386 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
GregCr 0:e6ceb13d2d05 1387 }
GregCr 0:e6ceb13d2d05 1388 break;
GregCr 0:e6ceb13d2d05 1389 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1390 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1391 {
GregCr 6:e7f02929cd3d 1392 // Clear Irq
GregCr 6:e7f02929cd3d 1393 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
GregCr 6:e7f02929cd3d 1394
mluis 13:618826a997e2 1395 if( ( fhssChangeChannel != NULL ) )
mluis 13:618826a997e2 1396 {
mluis 13:618826a997e2 1397 fhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1398 }
GregCr 6:e7f02929cd3d 1399 }
GregCr 0:e6ceb13d2d05 1400 break;
GregCr 0:e6ceb13d2d05 1401 default:
GregCr 0:e6ceb13d2d05 1402 break;
GregCr 0:e6ceb13d2d05 1403 }
GregCr 0:e6ceb13d2d05 1404 break;
modtronix 25:72381be1b0ce 1405 case TX_DONE:
GregCr 0:e6ceb13d2d05 1406 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1407 {
GregCr 0:e6ceb13d2d05 1408 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1409 break;
GregCr 0:e6ceb13d2d05 1410 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1411 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1412 {
GregCr 6:e7f02929cd3d 1413 // Clear Irq
GregCr 6:e7f02929cd3d 1414 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
GregCr 6:e7f02929cd3d 1415
mluis 13:618826a997e2 1416 if( ( fhssChangeChannel != NULL ) )
mluis 13:618826a997e2 1417 {
mluis 13:618826a997e2 1418 fhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1419 }
GregCr 6:e7f02929cd3d 1420 }
GregCr 0:e6ceb13d2d05 1421 break;
GregCr 0:e6ceb13d2d05 1422 default:
GregCr 0:e6ceb13d2d05 1423 break;
GregCr 0:e6ceb13d2d05 1424 }
GregCr 0:e6ceb13d2d05 1425 break;
GregCr 0:e6ceb13d2d05 1426 default:
GregCr 0:e6ceb13d2d05 1427 break;
GregCr 0:e6ceb13d2d05 1428 }
GregCr 0:e6ceb13d2d05 1429 }
GregCr 0:e6ceb13d2d05 1430
GregCr 0:e6ceb13d2d05 1431 void SX1276::OnDio3Irq( void )
GregCr 0:e6ceb13d2d05 1432 {
GregCr 0:e6ceb13d2d05 1433 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1434 {
GregCr 0:e6ceb13d2d05 1435 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1436 break;
GregCr 0:e6ceb13d2d05 1437 case MODEM_LORA:
mluis 13:618826a997e2 1438 if( ( Read( REG_LR_IRQFLAGS ) & 0x01 ) == 0x01 )
mluis 13:618826a997e2 1439 {
mluis 13:618826a997e2 1440 // Clear Irq
mluis 13:618826a997e2 1441 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED_MASK | RFLR_IRQFLAGS_CADDONE);
mluis 13:618826a997e2 1442 if( ( cadDone != NULL ) )
mluis 13:618826a997e2 1443 {
mluis 13:618826a997e2 1444 cadDone( true );
mluis 13:618826a997e2 1445 }
GregCr 12:aa5b3bf7fdf4 1446 }
GregCr 12:aa5b3bf7fdf4 1447 else
mluis 13:618826a997e2 1448 {
mluis 13:618826a997e2 1449 // Clear Irq
mluis 13:618826a997e2 1450 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
mluis 13:618826a997e2 1451 if( ( cadDone != NULL ) )
mluis 13:618826a997e2 1452 {
mluis 13:618826a997e2 1453 cadDone( false );
mluis 13:618826a997e2 1454 }
GregCr 7:2b555111463f 1455 }
GregCr 0:e6ceb13d2d05 1456 break;
GregCr 0:e6ceb13d2d05 1457 default:
GregCr 0:e6ceb13d2d05 1458 break;
GregCr 0:e6ceb13d2d05 1459 }
GregCr 0:e6ceb13d2d05 1460 }
GregCr 0:e6ceb13d2d05 1461
modtronix 25:72381be1b0ce 1462 /*
GregCr 0:e6ceb13d2d05 1463 void SX1276::OnDio4Irq( void )
GregCr 0:e6ceb13d2d05 1464 {
GregCr 0:e6ceb13d2d05 1465 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1466 {
GregCr 0:e6ceb13d2d05 1467 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1468 {
GregCr 0:e6ceb13d2d05 1469 if( this->settings.FskPacketHandler.PreambleDetected == false )
GregCr 0:e6ceb13d2d05 1470 {
GregCr 0:e6ceb13d2d05 1471 this->settings.FskPacketHandler.PreambleDetected = true;
GregCr 0:e6ceb13d2d05 1472 }
GregCr 0:e6ceb13d2d05 1473 }
GregCr 0:e6ceb13d2d05 1474 break;
GregCr 0:e6ceb13d2d05 1475 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1476 break;
GregCr 0:e6ceb13d2d05 1477 default:
GregCr 0:e6ceb13d2d05 1478 break;
GregCr 0:e6ceb13d2d05 1479 }
GregCr 0:e6ceb13d2d05 1480 }
GregCr 0:e6ceb13d2d05 1481
GregCr 0:e6ceb13d2d05 1482 void SX1276::OnDio5Irq( void )
GregCr 0:e6ceb13d2d05 1483 {
GregCr 0:e6ceb13d2d05 1484 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1485 {
GregCr 0:e6ceb13d2d05 1486 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1487 break;
GregCr 0:e6ceb13d2d05 1488 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1489 break;
GregCr 0:e6ceb13d2d05 1490 default:
GregCr 0:e6ceb13d2d05 1491 break;
GregCr 0:e6ceb13d2d05 1492 }
mluis 13:618826a997e2 1493 }
modtronix 25:72381be1b0ce 1494 */