Capstone / SX1276Lib_modtronix

SX1276 library for modtronix inair9. Edited for use with NRF51DK board.

Dependents:   InAir9_PingPong

Fork of SX1276Lib_modtronix by modtronix H

sx1276/sx1276.cpp@20:7cf7c08f0088, 2015-04-02 (annotated)

Committer:
modtronix
Date:
Thu Apr 02 01:02:35 2015 +0000
Revision:
20:7cf7c08f0088
Parent:
19:ef26bd64cb67
Child:
22:20db480143c9
Added more BW and SF options

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
GregCr 8:0fe3e0e8007b 7 ( C )2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: Actual implementation of a SX1276 radio, inherits Radio
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
GregCr 0:e6ceb13d2d05 14 */
GregCr 0:e6ceb13d2d05 15 #include "sx1276.h"
GregCr 0:e6ceb13d2d05 16
GregCr 0:e6ceb13d2d05 17 const FskBandwidth_t SX1276::FskBandwidths[] =
GregCr 0:e6ceb13d2d05 18 {
GregCr 0:e6ceb13d2d05 19 { 2600 , 0x17 },
GregCr 0:e6ceb13d2d05 20 { 3100 , 0x0F },
GregCr 0:e6ceb13d2d05 21 { 3900 , 0x07 },
GregCr 0:e6ceb13d2d05 22 { 5200 , 0x16 },
GregCr 0:e6ceb13d2d05 23 { 6300 , 0x0E },
GregCr 0:e6ceb13d2d05 24 { 7800 , 0x06 },
GregCr 0:e6ceb13d2d05 25 { 10400 , 0x15 },
GregCr 0:e6ceb13d2d05 26 { 12500 , 0x0D },
GregCr 0:e6ceb13d2d05 27 { 15600 , 0x05 },
GregCr 0:e6ceb13d2d05 28 { 20800 , 0x14 },
GregCr 0:e6ceb13d2d05 29 { 25000 , 0x0C },
GregCr 0:e6ceb13d2d05 30 { 31300 , 0x04 },
GregCr 0:e6ceb13d2d05 31 { 41700 , 0x13 },
GregCr 0:e6ceb13d2d05 32 { 50000 , 0x0B },
GregCr 0:e6ceb13d2d05 33 { 62500 , 0x03 },
GregCr 0:e6ceb13d2d05 34 { 83333 , 0x12 },
GregCr 0:e6ceb13d2d05 35 { 100000, 0x0A },
GregCr 0:e6ceb13d2d05 36 { 125000, 0x02 },
GregCr 0:e6ceb13d2d05 37 { 166700, 0x11 },
GregCr 0:e6ceb13d2d05 38 { 200000, 0x09 },
mluis 15:04374b1c33fa 39 { 250000, 0x01 },
modtronix 20:7cf7c08f0088 40 { 300000, 0x00 }, // Invalid Badwidth
GregCr 0:e6ceb13d2d05 41 };
GregCr 0:e6ceb13d2d05 42
GregCr 0:e6ceb13d2d05 43
GregCr 7:2b555111463f 44 SX1276::SX1276( void ( *txDone )( ), void ( *txTimeout ) ( ), void ( *rxDone ) ( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr ),
mluis 13:618826a997e2 45 void ( *rxTimeout ) ( ), void ( *rxError ) ( ), void ( *fhssChangeChannel ) ( uint8_t channelIndex ), void ( *cadDone ) ( bool channelActivityDetected ),
mluis 13:618826a997e2 46 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
GregCr 0:e6ceb13d2d05 47 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
mluis 13:618826a997e2 48 : Radio( txDone, txTimeout, rxDone, rxTimeout, rxError, fhssChangeChannel, cadDone ),
mluis 13:618826a997e2 49 spi( mosi, miso, sclk ),
mluis 13:618826a997e2 50 nss( nss ),
mluis 13:618826a997e2 51 reset( reset ),
mluis 13:618826a997e2 52 dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ),
mluis 13:618826a997e2 53 isRadioActive( false )
GregCr 0:e6ceb13d2d05 54 {
mluis 13:618826a997e2 55 wait_ms( 10 );
mluis 13:618826a997e2 56 this->rxTx = 0;
mluis 13:618826a997e2 57 this->rxBuffer = new uint8_t[RX_BUFFER_SIZE];
mluis 13:618826a997e2 58 previousOpMode = RF_OPMODE_STANDBY;
mluis 13:618826a997e2 59
mluis 13:618826a997e2 60 this->dioIrq = new DioIrqHandler[6];
GregCr 0:e6ceb13d2d05 61
mluis 13:618826a997e2 62 this->dioIrq[0] = &SX1276::OnDio0Irq;
mluis 13:618826a997e2 63 this->dioIrq[1] = &SX1276::OnDio1Irq;
mluis 13:618826a997e2 64 this->dioIrq[2] = &SX1276::OnDio2Irq;
modtronix 18:cdb08d710838 65 //For SHD3I with inAir9 in imod3, on FRDM-KL25Z board. It uses A4 on FRDM-KL25Z board, which does not have interrupt
modtronix 18:cdb08d710838 66 #if( defined ( TARGET_KL25Z ) && defined(SHIELD_SHD3I_INAIR9) )
modtronix 18:cdb08d710838 67 this->dioIrq[3] = NULL;
modtronix 18:cdb08d710838 68 #else
mluis 13:618826a997e2 69 this->dioIrq[3] = &SX1276::OnDio3Irq;
modtronix 18:cdb08d710838 70 #endif
mluis 13:618826a997e2 71 this->dioIrq[4] = &SX1276::OnDio4Irq;
mluis 13:618826a997e2 72 this->dioIrq[5] = NULL;
mluis 13:618826a997e2 73
mluis 13:618826a997e2 74 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 75 }
GregCr 0:e6ceb13d2d05 76
GregCr 0:e6ceb13d2d05 77 SX1276::~SX1276( )
GregCr 0:e6ceb13d2d05 78 {
mluis 13:618826a997e2 79 delete this->rxBuffer;
mluis 13:618826a997e2 80 delete this->dioIrq;
GregCr 0:e6ceb13d2d05 81 }
GregCr 0:e6ceb13d2d05 82
GregCr 0:e6ceb13d2d05 83 void SX1276::RxChainCalibration( void )
GregCr 0:e6ceb13d2d05 84 {
GregCr 0:e6ceb13d2d05 85 uint8_t regPaConfigInitVal;
GregCr 0:e6ceb13d2d05 86 uint32_t initialFreq;
GregCr 0:e6ceb13d2d05 87
GregCr 0:e6ceb13d2d05 88 // Save context
GregCr 0:e6ceb13d2d05 89 regPaConfigInitVal = this->Read( REG_PACONFIG );
GregCr 0:e6ceb13d2d05 90 initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) |
GregCr 0:e6ceb13d2d05 91 ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) |
GregCr 0:e6ceb13d2d05 92 ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
GregCr 0:e6ceb13d2d05 93
GregCr 0:e6ceb13d2d05 94 // Cut the PA just in case, RFO output, power = -1 dBm
GregCr 0:e6ceb13d2d05 95 this->Write( REG_PACONFIG, 0x00 );
GregCr 0:e6ceb13d2d05 96
GregCr 0:e6ceb13d2d05 97 // Launch Rx chain calibration for LF band
GregCr 0:e6ceb13d2d05 98 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
GregCr 0:e6ceb13d2d05 99 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
GregCr 0:e6ceb13d2d05 100 {
GregCr 0:e6ceb13d2d05 101 }
GregCr 0:e6ceb13d2d05 102
GregCr 0:e6ceb13d2d05 103 // Sets a Frequency in HF band
GregCr 0:e6ceb13d2d05 104 settings.Channel= 868000000 ;
GregCr 0:e6ceb13d2d05 105
GregCr 0:e6ceb13d2d05 106 // Launch Rx chain calibration for HF band
GregCr 0:e6ceb13d2d05 107 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
GregCr 0:e6ceb13d2d05 108 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
GregCr 0:e6ceb13d2d05 109 {
GregCr 0:e6ceb13d2d05 110 }
GregCr 0:e6ceb13d2d05 111
GregCr 0:e6ceb13d2d05 112 // Restore context
GregCr 0:e6ceb13d2d05 113 this->Write( REG_PACONFIG, regPaConfigInitVal );
GregCr 0:e6ceb13d2d05 114 SetChannel( initialFreq );
GregCr 0:e6ceb13d2d05 115 }
GregCr 0:e6ceb13d2d05 116
GregCr 0:e6ceb13d2d05 117 RadioState SX1276::GetState( void )
GregCr 0:e6ceb13d2d05 118 {
GregCr 0:e6ceb13d2d05 119 return this->settings.State;
GregCr 0:e6ceb13d2d05 120 }
GregCr 0:e6ceb13d2d05 121
GregCr 0:e6ceb13d2d05 122 void SX1276::SetChannel( uint32_t freq )
GregCr 0:e6ceb13d2d05 123 {
GregCr 0:e6ceb13d2d05 124 this->settings.Channel = freq;
GregCr 0:e6ceb13d2d05 125 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 126 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 127 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 128 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
GregCr 0:e6ceb13d2d05 129 }
GregCr 0:e6ceb13d2d05 130
GregCr 0:e6ceb13d2d05 131 bool SX1276::IsChannelFree( ModemType modem, uint32_t freq, int8_t rssiThresh )
GregCr 0:e6ceb13d2d05 132 {
GregCr 7:2b555111463f 133 int16_t rssi = 0;
GregCr 0:e6ceb13d2d05 134
GregCr 0:e6ceb13d2d05 135 SetModem( modem );
GregCr 0:e6ceb13d2d05 136
GregCr 0:e6ceb13d2d05 137 SetChannel( freq );
GregCr 0:e6ceb13d2d05 138
GregCr 0:e6ceb13d2d05 139 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 140
GregCr 4:f0ce52e94d3f 141 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 142
GregCr 0:e6ceb13d2d05 143 rssi = GetRssi( modem );
GregCr 0:e6ceb13d2d05 144
GregCr 0:e6ceb13d2d05 145 Sleep( );
GregCr 0:e6ceb13d2d05 146
GregCr 7:2b555111463f 147 if( rssi > ( int16_t )rssiThresh )
GregCr 0:e6ceb13d2d05 148 {
GregCr 0:e6ceb13d2d05 149 return false;
GregCr 0:e6ceb13d2d05 150 }
GregCr 0:e6ceb13d2d05 151 return true;
GregCr 0:e6ceb13d2d05 152 }
GregCr 0:e6ceb13d2d05 153
GregCr 0:e6ceb13d2d05 154 uint32_t SX1276::Random( void )
GregCr 0:e6ceb13d2d05 155 {
GregCr 0:e6ceb13d2d05 156 uint8_t i;
GregCr 0:e6ceb13d2d05 157 uint32_t rnd = 0;
GregCr 0:e6ceb13d2d05 158
GregCr 0:e6ceb13d2d05 159 /*
GregCr 0:e6ceb13d2d05 160 * Radio setup for random number generation
GregCr 0:e6ceb13d2d05 161 */
GregCr 0:e6ceb13d2d05 162 // Set LoRa modem ON
GregCr 0:e6ceb13d2d05 163 SetModem( MODEM_LORA );
GregCr 0:e6ceb13d2d05 164
GregCr 0:e6ceb13d2d05 165 // Disable LoRa modem interrupts
GregCr 0:e6ceb13d2d05 166 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 167 RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 168 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 0:e6ceb13d2d05 169 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 170 RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 171 RFLR_IRQFLAGS_CADDONE |
GregCr 0:e6ceb13d2d05 172 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 173 RFLR_IRQFLAGS_CADDETECTED );
GregCr 0:e6ceb13d2d05 174
GregCr 0:e6ceb13d2d05 175 // Set radio in continuous reception
GregCr 0:e6ceb13d2d05 176 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 177
GregCr 0:e6ceb13d2d05 178 for( i = 0; i < 32; i++ )
GregCr 0:e6ceb13d2d05 179 {
GregCr 4:f0ce52e94d3f 180 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 181 // Unfiltered RSSI value reading. Only takes the LSB value
GregCr 0:e6ceb13d2d05 182 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
GregCr 0:e6ceb13d2d05 183 }
GregCr 0:e6ceb13d2d05 184
GregCr 0:e6ceb13d2d05 185 Sleep( );
GregCr 0:e6ceb13d2d05 186
GregCr 0:e6ceb13d2d05 187 return rnd;
GregCr 0:e6ceb13d2d05 188 }
GregCr 0:e6ceb13d2d05 189
GregCr 0:e6ceb13d2d05 190 /*!
GregCr 0:e6ceb13d2d05 191 * Returns the known FSK bandwidth registers value
GregCr 0:e6ceb13d2d05 192 *
GregCr 0:e6ceb13d2d05 193 * \param [IN] bandwidth Bandwidth value in Hz
GregCr 0:e6ceb13d2d05 194 * \retval regValue Bandwidth register value.
GregCr 0:e6ceb13d2d05 195 */
GregCr 0:e6ceb13d2d05 196 uint8_t SX1276::GetFskBandwidthRegValue( uint32_t bandwidth )
GregCr 0:e6ceb13d2d05 197 {
GregCr 0:e6ceb13d2d05 198 uint8_t i;
GregCr 0:e6ceb13d2d05 199
GregCr 0:e6ceb13d2d05 200 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
GregCr 0:e6ceb13d2d05 201 {
GregCr 0:e6ceb13d2d05 202 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
GregCr 0:e6ceb13d2d05 203 {
GregCr 0:e6ceb13d2d05 204 return FskBandwidths[i].RegValue;
GregCr 0:e6ceb13d2d05 205 }
GregCr 0:e6ceb13d2d05 206 }
GregCr 0:e6ceb13d2d05 207 // ERROR: Value not found
GregCr 0:e6ceb13d2d05 208 while( 1 );
GregCr 0:e6ceb13d2d05 209 }
GregCr 0:e6ceb13d2d05 210
GregCr 0:e6ceb13d2d05 211 void SX1276::SetRxConfig( ModemType modem, uint32_t bandwidth,
GregCr 0:e6ceb13d2d05 212 uint32_t datarate, uint8_t coderate,
GregCr 0:e6ceb13d2d05 213 uint32_t bandwidthAfc, uint16_t preambleLen,
GregCr 0:e6ceb13d2d05 214 uint16_t symbTimeout, bool fixLen,
mluis 13:618826a997e2 215 uint8_t payloadLen,
mluis 13:618826a997e2 216 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
GregCr 6:e7f02929cd3d 217 bool iqInverted, bool rxContinuous )
GregCr 0:e6ceb13d2d05 218 {
GregCr 0:e6ceb13d2d05 219 SetModem( modem );
GregCr 0:e6ceb13d2d05 220
GregCr 0:e6ceb13d2d05 221 switch( modem )
GregCr 0:e6ceb13d2d05 222 {
GregCr 0:e6ceb13d2d05 223 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 224 {
GregCr 0:e6ceb13d2d05 225 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 226 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 227 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
GregCr 0:e6ceb13d2d05 228 this->settings.Fsk.FixLen = fixLen;
mluis 13:618826a997e2 229 this->settings.Fsk.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 230 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 231 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 232 this->settings.Fsk.RxContinuous = rxContinuous;
GregCr 0:e6ceb13d2d05 233 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 234
GregCr 0:e6ceb13d2d05 235 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 236 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 237 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 238
GregCr 0:e6ceb13d2d05 239 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
GregCr 0:e6ceb13d2d05 240 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
GregCr 0:e6ceb13d2d05 241
mluis 14:8552d0b840be 242 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
mluis 14:8552d0b840be 243 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
GregCr 0:e6ceb13d2d05 244
GregCr 0:e6ceb13d2d05 245 Write( REG_PACKETCONFIG1,
GregCr 0:e6ceb13d2d05 246 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 247 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 248 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 249 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 250 ( crcOn << 4 ) );
mluis 13:618826a997e2 251 if( fixLen == 1 )
mluis 13:618826a997e2 252 {
mluis 13:618826a997e2 253 Write( REG_PAYLOADLENGTH, payloadLen );
mluis 13:618826a997e2 254 }
GregCr 0:e6ceb13d2d05 255 }
GregCr 0:e6ceb13d2d05 256 break;
GregCr 0:e6ceb13d2d05 257 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 258 {
modtronix 16:0927c093fd82 259 if( bandwidth > 9 )
GregCr 0:e6ceb13d2d05 260 {
modtronix 16:0927c093fd82 261 // Fatal error: Bandwidth must be 0-9 (7.8 - 500khz)
GregCr 0:e6ceb13d2d05 262 while( 1 );
GregCr 0:e6ceb13d2d05 263 }
modtronix 16:0927c093fd82 264 //bandwidth += 7; //Changed bandwidth from 0-2 to 0-10
GregCr 0:e6ceb13d2d05 265 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 266 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 267 this->settings.LoRa.Coderate = coderate;
GregCr 0:e6ceb13d2d05 268 this->settings.LoRa.FixLen = fixLen;
mluis 13:618826a997e2 269 this->settings.LoRa.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 270 this->settings.LoRa.CrcOn = crcOn;
mluis 13:618826a997e2 271 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 272 this->settings.LoRa.HopPeriod = hopPeriod;
GregCr 0:e6ceb13d2d05 273 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 274 this->settings.LoRa.RxContinuous = rxContinuous;
mluis 13:618826a997e2 275
GregCr 0:e6ceb13d2d05 276 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 277 {
GregCr 0:e6ceb13d2d05 278 datarate = 12;
GregCr 0:e6ceb13d2d05 279 }
GregCr 0:e6ceb13d2d05 280 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 281 {
GregCr 0:e6ceb13d2d05 282 datarate = 6;
GregCr 0:e6ceb13d2d05 283 }
GregCr 0:e6ceb13d2d05 284
modtronix 20:7cf7c08f0088 285 //bandwidth 6=62.5, 7=125, 8=250, 9=500, datarate=SF. LowDatarateOptimize is mandatory when symbol length > 16ms
modtronix 20:7cf7c08f0088 286 //LowDatarateOptimize = 0 when (BW=500) or (BW=250 and SF=12), else it is ON (Tsym > 16ms)
modtronix 20:7cf7c08f0088 287 if( ( ( bandwidth == 8 ) && ( datarate == 12 ) ) ||
modtronix 20:7cf7c08f0088 288 ( ( bandwidth == 7 ) && ( datarate > 10 ) ) ||
modtronix 20:7cf7c08f0088 289 ( ( bandwidth == 6 ) && ( datarate > 9 ) ) ||
modtronix 20:7cf7c08f0088 290 ( ( bandwidth == 5 ) && ( datarate > 9 ) ) ||
modtronix 20:7cf7c08f0088 291 ( ( bandwidth == 4 ) && ( datarate > 8 ) ) || ( bandwidth < 4 )
modtronix 20:7cf7c08f0088 292 //The below is actually correct method, but assume BW = 20.8 and lower will always have SF > 8
modtronix 20:7cf7c08f0088 293 // ( ( bandwidth == 3 ) && ( datarate > 8 ) ) ||
modtronix 20:7cf7c08f0088 294 // ( ( bandwidth == 2 ) && ( datarate > 7 ) ) ||
modtronix 20:7cf7c08f0088 295 // ( ( bandwidth == 1 ) && ( datarate > 7 ) ) ||
modtronix 20:7cf7c08f0088 296 // ( ( bandwidth == 0 ) && ( datarate > 6 ) )
modtronix 20:7cf7c08f0088 297 )
GregCr 0:e6ceb13d2d05 298 {
GregCr 0:e6ceb13d2d05 299 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 300 }
GregCr 0:e6ceb13d2d05 301 else
GregCr 0:e6ceb13d2d05 302 {
GregCr 0:e6ceb13d2d05 303 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 304 }
GregCr 0:e6ceb13d2d05 305
GregCr 0:e6ceb13d2d05 306 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 307 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 308 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 309 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 310 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
GregCr 0:e6ceb13d2d05 311 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 312 fixLen );
GregCr 0:e6ceb13d2d05 313
GregCr 0:e6ceb13d2d05 314 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 315 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 316 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 317 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
GregCr 0:e6ceb13d2d05 318 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
GregCr 0:e6ceb13d2d05 319 ( datarate << 4 ) | ( crcOn << 2 ) |
GregCr 0:e6ceb13d2d05 320 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
GregCr 0:e6ceb13d2d05 321
GregCr 0:e6ceb13d2d05 322 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 323 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 324 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 325 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
GregCr 0:e6ceb13d2d05 326
GregCr 0:e6ceb13d2d05 327 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
GregCr 0:e6ceb13d2d05 328
GregCr 0:e6ceb13d2d05 329 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 330 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
GregCr 0:e6ceb13d2d05 331
mluis 13:618826a997e2 332 if( fixLen == 1 )
mluis 13:618826a997e2 333 {
mluis 13:618826a997e2 334 Write( REG_LR_PAYLOADLENGTH, payloadLen );
mluis 13:618826a997e2 335 }
mluis 13:618826a997e2 336
GregCr 6:e7f02929cd3d 337 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 338 {
GregCr 6:e7f02929cd3d 339 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 340 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 341 }
GregCr 6:e7f02929cd3d 342
GregCr 0:e6ceb13d2d05 343 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 344 {
GregCr 0:e6ceb13d2d05 345 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 346 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 347 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 348 RFLR_DETECTIONOPTIMIZE_SF6 );
GregCr 0:e6ceb13d2d05 349 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 350 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 351 }
GregCr 0:e6ceb13d2d05 352 else
GregCr 0:e6ceb13d2d05 353 {
GregCr 0:e6ceb13d2d05 354 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 355 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 356 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 357 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 358 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 359 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 360 }
GregCr 0:e6ceb13d2d05 361 }
GregCr 0:e6ceb13d2d05 362 break;
GregCr 0:e6ceb13d2d05 363 }
GregCr 0:e6ceb13d2d05 364 }
GregCr 0:e6ceb13d2d05 365
GregCr 0:e6ceb13d2d05 366 void SX1276::SetTxConfig( ModemType modem, int8_t power, uint32_t fdev,
GregCr 0:e6ceb13d2d05 367 uint32_t bandwidth, uint32_t datarate,
GregCr 0:e6ceb13d2d05 368 uint8_t coderate, uint16_t preambleLen,
mluis 13:618826a997e2 369 bool fixLen, bool crcOn, bool freqHopOn,
mluis 13:618826a997e2 370 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
GregCr 0:e6ceb13d2d05 371 {
GregCr 0:e6ceb13d2d05 372 uint8_t paConfig = 0;
GregCr 0:e6ceb13d2d05 373 uint8_t paDac = 0;
GregCr 0:e6ceb13d2d05 374
GregCr 0:e6ceb13d2d05 375 SetModem( modem );
GregCr 0:e6ceb13d2d05 376
GregCr 0:e6ceb13d2d05 377 paConfig = Read( REG_PACONFIG );
GregCr 0:e6ceb13d2d05 378 paDac = Read( REG_PADAC );
GregCr 0:e6ceb13d2d05 379
GregCr 0:e6ceb13d2d05 380 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
GregCr 0:e6ceb13d2d05 381 paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
GregCr 0:e6ceb13d2d05 382
GregCr 0:e6ceb13d2d05 383 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
GregCr 0:e6ceb13d2d05 384 {
GregCr 0:e6ceb13d2d05 385 if( power > 17 )
GregCr 0:e6ceb13d2d05 386 {
GregCr 0:e6ceb13d2d05 387 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
GregCr 0:e6ceb13d2d05 388 }
GregCr 0:e6ceb13d2d05 389 else
GregCr 0:e6ceb13d2d05 390 {
GregCr 0:e6ceb13d2d05 391 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
GregCr 0:e6ceb13d2d05 392 }
GregCr 0:e6ceb13d2d05 393 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
GregCr 0:e6ceb13d2d05 394 {
GregCr 0:e6ceb13d2d05 395 if( power < 5 )
GregCr 0:e6ceb13d2d05 396 {
GregCr 0:e6ceb13d2d05 397 power = 5;
GregCr 0:e6ceb13d2d05 398 }
GregCr 0:e6ceb13d2d05 399 if( power > 20 )
GregCr 0:e6ceb13d2d05 400 {
GregCr 0:e6ceb13d2d05 401 power = 20;
GregCr 0:e6ceb13d2d05 402 }
GregCr 0:e6ceb13d2d05 403 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
GregCr 0:e6ceb13d2d05 404 }
GregCr 0:e6ceb13d2d05 405 else
GregCr 0:e6ceb13d2d05 406 {
GregCr 0:e6ceb13d2d05 407 if( power < 2 )
GregCr 0:e6ceb13d2d05 408 {
GregCr 0:e6ceb13d2d05 409 power = 2;
GregCr 0:e6ceb13d2d05 410 }
GregCr 0:e6ceb13d2d05 411 if( power > 17 )
GregCr 0:e6ceb13d2d05 412 {
GregCr 0:e6ceb13d2d05 413 power = 17;
GregCr 0:e6ceb13d2d05 414 }
GregCr 0:e6ceb13d2d05 415 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
GregCr 0:e6ceb13d2d05 416 }
GregCr 0:e6ceb13d2d05 417 }
GregCr 0:e6ceb13d2d05 418 else
GregCr 0:e6ceb13d2d05 419 {
GregCr 0:e6ceb13d2d05 420 if( power < -1 )
GregCr 0:e6ceb13d2d05 421 {
GregCr 0:e6ceb13d2d05 422 power = -1;
GregCr 0:e6ceb13d2d05 423 }
GregCr 0:e6ceb13d2d05 424 if( power > 14 )
GregCr 0:e6ceb13d2d05 425 {
GregCr 0:e6ceb13d2d05 426 power = 14;
GregCr 0:e6ceb13d2d05 427 }
GregCr 0:e6ceb13d2d05 428 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
GregCr 0:e6ceb13d2d05 429 }
GregCr 0:e6ceb13d2d05 430 Write( REG_PACONFIG, paConfig );
GregCr 0:e6ceb13d2d05 431 Write( REG_PADAC, paDac );
GregCr 0:e6ceb13d2d05 432
GregCr 0:e6ceb13d2d05 433 switch( modem )
GregCr 0:e6ceb13d2d05 434 {
GregCr 0:e6ceb13d2d05 435 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 436 {
GregCr 0:e6ceb13d2d05 437 this->settings.Fsk.Power = power;
GregCr 0:e6ceb13d2d05 438 this->settings.Fsk.Fdev = fdev;
GregCr 0:e6ceb13d2d05 439 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 440 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 441 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 442 this->settings.Fsk.FixLen = fixLen;
GregCr 0:e6ceb13d2d05 443 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 444 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 445 this->settings.Fsk.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 446
GregCr 0:e6ceb13d2d05 447 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 448 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
GregCr 0:e6ceb13d2d05 449 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
GregCr 0:e6ceb13d2d05 450
GregCr 0:e6ceb13d2d05 451 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 452 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 453 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 454
GregCr 0:e6ceb13d2d05 455 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 456 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 457
GregCr 0:e6ceb13d2d05 458 Write( REG_PACKETCONFIG1,
GregCr 0:e6ceb13d2d05 459 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 460 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 461 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 462 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 463 ( crcOn << 4 ) );
GregCr 0:e6ceb13d2d05 464 }
GregCr 0:e6ceb13d2d05 465 break;
GregCr 0:e6ceb13d2d05 466 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 467 {
GregCr 0:e6ceb13d2d05 468 this->settings.LoRa.Power = power;
modtronix 16:0927c093fd82 469 if( bandwidth > 9 )
GregCr 0:e6ceb13d2d05 470 {
modtronix 16:0927c093fd82 471 // Fatal error: Bandwidth must be 0-9 (7.8 - 500khz)
GregCr 0:e6ceb13d2d05 472 while( 1 );
GregCr 0:e6ceb13d2d05 473 }
modtronix 16:0927c093fd82 474 //bandwidth += 7;
GregCr 0:e6ceb13d2d05 475 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 476 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 477 this->settings.LoRa.Coderate = coderate;
GregCr 0:e6ceb13d2d05 478 this->settings.LoRa.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 479 this->settings.LoRa.FixLen = fixLen;
GregCr 0:e6ceb13d2d05 480 this->settings.LoRa.CrcOn = crcOn;
mluis 13:618826a997e2 481 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 482 this->settings.LoRa.HopPeriod = hopPeriod;
GregCr 0:e6ceb13d2d05 483 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 484 this->settings.LoRa.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 485
GregCr 0:e6ceb13d2d05 486 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 487 {
GregCr 0:e6ceb13d2d05 488 datarate = 12;
GregCr 0:e6ceb13d2d05 489 }
GregCr 0:e6ceb13d2d05 490 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 491 {
GregCr 0:e6ceb13d2d05 492 datarate = 6;
GregCr 0:e6ceb13d2d05 493 }
modtronix 20:7cf7c08f0088 494 //bandwidth 6=62.5, 7=125, 8=250, 9=500, datarate=SF. LowDatarateOptimize is mandatory when symbol length > 16ms
modtronix 20:7cf7c08f0088 495 //LowDatarateOptimize = 0 when (BW=500) or (BW=250 and SF=12), else it is ON (Tsym > 16ms)
modtronix 20:7cf7c08f0088 496 if( ( ( bandwidth == 8 ) && ( datarate == 12 ) ) ||
modtronix 20:7cf7c08f0088 497 ( ( bandwidth == 7 ) && ( datarate > 10 ) ) ||
modtronix 20:7cf7c08f0088 498 ( ( bandwidth == 6 ) && ( datarate > 9 ) ) ||
modtronix 20:7cf7c08f0088 499 ( ( bandwidth == 5 ) && ( datarate > 9 ) ) ||
modtronix 20:7cf7c08f0088 500 ( ( bandwidth == 4 ) && ( datarate > 8 ) ) || ( bandwidth < 4 )
modtronix 20:7cf7c08f0088 501 //The below is actually correct method, but assume BW = 20.8 and lower will always have SF > 8
modtronix 20:7cf7c08f0088 502 // ( ( bandwidth == 3 ) && ( datarate > 8 ) ) ||
modtronix 20:7cf7c08f0088 503 // ( ( bandwidth == 2 ) && ( datarate > 7 ) ) ||
modtronix 20:7cf7c08f0088 504 // ( ( bandwidth == 1 ) && ( datarate > 7 ) ) ||
modtronix 20:7cf7c08f0088 505 // ( ( bandwidth == 0 ) && ( datarate > 6 ) )
modtronix 20:7cf7c08f0088 506 )
GregCr 0:e6ceb13d2d05 507 {
GregCr 0:e6ceb13d2d05 508 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 509 }
GregCr 0:e6ceb13d2d05 510 else
GregCr 0:e6ceb13d2d05 511 {
GregCr 0:e6ceb13d2d05 512 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 513 }
GregCr 6:e7f02929cd3d 514
GregCr 6:e7f02929cd3d 515 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 516 {
GregCr 6:e7f02929cd3d 517 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 518 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 519 }
GregCr 6:e7f02929cd3d 520
GregCr 0:e6ceb13d2d05 521 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 522 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 523 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 524 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 525 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
GregCr 0:e6ceb13d2d05 526 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 527 fixLen );
GregCr 0:e6ceb13d2d05 528
GregCr 0:e6ceb13d2d05 529 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 530 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 531 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 532 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) |
GregCr 0:e6ceb13d2d05 533 ( datarate << 4 ) | ( crcOn << 2 ) );
GregCr 0:e6ceb13d2d05 534
GregCr 0:e6ceb13d2d05 535 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 536 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 537 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 538 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
GregCr 0:e6ceb13d2d05 539
GregCr 0:e6ceb13d2d05 540 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 541 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 542
GregCr 0:e6ceb13d2d05 543 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 544 {
GregCr 0:e6ceb13d2d05 545 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 546 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 547 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 548 RFLR_DETECTIONOPTIMIZE_SF6 );
GregCr 0:e6ceb13d2d05 549 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 550 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 551 }
GregCr 0:e6ceb13d2d05 552 else
GregCr 0:e6ceb13d2d05 553 {
GregCr 0:e6ceb13d2d05 554 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 555 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 556 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 557 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 558 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 559 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 560 }
GregCr 0:e6ceb13d2d05 561 }
GregCr 0:e6ceb13d2d05 562 break;
GregCr 0:e6ceb13d2d05 563 }
GregCr 0:e6ceb13d2d05 564 }
GregCr 0:e6ceb13d2d05 565
GregCr 0:e6ceb13d2d05 566 double SX1276::TimeOnAir( ModemType modem, uint8_t pktLen )
GregCr 0:e6ceb13d2d05 567 {
GregCr 0:e6ceb13d2d05 568 double airTime = 0.0;
GregCr 0:e6ceb13d2d05 569
GregCr 0:e6ceb13d2d05 570 switch( modem )
GregCr 0:e6ceb13d2d05 571 {
GregCr 0:e6ceb13d2d05 572 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 573 {
GregCr 4:f0ce52e94d3f 574 airTime = ceil( ( 8 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 575 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
GregCr 0:e6ceb13d2d05 576 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
GregCr 0:e6ceb13d2d05 577 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
GregCr 0:e6ceb13d2d05 578 pktLen +
GregCr 0:e6ceb13d2d05 579 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
GregCr 0:e6ceb13d2d05 580 this->settings.Fsk.Datarate ) * 1e6 );
GregCr 0:e6ceb13d2d05 581 }
GregCr 0:e6ceb13d2d05 582 break;
GregCr 0:e6ceb13d2d05 583 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 584 {
GregCr 0:e6ceb13d2d05 585 double bw = 0.0;
GregCr 0:e6ceb13d2d05 586 switch( this->settings.LoRa.Bandwidth )
GregCr 0:e6ceb13d2d05 587 {
modtronix 16:0927c093fd82 588 case 0: // 7.8 kHz
modtronix 16:0927c093fd82 589 bw = 78e2;
modtronix 16:0927c093fd82 590 break;
modtronix 16:0927c093fd82 591 case 1: // 10.4 kHz
modtronix 16:0927c093fd82 592 bw = 104e2;
modtronix 16:0927c093fd82 593 break;
modtronix 16:0927c093fd82 594 case 2: // 15.6 kHz
modtronix 16:0927c093fd82 595 bw = 156e2;
modtronix 16:0927c093fd82 596 break;
modtronix 16:0927c093fd82 597 case 3: // 20.8 kHz
modtronix 16:0927c093fd82 598 bw = 208e2;
modtronix 16:0927c093fd82 599 break;
modtronix 16:0927c093fd82 600 case 4: // 31.2 kHz
modtronix 16:0927c093fd82 601 bw = 312e2;
modtronix 16:0927c093fd82 602 break;
modtronix 16:0927c093fd82 603 case 5: // 41.4 kHz
modtronix 16:0927c093fd82 604 bw = 414e2;
modtronix 16:0927c093fd82 605 break;
modtronix 16:0927c093fd82 606 case 6: // 62.5 kHz
modtronix 16:0927c093fd82 607 bw = 625e2;
modtronix 16:0927c093fd82 608 break;
GregCr 0:e6ceb13d2d05 609 case 7: // 125 kHz
GregCr 0:e6ceb13d2d05 610 bw = 125e3;
GregCr 0:e6ceb13d2d05 611 break;
GregCr 0:e6ceb13d2d05 612 case 8: // 250 kHz
GregCr 0:e6ceb13d2d05 613 bw = 250e3;
GregCr 0:e6ceb13d2d05 614 break;
GregCr 0:e6ceb13d2d05 615 case 9: // 500 kHz
GregCr 0:e6ceb13d2d05 616 bw = 500e3;
GregCr 0:e6ceb13d2d05 617 break;
GregCr 0:e6ceb13d2d05 618 }
GregCr 0:e6ceb13d2d05 619
GregCr 0:e6ceb13d2d05 620 // Symbol rate : time for one symbol (secs)
GregCr 0:e6ceb13d2d05 621 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
GregCr 0:e6ceb13d2d05 622 double ts = 1 / rs;
GregCr 0:e6ceb13d2d05 623 // time of preamble
GregCr 0:e6ceb13d2d05 624 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
GregCr 0:e6ceb13d2d05 625 // Symbol length of payload and time
GregCr 0:e6ceb13d2d05 626 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
GregCr 0:e6ceb13d2d05 627 28 + 16 * this->settings.LoRa.CrcOn -
GregCr 0:e6ceb13d2d05 628 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
GregCr 0:e6ceb13d2d05 629 ( double )( 4 * this->settings.LoRa.Datarate -
GregCr 0:e6ceb13d2d05 630 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 8 : 0 ) ) ) *
GregCr 0:e6ceb13d2d05 631 ( this->settings.LoRa.Coderate + 4 );
GregCr 0:e6ceb13d2d05 632 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
GregCr 0:e6ceb13d2d05 633 double tPayload = nPayload * ts;
GregCr 0:e6ceb13d2d05 634 // Time on air
GregCr 0:e6ceb13d2d05 635 double tOnAir = tPreamble + tPayload;
GregCr 0:e6ceb13d2d05 636 // return us secs
GregCr 0:e6ceb13d2d05 637 airTime = floor( tOnAir * 1e6 + 0.999 );
GregCr 0:e6ceb13d2d05 638 }
GregCr 0:e6ceb13d2d05 639 break;
GregCr 0:e6ceb13d2d05 640 }
GregCr 0:e6ceb13d2d05 641 return airTime;
GregCr 0:e6ceb13d2d05 642 }
GregCr 0:e6ceb13d2d05 643
GregCr 0:e6ceb13d2d05 644 void SX1276::Send( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 645 {
GregCr 0:e6ceb13d2d05 646 uint32_t txTimeout = 0;
GregCr 0:e6ceb13d2d05 647
GregCr 5:11ec8a6ba4f0 648 this->settings.State = IDLE;
GregCr 5:11ec8a6ba4f0 649
GregCr 0:e6ceb13d2d05 650 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 651 {
GregCr 0:e6ceb13d2d05 652 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 653 {
GregCr 0:e6ceb13d2d05 654 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 655 this->settings.FskPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 656
GregCr 0:e6ceb13d2d05 657 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 658 {
GregCr 0:e6ceb13d2d05 659 WriteFifo( ( uint8_t* )&size, 1 );
GregCr 0:e6ceb13d2d05 660 }
GregCr 0:e6ceb13d2d05 661 else
GregCr 0:e6ceb13d2d05 662 {
GregCr 0:e6ceb13d2d05 663 Write( REG_PAYLOADLENGTH, size );
GregCr 0:e6ceb13d2d05 664 }
GregCr 0:e6ceb13d2d05 665
GregCr 0:e6ceb13d2d05 666 if( ( size > 0 ) && ( size <= 64 ) )
GregCr 0:e6ceb13d2d05 667 {
GregCr 0:e6ceb13d2d05 668 this->settings.FskPacketHandler.ChunkSize = size;
GregCr 0:e6ceb13d2d05 669 }
GregCr 0:e6ceb13d2d05 670 else
GregCr 0:e6ceb13d2d05 671 {
GregCr 0:e6ceb13d2d05 672 this->settings.FskPacketHandler.ChunkSize = 32;
GregCr 0:e6ceb13d2d05 673 }
GregCr 0:e6ceb13d2d05 674
GregCr 0:e6ceb13d2d05 675 // Write payload buffer
GregCr 0:e6ceb13d2d05 676 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 677 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 678 txTimeout = this->settings.Fsk.TxTimeout;
GregCr 0:e6ceb13d2d05 679 }
GregCr 0:e6ceb13d2d05 680 break;
GregCr 0:e6ceb13d2d05 681 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 682 {
GregCr 0:e6ceb13d2d05 683 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 684 {
GregCr 0:e6ceb13d2d05 685 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
GregCr 0:e6ceb13d2d05 686 }
GregCr 0:e6ceb13d2d05 687 else
GregCr 0:e6ceb13d2d05 688 {
GregCr 0:e6ceb13d2d05 689 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
GregCr 0:e6ceb13d2d05 690 }
GregCr 0:e6ceb13d2d05 691
GregCr 0:e6ceb13d2d05 692 this->settings.LoRaPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 693
GregCr 0:e6ceb13d2d05 694 // Initializes the payload size
GregCr 0:e6ceb13d2d05 695 Write( REG_LR_PAYLOADLENGTH, size );
GregCr 0:e6ceb13d2d05 696
GregCr 0:e6ceb13d2d05 697 // Full buffer used for Tx
GregCr 0:e6ceb13d2d05 698 Write( REG_LR_FIFOTXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 699 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 700
GregCr 0:e6ceb13d2d05 701 // FIFO operations can not take place in Sleep mode
GregCr 0:e6ceb13d2d05 702 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 703 {
GregCr 0:e6ceb13d2d05 704 Standby( );
GregCr 4:f0ce52e94d3f 705 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 706 }
GregCr 0:e6ceb13d2d05 707 // Write payload buffer
GregCr 0:e6ceb13d2d05 708 WriteFifo( buffer, size );
GregCr 0:e6ceb13d2d05 709 txTimeout = this->settings.LoRa.TxTimeout;
GregCr 0:e6ceb13d2d05 710 }
GregCr 0:e6ceb13d2d05 711 break;
GregCr 0:e6ceb13d2d05 712 }
GregCr 0:e6ceb13d2d05 713
GregCr 0:e6ceb13d2d05 714 Tx( txTimeout );
GregCr 0:e6ceb13d2d05 715 }
GregCr 0:e6ceb13d2d05 716
GregCr 0:e6ceb13d2d05 717 void SX1276::Sleep( void )
GregCr 0:e6ceb13d2d05 718 {
mluis 13:618826a997e2 719 // Initialize driver timeout timers
mluis 13:618826a997e2 720 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 721 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 722 SetOpMode( RF_OPMODE_SLEEP );
GregCr 0:e6ceb13d2d05 723 }
GregCr 0:e6ceb13d2d05 724
GregCr 0:e6ceb13d2d05 725 void SX1276::Standby( void )
GregCr 0:e6ceb13d2d05 726 {
GregCr 0:e6ceb13d2d05 727 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 728 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 729 SetOpMode( RF_OPMODE_STANDBY );
GregCr 0:e6ceb13d2d05 730 }
GregCr 0:e6ceb13d2d05 731
GregCr 0:e6ceb13d2d05 732 void SX1276::Rx( uint32_t timeout )
GregCr 0:e6ceb13d2d05 733 {
GregCr 0:e6ceb13d2d05 734 bool rxContinuous = false;
GregCr 6:e7f02929cd3d 735
GregCr 0:e6ceb13d2d05 736 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 737 {
GregCr 0:e6ceb13d2d05 738 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 739 {
GregCr 0:e6ceb13d2d05 740 rxContinuous = this->settings.Fsk.RxContinuous;
GregCr 0:e6ceb13d2d05 741
GregCr 0:e6ceb13d2d05 742 // DIO0=PayloadReady
GregCr 0:e6ceb13d2d05 743 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 744 // DIO2=SyncAddr
GregCr 0:e6ceb13d2d05 745 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 746 // DIO4=Preamble
GregCr 0:e6ceb13d2d05 747 // DIO5=ModeReady
GregCr 5:11ec8a6ba4f0 748 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & RF_DIOMAPPING1_DIO1_MASK &
GregCr 0:e6ceb13d2d05 749 RF_DIOMAPPING1_DIO2_MASK ) |
GregCr 0:e6ceb13d2d05 750 RF_DIOMAPPING1_DIO0_00 |
GregCr 0:e6ceb13d2d05 751 RF_DIOMAPPING1_DIO2_11 );
GregCr 0:e6ceb13d2d05 752
GregCr 0:e6ceb13d2d05 753 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 754 RF_DIOMAPPING2_MAP_MASK ) |
GregCr 0:e6ceb13d2d05 755 RF_DIOMAPPING2_DIO4_11 |
GregCr 0:e6ceb13d2d05 756 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
GregCr 0:e6ceb13d2d05 757
GregCr 0:e6ceb13d2d05 758 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 759
GregCr 0:e6ceb13d2d05 760 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 761 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 762 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 763 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 764 }
GregCr 0:e6ceb13d2d05 765 break;
GregCr 0:e6ceb13d2d05 766 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 767 {
GregCr 0:e6ceb13d2d05 768 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 769 {
GregCr 0:e6ceb13d2d05 770 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
GregCr 0:e6ceb13d2d05 771 }
GregCr 0:e6ceb13d2d05 772 else
GregCr 0:e6ceb13d2d05 773 {
GregCr 0:e6ceb13d2d05 774 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
GregCr 0:e6ceb13d2d05 775 }
GregCr 0:e6ceb13d2d05 776
GregCr 0:e6ceb13d2d05 777 rxContinuous = this->settings.LoRa.RxContinuous;
GregCr 0:e6ceb13d2d05 778
GregCr 6:e7f02929cd3d 779 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 780 {
GregCr 6:e7f02929cd3d 781 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 782 //RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 783 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 4:f0ce52e94d3f 784 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 785 RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 786 RFLR_IRQFLAGS_CADDONE |
GregCr 6:e7f02929cd3d 787 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 788 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 789
mluis 13:618826a997e2 790 // DIO0=RxDone, DIO2=FhssChangeChannel
mluis 13:618826a997e2 791 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 792 }
GregCr 6:e7f02929cd3d 793 else
GregCr 6:e7f02929cd3d 794 {
GregCr 6:e7f02929cd3d 795 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 6:e7f02929cd3d 796 //RFLR_IRQFLAGS_RXDONE |
GregCr 6:e7f02929cd3d 797 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 6:e7f02929cd3d 798 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 6:e7f02929cd3d 799 RFLR_IRQFLAGS_TXDONE |
GregCr 6:e7f02929cd3d 800 RFLR_IRQFLAGS_CADDONE |
GregCr 8:0fe3e0e8007b 801 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 6:e7f02929cd3d 802 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 803
GregCr 6:e7f02929cd3d 804 // DIO0=RxDone
GregCr 6:e7f02929cd3d 805 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 6:e7f02929cd3d 806 }
GregCr 0:e6ceb13d2d05 807
GregCr 0:e6ceb13d2d05 808 Write( REG_LR_FIFORXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 809 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 810 }
GregCr 0:e6ceb13d2d05 811 break;
GregCr 0:e6ceb13d2d05 812 }
GregCr 0:e6ceb13d2d05 813
GregCr 0:e6ceb13d2d05 814 memset( rxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
GregCr 0:e6ceb13d2d05 815
GregCr 0:e6ceb13d2d05 816 this->settings.State = RX;
GregCr 0:e6ceb13d2d05 817 if( timeout != 0 )
GregCr 0:e6ceb13d2d05 818 {
GregCr 0:e6ceb13d2d05 819 rxTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 820 }
GregCr 0:e6ceb13d2d05 821
GregCr 0:e6ceb13d2d05 822 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 823 {
GregCr 0:e6ceb13d2d05 824 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 825
GregCr 0:e6ceb13d2d05 826 if( rxContinuous == false )
GregCr 0:e6ceb13d2d05 827 {
GregCr 0:e6ceb13d2d05 828 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 829 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 830 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
GregCr 0:e6ceb13d2d05 831 1.0 ) + 1.0 ) /
GregCr 0:e6ceb13d2d05 832 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 833 }
GregCr 0:e6ceb13d2d05 834 }
GregCr 0:e6ceb13d2d05 835 else
GregCr 0:e6ceb13d2d05 836 {
GregCr 0:e6ceb13d2d05 837 if( rxContinuous == true )
GregCr 0:e6ceb13d2d05 838 {
GregCr 0:e6ceb13d2d05 839 SetOpMode( RFLR_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 840 }
GregCr 0:e6ceb13d2d05 841 else
GregCr 0:e6ceb13d2d05 842 {
GregCr 0:e6ceb13d2d05 843 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
GregCr 0:e6ceb13d2d05 844 }
GregCr 0:e6ceb13d2d05 845 }
GregCr 0:e6ceb13d2d05 846 }
GregCr 0:e6ceb13d2d05 847
GregCr 0:e6ceb13d2d05 848 void SX1276::Tx( uint32_t timeout )
GregCr 0:e6ceb13d2d05 849 {
GregCr 0:e6ceb13d2d05 850 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 851 {
GregCr 0:e6ceb13d2d05 852 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 853 {
GregCr 0:e6ceb13d2d05 854 // DIO0=PacketSent
GregCr 0:e6ceb13d2d05 855 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 856 // DIO2=FifoFull
GregCr 0:e6ceb13d2d05 857 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 858 // DIO4=LowBat
GregCr 0:e6ceb13d2d05 859 // DIO5=ModeReady
GregCr 5:11ec8a6ba4f0 860 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & RF_DIOMAPPING1_DIO1_MASK &
GregCr 0:e6ceb13d2d05 861 RF_DIOMAPPING1_DIO2_MASK ) );
GregCr 0:e6ceb13d2d05 862
GregCr 0:e6ceb13d2d05 863 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 864 RF_DIOMAPPING2_MAP_MASK ) );
GregCr 0:e6ceb13d2d05 865 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 866 }
GregCr 0:e6ceb13d2d05 867 break;
GregCr 0:e6ceb13d2d05 868 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 869 {
GregCr 6:e7f02929cd3d 870
GregCr 6:e7f02929cd3d 871 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 872 {
GregCr 6:e7f02929cd3d 873 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 6:e7f02929cd3d 874 RFLR_IRQFLAGS_RXDONE |
GregCr 6:e7f02929cd3d 875 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 6:e7f02929cd3d 876 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 6:e7f02929cd3d 877 //RFLR_IRQFLAGS_TXDONE |
GregCr 6:e7f02929cd3d 878 RFLR_IRQFLAGS_CADDONE |
GregCr 6:e7f02929cd3d 879 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 6:e7f02929cd3d 880 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 881
GregCr 6:e7f02929cd3d 882 // DIO0=TxDone
GregCr 8:0fe3e0e8007b 883 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
GregCr 6:e7f02929cd3d 884 // DIO2=FhssChangeChannel
GregCr 6:e7f02929cd3d 885 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 886 }
GregCr 6:e7f02929cd3d 887 else
GregCr 6:e7f02929cd3d 888 {
GregCr 6:e7f02929cd3d 889 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 890 RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 891 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 0:e6ceb13d2d05 892 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 893 //RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 894 RFLR_IRQFLAGS_CADDONE |
GregCr 0:e6ceb13d2d05 895 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 896 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 897
GregCr 6:e7f02929cd3d 898 // DIO0=TxDone
GregCr 6:e7f02929cd3d 899 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
GregCr 6:e7f02929cd3d 900 }
GregCr 0:e6ceb13d2d05 901 }
GregCr 0:e6ceb13d2d05 902 break;
GregCr 0:e6ceb13d2d05 903 }
GregCr 0:e6ceb13d2d05 904
GregCr 0:e6ceb13d2d05 905 this->settings.State = TX;
mluis 13:618826a997e2 906 txTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 907 SetOpMode( RF_OPMODE_TRANSMITTER );
GregCr 0:e6ceb13d2d05 908 }
GregCr 0:e6ceb13d2d05 909
GregCr 7:2b555111463f 910 void SX1276::StartCad( void )
GregCr 0:e6ceb13d2d05 911 {
GregCr 7:2b555111463f 912 switch( this->settings.Modem )
GregCr 7:2b555111463f 913 {
GregCr 7:2b555111463f 914 case MODEM_FSK:
GregCr 7:2b555111463f 915 {
GregCr 7:2b555111463f 916
GregCr 7:2b555111463f 917 }
GregCr 7:2b555111463f 918 break;
GregCr 7:2b555111463f 919 case MODEM_LORA:
GregCr 7:2b555111463f 920 {
GregCr 7:2b555111463f 921 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 7:2b555111463f 922 RFLR_IRQFLAGS_RXDONE |
GregCr 7:2b555111463f 923 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 7:2b555111463f 924 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 7:2b555111463f 925 RFLR_IRQFLAGS_TXDONE |
GregCr 7:2b555111463f 926 //RFLR_IRQFLAGS_CADDONE |
GregCr 12:aa5b3bf7fdf4 927 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
GregCr 12:aa5b3bf7fdf4 928 //RFLR_IRQFLAGS_CADDETECTED
GregCr 12:aa5b3bf7fdf4 929 );
GregCr 7:2b555111463f 930
GregCr 7:2b555111463f 931 // DIO3=CADDone
GregCr 7:2b555111463f 932 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 7:2b555111463f 933
GregCr 7:2b555111463f 934 this->settings.State = CAD;
GregCr 7:2b555111463f 935 SetOpMode( RFLR_OPMODE_CAD );
GregCr 7:2b555111463f 936 }
GregCr 7:2b555111463f 937 break;
GregCr 7:2b555111463f 938 default:
GregCr 7:2b555111463f 939 break;
GregCr 7:2b555111463f 940 }
GregCr 7:2b555111463f 941 }
GregCr 7:2b555111463f 942
GregCr 7:2b555111463f 943 int16_t SX1276::GetRssi( ModemType modem )
GregCr 7:2b555111463f 944 {
GregCr 7:2b555111463f 945 int16_t rssi = 0;
GregCr 0:e6ceb13d2d05 946
GregCr 0:e6ceb13d2d05 947 switch( modem )
GregCr 0:e6ceb13d2d05 948 {
GregCr 0:e6ceb13d2d05 949 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 950 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 951 break;
GregCr 0:e6ceb13d2d05 952 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 953 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 954 {
GregCr 0:e6ceb13d2d05 955 rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 956 }
GregCr 0:e6ceb13d2d05 957 else
GregCr 0:e6ceb13d2d05 958 {
GregCr 0:e6ceb13d2d05 959 rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 960 }
GregCr 0:e6ceb13d2d05 961 break;
GregCr 0:e6ceb13d2d05 962 default:
GregCr 0:e6ceb13d2d05 963 rssi = -1;
GregCr 0:e6ceb13d2d05 964 break;
GregCr 0:e6ceb13d2d05 965 }
GregCr 0:e6ceb13d2d05 966 return rssi;
GregCr 0:e6ceb13d2d05 967 }
GregCr 0:e6ceb13d2d05 968
GregCr 0:e6ceb13d2d05 969 void SX1276::SetOpMode( uint8_t opMode )
GregCr 0:e6ceb13d2d05 970 {
GregCr 0:e6ceb13d2d05 971 if( opMode != previousOpMode )
GregCr 0:e6ceb13d2d05 972 {
GregCr 0:e6ceb13d2d05 973 previousOpMode = opMode;
GregCr 0:e6ceb13d2d05 974 if( opMode == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 975 {
GregCr 0:e6ceb13d2d05 976 SetAntSwLowPower( true );
GregCr 0:e6ceb13d2d05 977 }
GregCr 0:e6ceb13d2d05 978 else
GregCr 0:e6ceb13d2d05 979 {
GregCr 0:e6ceb13d2d05 980 SetAntSwLowPower( false );
GregCr 0:e6ceb13d2d05 981 if( opMode == RF_OPMODE_TRANSMITTER )
GregCr 0:e6ceb13d2d05 982 {
GregCr 0:e6ceb13d2d05 983 SetAntSw( 1 );
GregCr 0:e6ceb13d2d05 984 }
GregCr 0:e6ceb13d2d05 985 else
GregCr 0:e6ceb13d2d05 986 {
GregCr 0:e6ceb13d2d05 987 SetAntSw( 0 );
GregCr 0:e6ceb13d2d05 988 }
GregCr 0:e6ceb13d2d05 989 }
GregCr 0:e6ceb13d2d05 990 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
GregCr 0:e6ceb13d2d05 991 }
GregCr 0:e6ceb13d2d05 992 }
GregCr 0:e6ceb13d2d05 993
GregCr 0:e6ceb13d2d05 994 void SX1276::SetModem( ModemType modem )
GregCr 0:e6ceb13d2d05 995 {
GregCr 4:f0ce52e94d3f 996 if( this->settings.Modem != modem )
GregCr 0:e6ceb13d2d05 997 {
mluis 13:618826a997e2 998 this->settings.Modem = modem;
mluis 13:618826a997e2 999 switch( this->settings.Modem )
mluis 13:618826a997e2 1000 {
mluis 13:618826a997e2 1001 default:
mluis 13:618826a997e2 1002 case MODEM_FSK:
mluis 13:618826a997e2 1003 SetOpMode( RF_OPMODE_SLEEP );
mluis 13:618826a997e2 1004 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
mluis 13:618826a997e2 1005
mluis 13:618826a997e2 1006 Write( REG_DIOMAPPING1, 0x00 );
mluis 13:618826a997e2 1007 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
mluis 13:618826a997e2 1008 break;
mluis 13:618826a997e2 1009 case MODEM_LORA:
mluis 13:618826a997e2 1010 SetOpMode( RF_OPMODE_SLEEP );
mluis 13:618826a997e2 1011 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
mluis 13:618826a997e2 1012 Write( 0x30, 0x00 ); // IF = 0
mluis 13:618826a997e2 1013 Write( REG_LR_DETECTOPTIMIZE, ( Read( REG_LR_DETECTOPTIMIZE ) & 0x7F ) ); // Manual IF
mluis 13:618826a997e2 1014 Write( REG_DIOMAPPING1, 0x00 );
mluis 13:618826a997e2 1015 Write( REG_DIOMAPPING2, 0x00 );
mluis 13:618826a997e2 1016 break;
mluis 13:618826a997e2 1017 }
GregCr 0:e6ceb13d2d05 1018 }
GregCr 0:e6ceb13d2d05 1019 }
GregCr 0:e6ceb13d2d05 1020
GregCr 0:e6ceb13d2d05 1021 void SX1276::OnTimeoutIrq( void )
GregCr 0:e6ceb13d2d05 1022 {
GregCr 0:e6ceb13d2d05 1023 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1024 {
GregCr 0:e6ceb13d2d05 1025 case RX:
GregCr 0:e6ceb13d2d05 1026 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 1027 {
GregCr 0:e6ceb13d2d05 1028 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1029 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1030 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1031 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1032
GregCr 0:e6ceb13d2d05 1033 // Clear Irqs
GregCr 0:e6ceb13d2d05 1034 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 0:e6ceb13d2d05 1035 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 0:e6ceb13d2d05 1036 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 0:e6ceb13d2d05 1037 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 0:e6ceb13d2d05 1038
GregCr 0:e6ceb13d2d05 1039 if( this->settings.Fsk.RxContinuous == true )
GregCr 0:e6ceb13d2d05 1040 {
GregCr 0:e6ceb13d2d05 1041 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1042 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1043 }
GregCr 0:e6ceb13d2d05 1044 else
GregCr 0:e6ceb13d2d05 1045 {
GregCr 5:11ec8a6ba4f0 1046 this->settings.State = IDLE;
GregCr 5:11ec8a6ba4f0 1047 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 1048 }
GregCr 0:e6ceb13d2d05 1049 }
GregCr 0:e6ceb13d2d05 1050 if( ( rxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1051 {
GregCr 0:e6ceb13d2d05 1052 rxTimeout( );
GregCr 0:e6ceb13d2d05 1053 }
GregCr 0:e6ceb13d2d05 1054 break;
GregCr 0:e6ceb13d2d05 1055 case TX:
mluis 13:618826a997e2 1056 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1057 if( ( txTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1058 {
GregCr 0:e6ceb13d2d05 1059 txTimeout( );
GregCr 0:e6ceb13d2d05 1060 }
GregCr 0:e6ceb13d2d05 1061 break;
GregCr 0:e6ceb13d2d05 1062 default:
GregCr 0:e6ceb13d2d05 1063 break;
GregCr 0:e6ceb13d2d05 1064 }
GregCr 0:e6ceb13d2d05 1065 }
GregCr 0:e6ceb13d2d05 1066
GregCr 0:e6ceb13d2d05 1067 void SX1276::OnDio0Irq( void )
GregCr 0:e6ceb13d2d05 1068 {
GregCr 0:e6ceb13d2d05 1069 __IO uint8_t irqFlags = 0;
modtronix 20:7cf7c08f0088 1070
GregCr 0:e6ceb13d2d05 1071 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1072 {
GregCr 0:e6ceb13d2d05 1073 case RX:
GregCr 0:e6ceb13d2d05 1074 //TimerStop( &RxTimeoutTimer );
GregCr 0:e6ceb13d2d05 1075 // RxDone interrupt
GregCr 0:e6ceb13d2d05 1076 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1077 {
GregCr 0:e6ceb13d2d05 1078 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1079 irqFlags = Read( REG_IRQFLAGS2 );
GregCr 0:e6ceb13d2d05 1080 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
GregCr 0:e6ceb13d2d05 1081 {
GregCr 0:e6ceb13d2d05 1082 // Clear Irqs
GregCr 0:e6ceb13d2d05 1083 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 0:e6ceb13d2d05 1084 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 0:e6ceb13d2d05 1085 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 0:e6ceb13d2d05 1086 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 0:e6ceb13d2d05 1087
GregCr 0:e6ceb13d2d05 1088 if( this->settings.Fsk.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1089 {
GregCr 0:e6ceb13d2d05 1090 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1091 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 1092 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 1093 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
GregCr 0:e6ceb13d2d05 1094 1.0 ) + 1.0 ) /
GregCr 0:e6ceb13d2d05 1095 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 1096 }
GregCr 0:e6ceb13d2d05 1097 else
GregCr 0:e6ceb13d2d05 1098 {
GregCr 0:e6ceb13d2d05 1099 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1100 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1101 }
GregCr 0:e6ceb13d2d05 1102 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1103
GregCr 0:e6ceb13d2d05 1104 if( ( rxError != NULL ) )
GregCr 0:e6ceb13d2d05 1105 {
GregCr 0:e6ceb13d2d05 1106 rxError( );
GregCr 0:e6ceb13d2d05 1107 }
GregCr 0:e6ceb13d2d05 1108 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1109 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1110 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1111 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1112 break;
GregCr 0:e6ceb13d2d05 1113 }
GregCr 0:e6ceb13d2d05 1114
GregCr 0:e6ceb13d2d05 1115 // Read received packet size
GregCr 0:e6ceb13d2d05 1116 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1117 {
GregCr 0:e6ceb13d2d05 1118 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1119 {
GregCr 0:e6ceb13d2d05 1120 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1121 }
GregCr 0:e6ceb13d2d05 1122 else
GregCr 0:e6ceb13d2d05 1123 {
GregCr 0:e6ceb13d2d05 1124 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1125 }
GregCr 0:e6ceb13d2d05 1126 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1127 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1128 }
GregCr 0:e6ceb13d2d05 1129 else
GregCr 0:e6ceb13d2d05 1130 {
GregCr 0:e6ceb13d2d05 1131 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1132 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1133 }
GregCr 0:e6ceb13d2d05 1134
GregCr 0:e6ceb13d2d05 1135 if( this->settings.Fsk.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1136 {
GregCr 0:e6ceb13d2d05 1137 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1138 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 1139 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 1140 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
GregCr 0:e6ceb13d2d05 1141 1.0 ) + 1.0 ) /
GregCr 0:e6ceb13d2d05 1142 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 1143 }
GregCr 0:e6ceb13d2d05 1144 else
GregCr 0:e6ceb13d2d05 1145 {
GregCr 0:e6ceb13d2d05 1146 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1147 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1148 }
GregCr 0:e6ceb13d2d05 1149 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1150
GregCr 0:e6ceb13d2d05 1151 if( (rxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1152 {
GregCr 0:e6ceb13d2d05 1153 rxDone( rxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
GregCr 0:e6ceb13d2d05 1154 }
GregCr 0:e6ceb13d2d05 1155 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1156 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1157 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1158 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1159 break;
GregCr 0:e6ceb13d2d05 1160 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1161 {
GregCr 0:e6ceb13d2d05 1162 uint8_t snr = 0;
GregCr 0:e6ceb13d2d05 1163
GregCr 0:e6ceb13d2d05 1164 // Clear Irq
GregCr 0:e6ceb13d2d05 1165 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
GregCr 0:e6ceb13d2d05 1166
GregCr 0:e6ceb13d2d05 1167 irqFlags = Read( REG_LR_IRQFLAGS );
GregCr 0:e6ceb13d2d05 1168 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
GregCr 0:e6ceb13d2d05 1169 {
GregCr 0:e6ceb13d2d05 1170 // Clear Irq
GregCr 0:e6ceb13d2d05 1171 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
GregCr 0:e6ceb13d2d05 1172
GregCr 0:e6ceb13d2d05 1173 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1174 {
GregCr 0:e6ceb13d2d05 1175 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1176 }
GregCr 0:e6ceb13d2d05 1177 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1178
GregCr 4:f0ce52e94d3f 1179 if( ( rxError != NULL ) )
GregCr 0:e6ceb13d2d05 1180 {
GregCr 0:e6ceb13d2d05 1181 rxError( );
GregCr 0:e6ceb13d2d05 1182 }
GregCr 0:e6ceb13d2d05 1183 break;
GregCr 0:e6ceb13d2d05 1184 }
GregCr 0:e6ceb13d2d05 1185
GregCr 0:e6ceb13d2d05 1186 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
GregCr 0:e6ceb13d2d05 1187 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
GregCr 0:e6ceb13d2d05 1188 {
GregCr 0:e6ceb13d2d05 1189 // Invert and divide by 4
GregCr 0:e6ceb13d2d05 1190 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1191 snr = -snr;
GregCr 0:e6ceb13d2d05 1192 }
GregCr 0:e6ceb13d2d05 1193 else
GregCr 0:e6ceb13d2d05 1194 {
GregCr 0:e6ceb13d2d05 1195 // Divide by 4
GregCr 0:e6ceb13d2d05 1196 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1197 }
GregCr 0:e6ceb13d2d05 1198
GregCr 7:2b555111463f 1199 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
GregCr 0:e6ceb13d2d05 1200 if( this->settings.LoRaPacketHandler.SnrValue < 0 )
GregCr 0:e6ceb13d2d05 1201 {
GregCr 0:e6ceb13d2d05 1202 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1203 {
GregCr 0:e6ceb13d2d05 1204 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1205 snr;
GregCr 0:e6ceb13d2d05 1206 }
GregCr 0:e6ceb13d2d05 1207 else
GregCr 0:e6ceb13d2d05 1208 {
GregCr 0:e6ceb13d2d05 1209 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1210 snr;
GregCr 0:e6ceb13d2d05 1211 }
GregCr 0:e6ceb13d2d05 1212 }
GregCr 0:e6ceb13d2d05 1213 else
GregCr 0:e6ceb13d2d05 1214 {
GregCr 0:e6ceb13d2d05 1215 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1216 {
GregCr 0:e6ceb13d2d05 1217 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1218 }
GregCr 0:e6ceb13d2d05 1219 else
GregCr 0:e6ceb13d2d05 1220 {
GregCr 0:e6ceb13d2d05 1221 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1222 }
GregCr 0:e6ceb13d2d05 1223 }
GregCr 0:e6ceb13d2d05 1224
GregCr 0:e6ceb13d2d05 1225 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
GregCr 0:e6ceb13d2d05 1226 ReadFifo( rxBuffer, this->settings.LoRaPacketHandler.Size );
GregCr 0:e6ceb13d2d05 1227
GregCr 0:e6ceb13d2d05 1228 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1229 {
GregCr 0:e6ceb13d2d05 1230 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1231 }
GregCr 0:e6ceb13d2d05 1232 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1233
GregCr 0:e6ceb13d2d05 1234 if( ( rxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1235 {
GregCr 0:e6ceb13d2d05 1236 rxDone( rxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
GregCr 0:e6ceb13d2d05 1237 }
GregCr 0:e6ceb13d2d05 1238 }
GregCr 0:e6ceb13d2d05 1239 break;
GregCr 0:e6ceb13d2d05 1240 default:
GregCr 0:e6ceb13d2d05 1241 break;
GregCr 0:e6ceb13d2d05 1242 }
GregCr 0:e6ceb13d2d05 1243 break;
GregCr 0:e6ceb13d2d05 1244 case TX:
GregCr 0:e6ceb13d2d05 1245 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1246 // TxDone interrupt
GregCr 0:e6ceb13d2d05 1247 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1248 {
GregCr 0:e6ceb13d2d05 1249 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1250 // Clear Irq
GregCr 0:e6ceb13d2d05 1251 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
GregCr 0:e6ceb13d2d05 1252 // Intentional fall through
GregCr 0:e6ceb13d2d05 1253 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1254 default:
GregCr 0:e6ceb13d2d05 1255 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1256 if( ( txDone != NULL ) )
GregCr 0:e6ceb13d2d05 1257 {
GregCr 0:e6ceb13d2d05 1258 txDone( );
GregCr 0:e6ceb13d2d05 1259 }
GregCr 0:e6ceb13d2d05 1260 break;
GregCr 0:e6ceb13d2d05 1261 }
GregCr 0:e6ceb13d2d05 1262 break;
GregCr 0:e6ceb13d2d05 1263 default:
GregCr 0:e6ceb13d2d05 1264 break;
GregCr 0:e6ceb13d2d05 1265 }
GregCr 0:e6ceb13d2d05 1266 }
GregCr 0:e6ceb13d2d05 1267
GregCr 0:e6ceb13d2d05 1268 void SX1276::OnDio1Irq( void )
GregCr 0:e6ceb13d2d05 1269 {
GregCr 0:e6ceb13d2d05 1270 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1271 {
GregCr 0:e6ceb13d2d05 1272 case RX:
GregCr 0:e6ceb13d2d05 1273 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1274 {
GregCr 0:e6ceb13d2d05 1275 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1276 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1277 // Read received packet size
GregCr 0:e6ceb13d2d05 1278 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1279 {
GregCr 0:e6ceb13d2d05 1280 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1281 {
GregCr 0:e6ceb13d2d05 1282 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1283 }
GregCr 0:e6ceb13d2d05 1284 else
GregCr 0:e6ceb13d2d05 1285 {
GregCr 0:e6ceb13d2d05 1286 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1287 }
GregCr 0:e6ceb13d2d05 1288 }
GregCr 0:e6ceb13d2d05 1289
GregCr 0:e6ceb13d2d05 1290 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
GregCr 0:e6ceb13d2d05 1291 {
GregCr 0:e6ceb13d2d05 1292 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
GregCr 0:e6ceb13d2d05 1293 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
GregCr 0:e6ceb13d2d05 1294 }
GregCr 0:e6ceb13d2d05 1295 else
GregCr 0:e6ceb13d2d05 1296 {
GregCr 0:e6ceb13d2d05 1297 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1298 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1299 }
GregCr 0:e6ceb13d2d05 1300 break;
GregCr 0:e6ceb13d2d05 1301 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1302 // Sync time out
GregCr 0:e6ceb13d2d05 1303 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1304 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1305 if( ( rxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1306 {
GregCr 0:e6ceb13d2d05 1307 rxTimeout( );
GregCr 0:e6ceb13d2d05 1308 }
GregCr 0:e6ceb13d2d05 1309 break;
GregCr 0:e6ceb13d2d05 1310 default:
GregCr 0:e6ceb13d2d05 1311 break;
GregCr 0:e6ceb13d2d05 1312 }
GregCr 0:e6ceb13d2d05 1313 break;
GregCr 0:e6ceb13d2d05 1314 case TX:
GregCr 0:e6ceb13d2d05 1315 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1316 {
GregCr 0:e6ceb13d2d05 1317 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1318 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1319 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
GregCr 0:e6ceb13d2d05 1320 {
GregCr 0:e6ceb13d2d05 1321 WriteFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 1322 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 1323 }
GregCr 0:e6ceb13d2d05 1324 else
GregCr 0:e6ceb13d2d05 1325 {
GregCr 0:e6ceb13d2d05 1326 // Write the last chunk of data
GregCr 0:e6ceb13d2d05 1327 WriteFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1328 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
GregCr 0:e6ceb13d2d05 1329 }
GregCr 0:e6ceb13d2d05 1330 break;
GregCr 0:e6ceb13d2d05 1331 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1332 break;
GregCr 0:e6ceb13d2d05 1333 default:
GregCr 0:e6ceb13d2d05 1334 break;
GregCr 0:e6ceb13d2d05 1335 }
GregCr 0:e6ceb13d2d05 1336 break;
GregCr 0:e6ceb13d2d05 1337 default:
GregCr 0:e6ceb13d2d05 1338 break;
GregCr 0:e6ceb13d2d05 1339 }
GregCr 0:e6ceb13d2d05 1340 }
GregCr 0:e6ceb13d2d05 1341
GregCr 0:e6ceb13d2d05 1342 void SX1276::OnDio2Irq( void )
GregCr 0:e6ceb13d2d05 1343 {
GregCr 0:e6ceb13d2d05 1344 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1345 {
GregCr 0:e6ceb13d2d05 1346 case RX:
GregCr 0:e6ceb13d2d05 1347 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1348 {
GregCr 0:e6ceb13d2d05 1349 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1350 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
GregCr 0:e6ceb13d2d05 1351 {
GregCr 0:e6ceb13d2d05 1352 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 1353
GregCr 0:e6ceb13d2d05 1354 this->settings.FskPacketHandler.SyncWordDetected = true;
GregCr 0:e6ceb13d2d05 1355
GregCr 0:e6ceb13d2d05 1356 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 1357
GregCr 0:e6ceb13d2d05 1358 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
GregCr 0:e6ceb13d2d05 1359 ( uint16_t )Read( REG_AFCLSB ) ) *
GregCr 0:e6ceb13d2d05 1360 ( double )FREQ_STEP;
GregCr 0:e6ceb13d2d05 1361 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
GregCr 0:e6ceb13d2d05 1362 }
GregCr 0:e6ceb13d2d05 1363 break;
GregCr 0:e6ceb13d2d05 1364 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1365 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1366 {
GregCr 6:e7f02929cd3d 1367 // Clear Irq
GregCr 6:e7f02929cd3d 1368 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
GregCr 6:e7f02929cd3d 1369
mluis 13:618826a997e2 1370 if( ( fhssChangeChannel != NULL ) )
mluis 13:618826a997e2 1371 {
mluis 13:618826a997e2 1372 fhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1373 }
GregCr 6:e7f02929cd3d 1374 }
GregCr 0:e6ceb13d2d05 1375 break;
GregCr 0:e6ceb13d2d05 1376 default:
GregCr 0:e6ceb13d2d05 1377 break;
GregCr 0:e6ceb13d2d05 1378 }
GregCr 0:e6ceb13d2d05 1379 break;
GregCr 0:e6ceb13d2d05 1380 case TX:
GregCr 0:e6ceb13d2d05 1381 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1382 {
GregCr 0:e6ceb13d2d05 1383 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1384 break;
GregCr 0:e6ceb13d2d05 1385 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1386 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1387 {
GregCr 6:e7f02929cd3d 1388 // Clear Irq
GregCr 6:e7f02929cd3d 1389 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
GregCr 6:e7f02929cd3d 1390
mluis 13:618826a997e2 1391 if( ( fhssChangeChannel != NULL ) )
mluis 13:618826a997e2 1392 {
mluis 13:618826a997e2 1393 fhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1394 }
GregCr 6:e7f02929cd3d 1395 }
GregCr 0:e6ceb13d2d05 1396 break;
GregCr 0:e6ceb13d2d05 1397 default:
GregCr 0:e6ceb13d2d05 1398 break;
GregCr 0:e6ceb13d2d05 1399 }
GregCr 0:e6ceb13d2d05 1400 break;
GregCr 0:e6ceb13d2d05 1401 default:
GregCr 0:e6ceb13d2d05 1402 break;
GregCr 0:e6ceb13d2d05 1403 }
GregCr 0:e6ceb13d2d05 1404 }
GregCr 0:e6ceb13d2d05 1405
GregCr 0:e6ceb13d2d05 1406 void SX1276::OnDio3Irq( void )
GregCr 0:e6ceb13d2d05 1407 {
GregCr 0:e6ceb13d2d05 1408 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1409 {
GregCr 0:e6ceb13d2d05 1410 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1411 break;
GregCr 0:e6ceb13d2d05 1412 case MODEM_LORA:
mluis 13:618826a997e2 1413 if( ( Read( REG_LR_IRQFLAGS ) & 0x01 ) == 0x01 )
mluis 13:618826a997e2 1414 {
mluis 13:618826a997e2 1415 // Clear Irq
mluis 13:618826a997e2 1416 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED_MASK | RFLR_IRQFLAGS_CADDONE);
mluis 13:618826a997e2 1417 if( ( cadDone != NULL ) )
mluis 13:618826a997e2 1418 {
mluis 13:618826a997e2 1419 cadDone( true );
mluis 13:618826a997e2 1420 }
GregCr 12:aa5b3bf7fdf4 1421 }
GregCr 12:aa5b3bf7fdf4 1422 else
mluis 13:618826a997e2 1423 {
mluis 13:618826a997e2 1424 // Clear Irq
mluis 13:618826a997e2 1425 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
mluis 13:618826a997e2 1426 if( ( cadDone != NULL ) )
mluis 13:618826a997e2 1427 {
mluis 13:618826a997e2 1428 cadDone( false );
mluis 13:618826a997e2 1429 }
GregCr 7:2b555111463f 1430 }
GregCr 0:e6ceb13d2d05 1431 break;
GregCr 0:e6ceb13d2d05 1432 default:
GregCr 0:e6ceb13d2d05 1433 break;
GregCr 0:e6ceb13d2d05 1434 }
GregCr 0:e6ceb13d2d05 1435 }
GregCr 0:e6ceb13d2d05 1436
GregCr 0:e6ceb13d2d05 1437 void SX1276::OnDio4Irq( void )
GregCr 0:e6ceb13d2d05 1438 {
GregCr 0:e6ceb13d2d05 1439 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1440 {
GregCr 0:e6ceb13d2d05 1441 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1442 {
GregCr 0:e6ceb13d2d05 1443 if( this->settings.FskPacketHandler.PreambleDetected == false )
GregCr 0:e6ceb13d2d05 1444 {
GregCr 0:e6ceb13d2d05 1445 this->settings.FskPacketHandler.PreambleDetected = true;
GregCr 0:e6ceb13d2d05 1446 }
GregCr 0:e6ceb13d2d05 1447 }
GregCr 0:e6ceb13d2d05 1448 break;
GregCr 0:e6ceb13d2d05 1449 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1450 break;
GregCr 0:e6ceb13d2d05 1451 default:
GregCr 0:e6ceb13d2d05 1452 break;
GregCr 0:e6ceb13d2d05 1453 }
GregCr 0:e6ceb13d2d05 1454 }
GregCr 0:e6ceb13d2d05 1455
GregCr 0:e6ceb13d2d05 1456 void SX1276::OnDio5Irq( void )
GregCr 0:e6ceb13d2d05 1457 {
GregCr 0:e6ceb13d2d05 1458 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1459 {
GregCr 0:e6ceb13d2d05 1460 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1461 break;
GregCr 0:e6ceb13d2d05 1462 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1463 break;
GregCr 0:e6ceb13d2d05 1464 default:
GregCr 0:e6ceb13d2d05 1465 break;
GregCr 0:e6ceb13d2d05 1466 }
mluis 13:618826a997e2 1467 }