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_mcg_config Struct Reference

_mcg_config Struct Reference
[Clock]

MCG configure structure for mode change. More...

#include <fsl_clock.h>

Data Fields

mcg_mode_t mcgMode
uint8_t irclkEnableMode
mcg_irc_mode_t ircs
uint8_t fcrdiv
uint8_t frdiv
mcg_drs_t drs
mcg_dmx32_t dmx32
mcg_oscsel_t oscsel
mcg_pll_config_t pll0Config
mcg_pll_clk_select_t pllcs

Detailed Description

MCG configure structure for mode change.

When porting to a new board, please set the following members according to board setting: 1. frdiv: If FLL uses the external reference clock, please set this value to make sure external reference clock divided by frdiv is in the range 31.25kHz to 39.0625kHz. 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after PRDIV should be in the range of FSL_FEATURE_MCG_PLL_REF_MIN to FSL_FEATURE_MCG_PLL_REF_MAX.

Definition at line 654 of file fsl_clock.h.


Field Documentation

MCG_C4[DMX32].

Definition at line 666 of file fsl_clock.h.

DCO range MCG_C4[DRST_DRS].

Definition at line 665 of file fsl_clock.h.

uint8_t fcrdiv

Divider, MCG_SC[FCRDIV].

Definition at line 661 of file fsl_clock.h.

uint8_t frdiv

Divider MCG_C1[FRDIV].

Definition at line 664 of file fsl_clock.h.

uint8_t irclkEnableMode

MCGIRCLK enable mode.

Definition at line 659 of file fsl_clock.h.

Source, MCG_C2[IRCS].

Definition at line 660 of file fsl_clock.h.

MCG mode.

Definition at line 656 of file fsl_clock.h.

OSC select MCG_C7[OSCSEL].

Definition at line 667 of file fsl_clock.h.

MCGPLL0CLK configuration.

Definition at line 670 of file fsl_clock.h.

PLL select as output, PLLCS.

Definition at line 672 of file fsl_clock.h.