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fsl_clock.h
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00001 /* 00002 * Copyright (c) 2015, Freescale Semiconductor, Inc. 00003 * All rights reserved. 00004 * 00005 * Redistribution and use in source and binary forms, with or without modification, 00006 * are permitted provided that the following conditions are met: 00007 * 00008 * o Redistributions of source code must retain the above copyright notice, this list 00009 * of conditions and the following disclaimer. 00010 * 00011 * o Redistributions in binary form must reproduce the above copyright notice, this 00012 * list of conditions and the following disclaimer in the documentation and/or 00013 * other materials provided with the distribution. 00014 * 00015 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its 00016 * contributors may be used to endorse or promote products derived from this 00017 * software without specific prior written permission. 00018 * 00019 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 00020 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 00021 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00022 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 00023 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 00024 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 00025 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 00026 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00027 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 00028 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00029 */ 00030 00031 #ifndef _FSL_CLOCK_H_ 00032 #define _FSL_CLOCK_H_ 00033 00034 #include "fsl_device_registers.h" 00035 #include "fsl_common.h" 00036 #include <stdint.h> 00037 #include <stdbool.h> 00038 #include <assert.h> 00039 00040 /*! @addtogroup clock */ 00041 /*! @{ */ 00042 00043 /*! @file */ 00044 00045 /******************************************************************************* 00046 * Definitions 00047 ******************************************************************************/ 00048 00049 /*! @name Driver version */ 00050 /*@{*/ 00051 /*! @brief CLOCK driver version 2.2.0. */ 00052 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) 00053 /*@}*/ 00054 00055 /*! @brief External XTAL0 (OSC0) clock frequency. 00056 * 00057 * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz, when the clock is setup, use the 00058 * function CLOCK_SetXtal0Freq to set the value in to clock driver. For example, 00059 * if XTAL0 is 8MHz, 00060 * @code 00061 * CLOCK_InitOsc0(...); // Setup the OSC0 00062 * CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value to clock driver. 00063 * @endcode 00064 * 00065 * This is important for the multicore platforms, only one core needs to setup 00066 * OSC0 using CLOCK_InitOsc0, all other cores need to call CLOCK_SetXtal0Freq 00067 * to get valid clock frequency. 00068 */ 00069 extern uint32_t g_xtal0Freq; 00070 00071 /*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency. 00072 * 00073 * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz, when the clock is setup, use the 00074 * function CLOCK_SetXtal32Freq to set the value in to clock driver. 00075 * 00076 * This is important for the multicore platforms, only one core needs to setup 00077 * the clock, all other cores need to call CLOCK_SetXtal32Freq 00078 * to get valid clock frequency. 00079 */ 00080 extern uint32_t g_xtal32Freq; 00081 00082 /*! @brief IRC48M clock frequency in Hz. */ 00083 #define MCG_INTERNAL_IRC_48M 48000000U 00084 00085 #if (defined(OSC) && !(defined(OSC0))) 00086 #define OSC0 OSC 00087 #endif 00088 00089 /*! @brief Clock ip name array for DMAMUX. */ 00090 #define DMAMUX_CLOCKS \ 00091 { \ 00092 kCLOCK_Dmamux0 \ 00093 } 00094 00095 /*! @brief Clock ip name array for RTC. */ 00096 #define RTC_CLOCKS \ 00097 { \ 00098 kCLOCK_Rtc0 \ 00099 } 00100 00101 /*! @brief Clock ip name array for PORT. */ 00102 #define PORT_CLOCKS \ 00103 { \ 00104 kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \ 00105 } 00106 00107 /*! @brief Clock ip name array for SAI. */ 00108 #define SAI_CLOCKS \ 00109 { \ 00110 kCLOCK_Sai0 \ 00111 } 00112 00113 /*! @brief Clock ip name array for FLEXBUS. */ 00114 #define FLEXBUS_CLOCKS \ 00115 { \ 00116 kCLOCK_Flexbus0 \ 00117 } 00118 00119 /*! @brief Clock ip name array for TSI. */ 00120 #define TSI_CLOCKS \ 00121 { \ 00122 kCLOCK_Tsi0 \ 00123 } 00124 00125 /*! @brief Clock ip name array for LPUART. */ 00126 #define LPUART_CLOCKS \ 00127 { \ 00128 kCLOCK_Lpuart0 \ 00129 } 00130 00131 /*! @brief Clock ip name array for EWM. */ 00132 #define EWM_CLOCKS \ 00133 { \ 00134 kCLOCK_Ewm0 \ 00135 } 00136 00137 /*! @brief Clock ip name array for PIT. */ 00138 #define PIT_CLOCKS \ 00139 { \ 00140 kCLOCK_Pit0 \ 00141 } 00142 00143 /*! @brief Clock ip name array for DSPI. */ 00144 #define DSPI_CLOCKS \ 00145 { \ 00146 kCLOCK_Spi0, kCLOCK_Spi1, kCLOCK_Spi2 \ 00147 } 00148 00149 /*! @brief Clock ip name array for LPTMR. */ 00150 #define LPTMR_CLOCKS \ 00151 { \ 00152 kCLOCK_Lptmr0 \ 00153 } 00154 00155 /*! @brief Clock ip name array for SDHC. */ 00156 #define SDHC_CLOCKS \ 00157 { \ 00158 kCLOCK_Sdhc0 \ 00159 } 00160 00161 /*! @brief Clock ip name array for FTM. */ 00162 #define FTM_CLOCKS \ 00163 { \ 00164 kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2, kCLOCK_Ftm3 \ 00165 } 00166 00167 /*! @brief Clock ip name array for EDMA. */ 00168 #define EDMA_CLOCKS \ 00169 { \ 00170 kCLOCK_Dma0 \ 00171 } 00172 00173 /*! @brief Clock ip name array for FLEXCAN. */ 00174 #define FLEXCAN_CLOCKS \ 00175 { \ 00176 kCLOCK_Flexcan0, kCLOCK_Flexcan1 \ 00177 } 00178 00179 /*! @brief Clock ip name array for DAC. */ 00180 #define DAC_CLOCKS \ 00181 { \ 00182 kCLOCK_Dac0, kCLOCK_Dac1 \ 00183 } 00184 00185 /*! @brief Clock ip name array for ADC16. */ 00186 #define ADC16_CLOCKS \ 00187 { \ 00188 kCLOCK_Adc0, kCLOCK_Adc1 \ 00189 } 00190 00191 /*! @brief Clock ip name array for SDRAM. */ 00192 #define SDRAM_CLOCKS \ 00193 { \ 00194 kCLOCK_Sdramc0 \ 00195 } 00196 00197 /*! @brief Clock ip name array for MPU. */ 00198 #define MPU_CLOCKS \ 00199 { \ 00200 kCLOCK_Mpu0 \ 00201 } 00202 00203 /*! @brief Clock ip name array for VREF. */ 00204 #define VREF_CLOCKS \ 00205 { \ 00206 kCLOCK_Vref0 \ 00207 } 00208 00209 /*! @brief Clock ip name array for CMT. */ 00210 #define CMT_CLOCKS \ 00211 { \ 00212 kCLOCK_Cmt0 \ 00213 } 00214 00215 /*! @brief Clock ip name array for UART. */ 00216 #define UART_CLOCKS \ 00217 { \ 00218 kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4 \ 00219 } 00220 00221 /*! @brief Clock ip name array for TPM. */ 00222 #define TPM_CLOCKS \ 00223 { \ 00224 kCLOCK_IpInvalid, kCLOCK_Tpm1, kCLOCK_Tpm2 \ 00225 } 00226 00227 /*! @brief Clock ip name array for RNGA. */ 00228 #define RNGA_CLOCKS \ 00229 { \ 00230 kCLOCK_Rnga0 \ 00231 } 00232 00233 /*! @brief Clock ip name array for CRC. */ 00234 #define CRC_CLOCKS \ 00235 { \ 00236 kCLOCK_Crc0 \ 00237 } 00238 00239 /*! @brief Clock ip name array for I2C. */ 00240 #define I2C_CLOCKS \ 00241 { \ 00242 kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3 \ 00243 } 00244 00245 /*! @brief Clock ip name array for FTF. */ 00246 #define FTF_CLOCKS \ 00247 { \ 00248 kCLOCK_Ftf0 \ 00249 } 00250 00251 /*! @brief Clock ip name array for PDB. */ 00252 #define PDB_CLOCKS \ 00253 { \ 00254 kCLOCK_Pdb0 \ 00255 } 00256 00257 /*! @brief Clock ip name array for CMP. */ 00258 #define CMP_CLOCKS \ 00259 { \ 00260 kCLOCK_Cmp0, kCLOCK_Cmp1, kCLOCK_Cmp2, kCLOCK_Cmp3 \ 00261 } 00262 00263 /*! 00264 * @brief LPO clock frequency. 00265 */ 00266 #define LPO_CLK_FREQ 1000U 00267 00268 /*! @brief Peripherals clock source definition. */ 00269 #define SYS_CLK kCLOCK_CoreSysClk 00270 #define BUS_CLK kCLOCK_BusClk 00271 00272 #define I2C0_CLK_SRC BUS_CLK 00273 #define I2C1_CLK_SRC BUS_CLK 00274 #define I2C2_CLK_SRC BUS_CLK 00275 #define I2C3_CLK_SRC BUS_CLK 00276 #define DSPI0_CLK_SRC BUS_CLK 00277 #define DSPI1_CLK_SRC BUS_CLK 00278 #define DSPI2_CLK_SRC BUS_CLK 00279 #define UART0_CLK_SRC SYS_CLK 00280 #define UART1_CLK_SRC SYS_CLK 00281 #define UART2_CLK_SRC BUS_CLK 00282 #define UART3_CLK_SRC BUS_CLK 00283 #define UART4_CLK_SRC BUS_CLK 00284 00285 /*! @brief Clock name used to get clock frequency. */ 00286 typedef enum _clock_name 00287 { 00288 00289 /* ----------------------------- System layer clock -------------------------------*/ 00290 kCLOCK_CoreSysClk , /*!< Core/system clock */ 00291 kCLOCK_PlatClk , /*!< Platform clock */ 00292 kCLOCK_BusClk , /*!< Bus clock */ 00293 kCLOCK_FlexBusClk , /*!< FlexBus clock */ 00294 kCLOCK_FlashClk , /*!< Flash clock */ 00295 kCLOCK_FastPeriphClk , /*!< Fast peripheral clock */ 00296 kCLOCK_PllFllSelClk , /*!< The clock after SIM[PLLFLLSEL]. */ 00297 00298 /* ---------------------------------- OSC clock -----------------------------------*/ 00299 kCLOCK_Er32kClk , /*!< External reference 32K clock (ERCLK32K) */ 00300 kCLOCK_Osc0ErClk , /*!< OSC0 external reference clock (OSC0ERCLK) */ 00301 kCLOCK_Osc1ErClk , /*!< OSC1 external reference clock (OSC1ERCLK) */ 00302 kCLOCK_Osc0ErClkUndiv , /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */ 00303 00304 /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/ 00305 kCLOCK_McgFixedFreqClk , /*!< MCG fixed frequency clock (MCGFFCLK) */ 00306 kCLOCK_McgInternalRefClk , /*!< MCG internal reference clock (MCGIRCLK) */ 00307 kCLOCK_McgFllClk , /*!< MCGFLLCLK */ 00308 kCLOCK_McgPll0Clk , /*!< MCGPLL0CLK */ 00309 kCLOCK_McgPll1Clk , /*!< MCGPLL1CLK */ 00310 kCLOCK_McgExtPllClk , /*!< EXT_PLLCLK */ 00311 kCLOCK_McgPeriphClk , /*!< MCG peripheral clock (MCGPCLK) */ 00312 kCLOCK_McgIrc48MClk , /*!< MCG IRC48M clock */ 00313 00314 /* --------------------------------- Other clock ----------------------------------*/ 00315 kCLOCK_LpoClk , /*!< LPO clock */ 00316 00317 } clock_name_t; 00318 00319 /*! @brief USB clock source definition. */ 00320 typedef enum _clock_usb_src 00321 { 00322 kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(1U), /*!< Use PLL0. */ 00323 kCLOCK_UsbSrcUsbPfd = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(2U), /*!< Use USBPFDCLK. */ 00324 kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(3U), /*!< Use IRC48M. */ 00325 kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U) /*!< Use USB_CLKIN. */ 00326 } clock_usb_src_t; 00327 00328 /*------------------------------------------------------------------------------ 00329 00330 clock_gate_t definition: 00331 00332 31 16 0 00333 ----------------------------------------------------------------- 00334 | SIM_SCGC register offset | control bit offset in SCGC | 00335 ----------------------------------------------------------------- 00336 00337 For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the 00338 SIM_SCGC3 offset in SIM is 0x1030, then kClockGateSdhc0 is defined as 00339 00340 kClockGateSdhc0 = (0x1030 << 16) | 17; 00341 00342 ------------------------------------------------------------------------------*/ 00343 00344 #define CLK_GATE_REG_OFFSET_SHIFT 16U 00345 #define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U 00346 #define CLK_GATE_BIT_SHIFT_SHIFT 0U 00347 #define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU 00348 00349 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ 00350 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ 00351 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) 00352 00353 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) 00354 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) 00355 00356 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ 00357 typedef enum _clock_ip_name 00358 { 00359 kCLOCK_IpInvalid = 0U, 00360 kCLOCK_I2c2 = CLK_GATE_DEFINE(0x1028U, 6U), 00361 kCLOCK_I2c3 = CLK_GATE_DEFINE(0x1028U, 7U), 00362 kCLOCK_Uart4 = CLK_GATE_DEFINE(0x1028U, 10U), 00363 00364 kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x102CU, 4U), 00365 kCLOCK_Tpm1 = CLK_GATE_DEFINE(0x102CU, 9U), 00366 kCLOCK_Tpm2 = CLK_GATE_DEFINE(0x102CU, 10U), 00367 kCLOCK_Dac0 = CLK_GATE_DEFINE(0x102CU, 12U), 00368 kCLOCK_Dac1 = CLK_GATE_DEFINE(0x102CU, 13U), 00369 00370 kCLOCK_Rnga0 = CLK_GATE_DEFINE(0x1030U, 0U), 00371 kCLOCK_Usbhs0 = CLK_GATE_DEFINE(0x1030U, 1U), 00372 kCLOCK_UsbhsPhy0 = CLK_GATE_DEFINE(0x1030U, 2U), 00373 kCLOCK_UsbhsDcd0 = CLK_GATE_DEFINE(0x1030U, 3U), 00374 kCLOCK_Flexcan1 = CLK_GATE_DEFINE(0x1030U, 4U), 00375 kCLOCK_Spi2 = CLK_GATE_DEFINE(0x1030U, 12U), 00376 kCLOCK_Sdhc0 = CLK_GATE_DEFINE(0x1030U, 17U), 00377 kCLOCK_Ftm3 = CLK_GATE_DEFINE(0x1030U, 25U), 00378 kCLOCK_Adc1 = CLK_GATE_DEFINE(0x1030U, 27U), 00379 00380 kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U), 00381 kCLOCK_Cmt0 = CLK_GATE_DEFINE(0x1034U, 2U), 00382 kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U), 00383 kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U), 00384 kCLOCK_Uart0 = CLK_GATE_DEFINE(0x1034U, 10U), 00385 kCLOCK_Uart1 = CLK_GATE_DEFINE(0x1034U, 11U), 00386 kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U), 00387 kCLOCK_Uart3 = CLK_GATE_DEFINE(0x1034U, 13U), 00388 kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U), 00389 kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U), 00390 kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U), 00391 kCLOCK_Cmp2 = CLK_GATE_DEFINE(0x1034U, 19U), 00392 kCLOCK_Cmp3 = CLK_GATE_DEFINE(0x1034U, 19U), 00393 kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U), 00394 00395 kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U), 00396 kCLOCK_Tsi0 = CLK_GATE_DEFINE(0x1038U, 5U), 00397 kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U), 00398 kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U), 00399 kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U), 00400 kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U), 00401 kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U), 00402 00403 kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U), 00404 kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U), 00405 kCLOCK_Flexcan0 = CLK_GATE_DEFINE(0x103CU, 4U), 00406 kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U), 00407 kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U), 00408 kCLOCK_Sai0 = CLK_GATE_DEFINE(0x103CU, 15U), 00409 kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U), 00410 kCLOCK_Usbdcd0 = CLK_GATE_DEFINE(0x103CU, 21U), 00411 kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U), 00412 kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U), 00413 kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U), 00414 kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U), 00415 kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x103CU, 26U), 00416 kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U), 00417 kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U), 00418 00419 kCLOCK_Flexbus0 = CLK_GATE_DEFINE(0x1040U, 0U), 00420 kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U), 00421 kCLOCK_Mpu0 = CLK_GATE_DEFINE(0x1040U, 2U), 00422 kCLOCK_Sdramc0 = CLK_GATE_DEFINE(0x1040U, 3U), 00423 } clock_ip_name_t; 00424 00425 /*!@brief SIM configuration structure for clock setting. */ 00426 typedef struct _sim_clock_config 00427 { 00428 uint8_t pllFllSel ; /*!< PLL/FLL/IRC48M selection. */ 00429 uint8_t pllFllDiv ; /*!< PLLFLLSEL clock divider divisor. */ 00430 uint8_t pllFllFrac ; /*!< PLLFLLSEL clock divider fraction. */ 00431 uint8_t er32kSrc ; /*!< ERCLK32K source selection. */ 00432 uint32_t clkdiv1 ; /*!< SIM_CLKDIV1. */ 00433 } sim_clock_config_t; 00434 00435 /*! @brief OSC work mode. */ 00436 typedef enum _osc_mode 00437 { 00438 kOSC_ModeExt = 0U, /*!< Use external clock. */ 00439 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK))) 00440 kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */ 00441 #else 00442 kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */ 00443 #endif 00444 kOSC_ModeOscHighGain = 0U 00445 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK))) 00446 | 00447 MCG_C2_EREFS_MASK 00448 #else 00449 | 00450 MCG_C2_EREFS0_MASK 00451 #endif 00452 #if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK))) 00453 | 00454 MCG_C2_HGO_MASK, /*!< Oscillator high gain. */ 00455 #else 00456 | 00457 MCG_C2_HGO0_MASK , /*!< Oscillator high gain. */ 00458 #endif 00459 } osc_mode_t; 00460 00461 /*! @brief Oscillator capacitor load setting.*/ 00462 enum _osc_cap_load 00463 { 00464 kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */ 00465 kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */ 00466 kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */ 00467 kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */ 00468 }; 00469 00470 /*! @brief OSCERCLK enable mode. */ 00471 enum _oscer_enable_mode 00472 { 00473 kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */ 00474 kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */ 00475 }; 00476 00477 /*! @brief OSC configuration for OSCERCLK. */ 00478 typedef struct _oscer_config 00479 { 00480 uint8_t enableMode ; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */ 00481 00482 uint8_t erclkDiv ; /*!< Divider for OSCERCLK.*/ 00483 } oscer_config_t; 00484 00485 /*! 00486 * @brief OSC Initialization Configuration Structure 00487 * 00488 * Defines the configuration data structure to initialize the OSC. 00489 * When porting to a new board, please set the following members 00490 * according to board setting: 00491 * 1. freq: The external frequency. 00492 * 2. workMode: The OSC module mode. 00493 */ 00494 typedef struct _osc_config 00495 { 00496 uint32_t freq ; /*!< External clock frequency. */ 00497 uint8_t capLoad ; /*!< Capacitor load setting. */ 00498 osc_mode_t workMode ; /*!< OSC work mode setting. */ 00499 oscer_config_t oscerConfig ; /*!< Configuration for OSCERCLK. */ 00500 } osc_config_t; 00501 00502 /*! @brief MCG FLL reference clock source select. */ 00503 typedef enum _mcg_fll_src 00504 { 00505 kMCG_FllSrcExternal , /*!< External reference clock is selected */ 00506 kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */ 00507 } mcg_fll_src_t; 00508 00509 /*! @brief MCG internal reference clock select */ 00510 typedef enum _mcg_irc_mode 00511 { 00512 kMCG_IrcSlow , /*!< Slow internal reference clock selected */ 00513 kMCG_IrcFast /*!< Fast internal reference clock selected */ 00514 } mcg_irc_mode_t; 00515 00516 /*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */ 00517 typedef enum _mcg_dmx32 00518 { 00519 kMCG_Dmx32Default , /*!< DCO has a default range of 25% */ 00520 kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */ 00521 } mcg_dmx32_t; 00522 00523 /*! @brief MCG DCO range select */ 00524 typedef enum _mcg_drs 00525 { 00526 kMCG_DrsLow , /*!< Low frequency range */ 00527 kMCG_DrsMid , /*!< Mid frequency range */ 00528 kMCG_DrsMidHigh , /*!< Mid-High frequency range */ 00529 kMCG_DrsHigh /*!< High frequency range */ 00530 } mcg_drs_t; 00531 00532 /*! @brief MCG PLL reference clock select */ 00533 typedef enum _mcg_pll_ref_src 00534 { 00535 kMCG_PllRefOsc0 , /*!< Selects OSC0 as PLL reference clock */ 00536 kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */ 00537 } mcg_pll_ref_src_t; 00538 00539 /*! @brief MCGOUT clock source. */ 00540 typedef enum _mcg_clkout_src 00541 { 00542 kMCG_ClkOutSrcOut , /*!< Output of the FLL is selected (reset default) */ 00543 kMCG_ClkOutSrcInternal , /*!< Internal reference clock is selected */ 00544 kMCG_ClkOutSrcExternal , /*!< External reference clock is selected */ 00545 } mcg_clkout_src_t; 00546 00547 /*! @brief MCG Automatic Trim Machine Select */ 00548 typedef enum _mcg_atm_select 00549 { 00550 kMCG_AtmSel32k , /*!< 32 kHz Internal Reference Clock selected */ 00551 kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */ 00552 } mcg_atm_select_t; 00553 00554 /*! @brief MCG OSC Clock Select */ 00555 typedef enum _mcg_oscsel 00556 { 00557 kMCG_OscselOsc , /*!< Selects System Oscillator (OSCCLK) */ 00558 kMCG_OscselRtc , /*!< Selects 32 kHz RTC Oscillator */ 00559 kMCG_OscselIrc /*!< Selects 48 MHz IRC Oscillator */ 00560 } mcg_oscsel_t; 00561 00562 /*! @brief MCG PLLCS select */ 00563 typedef enum _mcg_pll_clk_select 00564 { 00565 kMCG_PllClkSelPll0 , /*!< PLL0 output clock is selected */ 00566 kMCG_PllClkSelExtPll /* External PLL clock is selected */ 00567 } mcg_pll_clk_select_t; 00568 00569 /*! @brief MCG clock monitor mode. */ 00570 typedef enum _mcg_monitor_mode 00571 { 00572 kMCG_MonitorNone , /*!< Clock monitor is disabled. */ 00573 kMCG_MonitorInt , /*!< Trigger interrupt when clock lost. */ 00574 kMCG_MonitorReset /*!< System reset when clock lost. */ 00575 } mcg_monitor_mode_t; 00576 00577 /*! @brief MCG status. */ 00578 enum _mcg_status 00579 { 00580 kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG , 0), /*!< Can't switch to target mode. */ 00581 kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG , 1), /*!< Current mode invalid for the specific 00582 function. */ 00583 kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG , 2), /*!< Invalid bus clock for ATM. */ 00584 kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG , 3), /*!< Invalid desired frequency for ATM. */ 00585 kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG , 4), /*!< IRC is used when using ATM. */ 00586 kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG , 5), /*!< Hardware fail occurs during ATM. */ 00587 kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG , 6) /*!< Could not change clock source because 00588 it is used currently. */ 00589 }; 00590 00591 /*! @brief MCG status flags. */ 00592 enum _mcg_status_flags_t 00593 { 00594 kMCG_Osc0LostFlag = (1U << 0U), /*!< OSC0 lost. */ 00595 kMCG_Osc0InitFlag = (1U << 1U), /*!< OSC0 crystal initialized. */ 00596 kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost. */ 00597 kMCG_Pll0LostFlag = (1U << 5U), /*!< PLL0 lost. */ 00598 kMCG_Pll0LockFlag = (1U << 6U), /*!< PLL0 locked. */ 00599 kMCG_ExtPllLostFlag = (1U << 9U), /*!< External PLL lost. */ 00600 }; 00601 00602 /*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */ 00603 enum _mcg_irclk_enable_mode 00604 { 00605 kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */ 00606 kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */ 00607 }; 00608 00609 /*! @brief MCG PLL clock enable mode definition. */ 00610 enum _mcg_pll_enable_mode 00611 { 00612 kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable indepencent of 00613 MCG clock mode. Generally, PLL 00614 is disabled in FLL modes 00615 (FEI/FBI/FEE/FBE), set PLL clock 00616 enable independent will enable 00617 PLL in the FLL modes. */ 00618 kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */ 00619 }; 00620 00621 /*! @brief MCG mode definitions */ 00622 typedef enum _mcg_mode 00623 { 00624 kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */ 00625 kMCG_ModeFBI , /*!< FBI - FLL Bypassed Internal */ 00626 kMCG_ModeBLPI , /*!< BLPI - Bypassed Low Power Internal */ 00627 kMCG_ModeFEE , /*!< FEE - FLL Engaged External */ 00628 kMCG_ModeFBE , /*!< FBE - FLL Bypassed External */ 00629 kMCG_ModeBLPE , /*!< BLPE - Bypassed Low Power External */ 00630 kMCG_ModePBE , /*!< PBE - PLL Bypassed External */ 00631 kMCG_ModePEE , /*!< PEE - PLL Engaged External */ 00632 kMCG_ModeError /*!< Unknown mode */ 00633 } mcg_mode_t; 00634 00635 /*! @brief MCG PLL configuration. */ 00636 typedef struct _mcg_pll_config 00637 { 00638 uint8_t enableMode ; /*!< Enable mode. OR'ed value of @ref _mcg_pll_enable_mode. */ 00639 uint8_t prdiv ; /*!< Reference divider PRDIV. */ 00640 uint8_t vdiv ; /*!< VCO divider VDIV. */ 00641 } mcg_pll_config_t; 00642 00643 /*! @brief MCG configure structure for mode change. 00644 * 00645 * When porting to a new board, please set the following members 00646 * according to board setting: 00647 * 1. frdiv: If FLL uses the external reference clock, please set this 00648 * value to make sure external reference clock divided by frdiv is 00649 * in the range 31.25kHz to 39.0625kHz. 00650 * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after 00651 * PRDIV should be in the range of FSL_FEATURE_MCG_PLL_REF_MIN to 00652 * FSL_FEATURE_MCG_PLL_REF_MAX. 00653 */ 00654 typedef struct _mcg_config 00655 { 00656 mcg_mode_t mcgMode ; /*!< MCG mode. */ 00657 00658 /* ----------------------- MCGIRCCLK settings ------------------------ */ 00659 uint8_t irclkEnableMode ; /*!< MCGIRCLK enable mode. */ 00660 mcg_irc_mode_t ircs ; /*!< Source, MCG_C2[IRCS]. */ 00661 uint8_t fcrdiv ; /*!< Divider, MCG_SC[FCRDIV]. */ 00662 00663 /* ------------------------ MCG FLL settings ------------------------- */ 00664 uint8_t frdiv ; /*!< Divider MCG_C1[FRDIV]. */ 00665 mcg_drs_t drs ; /*!< DCO range MCG_C4[DRST_DRS]. */ 00666 mcg_dmx32_t dmx32 ; /*!< MCG_C4[DMX32]. */ 00667 mcg_oscsel_t oscsel ; /*!< OSC select MCG_C7[OSCSEL]. */ 00668 00669 /* ------------------------ MCG PLL settings ------------------------- */ 00670 mcg_pll_config_t pll0Config ; /*!< MCGPLL0CLK configuration. */ 00671 00672 mcg_pll_clk_select_t pllcs ; /*!< PLL select as output, PLLCS.*/ 00673 00674 } mcg_config_t; 00675 00676 /******************************************************************************* 00677 * API 00678 ******************************************************************************/ 00679 00680 #if defined(__cplusplus) 00681 extern "C" { 00682 #endif /* __cplusplus */ 00683 00684 /*! 00685 * @brief Enable the clock for specific IP. 00686 * 00687 * @param name Which clock to enable, see \ref clock_ip_name_t. 00688 */ 00689 static inline void CLOCK_EnableClock(clock_ip_name_t name) 00690 { 00691 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); 00692 (*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); 00693 } 00694 00695 /*! 00696 * @brief Disable the clock for specific IP. 00697 * 00698 * @param name Which clock to disable, see \ref clock_ip_name_t. 00699 */ 00700 static inline void CLOCK_DisableClock(clock_ip_name_t name) 00701 { 00702 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); 00703 (*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); 00704 } 00705 00706 /*! 00707 * @brief Set ERCLK32K source. 00708 * 00709 * @param src The value to set ERCLK32K clock source. 00710 */ 00711 static inline void CLOCK_SetEr32kClock(uint32_t src) 00712 { 00713 SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src)); 00714 } 00715 00716 /*! 00717 * @brief Set SDHC0 clock source. 00718 * 00719 * @param src The value to set SDHC0 clock source. 00720 */ 00721 static inline void CLOCK_SetSdhc0Clock(uint32_t src) 00722 { 00723 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_SDHCSRC_MASK) | SIM_SOPT2_SDHCSRC(src)); 00724 } 00725 00726 /*! 00727 * @brief Set LPUART clock source. 00728 * 00729 * @param src The value to set LPUART clock source. 00730 */ 00731 static inline void CLOCK_SetLpuartClock(uint32_t src) 00732 { 00733 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUARTSRC_MASK) | SIM_SOPT2_LPUARTSRC(src)); 00734 } 00735 00736 /*! 00737 * @brief Set TPM clock source. 00738 * 00739 * @param src The value to set TPM clock source. 00740 */ 00741 static inline void CLOCK_SetTpmClock(uint32_t src) 00742 { 00743 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TPMSRC_MASK) | SIM_SOPT2_TPMSRC(src)); 00744 } 00745 00746 /*! 00747 * @brief Set debug trace clock source. 00748 * 00749 * @param src The value to set debug trace clock source. 00750 */ 00751 static inline void CLOCK_SetTraceClock(uint32_t src, uint32_t divValue, uint32_t fracValue) 00752 { 00753 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) | SIM_SOPT2_TRACECLKSEL(src)); 00754 SIM->CLKDIV4 = SIM_CLKDIV4_TRACEDIV(divValue) | SIM_CLKDIV4_TRACEFRAC(fracValue); 00755 } 00756 00757 /*! 00758 * @brief Set PLLFLLSEL clock source. 00759 * 00760 * @param src The value to set PLLFLLSEL clock source. 00761 */ 00762 static inline void CLOCK_SetPllFllSelClock(uint32_t src, uint32_t divValue, uint32_t fracValue) 00763 { 00764 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src)); 00765 SIM->CLKDIV3 = SIM_CLKDIV3_PLLFLLDIV(divValue) | SIM_CLKDIV3_PLLFLLFRAC(fracValue); 00766 } 00767 00768 /*! 00769 * @brief Set CLKOUT source. 00770 * 00771 * @param src The value to set CLKOUT source. 00772 */ 00773 static inline void CLOCK_SetClkOutClock(uint32_t src) 00774 { 00775 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src)); 00776 } 00777 00778 /*! 00779 * @brief Set RTC_CLKOUT source. 00780 * 00781 * @param src The value to set RTC_CLKOUT source. 00782 */ 00783 static inline void CLOCK_SetRtcClkOutClock(uint32_t src) 00784 { 00785 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src)); 00786 } 00787 00788 /*! @brief Enable USB HS clock. 00789 * 00790 * @param src USB HS clock source. 00791 * @param freq The frequency specified by src. 00792 * @retval true The clock is set successfully. 00793 * @retval false The clock source is invalid to get proper USB HS clock. 00794 */ 00795 bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq); 00796 00797 /*! @brief Disable USB HS clock. 00798 * 00799 * Disable USB HS clock. 00800 */ 00801 static inline void CLOCK_DisableUsbhs0Clock (void) 00802 { 00803 SIM->SOPT2 &= ~SIM_SOPT2_USBREGEN_MASK; 00804 SIM->SCGC3 &= ~(SIM_SCGC3_USBHS_MASK | SIM_SCGC3_USBHSPHY_MASK); 00805 } 00806 00807 /*! @brief Enable USB FS clock. 00808 * 00809 * @param src USB FS clock source. 00810 * @param freq The frequency specified by src. 00811 * @retval true The clock is set successfully. 00812 * @retval false The clock source is invalid to get proper USB FS clock. 00813 */ 00814 bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq); 00815 00816 /*! @brief Disable USB FS clock. 00817 * 00818 * Disable USB FS clock. 00819 */ 00820 static inline void CLOCK_DisableUsbfs0Clock (void) 00821 { 00822 CLOCK_DisableClock(kCLOCK_Usbfs0); 00823 } 00824 00825 /*! 00826 * @brief System clock divider 00827 * 00828 * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV3], SIM_CLKDIV1[OUTDIV4]. 00829 * 00830 * @param outdiv1 Clock 1 output divider value. 00831 * 00832 * @param outdiv2 Clock 2 output divider value. 00833 * 00834 * @param outdiv3 Clock 3 output divider value. 00835 * 00836 * @param outdiv4 Clock 4 output divider value. 00837 */ 00838 static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv3, uint32_t outdiv4) 00839 { 00840 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV3(outdiv3) | 00841 SIM_CLKDIV1_OUTDIV4(outdiv4); 00842 } 00843 00844 /*! 00845 * @brief Gets the clock frequency for a specific clock name. 00846 * 00847 * This function checks the current clock configurations and then calculates 00848 * the clock frequency for a specific clock name defined in clock_name_t. 00849 * The MCG must be properly configured before using this function. 00850 * 00851 * @param clockName Clock names defined in clock_name_t 00852 * @return Clock frequency value in Hertz 00853 */ 00854 uint32_t CLOCK_GetFreq(clock_name_t clockName); 00855 00856 /*! 00857 * @brief Get the core clock or system clock frequency. 00858 * 00859 * @return Clock frequency in Hz. 00860 */ 00861 uint32_t CLOCK_GetCoreSysClkFreq(void); 00862 00863 /*! 00864 * @brief Get the platform clock frequency. 00865 * 00866 * @return Clock frequency in Hz. 00867 */ 00868 uint32_t CLOCK_GetPlatClkFreq(void); 00869 00870 /*! 00871 * @brief Get the bus clock frequency. 00872 * 00873 * @return Clock frequency in Hz. 00874 */ 00875 uint32_t CLOCK_GetBusClkFreq(void); 00876 00877 /*! 00878 * @brief Get the flexbus clock frequency. 00879 * 00880 * @return Clock frequency in Hz. 00881 */ 00882 uint32_t CLOCK_GetFlexBusClkFreq(void); 00883 00884 /*! 00885 * @brief Get the flash clock frequency. 00886 * 00887 * @return Clock frequency in Hz. 00888 */ 00889 uint32_t CLOCK_GetFlashClkFreq(void); 00890 00891 /*! 00892 * @brief Get the output clock frequency selected by SIM[PLLFLLSEL]. 00893 * 00894 * @return Clock frequency in Hz. 00895 */ 00896 uint32_t CLOCK_GetPllFllSelClkFreq(void); 00897 00898 /*! 00899 * @brief Get the external reference 32K clock frequency (ERCLK32K). 00900 * 00901 * @return Clock frequency in Hz. 00902 */ 00903 uint32_t CLOCK_GetEr32kClkFreq(void); 00904 00905 /*! 00906 * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK). 00907 * 00908 * @return Clock frequency in Hz. 00909 */ 00910 uint32_t CLOCK_GetOsc0ErClkFreq(void); 00911 00912 /*! 00913 * @brief Get the OSC0 external reference undivided clock frequency (OSC0ERCLK_UNDIV). 00914 * 00915 * @return Clock frequency in Hz. 00916 */ 00917 uint32_t CLOCK_GetOsc0ErClkUndivFreq(void); 00918 00919 /*! 00920 * @brief Set the clock configure in SIM module. 00921 * 00922 * This function sets system layer clock settings in SIM module. 00923 * 00924 * @param config Pointer to the configure structure. 00925 */ 00926 void CLOCK_SetSimConfig(sim_clock_config_t const *config); 00927 00928 /*! 00929 * @brief Set the system clock dividers in SIM to safe value. 00930 * 00931 * The system level clocks (core clock, bus clock, flexbus clock and flash clock) 00932 * must be in allowed ranges. During MCG clock mode switch, the MCG output clock 00933 * changes then the system level clocks may be out of range. This function could 00934 * be used before MCG mode change, to make sure system level clocks are in allowed 00935 * range. 00936 * 00937 * @param config Pointer to the configure structure. 00938 */ 00939 static inline void CLOCK_SetSimSafeDivs(void) 00940 { 00941 SIM->CLKDIV1 = 0x03770000U; 00942 } 00943 00944 /*! @name MCG frequency functions. */ 00945 /*@{*/ 00946 00947 /*! 00948 * @brief Get the MCG output clock(MCGOUTCLK) frequency. 00949 * 00950 * This function gets the MCG output clock frequency (Hz) based on current MCG 00951 * register value. 00952 * 00953 * @return The frequency of MCGOUTCLK. 00954 */ 00955 uint32_t CLOCK_GetOutClkFreq(void); 00956 00957 /*! 00958 * @brief Get the MCG FLL clock(MCGFLLCLK) frequency. 00959 * 00960 * This function gets the MCG FLL clock frequency (Hz) based on current MCG 00961 * register value. The FLL is only enabled in FEI/FBI/FEE/FBE mode, in other 00962 * modes, FLL is disabled in low power state. 00963 * 00964 * @return The frequency of MCGFLLCLK. 00965 */ 00966 uint32_t CLOCK_GetFllFreq(void); 00967 00968 /*! 00969 * @brief Get the MCG internal reference clock(MCGIRCLK) frequency. 00970 * 00971 * This function gets the MCG internal reference clock frequency (Hz) based 00972 * on current MCG register value. 00973 * 00974 * @return The frequency of MCGIRCLK. 00975 */ 00976 uint32_t CLOCK_GetInternalRefClkFreq(void); 00977 00978 /*! 00979 * @brief Get the MCG fixed frequency clock(MCGFFCLK) frequency. 00980 * 00981 * This function gets the MCG fixed frequency clock frequency (Hz) based 00982 * on current MCG register value. 00983 * 00984 * @return The frequency of MCGFFCLK. 00985 */ 00986 uint32_t CLOCK_GetFixedFreqClkFreq(void); 00987 00988 /*! 00989 * @brief Get the MCG PLL0 clock(MCGPLL0CLK) frequency. 00990 * 00991 * This function gets the MCG PLL0 clock frequency (Hz) based on current MCG 00992 * register value. 00993 * 00994 * @return The frequency of MCGPLL0CLK. 00995 */ 00996 uint32_t CLOCK_GetPll0Freq(void); 00997 00998 /*! 00999 * @brief Get the MCG external PLL frequency. 01000 * 01001 * This function gets the MCG external PLL frequency (Hz). 01002 * 01003 * @return The frequency of MCG external PLL. 01004 */ 01005 uint32_t CLOCK_GetExtPllFreq(void); 01006 01007 /*! 01008 * @brief Set the MCG external PLL frequency. 01009 * 01010 * This function sets the MCG external PLL frequency (Hz), the MCG external PLL 01011 * frequency is passed in to MCG driver through this function. Please call this 01012 * function after the external PLL frequency is changed, otherwise the APIs for 01013 * get frequency may returns wrong value. 01014 * 01015 * @param The frequency of MCG external PLL. 01016 */ 01017 void CLOCK_SetExtPllFreq(uint32_t freq); 01018 01019 /*@}*/ 01020 01021 /*! @name MCG clock configuration. */ 01022 /*@{*/ 01023 01024 /*! 01025 * @brief Enable or disable MCG low power. 01026 * 01027 * Enable MCG low power will disable the PLL and FLL in bypass modes. That is, 01028 * in FBE and PBE modes, enable low power will set MCG to BLPE mode, in FBI and 01029 * PBI mode, enable low power will set MCG to BLPI mode. 01030 * When disable MCG low power, the PLL or FLL will be enabled based on MCG setting. 01031 * 01032 * @param enable True to enable MCG low power, false to disable MCG low power. 01033 */ 01034 static inline void CLOCK_SetLowPowerEnable(bool enable) 01035 { 01036 if (enable) 01037 { 01038 MCG->C2 |= MCG_C2_LP_MASK; 01039 } 01040 else 01041 { 01042 MCG->C2 &= ~MCG_C2_LP_MASK; 01043 } 01044 } 01045 01046 /*! 01047 * @brief Configure the Internal Reference clock (MCGIRCLK) 01048 * 01049 * This function setups the \c MCGIRCLK base on parameters. It selects the IRC 01050 * source, if fast IRC is used, this function also sets the fast IRC divider. 01051 * This function also sets whether enable \c MCGIRCLK in stop mode. 01052 * Calling this function in FBI/PBI/BLPI modes may change the system clock, so 01053 * it is not allowed to use this in these modes. 01054 * 01055 * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode. 01056 * @param ircs MCGIRCLK clock source, choose fast or slow. 01057 * @param fcrdiv Fast IRC divider setting (\c FCRDIV). 01058 * @retval kStatus_MCG_SourceUsed MCGIRCLK is used as system clock, should not configure MCGIRCLK. 01059 * @retval kStatus_Success MCGIRCLK configuration finished successfully. 01060 */ 01061 status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv); 01062 01063 /*! 01064 * @brief Select the MCG external reference clock. 01065 * 01066 * Select the MCG external reference clock source, it changes the MCG_C7[OSCSEL] 01067 * and wait for the clock source stable. Should not change external reference 01068 * clock in FEE/FBE/BLPE/PBE/PEE mdes, so don't call this function in these modes. 01069 * 01070 * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL]. 01071 * @retval kStatus_MCG_SourceUsed External reference clock is used, should not change. 01072 * @retval kStatus_Success External reference clock set successfully. 01073 */ 01074 status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel); 01075 01076 /*! 01077 * @brief Enables the PLL0 in FLL mode. 01078 * 01079 * This function setups the PLL0 in FLL mode, make sure the PLL reference 01080 * clock is enabled before calling this function. This function reconfigures 01081 * the PLL0, make sure the PLL0 is not used as a clock source while calling 01082 * this function. The function CLOCK_CalcPllDiv can help to get the proper PLL 01083 * divider values. 01084 * 01085 * @param config Pointer to the configuration structure. 01086 */ 01087 void CLOCK_EnablePll0(mcg_pll_config_t const *config); 01088 01089 /*! 01090 * @brief Disables the PLL0 in FLL mode. 01091 * 01092 * This function disables the PLL0 in FLL mode, it should be used together with 01093 * @ref CLOCK_EnablePll0. 01094 */ 01095 static inline void CLOCK_DisablePll0(void) 01096 { 01097 MCG->C5 &= ~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK); 01098 } 01099 01100 /*! 01101 * @brief Calculates the PLL divider setting for desired output frequency. 01102 * 01103 * This function calculates the proper reference clock divider (\c PRDIV) and 01104 * VCO divider (\c VDIV) to generate desired PLL output frequency. It returns the 01105 * closest frequency PLL could generate, the corresponding \c PRDIV/VDIV are 01106 * returned from parameters. If desired frequency is not valid, this function 01107 * returns 0. 01108 * 01109 * @param refFreq PLL reference clock frequency. 01110 * @param desireFreq Desired PLL output frequency. 01111 * @param prdiv PRDIV value to generate desired PLL frequency. 01112 * @param vdiv VDIV value to generate desired PLL frequency. 01113 * @return Closest frequency PLL could generate. 01114 */ 01115 uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv); 01116 01117 /*@}*/ 01118 01119 /*! @name MCG clock lock monitor functions. */ 01120 /*@{*/ 01121 01122 /*! 01123 * @brief Set the OSC0 clock monitor mode. 01124 * 01125 * Set the OSC0 clock monitor mode, see @ref mcg_monitor_mode_t for details. 01126 * 01127 * @param mode The monitor mode to set. 01128 */ 01129 void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode); 01130 01131 /*! 01132 * @brief Set the RTC OSC clock monitor mode. 01133 * 01134 * Set the RTC OSC clock monitor mode, see @ref mcg_monitor_mode_t for details. 01135 * 01136 * @param mode The monitor mode to set. 01137 */ 01138 void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode); 01139 01140 /*! 01141 * @brief Set the PLL0 clock monitor mode. 01142 * 01143 * Set the PLL0 clock monitor mode, see @ref mcg_monitor_mode_t for details. 01144 * 01145 * @param mode The monitor mode to set. 01146 */ 01147 void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode); 01148 01149 /*! 01150 * @brief Set the external PLL clock monitor mode. 01151 * 01152 * Set the external PLL clock monitor mode, see @ref mcg_monitor_mode_t 01153 * for details. 01154 * 01155 * @param mode The monitor mode to set. 01156 */ 01157 void CLOCK_SetExtPllMonitorMode(mcg_monitor_mode_t mode); 01158 01159 /*! 01160 * @brief Get the MCG status flags. 01161 * 01162 * This function gets the MCG clock status flags, all the status flags are 01163 * returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To 01164 * check specific flags, compare the return value with the flags. 01165 * 01166 * Example: 01167 * @code 01168 // To check the clock lost lock status of OSC0 and PLL0. 01169 uint32_t mcgFlags; 01170 01171 mcgFlags = CLOCK_GetStatusFlags(); 01172 01173 if (mcgFlags & kMCG_Osc0LostFlag) 01174 { 01175 // OSC0 clock lock lost. Do something. 01176 } 01177 if (mcgFlags & kMCG_Pll0LostFlag) 01178 { 01179 // PLL0 clock lock lost. Do something. 01180 } 01181 @endcode 01182 * 01183 * @return Logical OR value of the @ref _mcg_status_flags_t. 01184 */ 01185 uint32_t CLOCK_GetStatusFlags(void); 01186 01187 /*! 01188 * @brief Clears the MCG status flags. 01189 * 01190 * This function clears the MCG clock lock lost status. The parameter is logical 01191 * OR value of the flags to clear, see @ref _mcg_status_flags_t. 01192 * 01193 * Example: 01194 * @code 01195 // To clear the clock lost lock status flags of OSC0 and PLL0. 01196 01197 CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag); 01198 @endcode 01199 * 01200 * @param mask The status flags to clear. This is a logical OR of members of the 01201 * enumeration @ref _mcg_status_flags_t. 01202 */ 01203 void CLOCK_ClearStatusFlags(uint32_t mask); 01204 01205 /*@}*/ 01206 01207 /*! 01208 * @name OSC configuration 01209 * @{ 01210 */ 01211 01212 /*! 01213 * @brief Configures the OSC external reference clock (OSCERCLK). 01214 * 01215 * This function configures the OSC external reference clock (OSCERCLK). 01216 * For example, to enable the OSCERCLK in normal mode and stop mode, and also set 01217 * the output divider to 1, as follows: 01218 * 01219 @code 01220 oscer_config_t config = 01221 { 01222 .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop, 01223 .erclkDiv = 1U, 01224 }; 01225 01226 OSC_SetExtRefClkConfig(OSC, &config); 01227 @endcode 01228 * 01229 * @param base OSC peripheral address. 01230 * @param config Pointer to the configuration structure. 01231 */ 01232 static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config) 01233 { 01234 uint8_t reg = base->CR; 01235 01236 reg &= ~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK); 01237 reg |= config->enableMode ; 01238 01239 base->CR = reg; 01240 01241 base->DIV = OSC_DIV_ERPS(config->erclkDiv ); 01242 } 01243 01244 /*! 01245 * @brief Sets the capacitor load configuration for the oscillator. 01246 * 01247 * This function sets the specified capacitors configuration for the oscillator. 01248 * This should be done in the early system level initialization function call 01249 * based on the system configuration. 01250 * 01251 * @param base OSC peripheral address. 01252 * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load. 01253 * 01254 * Example: 01255 @code 01256 // To enable only 2 pF and 8 pF capacitor load, please use like this. 01257 OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P); 01258 @endcode 01259 */ 01260 static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad) 01261 { 01262 uint8_t reg = base->CR; 01263 01264 reg &= ~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK); 01265 reg |= capLoad; 01266 01267 base->CR = reg; 01268 } 01269 01270 /*! 01271 * @brief Initialize OSC0. 01272 * 01273 * This function initializes OSC0 according to board configuration. 01274 * 01275 * @param config Pointer to the OSC0 configuration structure. 01276 */ 01277 void CLOCK_InitOsc0(osc_config_t const *config); 01278 01279 /*! 01280 * @brief Deinitialize OSC0. 01281 * 01282 * This function deinitializes OSC0. 01283 */ 01284 void CLOCK_DeinitOsc0(void); 01285 01286 /* @} */ 01287 01288 /*! 01289 * @name External clock frequency 01290 * @{ 01291 */ 01292 01293 /*! 01294 * @brief Set the XTAL0 frequency based on board setting. 01295 * 01296 * @param freq The XTAL0/EXTAL0 input clock frequency in Hz. 01297 */ 01298 static inline void CLOCK_SetXtal0Freq(uint32_t freq) 01299 { 01300 g_xtal0Freq = freq; 01301 } 01302 01303 /*! 01304 * @brief Set the XTAL32/RTC_CLKIN frequency based on board setting. 01305 * 01306 * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz. 01307 */ 01308 static inline void CLOCK_SetXtal32Freq(uint32_t freq) 01309 { 01310 g_xtal32Freq = freq; 01311 } 01312 /* @} */ 01313 01314 /*! 01315 * @name MCG auto-trim machine. 01316 * @{ 01317 */ 01318 01319 /*! 01320 * @brief Auto trim the internal reference clock. 01321 * 01322 * This function trims the internal reference clock using external clock. If 01323 * successful, it returns the kStatus_Success and the frequency after 01324 * trimming is received in the parameter @p actualFreq. If an error occurs, 01325 * the error code is returned. 01326 * 01327 * @param extFreq External clock frequency, should be bus clock. 01328 * @param desireFreq Frequency want to trim to. 01329 * @param actualFreq Actual frequency after trim. 01330 * @param atms Trim fast or slow internal reference clock. 01331 * @retval kStatus_Success ATM success. 01332 * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for ATM. 01333 * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency. 01334 * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as bus clock source. 01335 * @retval kStatus_MCG_AtmHardwareFail Hardware fails during trim. 01336 */ 01337 status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms); 01338 /* @} */ 01339 01340 /*! @name MCG mode functions. */ 01341 /*@{*/ 01342 01343 /*! 01344 * @brief Gets the current MCG mode. 01345 * 01346 * This function checks the MCG registers and determine current MCG mode. 01347 * 01348 * @return Current MCG mode or error code, see @ref mcg_mode_t. 01349 */ 01350 mcg_mode_t CLOCK_GetMode(void); 01351 01352 /*! 01353 * @brief Set MCG to FEI mode. 01354 * 01355 * This function sets MCG to FEI mode. If could not set to FEI mode directly 01356 * from current mode, this function returns error. 01357 * 01358 * @param dmx32 DMX32 in FEI mode. 01359 * @param drs The DCO range selection. 01360 * @param fllStableDelay Delay function to make sure FLL is stable, if pass 01361 * in NULL, then does not delay. 01362 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. 01363 * @retval kStatus_Success Switch to target mode successfully. 01364 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed 01365 * to frequency above 32768Hz. 01366 */ 01367 status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); 01368 01369 /*! 01370 * @brief Set MCG to FEE mode. 01371 * 01372 * This function sets MCG to FEE mode. If could not set to FEE mode directly 01373 * from current mode, this function returns error. 01374 * 01375 * @param frdiv FLL reference clock divider setting, FRDIV. 01376 * @param dmx32 DMX32 in FEE mode. 01377 * @param drs The DCO range selection. 01378 * @param fllStableDelay Delay function to make sure FLL is stable, if pass 01379 * in NULL, then does not delay. 01380 * 01381 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. 01382 * @retval kStatus_Success Switch to target mode successfully. 01383 */ 01384 status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); 01385 01386 /*! 01387 * @brief Set MCG to FBI mode. 01388 * 01389 * This function sets MCG to FBI mode. If could not set to FBI mode directly 01390 * from current mode, this function returns error. 01391 * 01392 * @param dmx32 DMX32 in FBI mode. 01393 * @param drs The DCO range selection. 01394 * @param fllStableDelay Delay function to make sure FLL is stable. If FLL 01395 * is not used in FBI mode, this parameter could be NULL. Pass in 01396 * NULL does not delay. 01397 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. 01398 * @retval kStatus_Success Switch to target mode successfully. 01399 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed 01400 * to frequency above 32768Hz. 01401 */ 01402 status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); 01403 01404 /*! 01405 * @brief Set MCG to FBE mode. 01406 * 01407 * This function sets MCG to FBE mode. If could not set to FBE mode directly 01408 * from current mode, this function returns error. 01409 * 01410 * @param frdiv FLL reference clock divider setting, FRDIV. 01411 * @param dmx32 DMX32 in FBE mode. 01412 * @param drs The DCO range selection. 01413 * @param fllStableDelay Delay function to make sure FLL is stable. If FLL 01414 * is not used in FBE mode, this parameter could be NULL. Pass in NULL 01415 * does not delay. 01416 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. 01417 * @retval kStatus_Success Switch to target mode successfully. 01418 */ 01419 status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); 01420 01421 /*! 01422 * @brief Set MCG to BLPI mode. 01423 * 01424 * This function sets MCG to BLPI mode. If could not set to BLPI mode directly 01425 * from current mode, this function returns error. 01426 * 01427 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. 01428 * @retval kStatus_Success Switch to target mode successfully. 01429 */ 01430 status_t CLOCK_SetBlpiMode(void); 01431 01432 /*! 01433 * @brief Set MCG to BLPE mode. 01434 * 01435 * This function sets MCG to BLPE mode. If could not set to BLPE mode directly 01436 * from current mode, this function returns error. 01437 * 01438 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. 01439 * @retval kStatus_Success Switch to target mode successfully. 01440 */ 01441 status_t CLOCK_SetBlpeMode(void); 01442 01443 /*! 01444 * @brief Set MCG to PBE mode. 01445 * 01446 * This function sets MCG to PBE mode. If could not set to PBE mode directly 01447 * from current mode, this function returns error. 01448 * 01449 * @param pllcs The PLL selection, PLLCS. 01450 * @param config Pointer to the PLL configuration. 01451 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. 01452 * @retval kStatus_Success Switch to target mode successfully. 01453 * 01454 * @note 01455 * 1. The parameter \c pllcs selects the PLL, for some platforms, there is 01456 * only one PLL, the parameter pllcs is kept for interface compatible. 01457 * 2. The parameter \c config is the PLL configuration structure, on some 01458 * platforms, could choose the external PLL directly. This means that the 01459 * configuration structure is not necessary, pass in NULL for this case. 01460 * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL); 01461 */ 01462 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config); 01463 01464 /*! 01465 * @brief Set MCG to PEE mode. 01466 * 01467 * This function sets MCG to PEE mode. 01468 * 01469 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. 01470 * @retval kStatus_Success Switch to target mode successfully. 01471 * 01472 * @note This function only change CLKS to use PLL/FLL output. If the 01473 * PRDIV/VDIV are different from PBE mode, please setup these 01474 * settings in PBE mode and wait for stable then switch to PEE mode. 01475 */ 01476 status_t CLOCK_SetPeeMode(void); 01477 01478 /*! 01479 * @brief Switch MCG to FBE mode quickly from external mode. 01480 * 01481 * This function changes MCG from external modes (PEE/PBE/BLPE/FEE) to FBE mode quickly. 01482 * It only changes to use external clock as the system clock souce and disable PLL, but does not 01483 * configure FLL settings. This is a lite function with small code size, it is useful 01484 * during mode switch. For example, to switch from PEE mode to FEI mode: 01485 * 01486 * @code 01487 * CLOCK_ExternalModeToFbeModeQuick(); 01488 * CLOCK_SetFeiMode(...); 01489 * @endcode 01490 * 01491 * @retval kStatus_Success Change successfully. 01492 * @retval kStatus_MCG_ModeInvalid Current mode is not external modes, should not call this function. 01493 */ 01494 status_t CLOCK_ExternalModeToFbeModeQuick(void); 01495 01496 /*! 01497 * @brief Switch MCG to FBI mode quickly from internal modes. 01498 * 01499 * This function changes MCG from internal modes (PEI/PBI/BLPI/FEI) to FBI mode quickly. 01500 * It only changes to use MCGIRCLK as the system clock souce and disable PLL, but does not 01501 * configure FLL settings. This is a lite function with small code size, it is useful 01502 * during mode switch. For example, to switch from PEI mode to FEE mode: 01503 * 01504 * @code 01505 * CLOCK_InternalModeToFbiModeQuick(); 01506 * CLOCK_SetFeeMode(...); 01507 * @endcode 01508 * 01509 * @retval kStatus_Success Change successfully. 01510 * @retval kStatus_MCG_ModeInvalid Current mode is not internal mode, should not call this function. 01511 */ 01512 status_t CLOCK_InternalModeToFbiModeQuick(void); 01513 01514 /*! 01515 * @brief Set MCG to FEI mode during system boot up. 01516 * 01517 * This function sets MCG to FEI mode from reset mode, it could be used to 01518 * set up MCG during system boot up. 01519 * 01520 * @param dmx32 DMX32 in FEI mode. 01521 * @param drs The DCO range selection. 01522 * @param fllStableDelay Delay function to make sure FLL is stable. 01523 * 01524 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. 01525 * @retval kStatus_Success Switch to target mode successfully. 01526 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed 01527 * to frequency above 32768Hz. 01528 */ 01529 status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); 01530 01531 /*! 01532 * @brief Set MCG to FEE mode during system bootup. 01533 * 01534 * This function sets MCG to FEE mode from reset mode, it could be used to 01535 * set up MCG during system boot up. 01536 * 01537 * @param oscsel OSC clock select, OSCSEL. 01538 * @param frdiv FLL reference clock divider setting, FRDIV. 01539 * @param dmx32 DMX32 in FEE mode. 01540 * @param drs The DCO range selection. 01541 * @param fllStableDelay Delay function to make sure FLL is stable. 01542 * 01543 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. 01544 * @retval kStatus_Success Switch to target mode successfully. 01545 */ 01546 status_t CLOCK_BootToFeeMode( 01547 mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); 01548 01549 /*! 01550 * @brief Set MCG to BLPI mode during system boot up. 01551 * 01552 * This function sets MCG to BLPI mode from reset mode, it could be used to 01553 * setup MCG during sytem boot up. 01554 * 01555 * @param fcrdiv Fast IRC divider, FCRDIV. 01556 * @param ircs The internal reference clock to select, IRCS. 01557 * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode. 01558 * 01559 * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting. 01560 * @retval kStatus_Success Switch to target mode successfully. 01561 */ 01562 status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode); 01563 01564 /*! 01565 * @brief Set MCG to BLPE mode during sytem boot up. 01566 * 01567 * This function sets MCG to BLPE mode from reset mode, it could be used to 01568 * setup MCG during sytem boot up. 01569 * 01570 * @param oscsel OSC clock select, MCG_C7[OSCSEL]. 01571 * 01572 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. 01573 * @retval kStatus_Success Switch to target mode successfully. 01574 */ 01575 status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel); 01576 01577 /*! 01578 * @brief Set MCG to PEE mode during system boot up. 01579 * 01580 * This function sets MCG to PEE mode from reset mode, it could be used to 01581 * setup MCG during system boot up. 01582 * 01583 * @param oscsel OSC clock select, MCG_C7[OSCSEL]. 01584 * @param pllcs The PLL selection, PLLCS. 01585 * @param config Pointer to the PLL configuration. 01586 * 01587 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. 01588 * @retval kStatus_Success Switch to target mode successfully. 01589 */ 01590 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config); 01591 01592 /*! 01593 * @brief Set MCG to some target mode. 01594 * 01595 * This function sets MCG to some target mode defined by the configure 01596 * structure, if cannot switch to target mode directly, this function will 01597 * choose the proper path. 01598 * 01599 * @param config Pointer to the target MCG mode configuration structure. 01600 * @return Return kStatus_Success if switch successfully, otherwise return error code #_mcg_status. 01601 * 01602 * @note If external clock is used in the target mode, please make sure it is 01603 * enabled, for example, if the OSC0 is used, please setup OSC0 correctly before 01604 * this funciton. 01605 */ 01606 status_t CLOCK_SetMcgConfig(mcg_config_t const *config); 01607 01608 /*@}*/ 01609 01610 #if defined(__cplusplus) 01611 } 01612 #endif /* __cplusplus */ 01613 01614 /*! @} */ 01615 01616 #endif /* _FSL_CLOCK_H_ */
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