fsl_edma.c

00001 /*
00002  * Copyright (c) 2015, Freescale Semiconductor, Inc.
00003  * Copyright 2016-2018 NXP
00004  * All rights reserved.
00005  *
00006  * SPDX-License-Identifier: BSD-3-Clause
00007  */
00008 
00009 #include "fsl_edma.h"
00010 #include "fsl_clock.h "
00011 
00012 /*******************************************************************************
00013  * Definitions
00014  ******************************************************************************/
00015 
00016 /* Component ID definition, used by tools. */
00017 #ifndef FSL_COMPONENT_ID
00018 #define FSL_COMPONENT_ID "platform.drivers.edma"
00019 #endif
00020 
00021 #define EDMA_TRANSFER_ENABLED_MASK 0x80U
00022 
00023 /*******************************************************************************
00024  * Prototypes
00025  ******************************************************************************/
00026 
00027 /*!
00028  * @brief Get instance number for EDMA.
00029  *
00030  * @param base EDMA peripheral base address.
00031  */
00032 static uint32_t EDMA_GetInstance(DMA_Type *base);
00033 
00034 /*******************************************************************************
00035  * Variables
00036  ******************************************************************************/
00037 
00038 /*! @brief Array to map EDMA instance number to base pointer. */
00039 static DMA_Type *const s_edmaBases[] = DMA_BASE_PTRS;
00040 
00041 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
00042 /*! @brief Array to map EDMA instance number to clock name. */
00043 static const clock_ip_name_t s_edmaClockName[] = EDMA_CLOCKS;
00044 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
00045 
00046 /*! @brief Array to map EDMA instance number to IRQ number. */
00047 static const IRQn_Type s_edmaIRQNumber[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = DMA_CHN_IRQS;
00048 
00049 /*! @brief Pointers to transfer handle for each EDMA channel. */
00050 static edma_handle_t *s_EDMAHandle[FSL_FEATURE_EDMA_MODULE_CHANNEL * FSL_FEATURE_SOC_EDMA_COUNT];
00051 
00052 /*******************************************************************************
00053  * Code
00054  ******************************************************************************/
00055 
00056 static uint32_t EDMA_GetInstance(DMA_Type *base)
00057 {
00058     uint32_t instance;
00059 
00060     /* Find the instance index from base address mappings. */
00061     for (instance = 0; instance < ARRAY_SIZE(s_edmaBases); instance++)
00062     {
00063         if (s_edmaBases[instance] == base)
00064         {
00065             break;
00066         }
00067     }
00068 
00069     assert(instance < ARRAY_SIZE(s_edmaBases));
00070 
00071     return instance;
00072 }
00073 
00074 /*!
00075  * brief Push content of TCD structure into hardware TCD register.
00076  *
00077  * param base EDMA peripheral base address.
00078  * param channel EDMA channel number.
00079  * param tcd Point to TCD structure.
00080  */
00081 void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd)
00082 {
00083     assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
00084     assert(tcd != NULL);
00085     assert(((uint32_t)tcd & 0x1FU) == 0);
00086 
00087     /* Push tcd into hardware TCD register */
00088     base->TCD[channel].SADDR = tcd->SADDR ;
00089     base->TCD[channel].SOFF = tcd->SOFF ;
00090     base->TCD[channel].ATTR = tcd->ATTR ;
00091     base->TCD[channel].NBYTES_MLNO = tcd->NBYTES ;
00092     base->TCD[channel].SLAST = tcd->SLAST ;
00093     base->TCD[channel].DADDR = tcd->DADDR ;
00094     base->TCD[channel].DOFF = tcd->DOFF ;
00095     base->TCD[channel].CITER_ELINKNO = tcd->CITER ;
00096     base->TCD[channel].DLAST_SGA = tcd->DLAST_SGA ;
00097     /* Clear DONE bit first, otherwise ESG cannot be set */
00098     base->TCD[channel].CSR = 0;
00099     base->TCD[channel].CSR = tcd->CSR ;
00100     base->TCD[channel].BITER_ELINKNO = tcd->BITER ;
00101 }
00102 
00103 /*!
00104  * brief Initializes the eDMA peripheral.
00105  *
00106  * This function ungates the eDMA clock and configures the eDMA peripheral according
00107  * to the configuration structure.
00108  *
00109  * param base eDMA peripheral base address.
00110  * param config A pointer to the configuration structure, see "edma_config_t".
00111  * note This function enables the minor loop map feature.
00112  */
00113 void EDMA_Init(DMA_Type *base, const edma_config_t *config)
00114 {
00115     assert(config != NULL);
00116 
00117     uint32_t tmpreg;
00118 
00119 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
00120     /* Ungate EDMA peripheral clock */
00121     CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]);
00122 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
00123 
00124     /* clear all the enabled request, status to make sure EDMA status is in normal condition */
00125     base->ERQ = 0U;
00126     base->INT = 0xFFFFFFFFU;
00127     base->ERR = 0xFFFFFFFFU;
00128     /* Configure EDMA peripheral according to the configuration structure. */
00129     tmpreg = base->CR;
00130     tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK);
00131     tmpreg |= (DMA_CR_ERCA(config->enableRoundRobinArbitration ) | DMA_CR_HOE(config->enableHaltOnError ) |
00132                DMA_CR_CLM(config->enableContinuousLinkMode ) | DMA_CR_EDBG(config->enableDebugMode ) | DMA_CR_EMLM(true));
00133     base->CR = tmpreg;
00134 }
00135 
00136 /*!
00137  * brief Deinitializes the eDMA peripheral.
00138  *
00139  * This function gates the eDMA clock.
00140  *
00141  * param base eDMA peripheral base address.
00142  */
00143 void EDMA_Deinit(DMA_Type *base)
00144 {
00145 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
00146     /* Gate EDMA peripheral clock */
00147     CLOCK_DisableClock(s_edmaClockName[EDMA_GetInstance(base)]);
00148 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
00149 }
00150 
00151 /*!
00152  * brief Gets the eDMA default configuration structure.
00153  *
00154  * This function sets the configuration structure to default values.
00155  * The default configuration is set to the following values.
00156  * code
00157  *   config.enableContinuousLinkMode = false;
00158  *   config.enableHaltOnError = true;
00159  *   config.enableRoundRobinArbitration = false;
00160  *   config.enableDebugMode = false;
00161  * endcode
00162  *
00163  * param config A pointer to the eDMA configuration structure.
00164  */
00165 void EDMA_GetDefaultConfig(edma_config_t *config)
00166 {
00167     assert(config != NULL);
00168 
00169     /* Initializes the configure structure to zero. */
00170     memset(config, 0, sizeof(*config));
00171 
00172     config->enableRoundRobinArbitration  = false;
00173     config->enableHaltOnError  = true;
00174     config->enableContinuousLinkMode  = false;
00175     config->enableDebugMode  = false;
00176 }
00177 
00178 /*!
00179  * brief Sets all TCD registers to default values.
00180  *
00181  * This function sets TCD registers for this channel to default values.
00182  *
00183  * param base eDMA peripheral base address.
00184  * param channel eDMA channel number.
00185  * note This function must not be called while the channel transfer is ongoing
00186  *       or it causes unpredictable results.
00187  * note This function enables the auto stop request feature.
00188  */
00189 void EDMA_ResetChannel(DMA_Type *base, uint32_t channel)
00190 {
00191     assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
00192 
00193     EDMA_TcdReset((edma_tcd_t *)&base->TCD[channel]);
00194 }
00195 
00196 /*!
00197  * brief Configures the eDMA transfer attribute.
00198  *
00199  * This function configures the transfer attribute, including source address, destination address,
00200  * transfer size, address offset, and so on. It also configures the scatter gather feature if the
00201  * user supplies the TCD address.
00202  * Example:
00203  * code
00204  *  edma_transfer_t config;
00205  *  edma_tcd_t tcd;
00206  *  config.srcAddr = ..;
00207  *  config.destAddr = ..;
00208  *  ...
00209  *  EDMA_SetTransferConfig(DMA0, channel, &config, &stcd);
00210  * endcode
00211  *
00212  * param base eDMA peripheral base address.
00213  * param channel eDMA channel number.
00214  * param config Pointer to eDMA transfer configuration structure.
00215  * param nextTcd Point to TCD structure. It can be NULL if users
00216  *                do not want to enable scatter/gather feature.
00217  * note If nextTcd is not NULL, it means scatter gather feature is enabled
00218  *       and DREQ bit is cleared in the previous transfer configuration, which
00219  *       is set in the eDMA_ResetChannel.
00220  */
00221 void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)
00222 {
00223     assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
00224     assert(config != NULL);
00225     assert(((uint32_t)nextTcd & 0x1FU) == 0);
00226 
00227     EDMA_TcdSetTransferConfig((edma_tcd_t *)&base->TCD[channel], config, nextTcd);
00228 }
00229 
00230 /*!
00231  * brief Configures the eDMA minor offset feature.
00232  *
00233  * The minor offset means that the signed-extended value is added to the source address or destination
00234  * address after each minor loop.
00235  *
00236  * param base eDMA peripheral base address.
00237  * param channel eDMA channel number.
00238  * param config A pointer to the minor offset configuration structure.
00239  */
00240 void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config)
00241 {
00242     assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
00243     assert(config != NULL);
00244 
00245     uint32_t tmpreg;
00246 
00247     tmpreg = base->TCD[channel].NBYTES_MLOFFYES;
00248     tmpreg &= ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK);
00249     tmpreg |=
00250         (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset ) |
00251          DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset ) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset ));
00252     base->TCD[channel].NBYTES_MLOFFYES = tmpreg;
00253 }
00254 
00255 /*!
00256  * brief Sets the channel link for the eDMA transfer.
00257  *
00258  * This function configures either the minor link or the major link mode. The minor link means that the channel link is
00259  * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is
00260  * exhausted.
00261  *
00262  * param base eDMA peripheral base address.
00263  * param channel eDMA channel number.
00264  * param type A channel link type, which can be one of the following:
00265  *   arg kEDMA_LinkNone
00266  *   arg kEDMA_MinorLink
00267  *   arg kEDMA_MajorLink
00268  * param linkedChannel The linked channel number.
00269  * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
00270  */
00271 void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel)
00272 {
00273     assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
00274     assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
00275 
00276     EDMA_TcdSetChannelLink((edma_tcd_t *)&base->TCD[channel], type, linkedChannel);
00277 }
00278 
00279 /*!
00280  * brief Sets the bandwidth for the eDMA transfer.
00281  *
00282  * Because the eDMA processes the minor loop, it continuously generates read/write sequences
00283  * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of
00284  * each read/write access to control the bus request bandwidth seen by the crossbar switch.
00285  *
00286  * param base eDMA peripheral base address.
00287  * param channel eDMA channel number.
00288  * param bandWidth A bandwidth setting, which can be one of the following:
00289  *     arg kEDMABandwidthStallNone
00290  *     arg kEDMABandwidthStall4Cycle
00291  *     arg kEDMABandwidthStall8Cycle
00292  */
00293 void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth)
00294 {
00295     assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
00296 
00297     base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth);
00298 }
00299 
00300 /*!
00301  * brief Sets the source modulo and the destination modulo for the eDMA transfer.
00302  *
00303  * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
00304  * calculation is performed or the original register value. It provides the ability to implement a circular data
00305  * queue easily.
00306  *
00307  * param base eDMA peripheral base address.
00308  * param channel eDMA channel number.
00309  * param srcModulo A source modulo value.
00310  * param destModulo A destination modulo value.
00311  */
00312 void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo)
00313 {
00314     assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
00315 
00316     uint32_t tmpreg;
00317 
00318     tmpreg = base->TCD[channel].ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK));
00319     base->TCD[channel].ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo);
00320 }
00321 
00322 /*!
00323  * brief Enables the interrupt source for the eDMA transfer.
00324  *
00325  * param base eDMA peripheral base address.
00326  * param channel eDMA channel number.
00327  * param mask The mask of interrupt source to be set. Users need to use
00328  *             the defined edma_interrupt_enable_t type.
00329  */
00330 void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask)
00331 {
00332     assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
00333 
00334     /* Enable error interrupt */
00335     if (mask & kEDMA_ErrorInterruptEnable )
00336     {
00337         base->EEI |= (0x1U << channel);
00338     }
00339 
00340     /* Enable Major interrupt */
00341     if (mask & kEDMA_MajorInterruptEnable )
00342     {
00343         base->TCD[channel].CSR |= DMA_CSR_INTMAJOR_MASK;
00344     }
00345 
00346     /* Enable Half major interrupt */
00347     if (mask & kEDMA_HalfInterruptEnable )
00348     {
00349         base->TCD[channel].CSR |= DMA_CSR_INTHALF_MASK;
00350     }
00351 }
00352 
00353 /*!
00354  * brief Disables the interrupt source for the eDMA transfer.
00355  *
00356  * param base eDMA peripheral base address.
00357  * param channel eDMA channel number.
00358  * param mask The mask of the interrupt source to be set. Use
00359  *             the defined edma_interrupt_enable_t type.
00360  */
00361 void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask)
00362 {
00363     assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
00364 
00365     /* Disable error interrupt */
00366     if (mask & kEDMA_ErrorInterruptEnable )
00367     {
00368         base->EEI &= ~(0x1U << channel);
00369     }
00370 
00371     /* Disable Major interrupt */
00372     if (mask & kEDMA_MajorInterruptEnable )
00373     {
00374         base->TCD[channel].CSR &= ~DMA_CSR_INTMAJOR_MASK;
00375     }
00376 
00377     /* Disable Half major interrupt */
00378     if (mask & kEDMA_HalfInterruptEnable )
00379     {
00380         base->TCD[channel].CSR &= ~DMA_CSR_INTHALF_MASK;
00381     }
00382 }
00383 
00384 /*!
00385  * brief Sets all fields to default values for the TCD structure.
00386  *
00387  * This function sets all fields for this TCD structure to default value.
00388  *
00389  * param tcd Pointer to the TCD structure.
00390  * note This function enables the auto stop request feature.
00391  */
00392 void EDMA_TcdReset(edma_tcd_t *tcd)
00393 {
00394     assert(tcd != NULL);
00395     assert(((uint32_t)tcd & 0x1FU) == 0);
00396 
00397     /* Reset channel TCD */
00398     tcd->SADDR  = 0U;
00399     tcd->SOFF  = 0U;
00400     tcd->ATTR  = 0U;
00401     tcd->NBYTES  = 0U;
00402     tcd->SLAST  = 0U;
00403     tcd->DADDR  = 0U;
00404     tcd->DOFF  = 0U;
00405     tcd->CITER  = 0U;
00406     tcd->DLAST_SGA  = 0U;
00407     /* Enable auto disable request feature */
00408     tcd->CSR  = DMA_CSR_DREQ(true);
00409     tcd->BITER  = 0U;
00410 }
00411 
00412 /*!
00413  * brief Configures the eDMA TCD transfer attribute.
00414  *
00415  * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers.
00416  * The STCD is used in the scatter-gather mode.
00417  * This function configures the TCD transfer attribute, including source address, destination address,
00418  * transfer size, address offset, and so on. It also configures the scatter gather feature if the
00419  * user supplies the next TCD address.
00420  * Example:
00421  * code
00422  *   edma_transfer_t config = {
00423  *   ...
00424  *   }
00425  *   edma_tcd_t tcd __aligned(32);
00426  *   edma_tcd_t nextTcd __aligned(32);
00427  *   EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);
00428  * endcode
00429  *
00430  * param tcd Pointer to the TCD structure.
00431  * param config Pointer to eDMA transfer configuration structure.
00432  * param nextTcd Pointer to the next TCD structure. It can be NULL if users
00433  *                do not want to enable scatter/gather feature.
00434  * note TCD address should be 32 bytes aligned or it causes an eDMA error.
00435  * note If the nextTcd is not NULL, the scatter gather feature is enabled
00436  *       and DREQ bit is cleared in the previous transfer configuration, which
00437  *       is set in the EDMA_TcdReset.
00438  */
00439 void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)
00440 {
00441     assert(tcd != NULL);
00442     assert(((uint32_t)tcd & 0x1FU) == 0);
00443     assert(config != NULL);
00444     assert(((uint32_t)nextTcd & 0x1FU) == 0);
00445 
00446     /* source address */
00447     tcd->SADDR  = config->srcAddr ;
00448     /* destination address */
00449     tcd->DADDR  = config->destAddr ;
00450     /* Source data and destination data transfer size */
00451     tcd->ATTR  = DMA_ATTR_SSIZE(config->srcTransferSize ) | DMA_ATTR_DSIZE(config->destTransferSize );
00452     /* Source address signed offset */
00453     tcd->SOFF  = config->srcOffset ;
00454     /* Destination address signed offset */
00455     tcd->DOFF  = config->destOffset ;
00456     /* Minor byte transfer count */
00457     tcd->NBYTES  = config->minorLoopBytes ;
00458     /* Current major iteration count */
00459     tcd->CITER  = config->majorLoopCounts ;
00460     /* Starting major iteration count */
00461     tcd->BITER  = config->majorLoopCounts ;
00462     /* Enable scatter/gather processing */
00463     if (nextTcd != NULL)
00464     {
00465         tcd->DLAST_SGA  = (uint32_t)nextTcd;
00466         /*
00467             Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig,
00468             user must call EDMA_TcdReset or EDMA_ResetChannel which will set
00469             DREQ, so must use "|" or "&" rather than "=".
00470 
00471             Clear the DREQ bit because scatter gather has been enabled, so the
00472             previous transfer is not the last transfer, and channel request should
00473             be enabled at the next transfer(the next TCD).
00474         */
00475         tcd->CSR  = (tcd->CSR  | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK;
00476     }
00477 }
00478 
00479 /*!
00480  * brief Configures the eDMA TCD minor offset feature.
00481  *
00482  * A minor offset is a signed-extended value added to the source address or a destination
00483  * address after each minor loop.
00484  *
00485  * param tcd A point to the TCD structure.
00486  * param config A pointer to the minor offset configuration structure.
00487  */
00488 void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config)
00489 {
00490     assert(tcd != NULL);
00491     assert(((uint32_t)tcd & 0x1FU) == 0);
00492 
00493     uint32_t tmpreg;
00494 
00495     tmpreg = tcd->NBYTES  &
00496              ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK);
00497     tmpreg |=
00498         (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset ) |
00499          DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset ) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset ));
00500     tcd->NBYTES  = tmpreg;
00501 }
00502 
00503 /*!
00504  * brief Sets the channel link for the eDMA TCD.
00505  *
00506  * This function configures either a minor link or a major link. The minor link means the channel link is
00507  * triggered every time CITER decreases by 1. The major link means that the channel link  is triggered when the CITER is
00508  * exhausted.
00509  *
00510  * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
00511  * param tcd Point to the TCD structure.
00512  * param type Channel link type, it can be one of:
00513  *   arg kEDMA_LinkNone
00514  *   arg kEDMA_MinorLink
00515  *   arg kEDMA_MajorLink
00516  * param linkedChannel The linked channel number.
00517  */
00518 void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)
00519 {
00520     assert(tcd != NULL);
00521     assert(((uint32_t)tcd & 0x1FU) == 0);
00522     assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
00523 
00524     if (type == kEDMA_MinorLink ) /* Minor link config */
00525     {
00526         uint32_t tmpreg;
00527 
00528         /* Enable minor link */
00529         tcd->CITER  |= DMA_CITER_ELINKYES_ELINK_MASK;
00530         tcd->BITER  |= DMA_BITER_ELINKYES_ELINK_MASK;
00531         /* Set linked channel */
00532         tmpreg = tcd->CITER  & (~DMA_CITER_ELINKYES_LINKCH_MASK);
00533         tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel);
00534         tcd->CITER  = tmpreg;
00535         tmpreg = tcd->BITER  & (~DMA_BITER_ELINKYES_LINKCH_MASK);
00536         tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel);
00537         tcd->BITER  = tmpreg;
00538     }
00539     else if (type == kEDMA_MajorLink ) /* Major link config */
00540     {
00541         uint32_t tmpreg;
00542 
00543         /* Enable major link */
00544         tcd->CSR  |= DMA_CSR_MAJORELINK_MASK;
00545         /* Set major linked channel */
00546         tmpreg = tcd->CSR  & (~DMA_CSR_MAJORLINKCH_MASK);
00547         tcd->CSR  = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel);
00548     }
00549     else /* Link none */
00550     {
00551         tcd->CITER  &= ~DMA_CITER_ELINKYES_ELINK_MASK;
00552         tcd->BITER  &= ~DMA_BITER_ELINKYES_ELINK_MASK;
00553         tcd->CSR  &= ~DMA_CSR_MAJORELINK_MASK;
00554     }
00555 }
00556 
00557 /*!
00558  * brief Sets the source modulo and the destination modulo for the eDMA TCD.
00559  *
00560  * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
00561  * calculation is performed or the original register value. It provides the ability to implement a circular data
00562  * queue easily.
00563  *
00564  * param tcd A pointer to the TCD structure.
00565  * param srcModulo A source modulo value.
00566  * param destModulo A destination modulo value.
00567  */
00568 void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)
00569 {
00570     assert(tcd != NULL);
00571     assert(((uint32_t)tcd & 0x1FU) == 0);
00572 
00573     uint32_t tmpreg;
00574 
00575     tmpreg = tcd->ATTR  & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK));
00576     tcd->ATTR  = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo);
00577 }
00578 
00579 /*!
00580  * brief Enables the interrupt source for the eDMA TCD.
00581  *
00582  * param tcd Point to the TCD structure.
00583  * param mask The mask of interrupt source to be set. Users need to use
00584  *             the defined edma_interrupt_enable_t type.
00585  */
00586 void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask)
00587 {
00588     assert(tcd != NULL);
00589 
00590     /* Enable Major interrupt */
00591     if (mask & kEDMA_MajorInterruptEnable )
00592     {
00593         tcd->CSR  |= DMA_CSR_INTMAJOR_MASK;
00594     }
00595 
00596     /* Enable Half major interrupt */
00597     if (mask & kEDMA_HalfInterruptEnable )
00598     {
00599         tcd->CSR  |= DMA_CSR_INTHALF_MASK;
00600     }
00601 }
00602 
00603 /*!
00604  * brief Disables the interrupt source for the eDMA TCD.
00605  *
00606  * param tcd Point to the TCD structure.
00607  * param mask The mask of interrupt source to be set. Users need to use
00608  *             the defined edma_interrupt_enable_t type.
00609  */
00610 void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask)
00611 {
00612     assert(tcd != NULL);
00613 
00614     /* Disable Major interrupt */
00615     if (mask & kEDMA_MajorInterruptEnable )
00616     {
00617         tcd->CSR  &= ~DMA_CSR_INTMAJOR_MASK;
00618     }
00619 
00620     /* Disable Half major interrupt */
00621     if (mask & kEDMA_HalfInterruptEnable )
00622     {
00623         tcd->CSR  &= ~DMA_CSR_INTHALF_MASK;
00624     }
00625 }
00626 
00627 /*!
00628  * brief Gets the remaining major loop count from the eDMA current channel TCD.
00629  *
00630  * This function checks the TCD (Task Control Descriptor) status for a specified
00631  * eDMA channel and returns the number of major loop count that has not finished.
00632  *
00633  * param base eDMA peripheral base address.
00634  * param channel eDMA channel number.
00635  * return Major loop count which has not been transferred yet for the current TCD.
00636  * note 1. This function can only be used to get unfinished major loop count of transfer without
00637  *          the next TCD, or it might be inaccuracy.
00638  *       2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while
00639  *          the channel is running.
00640  *          Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO
00641  *          register is needed while the eDMA IP does not support getting it while a channel is active.
00642  *          In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine
00643  *          is working with while a channel is running.
00644  *          Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example
00645  *          copied before enabling the channel) is needed. The formula to calculate it is shown below:
00646  *          RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured)
00647  */
00648 uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel)
00649 {
00650     assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
00651 
00652     uint32_t remainingCount = 0;
00653 
00654     if (DMA_CSR_DONE_MASK & base->TCD[channel].CSR)
00655     {
00656         remainingCount = 0;
00657     }
00658     else
00659     {
00660         /* Calculate the unfinished bytes */
00661         if (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_ELINK_MASK)
00662         {
00663             remainingCount =
00664                 (base->TCD[channel].CITER_ELINKYES & DMA_CITER_ELINKYES_CITER_MASK) >> DMA_CITER_ELINKYES_CITER_SHIFT;
00665         }
00666         else
00667         {
00668             remainingCount =
00669                 (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT;
00670         }
00671     }
00672 
00673     return remainingCount;
00674 }
00675 
00676 /*!
00677  * brief Gets the eDMA channel status flags.
00678  *
00679  * param base eDMA peripheral base address.
00680  * param channel eDMA channel number.
00681  * return The mask of channel status flags. Users need to use the
00682  *         _edma_channel_status_flags type to decode the return variables.
00683  */
00684 uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel)
00685 {
00686     assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
00687 
00688     uint32_t retval = 0;
00689 
00690     /* Get DONE bit flag */
00691     retval |= ((base->TCD[channel].CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT);
00692     /* Get ERROR bit flag */
00693     retval |= (((base->ERR >> channel) & 0x1U) << 1U);
00694     /* Get INT bit flag */
00695     retval |= (((base->INT >> channel) & 0x1U) << 2U);
00696 
00697     return retval;
00698 }
00699 
00700 /*!
00701  * brief Clears the eDMA channel status flags.
00702  *
00703  * param base eDMA peripheral base address.
00704  * param channel eDMA channel number.
00705  * param mask The mask of channel status to be cleared. Users need to use
00706  *             the defined _edma_channel_status_flags type.
00707  */
00708 void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask)
00709 {
00710     assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
00711 
00712     /* Clear DONE bit flag */
00713     if (mask & kEDMA_DoneFlag )
00714     {
00715         base->CDNE = channel;
00716     }
00717     /* Clear ERROR bit flag */
00718     if (mask & kEDMA_ErrorFlag )
00719     {
00720         base->CERR = channel;
00721     }
00722     /* Clear INT bit flag */
00723     if (mask & kEDMA_InterruptFlag )
00724     {
00725         base->CINT = channel;
00726     }
00727 }
00728 
00729 static uint8_t Get_StartInstance(void)
00730 {
00731     static uint8_t StartInstanceNum;
00732 
00733 #if defined(DMA0)
00734     StartInstanceNum = EDMA_GetInstance(DMA0);
00735 #elif defined(DMA1)
00736     StartInstanceNum = EDMA_GetInstance(DMA1);
00737 #elif defined(DMA2)
00738     StartInstanceNum = EDMA_GetInstance(DMA2);
00739 #elif defined(DMA3)
00740     StartInstanceNum = EDMA_GetInstance(DMA3);
00741 #endif
00742 
00743     return StartInstanceNum;
00744 }
00745 
00746 /*!
00747  * brief Creates the eDMA handle.
00748  *
00749  * This function is called if using the transactional API for eDMA. This function
00750  * initializes the internal state of the eDMA handle.
00751  *
00752  * param handle eDMA handle pointer. The eDMA handle stores callback function and
00753  *               parameters.
00754  * param base eDMA peripheral base address.
00755  * param channel eDMA channel number.
00756  */
00757 void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel)
00758 {
00759     assert(handle != NULL);
00760     assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
00761 
00762     uint32_t edmaInstance;
00763     uint32_t channelIndex;
00764     uint8_t StartInstance;
00765     edma_tcd_t *tcdRegs;
00766 
00767     /* Zero the handle */
00768     memset(handle, 0, sizeof(*handle));
00769 
00770     handle->base  = base;
00771     handle->channel  = channel;
00772     /* Get the DMA instance number */
00773     edmaInstance = EDMA_GetInstance(base);
00774     StartInstance = Get_StartInstance();
00775     channelIndex = ((edmaInstance - StartInstance) * FSL_FEATURE_EDMA_MODULE_CHANNEL) + channel;
00776     s_EDMAHandle[channelIndex] = handle;
00777 
00778     /* Enable NVIC interrupt */
00779     EnableIRQ(s_edmaIRQNumber[edmaInstance][channel]);
00780 
00781     /*
00782        Reset TCD registers to zero. Unlike the EDMA_TcdReset(DREQ will be set),
00783        CSR will be 0. Because in order to suit EDMA busy check mechanism in
00784        EDMA_SubmitTransfer, CSR must be set 0.
00785     */
00786     tcdRegs = (edma_tcd_t *)&handle->base ->TCD[handle->channel ];
00787     tcdRegs->SADDR  = 0;
00788     tcdRegs->SOFF  = 0;
00789     tcdRegs->ATTR  = 0;
00790     tcdRegs->NBYTES  = 0;
00791     tcdRegs->SLAST  = 0;
00792     tcdRegs->DADDR  = 0;
00793     tcdRegs->DOFF  = 0;
00794     tcdRegs->CITER  = 0;
00795     tcdRegs->DLAST_SGA  = 0;
00796     tcdRegs->CSR  = 0;
00797     tcdRegs->BITER  = 0;
00798 }
00799 
00800 /*!
00801  * brief Installs the TCDs memory pool into the eDMA handle.
00802  *
00803  * This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used
00804  * while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block
00805  * (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer.
00806  * Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer.
00807  *
00808  * param handle eDMA handle pointer.
00809  * param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned.
00810  * param tcdSize The number of TCD slots.
00811  */
00812 void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize)
00813 {
00814     assert(handle != NULL);
00815     assert(((uint32_t)tcdPool & 0x1FU) == 0);
00816 
00817     /* Initialize tcd queue attribute. */
00818     handle->header  = 0;
00819     handle->tail  = 0;
00820     handle->tcdUsed  = 0;
00821     handle->tcdSize  = tcdSize;
00822     handle->flags  = 0;
00823     handle->tcdPool  = tcdPool;
00824 }
00825 
00826 /*!
00827  * brief Installs a callback function for the eDMA transfer.
00828  *
00829  * This callback is called in the eDMA IRQ handler. Use the callback to do something after
00830  * the current major loop transfer completes. This function will be called every time one tcd finished transfer.
00831  *
00832  * param handle eDMA handle pointer.
00833  * param callback eDMA callback function pointer.
00834  * param userData A parameter for the callback function.
00835  */
00836 void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData)
00837 {
00838     assert(handle != NULL);
00839 
00840     handle->callback  = callback;
00841     handle->userData  = userData;
00842 }
00843 
00844 /*!
00845  * brief Prepares the eDMA transfer structure.
00846  *
00847  * This function prepares the transfer configuration structure according to the user input.
00848  *
00849  * param config The user configuration structure of type edma_transfer_t.
00850  * param srcAddr eDMA transfer source address.
00851  * param srcWidth eDMA transfer source address width(bytes).
00852  * param destAddr eDMA transfer destination address.
00853  * param destWidth eDMA transfer destination address width(bytes).
00854  * param bytesEachRequest eDMA transfer bytes per channel request.
00855  * param transferBytes eDMA transfer bytes to be transferred.
00856  * param type eDMA transfer type.
00857  * note The data address and the data width must be consistent. For example, if the SRC
00858  *       is 4 bytes, the source address must be 4 bytes aligned, or it results in
00859  *       source address error (SAE).
00860  */
00861 void EDMA_PrepareTransfer(edma_transfer_config_t *config,
00862                           void *srcAddr,
00863                           uint32_t srcWidth,
00864                           void *destAddr,
00865                           uint32_t destWidth,
00866                           uint32_t bytesEachRequest,
00867                           uint32_t transferBytes,
00868                           edma_transfer_type_t type)
00869 {
00870     assert(config != NULL);
00871     assert(srcAddr != NULL);
00872     assert(destAddr != NULL);
00873     assert((srcWidth == 1U) || (srcWidth == 2U) || (srcWidth == 4U) || (srcWidth == 16U) || (srcWidth == 32U));
00874     assert((destWidth == 1U) || (destWidth == 2U) || (destWidth == 4U) || (destWidth == 16U) || (destWidth == 32U));
00875     assert(transferBytes % bytesEachRequest == 0);
00876 
00877     /* Initializes the configure structure to zero. */
00878     memset(config, 0, sizeof(*config));
00879 
00880     config->destAddr  = (uint32_t)destAddr;
00881     config->srcAddr  = (uint32_t)srcAddr;
00882     config->minorLoopBytes  = bytesEachRequest;
00883     config->majorLoopCounts  = transferBytes / bytesEachRequest;
00884     switch (srcWidth)
00885     {
00886         case 1U:
00887             config->srcTransferSize  = kEDMA_TransferSize1Bytes ;
00888             break;
00889         case 2U:
00890             config->srcTransferSize  = kEDMA_TransferSize2Bytes ;
00891             break;
00892         case 4U:
00893             config->srcTransferSize  = kEDMA_TransferSize4Bytes ;
00894             break;
00895         case 16U:
00896             config->srcTransferSize  = kEDMA_TransferSize16Bytes ;
00897             break;
00898         case 32U:
00899             config->srcTransferSize  = kEDMA_TransferSize32Bytes ;
00900             break;
00901         default:
00902             break;
00903     }
00904     switch (destWidth)
00905     {
00906         case 1U:
00907             config->destTransferSize  = kEDMA_TransferSize1Bytes ;
00908             break;
00909         case 2U:
00910             config->destTransferSize  = kEDMA_TransferSize2Bytes ;
00911             break;
00912         case 4U:
00913             config->destTransferSize  = kEDMA_TransferSize4Bytes ;
00914             break;
00915         case 16U:
00916             config->destTransferSize  = kEDMA_TransferSize16Bytes ;
00917             break;
00918         case 32U:
00919             config->destTransferSize  = kEDMA_TransferSize32Bytes ;
00920             break;
00921         default:
00922             break;
00923     }
00924     switch (type)
00925     {
00926         case kEDMA_MemoryToMemory :
00927             config->destOffset  = destWidth;
00928             config->srcOffset  = srcWidth;
00929             break;
00930         case kEDMA_MemoryToPeripheral :
00931             config->destOffset  = 0U;
00932             config->srcOffset  = srcWidth;
00933             break;
00934         case kEDMA_PeripheralToMemory :
00935             config->destOffset  = destWidth;
00936             config->srcOffset  = 0U;
00937             break;
00938         default:
00939             break;
00940     }
00941 }
00942 
00943 /*!
00944  * brief Submits the eDMA transfer request.
00945  *
00946  * This function submits the eDMA transfer request according to the transfer configuration structure.
00947  * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool.
00948  * The tcd pools is setup by call function EDMA_InstallTCDMemory before.
00949  *
00950  * param handle eDMA handle pointer.
00951  * param config Pointer to eDMA transfer configuration structure.
00952  * retval kStatus_EDMA_Success It means submit transfer request succeed.
00953  * retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
00954  * retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later.
00955  */
00956 status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config)
00957 {
00958     assert(handle != NULL);
00959     assert(config != NULL);
00960 
00961     edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base ->TCD[handle->channel ];
00962 
00963     if (handle->tcdPool  == NULL)
00964     {
00965         /*
00966             Check if EDMA is busy: if the given channel started transfer, CSR will be not zero. Because
00967             if it is the last transfer, DREQ will be set. If not, ESG will be set. So in order to suit
00968             this check mechanism, EDMA_CreatHandle will clear CSR register.
00969         */
00970         if ((tcdRegs->CSR  != 0) && ((tcdRegs->CSR  & DMA_CSR_DONE_MASK) == 0))
00971         {
00972             return kStatus_EDMA_Busy ;
00973         }
00974         else
00975         {
00976             EDMA_SetTransferConfig(handle->base , handle->channel , config, NULL);
00977             /* Enable auto disable request feature */
00978             handle->base ->TCD[handle->channel ].CSR |= DMA_CSR_DREQ_MASK;
00979             /* Enable major interrupt */
00980             handle->base ->TCD[handle->channel ].CSR |= DMA_CSR_INTMAJOR_MASK;
00981 
00982             return kStatus_Success;
00983         }
00984     }
00985     else /* Use the TCD queue. */
00986     {
00987         uint32_t primask;
00988         uint32_t csr;
00989         int8_t currentTcd;
00990         int8_t previousTcd;
00991         int8_t nextTcd;
00992 
00993         /* Check if tcd pool is full. */
00994         primask = DisableGlobalIRQ();
00995         if (handle->tcdUsed  >= handle->tcdSize )
00996         {
00997             EnableGlobalIRQ(primask);
00998 
00999             return kStatus_EDMA_QueueFull ;
01000         }
01001         currentTcd = handle->tail ;
01002         handle->tcdUsed ++;
01003         /* Calculate index of next TCD */
01004         nextTcd = currentTcd + 1U;
01005         if (nextTcd == handle->tcdSize )
01006         {
01007             nextTcd = 0U;
01008         }
01009         /* Advance queue tail index */
01010         handle->tail  = nextTcd;
01011         EnableGlobalIRQ(primask);
01012         /* Calculate index of previous TCD */
01013         previousTcd = currentTcd ? currentTcd - 1U : handle->tcdSize  - 1U;
01014         /* Configure current TCD block. */
01015         EDMA_TcdReset(&handle->tcdPool [currentTcd]);
01016         EDMA_TcdSetTransferConfig(&handle->tcdPool [currentTcd], config, NULL);
01017         /* Enable major interrupt */
01018         handle->tcdPool [currentTcd].CSR  |= DMA_CSR_INTMAJOR_MASK;
01019         /* Link current TCD with next TCD for identification of current TCD */
01020         handle->tcdPool [currentTcd].DLAST_SGA  = (uint32_t)&handle->tcdPool [nextTcd];
01021         /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */
01022         if (currentTcd != previousTcd)
01023         {
01024             /* Enable scatter/gather feature in the previous TCD block. */
01025             csr = (handle->tcdPool [previousTcd].CSR  | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK;
01026             handle->tcdPool [previousTcd].CSR  = csr;
01027             /*
01028                 Check if the TCD block in the registers is the previous one (points to current TCD block). It
01029                 is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to
01030                 link the TCD register in case link the current TCD with the dead chain when TCD loading occurs
01031                 before link the previous TCD block.
01032             */
01033             if (tcdRegs->DLAST_SGA  == (uint32_t)&handle->tcdPool [currentTcd])
01034             {
01035                 /* Clear the DREQ bits for the dynamic scatter gather */
01036                 tcdRegs->CSR  |= DMA_CSR_DREQ_MASK;
01037                 /* Enable scatter/gather also in the TCD registers. */
01038                 csr = tcdRegs->CSR  | DMA_CSR_ESG_MASK;
01039                 /* Must write the CSR register one-time, because the transfer maybe finished anytime. */
01040                 tcdRegs->CSR  = csr;
01041                 /*
01042                     It is very important to check the ESG bit!
01043                     Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can
01044                     be used to check if the dynamic TCD link operation is successful. If ESG bit is not set
01045                     and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and
01046                     the current TCD block has been loaded into TCD registers), it means transfer finished
01047                     and TCD link operation fail, so must install TCD content into TCD registers and enable
01048                     transfer again. And if ESG is set, it means transfer has not finished, so TCD dynamic
01049                     link succeed.
01050                 */
01051                 if (tcdRegs->CSR  & DMA_CSR_ESG_MASK)
01052                 {
01053                     tcdRegs->CSR  &= ~DMA_CSR_DREQ_MASK;
01054                     return kStatus_Success;
01055                 }
01056                 /*
01057                     Check whether the current TCD block is already loaded in the TCD registers. It is another
01058                     condition when ESG bit is not set: it means the dynamic TCD link succeed and the current
01059                     TCD block has been loaded into TCD registers.
01060                 */
01061                 if (tcdRegs->DLAST_SGA  == (uint32_t)&handle->tcdPool [nextTcd])
01062                 {
01063                     return kStatus_Success;
01064                 }
01065                 /*
01066                     If go to this, means the previous transfer finished, and the DONE bit is set.
01067                     So shall configure TCD registers.
01068                 */
01069             }
01070             else if (tcdRegs->DLAST_SGA  != 0)
01071             {
01072                 /* The current TCD block has been linked successfully. */
01073                 return kStatus_Success;
01074             }
01075             else
01076             {
01077                 /*
01078                     DLAST_SGA is 0 and it means the first submit transfer, so shall configure
01079                     TCD registers.
01080                 */
01081             }
01082         }
01083         /* There is no live chain, TCD block need to be installed in TCD registers. */
01084         EDMA_InstallTCD(handle->base , handle->channel , &handle->tcdPool [currentTcd]);
01085         /* Enable channel request again. */
01086         if (handle->flags  & EDMA_TRANSFER_ENABLED_MASK)
01087         {
01088             handle->base ->SERQ = DMA_SERQ_SERQ(handle->channel );
01089         }
01090 
01091         return kStatus_Success;
01092     }
01093 }
01094 
01095 /*!
01096  * brief eDMA starts transfer.
01097  *
01098  * This function enables the channel request. Users can call this function after submitting the transfer request
01099  * or before submitting the transfer request.
01100  *
01101  * param handle eDMA handle pointer.
01102  */
01103 void EDMA_StartTransfer(edma_handle_t *handle)
01104 {
01105     assert(handle != NULL);
01106 
01107     if (handle->tcdPool  == NULL)
01108     {
01109         handle->base ->SERQ = DMA_SERQ_SERQ(handle->channel );
01110     }
01111     else /* Use the TCD queue. */
01112     {
01113         uint32_t primask;
01114         edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base ->TCD[handle->channel ];
01115 
01116         handle->flags  |= EDMA_TRANSFER_ENABLED_MASK;
01117 
01118         /* Check if there was at least one descriptor submitted since reset (TCD in registers is valid) */
01119         if (tcdRegs->DLAST_SGA  != 0U)
01120         {
01121             primask = DisableGlobalIRQ();
01122             /* Check if channel request is actually disable. */
01123             if ((handle->base ->ERQ & (1U << handle->channel )) == 0U)
01124             {
01125                 /* Check if transfer is paused. */
01126                 if ((!(tcdRegs->CSR  & DMA_CSR_DONE_MASK)) || (tcdRegs->CSR  & DMA_CSR_ESG_MASK))
01127                 {
01128                     /*
01129                         Re-enable channel request must be as soon as possible, so must put it into
01130                         critical section to avoid task switching or interrupt service routine.
01131                     */
01132                     handle->base ->SERQ = DMA_SERQ_SERQ(handle->channel );
01133                 }
01134             }
01135             EnableGlobalIRQ(primask);
01136         }
01137     }
01138 }
01139 
01140 /*!
01141  * brief eDMA stops transfer.
01142  *
01143  * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer()
01144  * again to resume the transfer.
01145  *
01146  * param handle eDMA handle pointer.
01147  */
01148 void EDMA_StopTransfer(edma_handle_t *handle)
01149 {
01150     assert(handle != NULL);
01151 
01152     handle->flags  &= (~EDMA_TRANSFER_ENABLED_MASK);
01153     handle->base ->CERQ = DMA_CERQ_CERQ(handle->channel );
01154 }
01155 
01156 /*!
01157  * brief eDMA aborts transfer.
01158  *
01159  * This function disables the channel request and clear transfer status bits.
01160  * Users can submit another transfer after calling this API.
01161  *
01162  * param handle DMA handle pointer.
01163  */
01164 void EDMA_AbortTransfer(edma_handle_t *handle)
01165 {
01166     handle->base ->CERQ = DMA_CERQ_CERQ(handle->channel );
01167     /*
01168         Clear CSR to release channel. Because if the given channel started transfer,
01169         CSR will be not zero. Because if it is the last transfer, DREQ will be set.
01170         If not, ESG will be set.
01171     */
01172     handle->base ->TCD[handle->channel ].CSR = 0;
01173     /* Cancel all next TCD transfer. */
01174     handle->base ->TCD[handle->channel ].DLAST_SGA = 0;
01175 
01176     /* Handle the tcd */
01177     if (handle->tcdPool  != NULL)
01178     {
01179         handle->header  = 0;
01180         handle->tail  = 0;
01181         handle->tcdUsed  = 0;
01182     }
01183 }
01184 
01185 /*!
01186  * brief eDMA IRQ handler for the current major loop transfer completion.
01187  *
01188  * This function clears the channel major interrupt flag and calls
01189  * the callback function if it is not NULL.
01190  *
01191  * Note:
01192  * For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed.
01193  * These include the final address adjustments and reloading of the BITER field into the CITER.
01194  * Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from
01195  * memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled).
01196  *
01197  * For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine.
01198  * As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index
01199  * in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be
01200  * (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have
01201  * been loaded into the eDMA engine at this point already.).
01202  *
01203  * For the last two continuous ISRs in a scatter/gather process, they  both load the last TCD (The last ISR does not
01204  * load a new TCD) from the memory pool to the eDMA engine when major loop completes.
01205  * Therefore, ensure that the header and tcdUsed updated are identical for them.
01206  * tcdUsed are both 0 in this case as no TCD to be loaded.
01207  *
01208  * See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for
01209  * further details.
01210  *
01211  * param handle eDMA handle pointer.
01212  */
01213 void EDMA_HandleIRQ(edma_handle_t *handle)
01214 {
01215     assert(handle != NULL);
01216 
01217     /* Clear EDMA interrupt flag */
01218     handle->base ->CINT = handle->channel ;
01219     if ((handle->tcdPool  == NULL) && (handle->callback  != NULL))
01220     {
01221         (handle->callback )(handle, handle->userData , true, 0);
01222     }
01223     else /* Use the TCD queue. Please refer to the API descriptions in the eDMA header file for detailed information. */
01224     {
01225         uint32_t sga = handle->base ->TCD[handle->channel ].DLAST_SGA;
01226         uint32_t sga_index;
01227         int32_t tcds_done;
01228         uint8_t new_header;
01229         bool transfer_done;
01230 
01231         /* Check if transfer is already finished. */
01232         transfer_done = ((handle->base ->TCD[handle->channel ].CSR & DMA_CSR_DONE_MASK) != 0);
01233         /* Get the offset of the next transfer TCD blocks to be loaded into the eDMA engine. */
01234         sga -= (uint32_t)handle->tcdPool ;
01235         /* Get the index of the next transfer TCD blocks to be loaded into the eDMA engine. */
01236         sga_index = sga / sizeof(edma_tcd_t);
01237         /* Adjust header positions. */
01238         if (transfer_done)
01239         {
01240             /* New header shall point to the next TCD to be loaded (current one is already finished) */
01241             new_header = sga_index;
01242         }
01243         else
01244         {
01245             /* New header shall point to this descriptor currently loaded (not finished yet) */
01246             new_header = sga_index ? sga_index - 1U : handle->tcdSize  - 1U;
01247         }
01248         /* Calculate the number of finished TCDs */
01249         if (new_header == handle->header )
01250         {
01251             if (handle->tcdUsed  == handle->tcdSize )
01252             {
01253                 tcds_done = handle->tcdUsed ;
01254             }
01255             else
01256             {
01257                 /* No TCD in the memory are going to be loaded or internal error occurs. */
01258                 tcds_done = 0;
01259             }
01260         }
01261         else
01262         {
01263             tcds_done = new_header - handle->header ;
01264             if (tcds_done < 0)
01265             {
01266                 tcds_done += handle->tcdSize ;
01267             }
01268         }
01269         /* Advance header which points to the TCD to be loaded into the eDMA engine from memory. */
01270         handle->header  = new_header;
01271         /* Release TCD blocks. tcdUsed is the TCD number which can be used/loaded in the memory pool. */
01272         handle->tcdUsed  -= tcds_done;
01273         /* Invoke callback function. */
01274         if (handle->callback )
01275         {
01276             (handle->callback )(handle, handle->userData , transfer_done, tcds_done);
01277         }
01278 
01279         /* clear the DONE bit here is meaningful for below cases:
01280          *1.A new TCD has been loaded to EDMA already:
01281          * need to clear the DONE bit in the IRQ handler to avoid TCD in EDMA been overwritten
01282          * if peripheral request isn't coming before next transfer request.
01283          *2.A new TCD has not been loaded to EDMA:
01284          * for the case that transfer request occur in the privious edma callback, this is a case that doesn't
01285          * need scatter gather, so keep DONE bit during the next transfer request will re-install the TCD.
01286          */
01287         if (transfer_done)
01288         {
01289             handle->base ->CDNE = handle->channel ;
01290         }
01291     }
01292 }
01293 
01294 /* 8 channels (Shared): kl28 */
01295 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 8U
01296 
01297 #if defined(DMA0)
01298 void DMA0_04_DriverIRQHandler(void)
01299 {
01300     if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag ) != 0U)
01301     {
01302         EDMA_HandleIRQ(s_EDMAHandle[0]);
01303     }
01304     if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
01305     {
01306         EDMA_HandleIRQ(s_EDMAHandle[4]);
01307     }
01308 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01309   exception return operation might vector to incorrect interrupt */
01310 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01311     __DSB();
01312 #endif
01313 }
01314 
01315 void DMA0_15_DriverIRQHandler(void)
01316 {
01317     if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
01318     {
01319         EDMA_HandleIRQ(s_EDMAHandle[1]);
01320     }
01321     if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
01322     {
01323         EDMA_HandleIRQ(s_EDMAHandle[5]);
01324     }
01325 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01326   exception return operation might vector to incorrect interrupt */
01327 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01328     __DSB();
01329 #endif
01330 }
01331 
01332 void DMA0_26_DriverIRQHandler(void)
01333 {
01334     if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
01335     {
01336         EDMA_HandleIRQ(s_EDMAHandle[2]);
01337     }
01338     if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
01339     {
01340         EDMA_HandleIRQ(s_EDMAHandle[6]);
01341     }
01342 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01343   exception return operation might vector to incorrect interrupt */
01344 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01345     __DSB();
01346 #endif
01347 }
01348 
01349 void DMA0_37_DriverIRQHandler(void)
01350 {
01351     if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
01352     {
01353         EDMA_HandleIRQ(s_EDMAHandle[3]);
01354     }
01355     if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
01356     {
01357         EDMA_HandleIRQ(s_EDMAHandle[7]);
01358     }
01359 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01360   exception return operation might vector to incorrect interrupt */
01361 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01362     __DSB();
01363 #endif
01364 }
01365 #endif
01366 
01367 #if defined(DMA1)
01368 
01369 #if defined(DMA0)
01370 void DMA1_04_DriverIRQHandler(void)
01371 {
01372     if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U)
01373     {
01374         EDMA_HandleIRQ(s_EDMAHandle[8]);
01375     }
01376     if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U)
01377     {
01378         EDMA_HandleIRQ(s_EDMAHandle[12]);
01379     }
01380 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01381   exception return operation might vector to incorrect interrupt */
01382 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01383     __DSB();
01384 #endif
01385 }
01386 
01387 void DMA1_15_DriverIRQHandler(void)
01388 {
01389     if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U)
01390     {
01391         EDMA_HandleIRQ(s_EDMAHandle[9]);
01392     }
01393     if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U)
01394     {
01395         EDMA_HandleIRQ(s_EDMAHandle[13]);
01396     }
01397 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01398   exception return operation might vector to incorrect interrupt */
01399 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01400     __DSB();
01401 #endif
01402 }
01403 
01404 void DMA1_26_DriverIRQHandler(void)
01405 {
01406     if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U)
01407     {
01408         EDMA_HandleIRQ(s_EDMAHandle[10]);
01409     }
01410     if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U)
01411     {
01412         EDMA_HandleIRQ(s_EDMAHandle[14]);
01413     }
01414 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01415   exception return operation might vector to incorrect interrupt */
01416 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01417     __DSB();
01418 #endif
01419 }
01420 
01421 void DMA1_37_DriverIRQHandler(void)
01422 {
01423     if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U)
01424     {
01425         EDMA_HandleIRQ(s_EDMAHandle[11]);
01426     }
01427     if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U)
01428     {
01429         EDMA_HandleIRQ(s_EDMAHandle[15]);
01430     }
01431 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01432   exception return operation might vector to incorrect interrupt */
01433 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01434     __DSB();
01435 #endif
01436 }
01437 
01438 #else
01439 void DMA1_04_DriverIRQHandler(void)
01440 {
01441     if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U)
01442     {
01443         EDMA_HandleIRQ(s_EDMAHandle[0]);
01444     }
01445     if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U)
01446     {
01447         EDMA_HandleIRQ(s_EDMAHandle[4]);
01448     }
01449 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01450   exception return operation might vector to incorrect interrupt */
01451 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01452     __DSB();
01453 #endif
01454 }
01455 
01456 void DMA1_15_DriverIRQHandler(void)
01457 {
01458     if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U)
01459     {
01460         EDMA_HandleIRQ(s_EDMAHandle[1]);
01461     }
01462     if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U)
01463     {
01464         EDMA_HandleIRQ(s_EDMAHandle[5]);
01465     }
01466 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01467   exception return operation might vector to incorrect interrupt */
01468 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01469     __DSB();
01470 #endif
01471 }
01472 
01473 void DMA1_26_DriverIRQHandler(void)
01474 {
01475     if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U)
01476     {
01477         EDMA_HandleIRQ(s_EDMAHandle[2]);
01478     }
01479     if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U)
01480     {
01481         EDMA_HandleIRQ(s_EDMAHandle[6]);
01482     }
01483 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01484   exception return operation might vector to incorrect interrupt */
01485 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01486     __DSB();
01487 #endif
01488 }
01489 
01490 void DMA1_37_DriverIRQHandler(void)
01491 {
01492     if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U)
01493     {
01494         EDMA_HandleIRQ(s_EDMAHandle[3]);
01495     }
01496     if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U)
01497     {
01498         EDMA_HandleIRQ(s_EDMAHandle[7]);
01499     }
01500 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01501   exception return operation might vector to incorrect interrupt */
01502 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01503     __DSB();
01504 #endif
01505 }
01506 #endif
01507 #endif
01508 #endif /* 8 channels (Shared) */
01509 
01510 /* 16 channels (Shared): K32H844P */
01511 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 16U
01512 
01513 void DMA0_08_DriverIRQHandler(void)
01514 {
01515     if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
01516     {
01517         EDMA_HandleIRQ(s_EDMAHandle[0]);
01518     }
01519     if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U)
01520     {
01521         EDMA_HandleIRQ(s_EDMAHandle[8]);
01522     }
01523 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01524   exception return operation might vector to incorrect interrupt */
01525 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01526     __DSB();
01527 #endif
01528 }
01529 
01530 void DMA0_19_DriverIRQHandler(void)
01531 {
01532     if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
01533     {
01534         EDMA_HandleIRQ(s_EDMAHandle[1]);
01535     }
01536     if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U)
01537     {
01538         EDMA_HandleIRQ(s_EDMAHandle[9]);
01539     }
01540 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01541   exception return operation might vector to incorrect interrupt */
01542 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01543     __DSB();
01544 #endif
01545 }
01546 
01547 void DMA0_210_DriverIRQHandler(void)
01548 {
01549     if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
01550     {
01551         EDMA_HandleIRQ(s_EDMAHandle[2]);
01552     }
01553     if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U)
01554     {
01555         EDMA_HandleIRQ(s_EDMAHandle[10]);
01556     }
01557 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01558   exception return operation might vector to incorrect interrupt */
01559 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01560     __DSB();
01561 #endif
01562 }
01563 
01564 void DMA0_311_DriverIRQHandler(void)
01565 {
01566     if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
01567     {
01568         EDMA_HandleIRQ(s_EDMAHandle[3]);
01569     }
01570     if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U)
01571     {
01572         EDMA_HandleIRQ(s_EDMAHandle[11]);
01573     }
01574 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01575   exception return operation might vector to incorrect interrupt */
01576 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01577     __DSB();
01578 #endif
01579 }
01580 
01581 void DMA0_412_DriverIRQHandler(void)
01582 {
01583     if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
01584     {
01585         EDMA_HandleIRQ(s_EDMAHandle[4]);
01586     }
01587     if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U)
01588     {
01589         EDMA_HandleIRQ(s_EDMAHandle[12]);
01590     }
01591 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01592   exception return operation might vector to incorrect interrupt */
01593 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01594     __DSB();
01595 #endif
01596 }
01597 
01598 void DMA0_513_DriverIRQHandler(void)
01599 {
01600     if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
01601     {
01602         EDMA_HandleIRQ(s_EDMAHandle[5]);
01603     }
01604     if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U)
01605     {
01606         EDMA_HandleIRQ(s_EDMAHandle[13]);
01607     }
01608 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01609   exception return operation might vector to incorrect interrupt */
01610 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01611     __DSB();
01612 #endif
01613 }
01614 
01615 void DMA0_614_DriverIRQHandler(void)
01616 {
01617     if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
01618     {
01619         EDMA_HandleIRQ(s_EDMAHandle[6]);
01620     }
01621     if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U)
01622     {
01623         EDMA_HandleIRQ(s_EDMAHandle[14]);
01624     }
01625 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01626   exception return operation might vector to incorrect interrupt */
01627 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01628     __DSB();
01629 #endif
01630 }
01631 
01632 void DMA0_715_DriverIRQHandler(void)
01633 {
01634     if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
01635     {
01636         EDMA_HandleIRQ(s_EDMAHandle[7]);
01637     }
01638     if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U)
01639     {
01640         EDMA_HandleIRQ(s_EDMAHandle[15]);
01641     }
01642 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01643   exception return operation might vector to incorrect interrupt */
01644 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01645     __DSB();
01646 #endif
01647 }
01648 
01649 #if defined(DMA1)
01650 void DMA1_08_DriverIRQHandler(void)
01651 {
01652     if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U)
01653     {
01654         EDMA_HandleIRQ(s_EDMAHandle[16]);
01655     }
01656     if ((EDMA_GetChannelStatusFlags(DMA1, 8U) & kEDMA_InterruptFlag) != 0U)
01657     {
01658         EDMA_HandleIRQ(s_EDMAHandle[24]);
01659     }
01660 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01661   exception return operation might vector to incorrect interrupt */
01662 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01663     __DSB();
01664 #endif
01665 }
01666 
01667 void DMA1_19_DriverIRQHandler(void)
01668 {
01669     if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U)
01670     {
01671         EDMA_HandleIRQ(s_EDMAHandle[17]);
01672     }
01673     if ((EDMA_GetChannelStatusFlags(DMA1, 9U) & kEDMA_InterruptFlag) != 0U)
01674     {
01675         EDMA_HandleIRQ(s_EDMAHandle[25]);
01676     }
01677 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01678   exception return operation might vector to incorrect interrupt */
01679 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01680     __DSB();
01681 #endif
01682 }
01683 
01684 void DMA1_210_DriverIRQHandler(void)
01685 {
01686     if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U)
01687     {
01688         EDMA_HandleIRQ(s_EDMAHandle[18]);
01689     }
01690     if ((EDMA_GetChannelStatusFlags(DMA1, 10U) & kEDMA_InterruptFlag) != 0U)
01691     {
01692         EDMA_HandleIRQ(s_EDMAHandle[26]);
01693     }
01694 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01695   exception return operation might vector to incorrect interrupt */
01696 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01697     __DSB();
01698 #endif
01699 }
01700 
01701 void DMA1_311_DriverIRQHandler(void)
01702 {
01703     if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U)
01704     {
01705         EDMA_HandleIRQ(s_EDMAHandle[19]);
01706     }
01707     if ((EDMA_GetChannelStatusFlags(DMA1, 11U) & kEDMA_InterruptFlag) != 0U)
01708     {
01709         EDMA_HandleIRQ(s_EDMAHandle[27]);
01710     }
01711 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01712   exception return operation might vector to incorrect interrupt */
01713 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01714     __DSB();
01715 #endif
01716 }
01717 
01718 void DMA1_412_DriverIRQHandler(void)
01719 {
01720     if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U)
01721     {
01722         EDMA_HandleIRQ(s_EDMAHandle[20]);
01723     }
01724     if ((EDMA_GetChannelStatusFlags(DMA1, 12U) & kEDMA_InterruptFlag) != 0U)
01725     {
01726         EDMA_HandleIRQ(s_EDMAHandle[28]);
01727     }
01728 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01729   exception return operation might vector to incorrect interrupt */
01730 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01731     __DSB();
01732 #endif
01733 }
01734 
01735 void DMA1_513_DriverIRQHandler(void)
01736 {
01737     if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U)
01738     {
01739         EDMA_HandleIRQ(s_EDMAHandle[21]);
01740     }
01741     if ((EDMA_GetChannelStatusFlags(DMA1, 13U) & kEDMA_InterruptFlag) != 0U)
01742     {
01743         EDMA_HandleIRQ(s_EDMAHandle[29]);
01744     }
01745 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01746   exception return operation might vector to incorrect interrupt */
01747 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01748     __DSB();
01749 #endif
01750 }
01751 
01752 void DMA1_614_DriverIRQHandler(void)
01753 {
01754     if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U)
01755     {
01756         EDMA_HandleIRQ(s_EDMAHandle[22]);
01757     }
01758     if ((EDMA_GetChannelStatusFlags(DMA1, 14U) & kEDMA_InterruptFlag) != 0U)
01759     {
01760         EDMA_HandleIRQ(s_EDMAHandle[30]);
01761     }
01762 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01763   exception return operation might vector to incorrect interrupt */
01764 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01765     __DSB();
01766 #endif
01767 }
01768 
01769 void DMA1_715_DriverIRQHandler(void)
01770 {
01771     if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U)
01772     {
01773         EDMA_HandleIRQ(s_EDMAHandle[23]);
01774     }
01775     if ((EDMA_GetChannelStatusFlags(DMA1, 15U) & kEDMA_InterruptFlag) != 0U)
01776     {
01777         EDMA_HandleIRQ(s_EDMAHandle[31]);
01778     }
01779 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01780   exception return operation might vector to incorrect interrupt */
01781 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01782     __DSB();
01783 #endif
01784 }
01785 #endif
01786 #endif /* 16 channels (Shared) */
01787 
01788 /* 32 channels (Shared): k80 */
01789 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U
01790 
01791 void DMA0_DMA16_DriverIRQHandler(void)
01792 {
01793     if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
01794     {
01795         EDMA_HandleIRQ(s_EDMAHandle[0]);
01796     }
01797     if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U)
01798     {
01799         EDMA_HandleIRQ(s_EDMAHandle[16]);
01800     }
01801 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01802   exception return operation might vector to incorrect interrupt */
01803 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01804     __DSB();
01805 #endif
01806 }
01807 
01808 void DMA1_DMA17_DriverIRQHandler(void)
01809 {
01810     if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
01811     {
01812         EDMA_HandleIRQ(s_EDMAHandle[1]);
01813     }
01814     if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U)
01815     {
01816         EDMA_HandleIRQ(s_EDMAHandle[17]);
01817     }
01818 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01819   exception return operation might vector to incorrect interrupt */
01820 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01821     __DSB();
01822 #endif
01823 }
01824 
01825 void DMA2_DMA18_DriverIRQHandler(void)
01826 {
01827     if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
01828     {
01829         EDMA_HandleIRQ(s_EDMAHandle[2]);
01830     }
01831     if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U)
01832     {
01833         EDMA_HandleIRQ(s_EDMAHandle[18]);
01834     }
01835 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01836   exception return operation might vector to incorrect interrupt */
01837 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01838     __DSB();
01839 #endif
01840 }
01841 
01842 void DMA3_DMA19_DriverIRQHandler(void)
01843 {
01844     if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
01845     {
01846         EDMA_HandleIRQ(s_EDMAHandle[3]);
01847     }
01848     if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U)
01849     {
01850         EDMA_HandleIRQ(s_EDMAHandle[19]);
01851     }
01852 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01853   exception return operation might vector to incorrect interrupt */
01854 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01855     __DSB();
01856 #endif
01857 }
01858 
01859 void DMA4_DMA20_DriverIRQHandler(void)
01860 {
01861     if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
01862     {
01863         EDMA_HandleIRQ(s_EDMAHandle[4]);
01864     }
01865     if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U)
01866     {
01867         EDMA_HandleIRQ(s_EDMAHandle[20]);
01868     }
01869 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01870   exception return operation might vector to incorrect interrupt */
01871 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01872     __DSB();
01873 #endif
01874 }
01875 
01876 void DMA5_DMA21_DriverIRQHandler(void)
01877 {
01878     if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
01879     {
01880         EDMA_HandleIRQ(s_EDMAHandle[5]);
01881     }
01882     if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U)
01883     {
01884         EDMA_HandleIRQ(s_EDMAHandle[21]);
01885     }
01886 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01887   exception return operation might vector to incorrect interrupt */
01888 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01889     __DSB();
01890 #endif
01891 }
01892 
01893 void DMA6_DMA22_DriverIRQHandler(void)
01894 {
01895     if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
01896     {
01897         EDMA_HandleIRQ(s_EDMAHandle[6]);
01898     }
01899     if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U)
01900     {
01901         EDMA_HandleIRQ(s_EDMAHandle[22]);
01902     }
01903 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01904   exception return operation might vector to incorrect interrupt */
01905 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01906     __DSB();
01907 #endif
01908 }
01909 
01910 void DMA7_DMA23_DriverIRQHandler(void)
01911 {
01912     if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
01913     {
01914         EDMA_HandleIRQ(s_EDMAHandle[7]);
01915     }
01916     if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U)
01917     {
01918         EDMA_HandleIRQ(s_EDMAHandle[23]);
01919     }
01920 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01921   exception return operation might vector to incorrect interrupt */
01922 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01923     __DSB();
01924 #endif
01925 }
01926 
01927 void DMA8_DMA24_DriverIRQHandler(void)
01928 {
01929     if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U)
01930     {
01931         EDMA_HandleIRQ(s_EDMAHandle[8]);
01932     }
01933     if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U)
01934     {
01935         EDMA_HandleIRQ(s_EDMAHandle[24]);
01936     }
01937 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01938   exception return operation might vector to incorrect interrupt */
01939 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01940     __DSB();
01941 #endif
01942 }
01943 
01944 void DMA9_DMA25_DriverIRQHandler(void)
01945 {
01946     if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U)
01947     {
01948         EDMA_HandleIRQ(s_EDMAHandle[9]);
01949     }
01950     if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U)
01951     {
01952         EDMA_HandleIRQ(s_EDMAHandle[25]);
01953     }
01954 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01955   exception return operation might vector to incorrect interrupt */
01956 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01957     __DSB();
01958 #endif
01959 }
01960 
01961 void DMA10_DMA26_DriverIRQHandler(void)
01962 {
01963     if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U)
01964     {
01965         EDMA_HandleIRQ(s_EDMAHandle[10]);
01966     }
01967     if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U)
01968     {
01969         EDMA_HandleIRQ(s_EDMAHandle[26]);
01970     }
01971 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01972   exception return operation might vector to incorrect interrupt */
01973 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01974     __DSB();
01975 #endif
01976 }
01977 
01978 void DMA11_DMA27_DriverIRQHandler(void)
01979 {
01980     if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U)
01981     {
01982         EDMA_HandleIRQ(s_EDMAHandle[11]);
01983     }
01984     if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U)
01985     {
01986         EDMA_HandleIRQ(s_EDMAHandle[27]);
01987     }
01988 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
01989   exception return operation might vector to incorrect interrupt */
01990 #if defined __CORTEX_M && (__CORTEX_M == 4U)
01991     __DSB();
01992 #endif
01993 }
01994 
01995 void DMA12_DMA28_DriverIRQHandler(void)
01996 {
01997     if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U)
01998     {
01999         EDMA_HandleIRQ(s_EDMAHandle[12]);
02000     }
02001     if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U)
02002     {
02003         EDMA_HandleIRQ(s_EDMAHandle[28]);
02004     }
02005 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02006   exception return operation might vector to incorrect interrupt */
02007 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02008     __DSB();
02009 #endif
02010 }
02011 
02012 void DMA13_DMA29_DriverIRQHandler(void)
02013 {
02014     if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U)
02015     {
02016         EDMA_HandleIRQ(s_EDMAHandle[13]);
02017     }
02018     if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U)
02019     {
02020         EDMA_HandleIRQ(s_EDMAHandle[29]);
02021     }
02022 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02023   exception return operation might vector to incorrect interrupt */
02024 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02025     __DSB();
02026 #endif
02027 }
02028 
02029 void DMA14_DMA30_DriverIRQHandler(void)
02030 {
02031     if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U)
02032     {
02033         EDMA_HandleIRQ(s_EDMAHandle[14]);
02034     }
02035     if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U)
02036     {
02037         EDMA_HandleIRQ(s_EDMAHandle[30]);
02038     }
02039 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02040   exception return operation might vector to incorrect interrupt */
02041 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02042     __DSB();
02043 #endif
02044 }
02045 
02046 void DMA15_DMA31_DriverIRQHandler(void)
02047 {
02048     if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U)
02049     {
02050         EDMA_HandleIRQ(s_EDMAHandle[15]);
02051     }
02052     if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U)
02053     {
02054         EDMA_HandleIRQ(s_EDMAHandle[31]);
02055     }
02056 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02057   exception return operation might vector to incorrect interrupt */
02058 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02059     __DSB();
02060 #endif
02061 }
02062 #endif /* 32 channels (Shared) */
02063 
02064 /* 32 channels (Shared): MCIMX7U5_M4 */
02065 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U
02066 
02067 void DMA0_0_4_DriverIRQHandler(void)
02068 {
02069     if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
02070     {
02071         EDMA_HandleIRQ(s_EDMAHandle[0]);
02072     }
02073     if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
02074     {
02075         EDMA_HandleIRQ(s_EDMAHandle[4]);
02076     }
02077 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02078   exception return operation might vector to incorrect interrupt */
02079 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02080     __DSB();
02081 #endif
02082 }
02083 
02084 void DMA0_1_5_DriverIRQHandler(void)
02085 {
02086     if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
02087     {
02088         EDMA_HandleIRQ(s_EDMAHandle[1]);
02089     }
02090     if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
02091     {
02092         EDMA_HandleIRQ(s_EDMAHandle[5]);
02093     }
02094 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02095   exception return operation might vector to incorrect interrupt */
02096 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02097     __DSB();
02098 #endif
02099 }
02100 
02101 void DMA0_2_6_DriverIRQHandler(void)
02102 {
02103     if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
02104     {
02105         EDMA_HandleIRQ(s_EDMAHandle[2]);
02106     }
02107     if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
02108     {
02109         EDMA_HandleIRQ(s_EDMAHandle[6]);
02110     }
02111 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02112   exception return operation might vector to incorrect interrupt */
02113 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02114     __DSB();
02115 #endif
02116 }
02117 
02118 void DMA0_3_7_DriverIRQHandler(void)
02119 {
02120     if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
02121     {
02122         EDMA_HandleIRQ(s_EDMAHandle[3]);
02123     }
02124     if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
02125     {
02126         EDMA_HandleIRQ(s_EDMAHandle[7]);
02127     }
02128 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02129   exception return operation might vector to incorrect interrupt */
02130 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02131     __DSB();
02132 #endif
02133 }
02134 
02135 void DMA0_8_12_DriverIRQHandler(void)
02136 {
02137     if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U)
02138     {
02139         EDMA_HandleIRQ(s_EDMAHandle[8]);
02140     }
02141     if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U)
02142     {
02143         EDMA_HandleIRQ(s_EDMAHandle[12]);
02144     }
02145 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02146   exception return operation might vector to incorrect interrupt */
02147 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02148     __DSB();
02149 #endif
02150 }
02151 
02152 void DMA0_9_13_DriverIRQHandler(void)
02153 {
02154     if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U)
02155     {
02156         EDMA_HandleIRQ(s_EDMAHandle[9]);
02157     }
02158     if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U)
02159     {
02160         EDMA_HandleIRQ(s_EDMAHandle[13]);
02161     }
02162 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02163   exception return operation might vector to incorrect interrupt */
02164 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02165     __DSB();
02166 #endif
02167 }
02168 
02169 void DMA0_10_14_DriverIRQHandler(void)
02170 {
02171     if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U)
02172     {
02173         EDMA_HandleIRQ(s_EDMAHandle[10]);
02174     }
02175     if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U)
02176     {
02177         EDMA_HandleIRQ(s_EDMAHandle[14]);
02178     }
02179 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02180   exception return operation might vector to incorrect interrupt */
02181 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02182     __DSB();
02183 #endif
02184 }
02185 
02186 void DMA0_11_15_DriverIRQHandler(void)
02187 {
02188     if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U)
02189     {
02190         EDMA_HandleIRQ(s_EDMAHandle[11]);
02191     }
02192     if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U)
02193     {
02194         EDMA_HandleIRQ(s_EDMAHandle[15]);
02195     }
02196 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02197   exception return operation might vector to incorrect interrupt */
02198 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02199     __DSB();
02200 #endif
02201 }
02202 
02203 void DMA0_16_20_DriverIRQHandler(void)
02204 {
02205     if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U)
02206     {
02207         EDMA_HandleIRQ(s_EDMAHandle[16]);
02208     }
02209     if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U)
02210     {
02211         EDMA_HandleIRQ(s_EDMAHandle[20]);
02212     }
02213 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02214   exception return operation might vector to incorrect interrupt */
02215 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02216     __DSB();
02217 #endif
02218 }
02219 
02220 void DMA0_17_21_DriverIRQHandler(void)
02221 {
02222     if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U)
02223     {
02224         EDMA_HandleIRQ(s_EDMAHandle[17]);
02225     }
02226     if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U)
02227     {
02228         EDMA_HandleIRQ(s_EDMAHandle[21]);
02229     }
02230 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02231   exception return operation might vector to incorrect interrupt */
02232 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02233     __DSB();
02234 #endif
02235 }
02236 
02237 void DMA0_18_22_DriverIRQHandler(void)
02238 {
02239     if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U)
02240     {
02241         EDMA_HandleIRQ(s_EDMAHandle[18]);
02242     }
02243     if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U)
02244     {
02245         EDMA_HandleIRQ(s_EDMAHandle[22]);
02246     }
02247 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02248   exception return operation might vector to incorrect interrupt */
02249 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02250     __DSB();
02251 #endif
02252 }
02253 
02254 void DMA0_19_23_DriverIRQHandler(void)
02255 {
02256     if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U)
02257     {
02258         EDMA_HandleIRQ(s_EDMAHandle[19]);
02259     }
02260     if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U)
02261     {
02262         EDMA_HandleIRQ(s_EDMAHandle[23]);
02263     }
02264 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02265   exception return operation might vector to incorrect interrupt */
02266 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02267     __DSB();
02268 #endif
02269 }
02270 
02271 void DMA0_24_28_DriverIRQHandler(void)
02272 {
02273     if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U)
02274     {
02275         EDMA_HandleIRQ(s_EDMAHandle[24]);
02276     }
02277     if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U)
02278     {
02279         EDMA_HandleIRQ(s_EDMAHandle[28]);
02280     }
02281 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02282   exception return operation might vector to incorrect interrupt */
02283 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02284     __DSB();
02285 #endif
02286 }
02287 
02288 void DMA0_25_29_DriverIRQHandler(void)
02289 {
02290     if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U)
02291     {
02292         EDMA_HandleIRQ(s_EDMAHandle[25]);
02293     }
02294     if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U)
02295     {
02296         EDMA_HandleIRQ(s_EDMAHandle[29]);
02297     }
02298 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02299   exception return operation might vector to incorrect interrupt */
02300 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02301     __DSB();
02302 #endif
02303 }
02304 
02305 void DMA0_26_30_DriverIRQHandler(void)
02306 {
02307     if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U)
02308     {
02309         EDMA_HandleIRQ(s_EDMAHandle[26]);
02310     }
02311     if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U)
02312     {
02313         EDMA_HandleIRQ(s_EDMAHandle[30]);
02314     }
02315 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02316   exception return operation might vector to incorrect interrupt */
02317 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02318     __DSB();
02319 #endif
02320 }
02321 
02322 void DMA0_27_31_DriverIRQHandler(void)
02323 {
02324     if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U)
02325     {
02326         EDMA_HandleIRQ(s_EDMAHandle[27]);
02327     }
02328     if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U)
02329     {
02330         EDMA_HandleIRQ(s_EDMAHandle[31]);
02331     }
02332 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02333   exception return operation might vector to incorrect interrupt */
02334 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02335     __DSB();
02336 #endif
02337 }
02338 #endif /* 32 channels (Shared): MCIMX7U5 */
02339 
02340 /* 4 channels (No Shared): kv10  */
02341 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 0
02342 
02343 void DMA0_DriverIRQHandler(void)
02344 {
02345     EDMA_HandleIRQ(s_EDMAHandle[0]);
02346 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02347   exception return operation might vector to incorrect interrupt */
02348 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02349     __DSB();
02350 #endif
02351 }
02352 
02353 void DMA1_DriverIRQHandler(void)
02354 {
02355     EDMA_HandleIRQ(s_EDMAHandle[1]);
02356 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02357   exception return operation might vector to incorrect interrupt */
02358 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02359     __DSB();
02360 #endif
02361 }
02362 
02363 void DMA2_DriverIRQHandler(void)
02364 {
02365     EDMA_HandleIRQ(s_EDMAHandle[2]);
02366 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02367   exception return operation might vector to incorrect interrupt */
02368 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02369     __DSB();
02370 #endif
02371 }
02372 
02373 void DMA3_DriverIRQHandler(void)
02374 {
02375     EDMA_HandleIRQ(s_EDMAHandle[3]);
02376 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02377   exception return operation might vector to incorrect interrupt */
02378 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02379     __DSB();
02380 #endif
02381 }
02382 
02383 /* 8 channels (No Shared) */
02384 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 4U
02385 
02386 void DMA4_DriverIRQHandler(void)
02387 {
02388     EDMA_HandleIRQ(s_EDMAHandle[4]);
02389 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02390   exception return operation might vector to incorrect interrupt */
02391 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02392     __DSB();
02393 #endif
02394 }
02395 
02396 void DMA5_DriverIRQHandler(void)
02397 {
02398     EDMA_HandleIRQ(s_EDMAHandle[5]);
02399 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02400   exception return operation might vector to incorrect interrupt */
02401 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02402     __DSB();
02403 #endif
02404 }
02405 
02406 void DMA6_DriverIRQHandler(void)
02407 {
02408     EDMA_HandleIRQ(s_EDMAHandle[6]);
02409 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02410   exception return operation might vector to incorrect interrupt */
02411 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02412     __DSB();
02413 #endif
02414 }
02415 
02416 void DMA7_DriverIRQHandler(void)
02417 {
02418     EDMA_HandleIRQ(s_EDMAHandle[7]);
02419 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02420   exception return operation might vector to incorrect interrupt */
02421 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02422     __DSB();
02423 #endif
02424 }
02425 #endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 8 */
02426 
02427 /* 16 channels (No Shared) */
02428 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 8U
02429 
02430 void DMA8_DriverIRQHandler(void)
02431 {
02432     EDMA_HandleIRQ(s_EDMAHandle[8]);
02433 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02434   exception return operation might vector to incorrect interrupt */
02435 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02436     __DSB();
02437 #endif
02438 }
02439 
02440 void DMA9_DriverIRQHandler(void)
02441 {
02442     EDMA_HandleIRQ(s_EDMAHandle[9]);
02443 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02444   exception return operation might vector to incorrect interrupt */
02445 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02446     __DSB();
02447 #endif
02448 }
02449 
02450 void DMA10_DriverIRQHandler(void)
02451 {
02452     EDMA_HandleIRQ(s_EDMAHandle[10]);
02453 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02454   exception return operation might vector to incorrect interrupt */
02455 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02456     __DSB();
02457 #endif
02458 }
02459 
02460 void DMA11_DriverIRQHandler(void)
02461 {
02462     EDMA_HandleIRQ(s_EDMAHandle[11]);
02463 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02464   exception return operation might vector to incorrect interrupt */
02465 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02466     __DSB();
02467 #endif
02468 }
02469 
02470 void DMA12_DriverIRQHandler(void)
02471 {
02472     EDMA_HandleIRQ(s_EDMAHandle[12]);
02473 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02474   exception return operation might vector to incorrect interrupt */
02475 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02476     __DSB();
02477 #endif
02478 }
02479 
02480 void DMA13_DriverIRQHandler(void)
02481 {
02482     EDMA_HandleIRQ(s_EDMAHandle[13]);
02483 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02484   exception return operation might vector to incorrect interrupt */
02485 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02486     __DSB();
02487 #endif
02488 }
02489 
02490 void DMA14_DriverIRQHandler(void)
02491 {
02492     EDMA_HandleIRQ(s_EDMAHandle[14]);
02493 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02494   exception return operation might vector to incorrect interrupt */
02495 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02496     __DSB();
02497 #endif
02498 }
02499 
02500 void DMA15_DriverIRQHandler(void)
02501 {
02502     EDMA_HandleIRQ(s_EDMAHandle[15]);
02503 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02504   exception return operation might vector to incorrect interrupt */
02505 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02506     __DSB();
02507 #endif
02508 }
02509 #endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 16 */
02510 
02511 /* 32 channels (No Shared) */
02512 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 16U
02513 
02514 void DMA16_DriverIRQHandler(void)
02515 {
02516     EDMA_HandleIRQ(s_EDMAHandle[16]);
02517 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02518   exception return operation might vector to incorrect interrupt */
02519 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02520     __DSB();
02521 #endif
02522 }
02523 
02524 void DMA17_DriverIRQHandler(void)
02525 {
02526     EDMA_HandleIRQ(s_EDMAHandle[17]);
02527 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02528   exception return operation might vector to incorrect interrupt */
02529 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02530     __DSB();
02531 #endif
02532 }
02533 
02534 void DMA18_DriverIRQHandler(void)
02535 {
02536     EDMA_HandleIRQ(s_EDMAHandle[18]);
02537 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02538   exception return operation might vector to incorrect interrupt */
02539 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02540     __DSB();
02541 #endif
02542 }
02543 
02544 void DMA19_DriverIRQHandler(void)
02545 {
02546     EDMA_HandleIRQ(s_EDMAHandle[19]);
02547 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02548   exception return operation might vector to incorrect interrupt */
02549 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02550     __DSB();
02551 #endif
02552 }
02553 
02554 void DMA20_DriverIRQHandler(void)
02555 {
02556     EDMA_HandleIRQ(s_EDMAHandle[20]);
02557 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02558   exception return operation might vector to incorrect interrupt */
02559 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02560     __DSB();
02561 #endif
02562 }
02563 
02564 void DMA21_DriverIRQHandler(void)
02565 {
02566     EDMA_HandleIRQ(s_EDMAHandle[21]);
02567 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02568   exception return operation might vector to incorrect interrupt */
02569 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02570     __DSB();
02571 #endif
02572 }
02573 
02574 void DMA22_DriverIRQHandler(void)
02575 {
02576     EDMA_HandleIRQ(s_EDMAHandle[22]);
02577 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02578   exception return operation might vector to incorrect interrupt */
02579 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02580     __DSB();
02581 #endif
02582 }
02583 
02584 void DMA23_DriverIRQHandler(void)
02585 {
02586     EDMA_HandleIRQ(s_EDMAHandle[23]);
02587 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02588   exception return operation might vector to incorrect interrupt */
02589 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02590     __DSB();
02591 #endif
02592 }
02593 
02594 void DMA24_DriverIRQHandler(void)
02595 {
02596     EDMA_HandleIRQ(s_EDMAHandle[24]);
02597 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02598   exception return operation might vector to incorrect interrupt */
02599 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02600     __DSB();
02601 #endif
02602 }
02603 
02604 void DMA25_DriverIRQHandler(void)
02605 {
02606     EDMA_HandleIRQ(s_EDMAHandle[25]);
02607 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02608   exception return operation might vector to incorrect interrupt */
02609 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02610     __DSB();
02611 #endif
02612 }
02613 
02614 void DMA26_DriverIRQHandler(void)
02615 {
02616     EDMA_HandleIRQ(s_EDMAHandle[26]);
02617 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02618   exception return operation might vector to incorrect interrupt */
02619 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02620     __DSB();
02621 #endif
02622 }
02623 
02624 void DMA27_DriverIRQHandler(void)
02625 {
02626     EDMA_HandleIRQ(s_EDMAHandle[27]);
02627 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02628   exception return operation might vector to incorrect interrupt */
02629 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02630     __DSB();
02631 #endif
02632 }
02633 
02634 void DMA28_DriverIRQHandler(void)
02635 {
02636     EDMA_HandleIRQ(s_EDMAHandle[28]);
02637 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02638   exception return operation might vector to incorrect interrupt */
02639 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02640     __DSB();
02641 #endif
02642 }
02643 
02644 void DMA29_DriverIRQHandler(void)
02645 {
02646     EDMA_HandleIRQ(s_EDMAHandle[29]);
02647 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02648   exception return operation might vector to incorrect interrupt */
02649 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02650     __DSB();
02651 #endif
02652 }
02653 
02654 void DMA30_DriverIRQHandler(void)
02655 {
02656     EDMA_HandleIRQ(s_EDMAHandle[30]);
02657 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02658   exception return operation might vector to incorrect interrupt */
02659 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02660     __DSB();
02661 #endif
02662 }
02663 
02664 void DMA31_DriverIRQHandler(void)
02665 {
02666     EDMA_HandleIRQ(s_EDMAHandle[31]);
02667 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
02668   exception return operation might vector to incorrect interrupt */
02669 #if defined __CORTEX_M && (__CORTEX_M == 4U)
02670     __DSB();
02671 #endif
02672 }
02673 #endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 32 */
02674 
02675 #endif /* 4/8/16/32 channels (No Shared)  */