Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/atmel/sam3u2c/component/pdc.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 2 /* Atmel Microcontroller Software Support */
Pawel Zarembski 0:01f31e923fe2 3 /* SAM Software Package License */
Pawel Zarembski 0:01f31e923fe2 4 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 5 /* Copyright (c) %copyright_year%, Atmel Corporation */
Pawel Zarembski 0:01f31e923fe2 6 /* */
Pawel Zarembski 0:01f31e923fe2 7 /* All rights reserved. */
Pawel Zarembski 0:01f31e923fe2 8 /* */
Pawel Zarembski 0:01f31e923fe2 9 /* Redistribution and use in source and binary forms, with or without */
Pawel Zarembski 0:01f31e923fe2 10 /* modification, are permitted provided that the following condition is met: */
Pawel Zarembski 0:01f31e923fe2 11 /* */
Pawel Zarembski 0:01f31e923fe2 12 /* - Redistributions of source code must retain the above copyright notice, */
Pawel Zarembski 0:01f31e923fe2 13 /* this list of conditions and the disclaimer below. */
Pawel Zarembski 0:01f31e923fe2 14 /* */
Pawel Zarembski 0:01f31e923fe2 15 /* Atmel's name may not be used to endorse or promote products derived from */
Pawel Zarembski 0:01f31e923fe2 16 /* this software without specific prior written permission. */
Pawel Zarembski 0:01f31e923fe2 17 /* */
Pawel Zarembski 0:01f31e923fe2 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
Pawel Zarembski 0:01f31e923fe2 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
Pawel Zarembski 0:01f31e923fe2 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
Pawel Zarembski 0:01f31e923fe2 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
Pawel Zarembski 0:01f31e923fe2 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
Pawel Zarembski 0:01f31e923fe2 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
Pawel Zarembski 0:01f31e923fe2 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
Pawel Zarembski 0:01f31e923fe2 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
Pawel Zarembski 0:01f31e923fe2 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
Pawel Zarembski 0:01f31e923fe2 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
Pawel Zarembski 0:01f31e923fe2 28 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 #ifndef _SAM3U_PDC_COMPONENT_
Pawel Zarembski 0:01f31e923fe2 31 #define _SAM3U_PDC_COMPONENT_
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 /* ============================================================================= */
Pawel Zarembski 0:01f31e923fe2 34 /** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
Pawel Zarembski 0:01f31e923fe2 35 /* ============================================================================= */
Pawel Zarembski 0:01f31e923fe2 36 /** \addtogroup SAM3U_PDC Peripheral DMA Controller */
Pawel Zarembski 0:01f31e923fe2 37 /*@{*/
Pawel Zarembski 0:01f31e923fe2 38
Pawel Zarembski 0:01f31e923fe2 39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Pawel Zarembski 0:01f31e923fe2 40 /** \brief Pdc hardware registers */
Pawel Zarembski 0:01f31e923fe2 41 typedef struct {
Pawel Zarembski 0:01f31e923fe2 42 RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */
Pawel Zarembski 0:01f31e923fe2 43 RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x4) Receive Counter Register */
Pawel Zarembski 0:01f31e923fe2 44 RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */
Pawel Zarembski 0:01f31e923fe2 45 RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */
Pawel Zarembski 0:01f31e923fe2 46 RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */
Pawel Zarembski 0:01f31e923fe2 47 RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */
Pawel Zarembski 0:01f31e923fe2 48 RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */
Pawel Zarembski 0:01f31e923fe2 49 RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */
Pawel Zarembski 0:01f31e923fe2 50 WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */
Pawel Zarembski 0:01f31e923fe2 51 RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */
Pawel Zarembski 0:01f31e923fe2 52 } Pdc;
Pawel Zarembski 0:01f31e923fe2 53 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Pawel Zarembski 0:01f31e923fe2 54 /* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */
Pawel Zarembski 0:01f31e923fe2 55 #define PERIPH_RPR_RXPTR_Pos 0
Pawel Zarembski 0:01f31e923fe2 56 #define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */
Pawel Zarembski 0:01f31e923fe2 57 #define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 58 /* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */
Pawel Zarembski 0:01f31e923fe2 59 #define PERIPH_RCR_RXCTR_Pos 0
Pawel Zarembski 0:01f31e923fe2 60 #define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */
Pawel Zarembski 0:01f31e923fe2 61 #define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 62 /* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */
Pawel Zarembski 0:01f31e923fe2 63 #define PERIPH_TPR_TXPTR_Pos 0
Pawel Zarembski 0:01f31e923fe2 64 #define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */
Pawel Zarembski 0:01f31e923fe2 65 #define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 66 /* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */
Pawel Zarembski 0:01f31e923fe2 67 #define PERIPH_TCR_TXCTR_Pos 0
Pawel Zarembski 0:01f31e923fe2 68 #define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */
Pawel Zarembski 0:01f31e923fe2 69 #define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 70 /* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */
Pawel Zarembski 0:01f31e923fe2 71 #define PERIPH_RNPR_RXNPTR_Pos 0
Pawel Zarembski 0:01f31e923fe2 72 #define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */
Pawel Zarembski 0:01f31e923fe2 73 #define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 74 /* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */
Pawel Zarembski 0:01f31e923fe2 75 #define PERIPH_RNCR_RXNCTR_Pos 0
Pawel Zarembski 0:01f31e923fe2 76 #define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */
Pawel Zarembski 0:01f31e923fe2 77 #define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 78 /* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */
Pawel Zarembski 0:01f31e923fe2 79 #define PERIPH_TNPR_TXNPTR_Pos 0
Pawel Zarembski 0:01f31e923fe2 80 #define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */
Pawel Zarembski 0:01f31e923fe2 81 #define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 82 /* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */
Pawel Zarembski 0:01f31e923fe2 83 #define PERIPH_TNCR_TXNCTR_Pos 0
Pawel Zarembski 0:01f31e923fe2 84 #define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */
Pawel Zarembski 0:01f31e923fe2 85 #define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))
Pawel Zarembski 0:01f31e923fe2 86 /* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */
Pawel Zarembski 0:01f31e923fe2 87 #define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */
Pawel Zarembski 0:01f31e923fe2 88 #define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */
Pawel Zarembski 0:01f31e923fe2 89 #define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */
Pawel Zarembski 0:01f31e923fe2 90 #define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */
Pawel Zarembski 0:01f31e923fe2 91 /* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */
Pawel Zarembski 0:01f31e923fe2 92 #define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */
Pawel Zarembski 0:01f31e923fe2 93 #define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */
Pawel Zarembski 0:01f31e923fe2 94
Pawel Zarembski 0:01f31e923fe2 95 /*@}*/
Pawel Zarembski 0:01f31e923fe2 96
Pawel Zarembski 0:01f31e923fe2 97
Pawel Zarembski 0:01f31e923fe2 98 #endif /* _SAM3U_PDC_COMPONENT_ */