Thanks for your comments and feedback.
Gadgeteer pins are 0.05" (1,27 mm). One way to interface to 0.1" headers is to use breakout modules (5 for $5 at Mouser). Some third party modules can also help interfacing with breadboards, Arduino shields and other peripherals. Later this year Micromint will also offer other interface module alternatives.
The Bambino 200 and Bambino 200E share the same form factor, 4” x 2.3” (101.6 x 58.4 mm).
Both cores on the LPC4330 can certainly operate simultaneously at 204 MHz. Each core has its own interrupt vector table so ISRs can also be concurrent.
A common way to use asymmetric cores in embedded applications is to partition software tasks between cores. In other words, predetermine which core should do which tasks. In many cases the application requirements are a good starting point to determine the partitioning strategy. For example, on a motor controller the M0 can be designated to handle commands and communications via serial, USB and Ethernet interfaces while the M4 manages real time PWM and analog I/O. The M4 has DSP instructions available so it is a good choice for closed loop control or digital filters. Mailboxes in shared memory can be used when commands and data need to be exchanged between cores.
On the LPC4330 the cores share SRAM and I/O via an internal bus matrix. You can implement logic in your firmware to arbitrate resource access dynamically at runtime, but that requires more overhead so you should do it only when absolutely required. Following the partitioning strategy, it is simpler to designate which core has access to which resources statically (at compile time), e.g. separate memory blocks for each core's program data, set I/O's to be handled by each core, etc. From an mbed application's perspective, one way to think about it is as if you had two microcontrollers each with designated memory and I/O interfaces but with some shared resources like flash, microSD or mailboxes in SRAM.
Good task partitioning and resource arbitration strategies are as important as firmware efficiency in achieving high utilization rates on both cores. Software partitioning in asymmetric cores is much simpler than task scheduling in symmetric cores and does not require an RTOS. Some iteration in task partitioning is usually required during development to optimize core utilization, but most embedded applications do not need to move tasks dynamically from one core to another. In fact, in asymmetric processors this is difficult. In the case of the LPC4330 the M4 and M0 are not 100% binary compatible due to the different ARM architectures (ARMv7-M vs ARMv6-M) and instruction sets, so moving binary code between them would be challenging. If multitasking is required you can still use an RTOS to multiplex tasks within any of the cores.
David Fletcher.
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We at Micromint are excited to announce our Bambino 200 SBC based on the dual-core NXP LPC4330. Thanks to your open sourcing of the mbed SDK, we are supporting mbed development by encapsulating gadgeteer sockets into a class library. mbed applications can run on both cores (a cortex-M4 and a cortex-M0) at up to 204 MHz. For more details please visit the product page.
Production units of the base Bambino 200 will be available on May-31 for under $25 in single quantities. For custom configurations please contact our sales staff. Both hardware and software for the Bambino 200 are licensed as open source. Once boards are shipping we'll contribute the lpc43xx and lpc43xx_m0 ports to the mbed repository.
Thanks,
Jesus Alvarez, Micromint USA