How fast is DMA on the lpc1768 (mbytes/s)? I want to stream digital camera info into memory. I only want a few lines from the camera but would like full 3 bit resolution for each pixel. I'm thinking I need around 60mbits/s. Is this possible?

What interface are you using to connect to the camera? I've used DMA on Serials and SPIs. Even with very high sclk rates on SPI the DMA has had no problem keeping up with the peripheral.

I wanted to use NTSC video output with a high speed adc. I'm looking at around one line in 52microseconds (one line has around 1000pixels). What was the highest clock rate you've used?

I presume your external ADC is therefore going to connect to GPIO pins as a parallel interface with some sort of strobe line?

I'm guessing here, but are you using something like an LM1881 to get the video line timings?

I'm use to PAL with runs at 64uS line timing. Since when did NTSC get 1000pixels per line? PAL has 768pixels per line at high res.

With 3bits per pixel, I assume you just looking for digital data hidden in the first first lines of a broadcast signal, like teletext data?

Anyway, what it boils down to is how is the ADC connected to the Mbed. If it's parallel GPIO with a strobe then I can't see a reason for not being able to read it in. The main point is 1000pixels at 52uS. That's a pixel clk of 52nS (or around 19MHz). Tight fit but maybe possible. I've generally used a fifo being fed from the ADC and using a CPLD/LM1881 to provide the timing in the past. But it's been some time since I worked directly on video signals themselves.

(Edit: actually, the pixel clock will have to be higher. The video line is 52uS but the black/white display data is a subsection of this coming after the front porch and colur burst data. So to get 1000 sample of actual display data means the pixel clk will have to be run faster).

Yep planning on using the lm1881. And the 1000pixels was just an estimate. You are also right about the parallel GPIO. I was only going to take 3 bits because I don't need much precision for each pixel. I'm now also considering an external ram which I can later read, but I would probably still need to change the address on the ram after each adc... Any idea how many cycles it takes to turn an IO pin on and off? Any tother suggestions?

iirc the LM1881 datasheet has circuit samples that show gating the lines on a video signal. Old hat technology but useful. I may have more suggestions if I knew what teh end application was trying to do.

My last experience of frame grabbers used dual port vram and fifo buffers with a cpld and lm1881. But since dram reached speeds where you could interleave the video sampling and cpu access expensive vram seems to have dissapeared. Much like cheap fifo devices that seem to have evaporated since large fpgas can mop them up!

Also, iirc there's projects on here that do the reverse of what you are doing, making a video signal. They aren't what you are doing but may offer insight into managing high speed signals that you can learn from. See for example.