Here's the linker control file used by online IDE (from SVN):
LR_IROM1 0x00000000 0x80000 { ; load region size_region
ER_IROM1 0x00000000 0x80000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x10000000 0x8000 { ; RW data, Application data
.ANY (+RW +ZI)
}
RW_IRAM2 0x2007C000 0x4000 { ; RW data, USB RAM
.ANY (AHBSRAM0)
}
RW_IRAM3 0x20080000 0x4000 { ; RW data, ETH RAM
.ANY (AHBSRAM1)
}
RW_IRAM4 0x40038000 0x0800 { ; RW data, CAN RAM
.ANY (CANRAM)
}
}
As you can see, it places any code or RO data not marked specifically into the 0x00000-0x80000 range, and the RW stuff into IRAM1 (0x10000000-0x10008000). To place things into other ranges, you'll need to declare it as belonging to those sections (AHBSRAM0/1 or CANRAM). To do that, you can use __attribute__((section("name"))) (for variable declarations) or #pragma arm section. I don't know if actual code will execute from there, but I suspect at least the AHBSRAMx will.
See Using Scatter-loading Description Files for more details. The Linker User Guide is also available in PDF.
Hi,
According to LPC17xx user manual the LPC1768 has a total of 64kB of SRAM. I understand that there is a 32kB bank of SRAM connected to the CPU's instruction and data busses, which is readily accessible.
There are two more 16kB banks of SRAM which are stated as typically being used for peripheral data but can supposedly still be used for general purpose instruction and data storage.
However, from what I've searched through on the forums it seems like one can only access 32kB of SRAM. Is it possible to access the other 16kB banks?
Cheers,
Aaron