Yuliya Smirnova / ADE7912

adc

Dependents:   h7adc

ADE7912.cpp@2:f480200c8600, 2020-10-27 (annotated)

Committer:
yuliyasm
Date:
Tue Oct 27 13:23:41 2020 +0000
Revision:
2:f480200c8600
Child:
3:1d62b3be52e8
compile

Who changed what in which revision?

UserRevisionLine numberNew contents of line
yuliyasm 2:f480200c8600 1 #include "ADE7912.h"
yuliyasm 2:f480200c8600 2 #include "communication.h"
yuliyasm 2:f480200c8600 3 #include "stm32h7xx_hal.h"
yuliyasm 2:f480200c8600 4
yuliyasm 2:f480200c8600 5
yuliyasm 2:f480200c8600 6
yuliyasm 2:f480200c8600 7 uint8_t spiPackageTransmited = 0;
yuliyasm 2:f480200c8600 8 uint8_t spiPackageReceived = 0;
yuliyasm 2:f480200c8600 9
yuliyasm 2:f480200c8600 10
yuliyasm 2:f480200c8600 11 void ADE7912_WriteToReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, uint8_t addr, uint8_t *buf, uint8_t length)
yuliyasm 2:f480200c8600 12 {
yuliyasm 2:f480200c8600 13 HAL_GPIO_WritePin(ade->CS_ports[phase], ade->CS_pins[phase], GPIO_PIN_RESET);
yuliyasm 2:f480200c8600 14
yuliyasm 2:f480200c8600 15 uint8_t addrBuf = addr | ADE7912_WRITE_MODE;
yuliyasm 2:f480200c8600 16 WriteToRegisterBySPI(ade->spi, addrBuf, buf, length);
yuliyasm 2:f480200c8600 17
yuliyasm 2:f480200c8600 18 HAL_GPIO_WritePin(ade->CS_ports[phase], ade->CS_pins[phase], GPIO_PIN_SET);
yuliyasm 2:f480200c8600 19 }
yuliyasm 2:f480200c8600 20
yuliyasm 2:f480200c8600 21
yuliyasm 2:f480200c8600 22 void ADE7912_ReadFromReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, uint8_t addr, uint8_t *buf, uint8_t length)
yuliyasm 2:f480200c8600 23 {
yuliyasm 2:f480200c8600 24 HAL_GPIO_WritePin(ade->CS_ports[phase], ade->CS_pins[phase], GPIO_PIN_RESET);
yuliyasm 2:f480200c8600 25
yuliyasm 2:f480200c8600 26 uint8_t addrBuf = addr | ADE7912_READ_MODE;
yuliyasm 2:f480200c8600 27 ReadFromRegisterBySPI(ade->spi, addrBuf, buf, length);
yuliyasm 2:f480200c8600 28
yuliyasm 2:f480200c8600 29 HAL_GPIO_WritePin(ade->CS_ports[phase], ade->CS_pins[phase], GPIO_PIN_SET);
yuliyasm 2:f480200c8600 30 }
yuliyasm 2:f480200c8600 31
yuliyasm 2:f480200c8600 32
yuliyasm 2:f480200c8600 33
yuliyasm 2:f480200c8600 34 //void ADE7912_InitEXTIForDReady(struct ADE7912_Inst *ade, GPIO_TypeDef *port, uint16_t pin)
yuliyasm 2:f480200c8600 35 //{
yuliyasm 2:f480200c8600 36 // ade->DReadyPort = port;
yuliyasm 2:f480200c8600 37 // ade->DReadyPin = pin;
yuliyasm 2:f480200c8600 38 //
yuliyasm 2:f480200c8600 39 // switch (pin)
yuliyasm 2:f480200c8600 40 // {
yuliyasm 2:f480200c8600 41 // case GPIO_PIN_0:
yuliyasm 2:f480200c8600 42 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 43 // break;
yuliyasm 2:f480200c8600 44 // case GPIO_PIN_1:
yuliyasm 2:f480200c8600 45 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 46 // break;
yuliyasm 2:f480200c8600 47 // case GPIO_PIN_2:
yuliyasm 2:f480200c8600 48 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 49 // break;
yuliyasm 2:f480200c8600 50 // case GPIO_PIN_3:
yuliyasm 2:f480200c8600 51 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 52 // break;
yuliyasm 2:f480200c8600 53 // case GPIO_PIN_4:
yuliyasm 2:f480200c8600 54 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 55 // break;
yuliyasm 2:f480200c8600 56 // case GPIO_PIN_5:
yuliyasm 2:f480200c8600 57 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 58 // break;
yuliyasm 2:f480200c8600 59 // case GPIO_PIN_6:
yuliyasm 2:f480200c8600 60 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 61 // break;
yuliyasm 2:f480200c8600 62 // case GPIO_PIN_7:
yuliyasm 2:f480200c8600 63 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 64 // break;
yuliyasm 2:f480200c8600 65 // case GPIO_PIN_8:
yuliyasm 2:f480200c8600 66 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 67 // break;
yuliyasm 2:f480200c8600 68 // case GPIO_PIN_9:
yuliyasm 2:f480200c8600 69 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 70 // break;
yuliyasm 2:f480200c8600 71 // case GPIO_PIN_10:
yuliyasm 2:f480200c8600 72 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 73 // break;
yuliyasm 2:f480200c8600 74 // case GPIO_PIN_11:
yuliyasm 2:f480200c8600 75 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 76 // break;
yuliyasm 2:f480200c8600 77 // case GPIO_PIN_12:
yuliyasm 2:f480200c8600 78 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 79 // break;
yuliyasm 2:f480200c8600 80 // case GPIO_PIN_13:
yuliyasm 2:f480200c8600 81 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 82 // break;
yuliyasm 2:f480200c8600 83 // case GPIO_PIN_14:
yuliyasm 2:f480200c8600 84 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 85 // break;
yuliyasm 2:f480200c8600 86 // case GPIO_PIN_15:
yuliyasm 2:f480200c8600 87 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 88 // break;
yuliyasm 2:f480200c8600 89 // }
yuliyasm 2:f480200c8600 90 //
yuliyasm 2:f480200c8600 91 // GPIO_InitTypeDef GPIO_InitStruct = {0};
yuliyasm 2:f480200c8600 92
yuliyasm 2:f480200c8600 93 // /* GPIO Ports Clock Enable */
yuliyasm 2:f480200c8600 94 // __HAL_RCC_GPIOA_CLK_ENABLE();
yuliyasm 2:f480200c8600 95
yuliyasm 2:f480200c8600 96 // /*Configure GPIO pin : PA11 */
yuliyasm 2:f480200c8600 97 // GPIO_InitStruct.Pin = pin;
yuliyasm 2:f480200c8600 98 // GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
yuliyasm 2:f480200c8600 99 // GPIO_InitStruct.Pull = GPIO_NOPULL;
yuliyasm 2:f480200c8600 100 // HAL_GPIO_Init(port, &GPIO_InitStruct);
yuliyasm 2:f480200c8600 101
yuliyasm 2:f480200c8600 102 // /* EXTI interrupt init*/
yuliyasm 2:f480200c8600 103 //
yuliyasm 2:f480200c8600 104 //
yuliyasm 2:f480200c8600 105 //
yuliyasm 2:f480200c8600 106 //
yuliyasm 2:f480200c8600 107 // HAL_NVIC_SetPriority(EXTIinterrupt, 0, 0);
yuliyasm 2:f480200c8600 108 // HAL_NVIC_EnableIRQ(EXTIinterrupt);
yuliyasm 2:f480200c8600 109 //}
yuliyasm 2:f480200c8600 110
yuliyasm 2:f480200c8600 111
yuliyasm 2:f480200c8600 112 struct ADE7912_Inst* New_ADE7912(SPI_HandleTypeDef *spi)
yuliyasm 2:f480200c8600 113 {
yuliyasm 2:f480200c8600 114 struct ADE7912_Inst *ade = (struct ADE7912_Inst *)malloc(sizeof(struct ADE7912_Inst));
yuliyasm 2:f480200c8600 115 ade->spi = spi;
yuliyasm 2:f480200c8600 116 for(int phase = 0; phase < 4; phase += 1) {
yuliyasm 2:f480200c8600 117 ade->CS_pins[phase] = NULL;
yuliyasm 2:f480200c8600 118 ade->CS_ports[phase] = GPIOA;
yuliyasm 2:f480200c8600 119 ade->phasesData[phase] = NULL;
yuliyasm 2:f480200c8600 120 ade->phasesEnable[phase] = 0;
yuliyasm 2:f480200c8600 121 }
yuliyasm 2:f480200c8600 122 return ade;
yuliyasm 2:f480200c8600 123 }
yuliyasm 2:f480200c8600 124
yuliyasm 2:f480200c8600 125
yuliyasm 2:f480200c8600 126
yuliyasm 2:f480200c8600 127 void ADE7912_PhaseInit(struct ADE7912_Inst *ade, struct ADE7912_Phase_Settings *settings, enum ADE7912_Phases phase)
yuliyasm 2:f480200c8600 128 {
yuliyasm 2:f480200c8600 129 ade->CS_ports[phase] = settings->CS_port;
yuliyasm 2:f480200c8600 130 ade->CS_pins[phase] = settings->CS_pin;
yuliyasm 2:f480200c8600 131
yuliyasm 2:f480200c8600 132 ade->phasesData[phase] = (struct ADE7912_BrushRead_Data *)malloc(sizeof(struct ADE7912_BrushRead_Data));
yuliyasm 2:f480200c8600 133 ade->phasesData[phase]->V1WV = 0;
yuliyasm 2:f480200c8600 134 ade->phasesData[phase]->V2WV = 0;
yuliyasm 2:f480200c8600 135 ade->phasesData[phase]->IWV = 0;
yuliyasm 2:f480200c8600 136 ade->phasesData[phase]->ADC_CRC = 0;
yuliyasm 2:f480200c8600 137 ade->phasesData[phase]->STATUS0 = 0;
yuliyasm 2:f480200c8600 138 ade->phasesData[phase]->CNT_SNAPSHOT = 0;
yuliyasm 2:f480200c8600 139
yuliyasm 2:f480200c8600 140 ADE7912_ResetPhase(ade, phase);
yuliyasm 2:f480200c8600 141
yuliyasm 2:f480200c8600 142 ade->version[phase] = ADE7912_ReadADCVersionFromReg(ade, phase);
yuliyasm 2:f480200c8600 143
yuliyasm 2:f480200c8600 144 ADE7912_SetDataUpdateFreq(ade, phase, settings->freq);
yuliyasm 2:f480200c8600 145
yuliyasm 2:f480200c8600 146 ADE7912_SetPwrConverterEnabled(ade, phase, 1);
yuliyasm 2:f480200c8600 147
yuliyasm 2:f480200c8600 148 ADE7912_SetTempEnabled(ade, phase, 0);
yuliyasm 2:f480200c8600 149
yuliyasm 2:f480200c8600 150 ADE7912_SetBandwidth(ade, phase, settings->bandwidth);
yuliyasm 2:f480200c8600 151
yuliyasm 2:f480200c8600 152 ade->tempGain[phase] = settings->bandwidth == BW_3K3HZ ? ADE7912_TEMPGAIN_WITH_3K3_BW : ADE7912_TEMPGAIN_WITH_2K_BW;
yuliyasm 2:f480200c8600 153
yuliyasm 2:f480200c8600 154 ADE7912_SetCLKOUTFunctionality(ade, phase, settings->clkoutFunc);
yuliyasm 2:f480200c8600 155
yuliyasm 2:f480200c8600 156 uint32_t tmp;
yuliyasm 2:f480200c8600 157 tmp = ADE7912_ReadTemposFromReg(ade, phase) << 11;
yuliyasm 2:f480200c8600 158 //if (tmp & 0x00040000) tmp = ~(~(tmp - 1) | 0x0007FFFF) + 1;
yuliyasm 2:f480200c8600 159 ade->tempos[phase] = ADE7912_TEMPGAIN_WITH_3K3_BW * (float)tmp;
yuliyasm 2:f480200c8600 160
yuliyasm 2:f480200c8600 161 ADE7912_EnablePhase(ade, phase);
yuliyasm 2:f480200c8600 162
yuliyasm 2:f480200c8600 163 }
yuliyasm 2:f480200c8600 164
yuliyasm 2:f480200c8600 165
yuliyasm 2:f480200c8600 166
yuliyasm 2:f480200c8600 167 void ADE7912_EnablePhase(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
yuliyasm 2:f480200c8600 168 {
yuliyasm 2:f480200c8600 169 ade->phasesEnable[phase] = 1;
yuliyasm 2:f480200c8600 170 }
yuliyasm 2:f480200c8600 171
yuliyasm 2:f480200c8600 172
yuliyasm 2:f480200c8600 173
yuliyasm 2:f480200c8600 174 void ADE7912_DisablePhase(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
yuliyasm 2:f480200c8600 175 {
yuliyasm 2:f480200c8600 176 ade->phasesEnable[phase] = 0;
yuliyasm 2:f480200c8600 177 }
yuliyasm 2:f480200c8600 178
yuliyasm 2:f480200c8600 179 void ADE7912_ResetPhase(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
yuliyasm 2:f480200c8600 180 {
yuliyasm 2:f480200c8600 181 // Software reset start
yuliyasm 2:f480200c8600 182 uint8_t buf;
yuliyasm 2:f480200c8600 183 ADE7912_ReadFromReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
yuliyasm 2:f480200c8600 184
yuliyasm 2:f480200c8600 185 buf |= ADE7912_CONFIG_BIT_SWRST;
yuliyasm 2:f480200c8600 186 ADE7912_WriteToReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
yuliyasm 2:f480200c8600 187
yuliyasm 2:f480200c8600 188 // Wait for reset finished
yuliyasm 2:f480200c8600 189 while (1) {
yuliyasm 2:f480200c8600 190 uint8_t buf;
yuliyasm 2:f480200c8600 191 ADE7912_ReadFromReg(ade, phase, ADE7912_STATUS0_REG_ADDRESS, &buf, 1);
yuliyasm 2:f480200c8600 192
yuliyasm 2:f480200c8600 193 if (~buf & ADE7912_STATUS0_BIT_RESET_ON) break;
yuliyasm 2:f480200c8600 194 }
yuliyasm 2:f480200c8600 195 }
yuliyasm 2:f480200c8600 196
yuliyasm 2:f480200c8600 197
yuliyasm 2:f480200c8600 198
yuliyasm 2:f480200c8600 199 void ADE7912_UpdateData(struct ADE7912_Inst *ade)
yuliyasm 2:f480200c8600 200 {
yuliyasm 2:f480200c8600 201 uint8_t buf[14];
yuliyasm 2:f480200c8600 202
yuliyasm 2:f480200c8600 203 for(int phase = 0; phase < 4; phase += 1) {
yuliyasm 2:f480200c8600 204 if (ade->phasesEnable[phase]) {
yuliyasm 2:f480200c8600 205 ADE7912_ReadFromReg(ade, static_cast<ADE7912_Phases>(phase), ADE7912_BRUSH_READ_MODE, buf, 14);
yuliyasm 2:f480200c8600 206
yuliyasm 2:f480200c8600 207 uint32_t tmp;
yuliyasm 2:f480200c8600 208
yuliyasm 2:f480200c8600 209 tmp = (buf[0] << 16) | (buf[1] << 8) | buf[2];
yuliyasm 2:f480200c8600 210 if (tmp > 0x007FFFFF) tmp |= 0xFF000000;
yuliyasm 2:f480200c8600 211 ade->phasesData[phase]->IWV = (int32_t)tmp;
yuliyasm 2:f480200c8600 212
yuliyasm 2:f480200c8600 213 tmp = (buf[3] << 16) | (buf[4] << 8) | buf[5];
yuliyasm 2:f480200c8600 214 if (tmp > 0x007FFFFF) tmp |= 0xFF000000;
yuliyasm 2:f480200c8600 215 ade->phasesData[phase]->V1WV = (int32_t)tmp;
yuliyasm 2:f480200c8600 216
yuliyasm 2:f480200c8600 217 tmp = (buf[6] << 16) | (buf[7] << 8) | buf[8];
yuliyasm 2:f480200c8600 218 if (tmp > 0x007FFFFF) tmp |= 0xFF000000;
yuliyasm 2:f480200c8600 219 ade->phasesData[phase]->V2WV = (int32_t)tmp;
yuliyasm 2:f480200c8600 220
yuliyasm 2:f480200c8600 221 ade->phasesData[phase]->ADC_CRC = (buf[9] << 8) | buf[10];
yuliyasm 2:f480200c8600 222 ade->phasesData[phase]->STATUS0 = buf[11];
yuliyasm 2:f480200c8600 223 ade->phasesData[phase]->CNT_SNAPSHOT = (buf[12] << 8) | buf[13];
yuliyasm 2:f480200c8600 224 }
yuliyasm 2:f480200c8600 225 }
yuliyasm 2:f480200c8600 226 }
yuliyasm 2:f480200c8600 227
yuliyasm 2:f480200c8600 228
yuliyasm 2:f480200c8600 229
yuliyasm 2:f480200c8600 230 int ADE7912_BrrushReadData(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, struct ADE7912_BrushRead_Data *data)
yuliyasm 2:f480200c8600 231 {
yuliyasm 2:f480200c8600 232 if (ade->phasesEnable[phase]) {
yuliyasm 2:f480200c8600 233 data->IWV = ade->phasesData[phase]->IWV;
yuliyasm 2:f480200c8600 234 data->V1WV = ade->phasesData[phase]->V1WV;
yuliyasm 2:f480200c8600 235 data->V2WV = ade->phasesData[phase]->V2WV;
yuliyasm 2:f480200c8600 236 data->ADC_CRC = ade->phasesData[phase]->ADC_CRC;
yuliyasm 2:f480200c8600 237 data->STATUS0 = ade->phasesData[phase]->STATUS0;
yuliyasm 2:f480200c8600 238 data->CNT_SNAPSHOT = ade->phasesData[phase]->CNT_SNAPSHOT;
yuliyasm 2:f480200c8600 239
yuliyasm 2:f480200c8600 240 return 0;
yuliyasm 2:f480200c8600 241 } else return 1;
yuliyasm 2:f480200c8600 242 }
yuliyasm 2:f480200c8600 243
yuliyasm 2:f480200c8600 244
yuliyasm 2:f480200c8600 245
yuliyasm 2:f480200c8600 246 void ADE7912_SetDataUpdateFreq(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, enum ADE7912_DataUpdateFreq freq)
yuliyasm 2:f480200c8600 247 {
yuliyasm 2:f480200c8600 248
yuliyasm 2:f480200c8600 249 uint8_t buf;
yuliyasm 2:f480200c8600 250 ADE7912_ReadFromReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
yuliyasm 2:f480200c8600 251
yuliyasm 2:f480200c8600 252 HAL_Delay(1);
yuliyasm 2:f480200c8600 253
yuliyasm 2:f480200c8600 254 buf &= (uint8_t)~ADE7912_CONFIG_ADC_FREQ;
yuliyasm 2:f480200c8600 255 switch(freq) {
yuliyasm 2:f480200c8600 256 case F_8KHZ:
yuliyasm 2:f480200c8600 257 buf |= ADE7912_CONFIG_ADC_FREQ_8K;
yuliyasm 2:f480200c8600 258 break;
yuliyasm 2:f480200c8600 259 case F_4KHZ:
yuliyasm 2:f480200c8600 260 buf |= ADE7912_CONFIG_ADC_FREQ_4K;
yuliyasm 2:f480200c8600 261 break;
yuliyasm 2:f480200c8600 262 case F_2KHZ:
yuliyasm 2:f480200c8600 263 buf |= ADE7912_CONFIG_ADC_FREQ_2K;
yuliyasm 2:f480200c8600 264 break;
yuliyasm 2:f480200c8600 265 case F_1KHZ:
yuliyasm 2:f480200c8600 266 buf |= ADE7912_CONFIG_ADC_FREQ_1K;
yuliyasm 2:f480200c8600 267 break;
yuliyasm 2:f480200c8600 268 }
yuliyasm 2:f480200c8600 269 ADE7912_WriteToReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
yuliyasm 2:f480200c8600 270 }
yuliyasm 2:f480200c8600 271
yuliyasm 2:f480200c8600 272
yuliyasm 2:f480200c8600 273
yuliyasm 2:f480200c8600 274 uint8_t ADE7912_ReadADCVersionFromReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
yuliyasm 2:f480200c8600 275 {
yuliyasm 2:f480200c8600 276 uint8_t buf;
yuliyasm 2:f480200c8600 277 ADE7912_ReadFromReg(ade, phase, ADE7912_STATUS1_REG_ADDRESS, &buf, 1);
yuliyasm 2:f480200c8600 278
yuliyasm 2:f480200c8600 279 return buf & ADE7912_STATUS1_BIT_VERSION;
yuliyasm 2:f480200c8600 280 }
yuliyasm 2:f480200c8600 281
yuliyasm 2:f480200c8600 282
yuliyasm 2:f480200c8600 283
yuliyasm 2:f480200c8600 284 uint8_t ADE7912_ReadTemposFromReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
yuliyasm 2:f480200c8600 285 {
yuliyasm 2:f480200c8600 286 uint8_t buf;
yuliyasm 2:f480200c8600 287 ADE7912_ReadFromReg(ade, phase, ADE7912_TEMPOS_REG_ADDRESS, &buf, 1);
yuliyasm 2:f480200c8600 288
yuliyasm 2:f480200c8600 289 return buf;
yuliyasm 2:f480200c8600 290 }
yuliyasm 2:f480200c8600 291
yuliyasm 2:f480200c8600 292
yuliyasm 2:f480200c8600 293
yuliyasm 2:f480200c8600 294 void ADE7912_SetPwrConverterEnabled(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, bool enabled)
yuliyasm 2:f480200c8600 295 {
yuliyasm 2:f480200c8600 296 uint8_t buf;
yuliyasm 2:f480200c8600 297 ADE7912_ReadFromReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
yuliyasm 2:f480200c8600 298
yuliyasm 2:f480200c8600 299 HAL_Delay(1);
yuliyasm 2:f480200c8600 300
yuliyasm 2:f480200c8600 301 buf &= (uint8_t)~ADE7912_CONFIG_BIT_PWRDWNENB;
yuliyasm 2:f480200c8600 302 buf |= enabled ? ADE7912_CONFIG_BIT_PWRDWNENB : 0;
yuliyasm 2:f480200c8600 303 ADE7912_WriteToReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
yuliyasm 2:f480200c8600 304 }
yuliyasm 2:f480200c8600 305
yuliyasm 2:f480200c8600 306
yuliyasm 2:f480200c8600 307
yuliyasm 2:f480200c8600 308 void ADE7912_SetTempEnabled(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, bool enabled)
yuliyasm 2:f480200c8600 309 {
yuliyasm 2:f480200c8600 310 uint8_t buf;
yuliyasm 2:f480200c8600 311 ADE7912_ReadFromReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
yuliyasm 2:f480200c8600 312
yuliyasm 2:f480200c8600 313 HAL_Delay(1);
yuliyasm 2:f480200c8600 314
yuliyasm 2:f480200c8600 315 buf &= (uint8_t)~ADE7912_CONFIG_BIT_TEMPENB;
yuliyasm 2:f480200c8600 316 buf |= enabled ? ADE7912_CONFIG_BIT_TEMPENB : 0;
yuliyasm 2:f480200c8600 317 ADE7912_WriteToReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
yuliyasm 2:f480200c8600 318 }
yuliyasm 2:f480200c8600 319
yuliyasm 2:f480200c8600 320
yuliyasm 2:f480200c8600 321
yuliyasm 2:f480200c8600 322 void ADE7912_SetBandwidth(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, enum ADE7912_Bandwidths bandwidth)
yuliyasm 2:f480200c8600 323 {
yuliyasm 2:f480200c8600 324 uint8_t buf;
yuliyasm 2:f480200c8600 325 ADE7912_ReadFromReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
yuliyasm 2:f480200c8600 326
yuliyasm 2:f480200c8600 327 HAL_Delay(1);
yuliyasm 2:f480200c8600 328
yuliyasm 2:f480200c8600 329 buf &= (uint8_t)~ADE7912_CONFIG_BIT_BW;
yuliyasm 2:f480200c8600 330 switch(bandwidth) {
yuliyasm 2:f480200c8600 331 case BW_3K3HZ:
yuliyasm 2:f480200c8600 332 buf |= 0;
yuliyasm 2:f480200c8600 333 break;
yuliyasm 2:f480200c8600 334 case BW_2KHZ:
yuliyasm 2:f480200c8600 335 buf |= ADE7912_CONFIG_BIT_BW;
yuliyasm 2:f480200c8600 336 break;
yuliyasm 2:f480200c8600 337 }
yuliyasm 2:f480200c8600 338 ADE7912_WriteToReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
yuliyasm 2:f480200c8600 339 }
yuliyasm 2:f480200c8600 340
yuliyasm 2:f480200c8600 341
yuliyasm 2:f480200c8600 342
yuliyasm 2:f480200c8600 343 void ADE7912_LockConfigurationRegisters(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
yuliyasm 2:f480200c8600 344 {
yuliyasm 2:f480200c8600 345 uint8_t buf = 0xCA;
yuliyasm 2:f480200c8600 346 ADE7912_WriteToReg(ade, phase, ADE7912_LOCK_REG_ADDRESS, &buf, 1);
yuliyasm 2:f480200c8600 347 }
yuliyasm 2:f480200c8600 348
yuliyasm 2:f480200c8600 349
yuliyasm 2:f480200c8600 350
yuliyasm 2:f480200c8600 351 void ADE7912_UnlockConfigurationRegisters(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
yuliyasm 2:f480200c8600 352 {
yuliyasm 2:f480200c8600 353 uint8_t buf = 0x9C;
yuliyasm 2:f480200c8600 354 ADE7912_WriteToReg(ade, phase, ADE7912_LOCK_REG_ADDRESS, &buf, 1);
yuliyasm 2:f480200c8600 355 }
yuliyasm 2:f480200c8600 356
yuliyasm 2:f480200c8600 357
yuliyasm 2:f480200c8600 358
yuliyasm 2:f480200c8600 359 void ADE7912_SetCLKOUTFunctionality(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, enum ADE7912_CLKOUT_Functionality functionality)
yuliyasm 2:f480200c8600 360 {
yuliyasm 2:f480200c8600 361 uint8_t buf;
yuliyasm 2:f480200c8600 362 ADE7912_ReadFromReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
yuliyasm 2:f480200c8600 363
yuliyasm 2:f480200c8600 364 HAL_Delay(1);
yuliyasm 2:f480200c8600 365
yuliyasm 2:f480200c8600 366 buf &= (uint8_t)~ADE7912_CONFIG_BIT_CLKOUTENB;
yuliyasm 2:f480200c8600 367 switch(functionality) {
yuliyasm 2:f480200c8600 368 case CLKOUT:
yuliyasm 2:f480200c8600 369 buf |= ADE7912_CONFIG_BIT_CLKOUTENB;
yuliyasm 2:f480200c8600 370 break;
yuliyasm 2:f480200c8600 371 case DREADY:
yuliyasm 2:f480200c8600 372 buf |= 0;
yuliyasm 2:f480200c8600 373 break;
yuliyasm 2:f480200c8600 374 }
yuliyasm 2:f480200c8600 375 ADE7912_WriteToReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
yuliyasm 2:f480200c8600 376 }
yuliyasm 2:f480200c8600 377
yuliyasm 2:f480200c8600 378
yuliyasm 2:f480200c8600 379
yuliyasm 2:f480200c8600 380 uint8_t ADE7912_GetADCVersion(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
yuliyasm 2:f480200c8600 381 {
yuliyasm 2:f480200c8600 382 return ade->version[phase];
yuliyasm 2:f480200c8600 383 }
yuliyasm 2:f480200c8600 384
yuliyasm 2:f480200c8600 385
yuliyasm 2:f480200c8600 386
yuliyasm 2:f480200c8600 387 float ADE7912_GetVoltage(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
yuliyasm 2:f480200c8600 388 {
yuliyasm 2:f480200c8600 389 if (ade->phasesEnable[phase] == 1) {
yuliyasm 2:f480200c8600 390 return ade->phasesData[phase]->V1WV * ADE7912_VWV_TRANSLATE_COEF;
yuliyasm 2:f480200c8600 391 } else {
yuliyasm 2:f480200c8600 392 return 0;
yuliyasm 2:f480200c8600 393 }
yuliyasm 2:f480200c8600 394 }
yuliyasm 2:f480200c8600 395
yuliyasm 2:f480200c8600 396
yuliyasm 2:f480200c8600 397
yuliyasm 2:f480200c8600 398 float ADE7912_GetCurrent(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
yuliyasm 2:f480200c8600 399 {
yuliyasm 2:f480200c8600 400 if (ade->phasesEnable[phase] == 1) {
yuliyasm 2:f480200c8600 401 return ade->phasesData[phase]->IWV * ADE7912_IWV_TRANSLATE_COEF;
yuliyasm 2:f480200c8600 402 } else {
yuliyasm 2:f480200c8600 403 return 0;
yuliyasm 2:f480200c8600 404 }
yuliyasm 2:f480200c8600 405 }
yuliyasm 2:f480200c8600 406
yuliyasm 2:f480200c8600 407
yuliyasm 2:f480200c8600 408
yuliyasm 2:f480200c8600 409 float ADE7912_GetTemp(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
yuliyasm 2:f480200c8600 410 {
yuliyasm 2:f480200c8600 411 if (ade->phasesEnable[phase] == 1) {
yuliyasm 2:f480200c8600 412 return ade->tempGain[phase] * (float)ade->phasesData[phase]->V2WV - ade->tempos[phase] - ADE7912_CONST_TEMPOS;
yuliyasm 2:f480200c8600 413 } else {
yuliyasm 2:f480200c8600 414 return 0;
yuliyasm 2:f480200c8600 415 }
yuliyasm 2:f480200c8600 416 }
yuliyasm 2:f480200c8600 417
yuliyasm 2:f480200c8600 418
yuliyasm 2:f480200c8600 419