Yuliya Smirnova / ADE7912

adc

Dependents:   h7adc

ADE7912.h@0:e5d06036dd60, 2020-10-21 (annotated)

Committer:
yuliyasm
Date:
Wed Oct 21 20:45:11 2020 +0000
Revision:
0:e5d06036dd60
Child:
1:5796bdddf29c
beta

Who changed what in which revision?

UserRevisionLine numberNew contents of line
yuliyasm 0:e5d06036dd60 1 #ifndef ADE7912
yuliyasm 0:e5d06036dd60 2 #define ADE7912
yuliyasm 0:e5d06036dd60 3
yuliyasm 0:e5d06036dd60 4 #include "stm32h7xx_hal.h"
yuliyasm 0:e5d06036dd60 5 #include "stdlib.h"
yuliyasm 0:e5d06036dd60 6
yuliyasm 0:e5d06036dd60 7 // ADE7912 registers addresses
yuliyasm 0:e5d06036dd60 8 #define ADE7912_IWV_REG_ADDRESS 0x00
yuliyasm 0:e5d06036dd60 9 #define ADE7912_V1WV_REG_ADDRESS 0x08
yuliyasm 0:e5d06036dd60 10 #define ADE7912_V2WV_REG_ADDRESS 0x10
yuliyasm 0:e5d06036dd60 11 #define ADE7912_ADC_CRC_REG_ADDRESS 0x20
yuliyasm 0:e5d06036dd60 12 #define ADE7912_CTRL_CRC_REG_ADDRESS 0x28
yuliyasm 0:e5d06036dd60 13 #define ADE7912_CNT_SNAPSHOT_REG_ADDRESS 0x38
yuliyasm 0:e5d06036dd60 14 #define ADE7912_CONFIG_REG_ADDRESS 0x40
yuliyasm 0:e5d06036dd60 15 #define ADE7912_STATUS0_REG_ADDRESS 0x48
yuliyasm 0:e5d06036dd60 16 #define ADE7912_LOCK_REG_ADDRESS 0x50
yuliyasm 0:e5d06036dd60 17 #define ADE7912_SYNC_SNAP_REG_ADDRESS 0x58
yuliyasm 0:e5d06036dd60 18 #define ADE7912_COUNTER0_REG_ADDRESS 0x60
yuliyasm 0:e5d06036dd60 19 #define ADE7912_COUNTER1_REG_ADDRESS 0x68
yuliyasm 0:e5d06036dd60 20 #define ADE7912_EMI_CTRL_REG_ADDRESS 0x70
yuliyasm 0:e5d06036dd60 21 #define ADE7912_STATUS1_REG_ADDRESS 0x78
yuliyasm 0:e5d06036dd60 22 #define ADE7912_TEMPOS_REG_ADDRESS 0xC0
yuliyasm 0:e5d06036dd60 23
yuliyasm 0:e5d06036dd60 24 // ADE7912 bits of CONFIG register
yuliyasm 0:e5d06036dd60 25 #define ADE7912_CONFIG_BIT_CLKOUTENB 1 << 0
yuliyasm 0:e5d06036dd60 26 #define ADE7912_CONFIG_BIT_PWRDWNENB 1 << 1
yuliyasm 0:e5d06036dd60 27 #define ADE7912_CONFIG_BIT_TEMPENB 1 << 3
yuliyasm 0:e5d06036dd60 28 #define ADE7912_CONFIG_ADC_FREQ_1K 0x0 << 4
yuliyasm 0:e5d06036dd60 29 #define ADE7912_CONFIG_ADC_FREQ_2K 0x1 << 4
yuliyasm 0:e5d06036dd60 30 #define ADE7912_CONFIG_ADC_FREQ_4K 0x2 << 4
yuliyasm 0:e5d06036dd60 31 #define ADE7912_CONFIG_ADC_FREQ_8K 0x3 << 4
yuliyasm 0:e5d06036dd60 32 #define ADE7912_CONFIG_ADC_FREQ ADE7912_CONFIG_ADC_FREQ_8K
yuliyasm 0:e5d06036dd60 33 #define ADE7912_CONFIG_BIT_SWRST 1 << 6
yuliyasm 0:e5d06036dd60 34 #define ADE7912_CONFIG_BIT_BW 1 << 6
yuliyasm 0:e5d06036dd60 35
yuliyasm 0:e5d06036dd60 36 // ADE7912 bits of STATUS0 register
yuliyasm 0:e5d06036dd60 37 #define ADE7912_STATUS0_BIT_RESET_ON 1 << 0
yuliyasm 0:e5d06036dd60 38 #define ADE7912_STATUS0_BIT_CRC_STAT 1 << 1
yuliyasm 0:e5d06036dd60 39 #define ADE7912_STATUS0_BIT_IC_PROT 1 << 2
yuliyasm 0:e5d06036dd60 40
yuliyasm 0:e5d06036dd60 41 // ADE7912 bits of STATUS1 register
yuliyasm 0:e5d06036dd60 42 #define ADE7912_STATUS1_BIT_VERSION 0x7 << 0
yuliyasm 0:e5d06036dd60 43 #define ADE7912_STATUS1_BIT_ADC_NA 1 << 3
yuliyasm 0:e5d06036dd60 44
yuliyasm 0:e5d06036dd60 45 // ADE7912 transmite modes
yuliyasm 0:e5d06036dd60 46 #define ADE7912_READ_MODE 0x04
yuliyasm 0:e5d06036dd60 47 #define ADE7912_BRUSH_READ_MODE 0x04
yuliyasm 0:e5d06036dd60 48 #define ADE7912_WRITE_MODE 0x00
yuliyasm 0:e5d06036dd60 49
yuliyasm 0:e5d06036dd60 50 #define ADE7912_DALAY_TIME 2
yuliyasm 0:e5d06036dd60 51 #define ADE7912_WAITING_TIME 5 * ADE7912_DALAY_TIME
yuliyasm 0:e5d06036dd60 52
yuliyasm 0:e5d06036dd60 53 struct ADE7912_BrushRead_Data
yuliyasm 0:e5d06036dd60 54 {
yuliyasm 0:e5d06036dd60 55 int32_t IWV;
yuliyasm 0:e5d06036dd60 56 int32_t V1WV;
yuliyasm 0:e5d06036dd60 57 int32_t V2WV;
yuliyasm 0:e5d06036dd60 58 uint16_t ADC_CRC;
yuliyasm 0:e5d06036dd60 59 uint8_t STATUS0;
yuliyasm 0:e5d06036dd60 60 uint16_t CNT_SNAPSHOT;
yuliyasm 0:e5d06036dd60 61 };
yuliyasm 0:e5d06036dd60 62
yuliyasm 0:e5d06036dd60 63 struct ADE7912_Inst
yuliyasm 0:e5d06036dd60 64 {
yuliyasm 0:e5d06036dd60 65 SPI_HandleTypeDef *spi;
yuliyasm 0:e5d06036dd60 66 uint8_t phasesEnable[4];
yuliyasm 0:e5d06036dd60 67 GPIO_TypeDef *CS_ports[4];
yuliyasm 0:e5d06036dd60 68 uint16_t CS_pins[4];
yuliyasm 0:e5d06036dd60 69 struct ADE7912_BrushRead_Data *phasesData[4];
yuliyasm 0:e5d06036dd60 70 uint8_t version[4];
yuliyasm 0:e5d06036dd60 71 };
yuliyasm 0:e5d06036dd60 72
yuliyasm 0:e5d06036dd60 73
yuliyasm 0:e5d06036dd60 74
yuliyasm 0:e5d06036dd60 75 enum ADE7912_Phases
yuliyasm 0:e5d06036dd60 76 {
yuliyasm 0:e5d06036dd60 77 PHASE_A = 0,
yuliyasm 0:e5d06036dd60 78 PHASE_B,
yuliyasm 0:e5d06036dd60 79 PHASE_C,
yuliyasm 0:e5d06036dd60 80 COM
yuliyasm 0:e5d06036dd60 81 };
yuliyasm 0:e5d06036dd60 82
yuliyasm 0:e5d06036dd60 83 enum ADE7912_DataUpdateFreq
yuliyasm 0:e5d06036dd60 84 {
yuliyasm 0:e5d06036dd60 85 F_8KHZ,
yuliyasm 0:e5d06036dd60 86 F_4KHZ,
yuliyasm 0:e5d06036dd60 87 F_2KHZ,
yuliyasm 0:e5d06036dd60 88 F_1KHZ
yuliyasm 0:e5d06036dd60 89 };
yuliyasm 0:e5d06036dd60 90
yuliyasm 0:e5d06036dd60 91 enum ADE7912_Bandwidths
yuliyasm 0:e5d06036dd60 92 {
yuliyasm 0:e5d06036dd60 93 BW_3K3HZ,
yuliyasm 0:e5d06036dd60 94 BW_2KHZ
yuliyasm 0:e5d06036dd60 95 };
yuliyasm 0:e5d06036dd60 96
yuliyasm 0:e5d06036dd60 97 enum ADE7912_CLKOUT_Functionality
yuliyasm 0:e5d06036dd60 98 {
yuliyasm 0:e5d06036dd60 99 CLKOUT,
yuliyasm 0:e5d06036dd60 100 DREADY
yuliyasm 0:e5d06036dd60 101 };
yuliyasm 0:e5d06036dd60 102
yuliyasm 0:e5d06036dd60 103 struct ADE7912_Phase_Settings
yuliyasm 0:e5d06036dd60 104 {
yuliyasm 0:e5d06036dd60 105 GPIO_TypeDef *CS_port;
yuliyasm 0:e5d06036dd60 106 uint16_t CS_pin;
yuliyasm 0:e5d06036dd60 107 enum ADE7912_DataUpdateFreq freq;
yuliyasm 0:e5d06036dd60 108 enum ADE7912_Bandwidths bandwidth;
yuliyasm 0:e5d06036dd60 109 };
yuliyasm 0:e5d06036dd60 110
yuliyasm 0:e5d06036dd60 111 void ADE7912_WriteToReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, uint8_t addr, uint8_t *buf, uint8_t length);
yuliyasm 0:e5d06036dd60 112 void ADE7912_ReadFromReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, uint8_t addr, uint8_t *buf, uint8_t length);
yuliyasm 0:e5d06036dd60 113
yuliyasm 0:e5d06036dd60 114 void ADE7912_UpdateData(struct ADE7912_Inst *ade);
yuliyasm 0:e5d06036dd60 115 int ADE7912_GetPhaseData(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, struct ADE7912_BrushRead_Data *data);
yuliyasm 0:e5d06036dd60 116
yuliyasm 0:e5d06036dd60 117 struct ADE7912_Inst* New_ADE7912(SPI_HandleTypeDef *spi);
yuliyasm 0:e5d06036dd60 118 void ADE7912_PhaseInit(struct ADE7912_Inst *ade, struct ADE7912_Phase_Settings *settings, enum ADE7912_Phases phase);
yuliyasm 0:e5d06036dd60 119
yuliyasm 0:e5d06036dd60 120 void ADE7912_EnablePhase(struct ADE7912_Inst *ade, enum ADE7912_Phases phase);
yuliyasm 0:e5d06036dd60 121 void ADE7912_DisablePhase(struct ADE7912_Inst *ade, enum ADE7912_Phases phase);
yuliyasm 0:e5d06036dd60 122 void ADE7912_ResetPhase(struct ADE7912_Inst *ade, enum ADE7912_Phases phase);
yuliyasm 0:e5d06036dd60 123
yuliyasm 0:e5d06036dd60 124 void ADE7912_SetDataUdateFreq(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, enum ADE7912_DataUpdateFreq freq);
yuliyasm 0:e5d06036dd60 125 void ADE7912_SetPwrConverterEnabled(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, _Bool enabled);
yuliyasm 0:e5d06036dd60 126 void ADE7912_SetTempEnabled(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, _Bool enabled);
yuliyasm 0:e5d06036dd60 127 void ADE7912_SetBandwidth(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, enum ADE7912_Bandwidths bandwidth);
yuliyasm 0:e5d06036dd60 128 void ADE7912_SetCLKOUTFunctionality(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, enum ADE7912_CLKOUT_Functionality functionality);
yuliyasm 0:e5d06036dd60 129 uint8_t ADE7912_GetADCVersion(struct ADE7912_Inst *ade, enum ADE7912_Phases phase);
yuliyasm 0:e5d06036dd60 130
yuliyasm 0:e5d06036dd60 131 void ADE7912_LockConfigurationRegisters(struct ADE7912_Inst *ade, enum ADE7912_Phases phase);
yuliyasm 0:e5d06036dd60 132 void ADE7912_UnlockConfigurationRegisters(struct ADE7912_Inst *ade, enum ADE7912_Phases phase);
yuliyasm 0:e5d06036dd60 133
yuliyasm 0:e5d06036dd60 134 #endif