adc
ADE7912.h@1:5796bdddf29c, 2020-10-27 (annotated)
- Committer:
- yuliyasm
- Date:
- Tue Oct 27 12:13:16 2020 +0000
- Revision:
- 1:5796bdddf29c
- Parent:
- 0:e5d06036dd60
- Child:
- 2:f480200c8600
final
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
yuliyasm | 0:e5d06036dd60 | 1 | #ifndef ADE7912 |
yuliyasm | 0:e5d06036dd60 | 2 | #define ADE7912 |
yuliyasm | 0:e5d06036dd60 | 3 | |
yuliyasm | 0:e5d06036dd60 | 4 | #include "stm32h7xx_hal.h" |
yuliyasm | 0:e5d06036dd60 | 5 | #include "stdlib.h" |
yuliyasm | 0:e5d06036dd60 | 6 | |
yuliyasm | 0:e5d06036dd60 | 7 | // ADE7912 registers addresses |
yuliyasm | 0:e5d06036dd60 | 8 | #define ADE7912_IWV_REG_ADDRESS 0x00 |
yuliyasm | 0:e5d06036dd60 | 9 | #define ADE7912_V1WV_REG_ADDRESS 0x08 |
yuliyasm | 0:e5d06036dd60 | 10 | #define ADE7912_V2WV_REG_ADDRESS 0x10 |
yuliyasm | 0:e5d06036dd60 | 11 | #define ADE7912_ADC_CRC_REG_ADDRESS 0x20 |
yuliyasm | 0:e5d06036dd60 | 12 | #define ADE7912_CTRL_CRC_REG_ADDRESS 0x28 |
yuliyasm | 0:e5d06036dd60 | 13 | #define ADE7912_CNT_SNAPSHOT_REG_ADDRESS 0x38 |
yuliyasm | 0:e5d06036dd60 | 14 | #define ADE7912_CONFIG_REG_ADDRESS 0x40 |
yuliyasm | 0:e5d06036dd60 | 15 | #define ADE7912_STATUS0_REG_ADDRESS 0x48 |
yuliyasm | 0:e5d06036dd60 | 16 | #define ADE7912_LOCK_REG_ADDRESS 0x50 |
yuliyasm | 0:e5d06036dd60 | 17 | #define ADE7912_SYNC_SNAP_REG_ADDRESS 0x58 |
yuliyasm | 0:e5d06036dd60 | 18 | #define ADE7912_COUNTER0_REG_ADDRESS 0x60 |
yuliyasm | 0:e5d06036dd60 | 19 | #define ADE7912_COUNTER1_REG_ADDRESS 0x68 |
yuliyasm | 0:e5d06036dd60 | 20 | #define ADE7912_EMI_CTRL_REG_ADDRESS 0x70 |
yuliyasm | 0:e5d06036dd60 | 21 | #define ADE7912_STATUS1_REG_ADDRESS 0x78 |
yuliyasm | 0:e5d06036dd60 | 22 | #define ADE7912_TEMPOS_REG_ADDRESS 0xC0 |
yuliyasm | 0:e5d06036dd60 | 23 | |
yuliyasm | 0:e5d06036dd60 | 24 | // ADE7912 bits of CONFIG register |
yuliyasm | 0:e5d06036dd60 | 25 | #define ADE7912_CONFIG_BIT_CLKOUTENB 1 << 0 |
yuliyasm | 0:e5d06036dd60 | 26 | #define ADE7912_CONFIG_BIT_PWRDWNENB 1 << 1 |
yuliyasm | 0:e5d06036dd60 | 27 | #define ADE7912_CONFIG_BIT_TEMPENB 1 << 3 |
yuliyasm | 0:e5d06036dd60 | 28 | #define ADE7912_CONFIG_ADC_FREQ_1K 0x0 << 4 |
yuliyasm | 0:e5d06036dd60 | 29 | #define ADE7912_CONFIG_ADC_FREQ_2K 0x1 << 4 |
yuliyasm | 0:e5d06036dd60 | 30 | #define ADE7912_CONFIG_ADC_FREQ_4K 0x2 << 4 |
yuliyasm | 0:e5d06036dd60 | 31 | #define ADE7912_CONFIG_ADC_FREQ_8K 0x3 << 4 |
yuliyasm | 0:e5d06036dd60 | 32 | #define ADE7912_CONFIG_ADC_FREQ ADE7912_CONFIG_ADC_FREQ_8K |
yuliyasm | 0:e5d06036dd60 | 33 | #define ADE7912_CONFIG_BIT_SWRST 1 << 6 |
yuliyasm | 0:e5d06036dd60 | 34 | #define ADE7912_CONFIG_BIT_BW 1 << 6 |
yuliyasm | 0:e5d06036dd60 | 35 | |
yuliyasm | 0:e5d06036dd60 | 36 | // ADE7912 bits of STATUS0 register |
yuliyasm | 0:e5d06036dd60 | 37 | #define ADE7912_STATUS0_BIT_RESET_ON 1 << 0 |
yuliyasm | 0:e5d06036dd60 | 38 | #define ADE7912_STATUS0_BIT_CRC_STAT 1 << 1 |
yuliyasm | 0:e5d06036dd60 | 39 | #define ADE7912_STATUS0_BIT_IC_PROT 1 << 2 |
yuliyasm | 0:e5d06036dd60 | 40 | |
yuliyasm | 0:e5d06036dd60 | 41 | // ADE7912 bits of STATUS1 register |
yuliyasm | 0:e5d06036dd60 | 42 | #define ADE7912_STATUS1_BIT_VERSION 0x7 << 0 |
yuliyasm | 0:e5d06036dd60 | 43 | #define ADE7912_STATUS1_BIT_ADC_NA 1 << 3 |
yuliyasm | 0:e5d06036dd60 | 44 | |
yuliyasm | 0:e5d06036dd60 | 45 | // ADE7912 transmite modes |
yuliyasm | 0:e5d06036dd60 | 46 | #define ADE7912_READ_MODE 0x04 |
yuliyasm | 0:e5d06036dd60 | 47 | #define ADE7912_BRUSH_READ_MODE 0x04 |
yuliyasm | 0:e5d06036dd60 | 48 | #define ADE7912_WRITE_MODE 0x00 |
yuliyasm | 0:e5d06036dd60 | 49 | |
yuliyasm | 0:e5d06036dd60 | 50 | #define ADE7912_DALAY_TIME 2 |
yuliyasm | 0:e5d06036dd60 | 51 | #define ADE7912_WAITING_TIME 5 * ADE7912_DALAY_TIME |
yuliyasm | 0:e5d06036dd60 | 52 | |
yuliyasm | 1:5796bdddf29c | 53 | #define ADE7912_TEMPGAIN_WITH_3K3_BW 8.72101e-5f |
yuliyasm | 1:5796bdddf29c | 54 | #define ADE7912_TEMPGAIN_WITH_2K_BW 8.21015e-5f |
yuliyasm | 1:5796bdddf29c | 55 | #define ADE7912_CONST_TEMPOS 306.47f |
yuliyasm | 1:5796bdddf29c | 56 | |
yuliyasm | 1:5796bdddf29c | 57 | #define ADE7912_IWV_TRANSLATE_COEF 5.87344e-9f |
yuliyasm | 1:5796bdddf29c | 58 | #define ADE7912_VWV_TRANSLATE_COEF 9.39369e-8f |
yuliyasm | 1:5796bdddf29c | 59 | |
yuliyasm | 1:5796bdddf29c | 60 | struct ADE7912_BrushRead_Data { |
yuliyasm | 1:5796bdddf29c | 61 | int32_t IWV; |
yuliyasm | 1:5796bdddf29c | 62 | int32_t V1WV; |
yuliyasm | 1:5796bdddf29c | 63 | int32_t V2WV; |
yuliyasm | 1:5796bdddf29c | 64 | uint16_t ADC_CRC; |
yuliyasm | 1:5796bdddf29c | 65 | uint8_t STATUS0; |
yuliyasm | 1:5796bdddf29c | 66 | uint16_t CNT_SNAPSHOT; |
yuliyasm | 0:e5d06036dd60 | 67 | }; |
yuliyasm | 0:e5d06036dd60 | 68 | |
yuliyasm | 1:5796bdddf29c | 69 | struct ADE7912_Inst { |
yuliyasm | 1:5796bdddf29c | 70 | SPI_HandleTypeDef *spi; |
yuliyasm | 1:5796bdddf29c | 71 | uint8_t phasesEnable[4]; |
yuliyasm | 1:5796bdddf29c | 72 | GPIO_TypeDef *CS_ports[4]; |
yuliyasm | 1:5796bdddf29c | 73 | uint16_t CS_pins[4]; |
yuliyasm | 1:5796bdddf29c | 74 | struct ADE7912_BrushRead_Data *phasesData[4]; |
yuliyasm | 1:5796bdddf29c | 75 | uint8_t version[4]; |
yuliyasm | 1:5796bdddf29c | 76 | float tempos[4]; |
yuliyasm | 1:5796bdddf29c | 77 | float tempGain[4]; |
yuliyasm | 1:5796bdddf29c | 78 | GPIO_TypeDef *DReadyPort; |
yuliyasm | 1:5796bdddf29c | 79 | uint16_t DReadyPin; |
yuliyasm | 1:5796bdddf29c | 80 | IRQn_Type EXTIinterrupt; |
yuliyasm | 0:e5d06036dd60 | 81 | }; |
yuliyasm | 0:e5d06036dd60 | 82 | |
yuliyasm | 0:e5d06036dd60 | 83 | |
yuliyasm | 0:e5d06036dd60 | 84 | |
yuliyasm | 1:5796bdddf29c | 85 | enum ADE7912_Phases { |
yuliyasm | 1:5796bdddf29c | 86 | PHASE_A = 0, |
yuliyasm | 1:5796bdddf29c | 87 | PHASE_B, |
yuliyasm | 1:5796bdddf29c | 88 | PHASE_C, |
yuliyasm | 1:5796bdddf29c | 89 | COM |
yuliyasm | 0:e5d06036dd60 | 90 | }; |
yuliyasm | 0:e5d06036dd60 | 91 | |
yuliyasm | 1:5796bdddf29c | 92 | enum ADE7912_DataUpdateFreq { |
yuliyasm | 1:5796bdddf29c | 93 | F_8KHZ, |
yuliyasm | 1:5796bdddf29c | 94 | F_4KHZ, |
yuliyasm | 1:5796bdddf29c | 95 | F_2KHZ, |
yuliyasm | 1:5796bdddf29c | 96 | F_1KHZ |
yuliyasm | 0:e5d06036dd60 | 97 | }; |
yuliyasm | 0:e5d06036dd60 | 98 | |
yuliyasm | 1:5796bdddf29c | 99 | enum ADE7912_Bandwidths { |
yuliyasm | 1:5796bdddf29c | 100 | BW_3K3HZ, |
yuliyasm | 1:5796bdddf29c | 101 | BW_2KHZ |
yuliyasm | 0:e5d06036dd60 | 102 | }; |
yuliyasm | 0:e5d06036dd60 | 103 | |
yuliyasm | 1:5796bdddf29c | 104 | enum ADE7912_CLKOUT_Functionality { |
yuliyasm | 1:5796bdddf29c | 105 | CLKOUT, |
yuliyasm | 1:5796bdddf29c | 106 | DREADY |
yuliyasm | 0:e5d06036dd60 | 107 | }; |
yuliyasm | 0:e5d06036dd60 | 108 | |
yuliyasm | 1:5796bdddf29c | 109 | struct ADE7912_Phase_Settings { |
yuliyasm | 1:5796bdddf29c | 110 | GPIO_TypeDef *CS_port; |
yuliyasm | 1:5796bdddf29c | 111 | uint16_t CS_pin; |
yuliyasm | 1:5796bdddf29c | 112 | enum ADE7912_DataUpdateFreq freq; |
yuliyasm | 1:5796bdddf29c | 113 | enum ADE7912_Bandwidths bandwidth; |
yuliyasm | 1:5796bdddf29c | 114 | enum ADE7912_CLKOUT_Functionality clkoutFunc; |
yuliyasm | 0:e5d06036dd60 | 115 | }; |
yuliyasm | 0:e5d06036dd60 | 116 | |
yuliyasm | 1:5796bdddf29c | 117 | |
yuliyasm | 0:e5d06036dd60 | 118 | |
yuliyasm | 0:e5d06036dd60 | 119 | void ADE7912_UpdateData(struct ADE7912_Inst *ade); |
yuliyasm | 0:e5d06036dd60 | 120 | |
yuliyasm | 0:e5d06036dd60 | 121 | struct ADE7912_Inst* New_ADE7912(SPI_HandleTypeDef *spi); |
yuliyasm | 1:5796bdddf29c | 122 | |
yuliyasm | 0:e5d06036dd60 | 123 | void ADE7912_PhaseInit(struct ADE7912_Inst *ade, struct ADE7912_Phase_Settings *settings, enum ADE7912_Phases phase); |
yuliyasm | 0:e5d06036dd60 | 124 | void ADE7912_EnablePhase(struct ADE7912_Inst *ade, enum ADE7912_Phases phase); |
yuliyasm | 0:e5d06036dd60 | 125 | void ADE7912_DisablePhase(struct ADE7912_Inst *ade, enum ADE7912_Phases phase); |
yuliyasm | 0:e5d06036dd60 | 126 | void ADE7912_ResetPhase(struct ADE7912_Inst *ade, enum ADE7912_Phases phase); |
yuliyasm | 0:e5d06036dd60 | 127 | |
yuliyasm | 1:5796bdddf29c | 128 | void ADE7912_SetDataUpdateFreq(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, enum ADE7912_DataUpdateFreq freq); |
yuliyasm | 0:e5d06036dd60 | 129 | void ADE7912_SetPwrConverterEnabled(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, _Bool enabled); |
yuliyasm | 0:e5d06036dd60 | 130 | void ADE7912_SetTempEnabled(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, _Bool enabled); |
yuliyasm | 0:e5d06036dd60 | 131 | void ADE7912_SetBandwidth(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, enum ADE7912_Bandwidths bandwidth); |
yuliyasm | 0:e5d06036dd60 | 132 | void ADE7912_SetCLKOUTFunctionality(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, enum ADE7912_CLKOUT_Functionality functionality); |
yuliyasm | 0:e5d06036dd60 | 133 | |
yuliyasm | 0:e5d06036dd60 | 134 | void ADE7912_LockConfigurationRegisters(struct ADE7912_Inst *ade, enum ADE7912_Phases phase); |
yuliyasm | 0:e5d06036dd60 | 135 | void ADE7912_UnlockConfigurationRegisters(struct ADE7912_Inst *ade, enum ADE7912_Phases phase); |
yuliyasm | 0:e5d06036dd60 | 136 | |
yuliyasm | 1:5796bdddf29c | 137 | uint8_t ADE7912_GetADCVersion(struct ADE7912_Inst *ade, enum ADE7912_Phases phase); |
yuliyasm | 1:5796bdddf29c | 138 | float ADE7912_GetVoltage(struct ADE7912_Inst *ade, enum ADE7912_Phases phase); |
yuliyasm | 1:5796bdddf29c | 139 | float ADE7912_GetCurrent(struct ADE7912_Inst *ade, enum ADE7912_Phases phase); |
yuliyasm | 1:5796bdddf29c | 140 | float ADE7912_GetTemp(struct ADE7912_Inst *ade, enum ADE7912_Phases phase); |
yuliyasm | 1:5796bdddf29c | 141 | |
yuliyasm | 0:e5d06036dd60 | 142 | #endif |