Yihui Xiong
/
nrf51822_fix_i2c_spi_conflict
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Dependencies: BLE_API eMPL_MPU6050 nRF51822
Fork of
Seeed_Tiny_BLE_Flash
by 
Darren Huang
mbed-src/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/CMSDK_BEID.h@5:b8c02645e6af, 2015-11-17 (annotated)
- Committer:
- yihui
- Date:
- Tue Nov 17 07:48:56 2015 +0000
- Revision:
- 5:b8c02645e6af
fix i2c & spi conflict
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| yihui | 5:b8c02645e6af | 1 | /**************************************************************************//** |
| yihui | 5:b8c02645e6af | 2 | * @file CMSDK_BEID.h |
| yihui | 5:b8c02645e6af | 3 | * @brief CMSIS Core Peripheral Access Layer Header File for |
| yihui | 5:b8c02645e6af | 4 | * CMSDK_BEID Device |
| yihui | 5:b8c02645e6af | 5 | * @version V3.02 |
| yihui | 5:b8c02645e6af | 6 | * @date 15. November 2013 |
| yihui | 5:b8c02645e6af | 7 | * |
| yihui | 5:b8c02645e6af | 8 | * @note |
| yihui | 5:b8c02645e6af | 9 | * |
| yihui | 5:b8c02645e6af | 10 | ******************************************************************************/ |
| yihui | 5:b8c02645e6af | 11 | /* Copyright (c) 2011 - 2013 ARM LIMITED |
| yihui | 5:b8c02645e6af | 12 | |
| yihui | 5:b8c02645e6af | 13 | All rights reserved. |
| yihui | 5:b8c02645e6af | 14 | Redistribution and use in source and binary forms, with or without |
| yihui | 5:b8c02645e6af | 15 | modification, are permitted provided that the following conditions are met: |
| yihui | 5:b8c02645e6af | 16 | - Redistributions of source code must retain the above copyright |
| yihui | 5:b8c02645e6af | 17 | notice, this list of conditions and the following disclaimer. |
| yihui | 5:b8c02645e6af | 18 | - Redistributions in binary form must reproduce the above copyright |
| yihui | 5:b8c02645e6af | 19 | notice, this list of conditions and the following disclaimer in the |
| yihui | 5:b8c02645e6af | 20 | documentation and/or other materials provided with the distribution. |
| yihui | 5:b8c02645e6af | 21 | - Neither the name of ARM nor the names of its contributors may be used |
| yihui | 5:b8c02645e6af | 22 | to endorse or promote products derived from this software without |
| yihui | 5:b8c02645e6af | 23 | specific prior written permission. |
| yihui | 5:b8c02645e6af | 24 | * |
| yihui | 5:b8c02645e6af | 25 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| yihui | 5:b8c02645e6af | 26 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| yihui | 5:b8c02645e6af | 27 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| yihui | 5:b8c02645e6af | 28 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
| yihui | 5:b8c02645e6af | 29 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| yihui | 5:b8c02645e6af | 30 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| yihui | 5:b8c02645e6af | 31 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| yihui | 5:b8c02645e6af | 32 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| yihui | 5:b8c02645e6af | 33 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| yihui | 5:b8c02645e6af | 34 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| yihui | 5:b8c02645e6af | 35 | POSSIBILITY OF SUCH DAMAGE. |
| yihui | 5:b8c02645e6af | 36 | ---------------------------------------------------------------------------*/ |
| yihui | 5:b8c02645e6af | 37 | |
| yihui | 5:b8c02645e6af | 38 | |
| yihui | 5:b8c02645e6af | 39 | #ifndef CMSDK_BEID_H |
| yihui | 5:b8c02645e6af | 40 | #define CMSDK_BEID_H |
| yihui | 5:b8c02645e6af | 41 | |
| yihui | 5:b8c02645e6af | 42 | #ifdef __cplusplus |
| yihui | 5:b8c02645e6af | 43 | extern "C" { |
| yihui | 5:b8c02645e6af | 44 | #endif |
| yihui | 5:b8c02645e6af | 45 | |
| yihui | 5:b8c02645e6af | 46 | |
| yihui | 5:b8c02645e6af | 47 | /* ------------------------- Interrupt Number Definition ------------------------ */ |
| yihui | 5:b8c02645e6af | 48 | |
| yihui | 5:b8c02645e6af | 49 | typedef enum IRQn |
| yihui | 5:b8c02645e6af | 50 | { |
| yihui | 5:b8c02645e6af | 51 | /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ |
| yihui | 5:b8c02645e6af | 52 | NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ |
| yihui | 5:b8c02645e6af | 53 | HardFault_IRQn = -13, /* 3 HardFault Interrupt */ |
| yihui | 5:b8c02645e6af | 54 | MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ |
| yihui | 5:b8c02645e6af | 55 | BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ |
| yihui | 5:b8c02645e6af | 56 | UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ |
| yihui | 5:b8c02645e6af | 57 | SVCall_IRQn = -5, /* 11 SV Call Interrupt */ |
| yihui | 5:b8c02645e6af | 58 | DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ |
| yihui | 5:b8c02645e6af | 59 | PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ |
| yihui | 5:b8c02645e6af | 60 | SysTick_IRQn = -1, /* 15 System Tick Interrupt */ |
| yihui | 5:b8c02645e6af | 61 | |
| yihui | 5:b8c02645e6af | 62 | /* ---------------------- CMSDK_BEID Specific Interrupt Numbers ------------------ */ |
| yihui | 5:b8c02645e6af | 63 | UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */ |
| yihui | 5:b8c02645e6af | 64 | UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */ |
| yihui | 5:b8c02645e6af | 65 | UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */ |
| yihui | 5:b8c02645e6af | 66 | UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */ |
| yihui | 5:b8c02645e6af | 67 | UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */ |
| yihui | 5:b8c02645e6af | 68 | UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */ |
| yihui | 5:b8c02645e6af | 69 | UARTRX3_IRQn = 6, /* Was PORT0_ALL_IRQn Port 1 combined Interrupt */ |
| yihui | 5:b8c02645e6af | 70 | UARTTX3_IRQn = 7, /* Was PORT1_ALL_IRQn Port 1 combined Interrupt */ |
| yihui | 5:b8c02645e6af | 71 | TIMER0_IRQn = 8, /* TIMER 0 Interrupt */ |
| yihui | 5:b8c02645e6af | 72 | TIMER1_IRQn = 9, /* TIMER 1 Interrupt */ |
| yihui | 5:b8c02645e6af | 73 | DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */ |
| yihui | 5:b8c02645e6af | 74 | SPI_IRQn = 11, /* SPI Interrupt */ |
| yihui | 5:b8c02645e6af | 75 | UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */ |
| yihui | 5:b8c02645e6af | 76 | ETHERNET_IRQn = 13, /* Ethernet Interrupt */ |
| yihui | 5:b8c02645e6af | 77 | I2S_IRQn = 14, /* I2S Interrupt */ |
| yihui | 5:b8c02645e6af | 78 | TSC_IRQn = 15, /* Touch Screen Interrupt */ |
| yihui | 5:b8c02645e6af | 79 | // DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */ |
| yihui | 5:b8c02645e6af | 80 | PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */ |
| yihui | 5:b8c02645e6af | 81 | PORT0_1_IRQn = 17, /* There are 16 pins in total */ |
| yihui | 5:b8c02645e6af | 82 | PORT0_2_IRQn = 18, |
| yihui | 5:b8c02645e6af | 83 | PORT0_3_IRQn = 19, |
| yihui | 5:b8c02645e6af | 84 | PORT0_4_IRQn = 20, |
| yihui | 5:b8c02645e6af | 85 | PORT0_5_IRQn = 21, |
| yihui | 5:b8c02645e6af | 86 | PORT0_6_IRQn = 22, |
| yihui | 5:b8c02645e6af | 87 | PORT0_7_IRQn = 23, |
| yihui | 5:b8c02645e6af | 88 | PORT0_8_IRQn = 24, |
| yihui | 5:b8c02645e6af | 89 | PORT0_9_IRQn = 25, |
| yihui | 5:b8c02645e6af | 90 | PORT0_10_IRQn = 26, |
| yihui | 5:b8c02645e6af | 91 | PORT0_11_IRQn = 27, |
| yihui | 5:b8c02645e6af | 92 | PORT0_12_IRQn = 28, |
| yihui | 5:b8c02645e6af | 93 | PORT0_13_IRQn = 29, |
| yihui | 5:b8c02645e6af | 94 | PORT0_14_IRQn = 30, |
| yihui | 5:b8c02645e6af | 95 | PORT0_15_IRQn = 31, |
| yihui | 5:b8c02645e6af | 96 | } IRQn_Type; |
| yihui | 5:b8c02645e6af | 97 | |
| yihui | 5:b8c02645e6af | 98 | |
| yihui | 5:b8c02645e6af | 99 | /* ================================================================================ */ |
| yihui | 5:b8c02645e6af | 100 | /* ================ Processor and Core Peripheral Section ================ */ |
| yihui | 5:b8c02645e6af | 101 | /* ================================================================================ */ |
| yihui | 5:b8c02645e6af | 102 | |
| yihui | 5:b8c02645e6af | 103 | /* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */ |
| yihui | 5:b8c02645e6af | 104 | #define __CM3_REV 0x0201 /* Core revision r2p1 */ |
| yihui | 5:b8c02645e6af | 105 | #define __MPU_PRESENT 1 /* MPU present or not */ |
| yihui | 5:b8c02645e6af | 106 | #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */ |
| yihui | 5:b8c02645e6af | 107 | #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ |
| yihui | 5:b8c02645e6af | 108 | |
| yihui | 5:b8c02645e6af | 109 | #include <core_cm3.h> /* Processor and core peripherals */ |
| yihui | 5:b8c02645e6af | 110 | #include "system_CMSDK_BEID.h" /* System Header */ |
| yihui | 5:b8c02645e6af | 111 | |
| yihui | 5:b8c02645e6af | 112 | |
| yihui | 5:b8c02645e6af | 113 | /* ================================================================================ */ |
| yihui | 5:b8c02645e6af | 114 | /* ================ Device Specific Peripheral Section ================ */ |
| yihui | 5:b8c02645e6af | 115 | /* ================================================================================ */ |
| yihui | 5:b8c02645e6af | 116 | |
| yihui | 5:b8c02645e6af | 117 | /* ------------------- Start of section using anonymous unions ------------------ */ |
| yihui | 5:b8c02645e6af | 118 | #if defined ( __CC_ARM ) |
| yihui | 5:b8c02645e6af | 119 | #pragma push |
| yihui | 5:b8c02645e6af | 120 | #pragma anon_unions |
| yihui | 5:b8c02645e6af | 121 | #elif defined(__ICCARM__) |
| yihui | 5:b8c02645e6af | 122 | #pragma language=extended |
| yihui | 5:b8c02645e6af | 123 | #elif defined(__GNUC__) |
| yihui | 5:b8c02645e6af | 124 | /* anonymous unions are enabled by default */ |
| yihui | 5:b8c02645e6af | 125 | #elif defined(__TMS470__) |
| yihui | 5:b8c02645e6af | 126 | /* anonymous unions are enabled by default */ |
| yihui | 5:b8c02645e6af | 127 | #elif defined(__TASKING__) |
| yihui | 5:b8c02645e6af | 128 | #pragma warning 586 |
| yihui | 5:b8c02645e6af | 129 | #else |
| yihui | 5:b8c02645e6af | 130 | #warning Not supported compiler type |
| yihui | 5:b8c02645e6af | 131 | #endif |
| yihui | 5:b8c02645e6af | 132 | |
| yihui | 5:b8c02645e6af | 133 | /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ |
| yihui | 5:b8c02645e6af | 134 | typedef struct |
| yihui | 5:b8c02645e6af | 135 | { |
| yihui | 5:b8c02645e6af | 136 | __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ |
| yihui | 5:b8c02645e6af | 137 | __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ |
| yihui | 5:b8c02645e6af | 138 | __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ |
| yihui | 5:b8c02645e6af | 139 | union { |
| yihui | 5:b8c02645e6af | 140 | __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ |
| yihui | 5:b8c02645e6af | 141 | __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ |
| yihui | 5:b8c02645e6af | 142 | }; |
| yihui | 5:b8c02645e6af | 143 | __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ |
| yihui | 5:b8c02645e6af | 144 | |
| yihui | 5:b8c02645e6af | 145 | } CMSDK_UART_TypeDef; |
| yihui | 5:b8c02645e6af | 146 | |
| yihui | 5:b8c02645e6af | 147 | /* CMSDK_UART DATA Register Definitions */ |
| yihui | 5:b8c02645e6af | 148 | |
| yihui | 5:b8c02645e6af | 149 | #define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */ |
| yihui | 5:b8c02645e6af | 150 | #define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */ |
| yihui | 5:b8c02645e6af | 151 | |
| yihui | 5:b8c02645e6af | 152 | #define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */ |
| yihui | 5:b8c02645e6af | 153 | #define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */ |
| yihui | 5:b8c02645e6af | 154 | |
| yihui | 5:b8c02645e6af | 155 | #define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */ |
| yihui | 5:b8c02645e6af | 156 | #define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */ |
| yihui | 5:b8c02645e6af | 157 | |
| yihui | 5:b8c02645e6af | 158 | #define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */ |
| yihui | 5:b8c02645e6af | 159 | #define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */ |
| yihui | 5:b8c02645e6af | 160 | |
| yihui | 5:b8c02645e6af | 161 | #define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */ |
| yihui | 5:b8c02645e6af | 162 | #define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */ |
| yihui | 5:b8c02645e6af | 163 | |
| yihui | 5:b8c02645e6af | 164 | #define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */ |
| yihui | 5:b8c02645e6af | 165 | #define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */ |
| yihui | 5:b8c02645e6af | 166 | |
| yihui | 5:b8c02645e6af | 167 | #define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */ |
| yihui | 5:b8c02645e6af | 168 | #define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */ |
| yihui | 5:b8c02645e6af | 169 | |
| yihui | 5:b8c02645e6af | 170 | #define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */ |
| yihui | 5:b8c02645e6af | 171 | #define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */ |
| yihui | 5:b8c02645e6af | 172 | |
| yihui | 5:b8c02645e6af | 173 | #define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */ |
| yihui | 5:b8c02645e6af | 174 | #define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */ |
| yihui | 5:b8c02645e6af | 175 | |
| yihui | 5:b8c02645e6af | 176 | #define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */ |
| yihui | 5:b8c02645e6af | 177 | #define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */ |
| yihui | 5:b8c02645e6af | 178 | |
| yihui | 5:b8c02645e6af | 179 | #define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */ |
| yihui | 5:b8c02645e6af | 180 | #define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */ |
| yihui | 5:b8c02645e6af | 181 | |
| yihui | 5:b8c02645e6af | 182 | #define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */ |
| yihui | 5:b8c02645e6af | 183 | #define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */ |
| yihui | 5:b8c02645e6af | 184 | |
| yihui | 5:b8c02645e6af | 185 | #define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */ |
| yihui | 5:b8c02645e6af | 186 | #define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */ |
| yihui | 5:b8c02645e6af | 187 | |
| yihui | 5:b8c02645e6af | 188 | #define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */ |
| yihui | 5:b8c02645e6af | 189 | #define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */ |
| yihui | 5:b8c02645e6af | 190 | |
| yihui | 5:b8c02645e6af | 191 | #define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */ |
| yihui | 5:b8c02645e6af | 192 | #define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */ |
| yihui | 5:b8c02645e6af | 193 | |
| yihui | 5:b8c02645e6af | 194 | #define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */ |
| yihui | 5:b8c02645e6af | 195 | #define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */ |
| yihui | 5:b8c02645e6af | 196 | |
| yihui | 5:b8c02645e6af | 197 | #define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */ |
| yihui | 5:b8c02645e6af | 198 | #define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */ |
| yihui | 5:b8c02645e6af | 199 | |
| yihui | 5:b8c02645e6af | 200 | |
| yihui | 5:b8c02645e6af | 201 | /*----------------------------- Timer (TIMER) -------------------------------*/ |
| yihui | 5:b8c02645e6af | 202 | typedef struct |
| yihui | 5:b8c02645e6af | 203 | { |
| yihui | 5:b8c02645e6af | 204 | __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ |
| yihui | 5:b8c02645e6af | 205 | __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ |
| yihui | 5:b8c02645e6af | 206 | __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ |
| yihui | 5:b8c02645e6af | 207 | union { |
| yihui | 5:b8c02645e6af | 208 | __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ |
| yihui | 5:b8c02645e6af | 209 | __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ |
| yihui | 5:b8c02645e6af | 210 | }; |
| yihui | 5:b8c02645e6af | 211 | |
| yihui | 5:b8c02645e6af | 212 | } CMSDK_TIMER_TypeDef; |
| yihui | 5:b8c02645e6af | 213 | |
| yihui | 5:b8c02645e6af | 214 | /* CMSDK_TIMER CTRL Register Definitions */ |
| yihui | 5:b8c02645e6af | 215 | |
| yihui | 5:b8c02645e6af | 216 | #define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */ |
| yihui | 5:b8c02645e6af | 217 | #define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */ |
| yihui | 5:b8c02645e6af | 218 | |
| yihui | 5:b8c02645e6af | 219 | #define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */ |
| yihui | 5:b8c02645e6af | 220 | #define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */ |
| yihui | 5:b8c02645e6af | 221 | |
| yihui | 5:b8c02645e6af | 222 | #define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */ |
| yihui | 5:b8c02645e6af | 223 | #define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */ |
| yihui | 5:b8c02645e6af | 224 | |
| yihui | 5:b8c02645e6af | 225 | #define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */ |
| yihui | 5:b8c02645e6af | 226 | #define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */ |
| yihui | 5:b8c02645e6af | 227 | |
| yihui | 5:b8c02645e6af | 228 | #define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */ |
| yihui | 5:b8c02645e6af | 229 | #define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */ |
| yihui | 5:b8c02645e6af | 230 | |
| yihui | 5:b8c02645e6af | 231 | #define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */ |
| yihui | 5:b8c02645e6af | 232 | #define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */ |
| yihui | 5:b8c02645e6af | 233 | |
| yihui | 5:b8c02645e6af | 234 | #define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */ |
| yihui | 5:b8c02645e6af | 235 | #define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */ |
| yihui | 5:b8c02645e6af | 236 | |
| yihui | 5:b8c02645e6af | 237 | #define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */ |
| yihui | 5:b8c02645e6af | 238 | #define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */ |
| yihui | 5:b8c02645e6af | 239 | |
| yihui | 5:b8c02645e6af | 240 | |
| yihui | 5:b8c02645e6af | 241 | /*------------- Timer (TIM) --------------------------------------------------*/ |
| yihui | 5:b8c02645e6af | 242 | typedef struct |
| yihui | 5:b8c02645e6af | 243 | { |
| yihui | 5:b8c02645e6af | 244 | __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ |
| yihui | 5:b8c02645e6af | 245 | __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ |
| yihui | 5:b8c02645e6af | 246 | __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ |
| yihui | 5:b8c02645e6af | 247 | __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ |
| yihui | 5:b8c02645e6af | 248 | __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ |
| yihui | 5:b8c02645e6af | 249 | __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ |
| yihui | 5:b8c02645e6af | 250 | __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ |
| yihui | 5:b8c02645e6af | 251 | uint32_t RESERVED0; |
| yihui | 5:b8c02645e6af | 252 | __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ |
| yihui | 5:b8c02645e6af | 253 | __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ |
| yihui | 5:b8c02645e6af | 254 | __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ |
| yihui | 5:b8c02645e6af | 255 | __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ |
| yihui | 5:b8c02645e6af | 256 | __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ |
| yihui | 5:b8c02645e6af | 257 | __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ |
| yihui | 5:b8c02645e6af | 258 | __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ |
| yihui | 5:b8c02645e6af | 259 | uint32_t RESERVED1[945]; |
| yihui | 5:b8c02645e6af | 260 | __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ |
| yihui | 5:b8c02645e6af | 261 | __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ |
| yihui | 5:b8c02645e6af | 262 | } CMSDK_DUALTIMER_BOTH_TypeDef; |
| yihui | 5:b8c02645e6af | 263 | |
| yihui | 5:b8c02645e6af | 264 | #define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */ |
| yihui | 5:b8c02645e6af | 265 | #define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */ |
| yihui | 5:b8c02645e6af | 266 | |
| yihui | 5:b8c02645e6af | 267 | #define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */ |
| yihui | 5:b8c02645e6af | 268 | #define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */ |
| yihui | 5:b8c02645e6af | 269 | |
| yihui | 5:b8c02645e6af | 270 | #define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */ |
| yihui | 5:b8c02645e6af | 271 | #define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */ |
| yihui | 5:b8c02645e6af | 272 | |
| yihui | 5:b8c02645e6af | 273 | #define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */ |
| yihui | 5:b8c02645e6af | 274 | #define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */ |
| yihui | 5:b8c02645e6af | 275 | |
| yihui | 5:b8c02645e6af | 276 | #define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */ |
| yihui | 5:b8c02645e6af | 277 | #define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */ |
| yihui | 5:b8c02645e6af | 278 | |
| yihui | 5:b8c02645e6af | 279 | #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */ |
| yihui | 5:b8c02645e6af | 280 | #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */ |
| yihui | 5:b8c02645e6af | 281 | |
| yihui | 5:b8c02645e6af | 282 | #define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */ |
| yihui | 5:b8c02645e6af | 283 | #define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */ |
| yihui | 5:b8c02645e6af | 284 | |
| yihui | 5:b8c02645e6af | 285 | #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */ |
| yihui | 5:b8c02645e6af | 286 | #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ |
| yihui | 5:b8c02645e6af | 287 | |
| yihui | 5:b8c02645e6af | 288 | #define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */ |
| yihui | 5:b8c02645e6af | 289 | #define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */ |
| yihui | 5:b8c02645e6af | 290 | |
| yihui | 5:b8c02645e6af | 291 | #define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */ |
| yihui | 5:b8c02645e6af | 292 | #define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */ |
| yihui | 5:b8c02645e6af | 293 | |
| yihui | 5:b8c02645e6af | 294 | #define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */ |
| yihui | 5:b8c02645e6af | 295 | #define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */ |
| yihui | 5:b8c02645e6af | 296 | |
| yihui | 5:b8c02645e6af | 297 | #define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */ |
| yihui | 5:b8c02645e6af | 298 | #define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */ |
| yihui | 5:b8c02645e6af | 299 | |
| yihui | 5:b8c02645e6af | 300 | #define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */ |
| yihui | 5:b8c02645e6af | 301 | #define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */ |
| yihui | 5:b8c02645e6af | 302 | |
| yihui | 5:b8c02645e6af | 303 | #define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */ |
| yihui | 5:b8c02645e6af | 304 | #define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */ |
| yihui | 5:b8c02645e6af | 305 | |
| yihui | 5:b8c02645e6af | 306 | #define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */ |
| yihui | 5:b8c02645e6af | 307 | #define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */ |
| yihui | 5:b8c02645e6af | 308 | |
| yihui | 5:b8c02645e6af | 309 | #define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */ |
| yihui | 5:b8c02645e6af | 310 | #define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */ |
| yihui | 5:b8c02645e6af | 311 | |
| yihui | 5:b8c02645e6af | 312 | #define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */ |
| yihui | 5:b8c02645e6af | 313 | #define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */ |
| yihui | 5:b8c02645e6af | 314 | |
| yihui | 5:b8c02645e6af | 315 | #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */ |
| yihui | 5:b8c02645e6af | 316 | #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */ |
| yihui | 5:b8c02645e6af | 317 | |
| yihui | 5:b8c02645e6af | 318 | #define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */ |
| yihui | 5:b8c02645e6af | 319 | #define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */ |
| yihui | 5:b8c02645e6af | 320 | |
| yihui | 5:b8c02645e6af | 321 | #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */ |
| yihui | 5:b8c02645e6af | 322 | #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ |
| yihui | 5:b8c02645e6af | 323 | |
| yihui | 5:b8c02645e6af | 324 | #define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */ |
| yihui | 5:b8c02645e6af | 325 | #define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */ |
| yihui | 5:b8c02645e6af | 326 | |
| yihui | 5:b8c02645e6af | 327 | #define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */ |
| yihui | 5:b8c02645e6af | 328 | #define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */ |
| yihui | 5:b8c02645e6af | 329 | |
| yihui | 5:b8c02645e6af | 330 | #define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */ |
| yihui | 5:b8c02645e6af | 331 | #define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */ |
| yihui | 5:b8c02645e6af | 332 | |
| yihui | 5:b8c02645e6af | 333 | #define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */ |
| yihui | 5:b8c02645e6af | 334 | #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ |
| yihui | 5:b8c02645e6af | 335 | |
| yihui | 5:b8c02645e6af | 336 | |
| yihui | 5:b8c02645e6af | 337 | typedef struct |
| yihui | 5:b8c02645e6af | 338 | { |
| yihui | 5:b8c02645e6af | 339 | __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ |
| yihui | 5:b8c02645e6af | 340 | __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ |
| yihui | 5:b8c02645e6af | 341 | __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ |
| yihui | 5:b8c02645e6af | 342 | __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ |
| yihui | 5:b8c02645e6af | 343 | __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ |
| yihui | 5:b8c02645e6af | 344 | __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ |
| yihui | 5:b8c02645e6af | 345 | __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ |
| yihui | 5:b8c02645e6af | 346 | } CMSDK_DUALTIMER_SINGLE_TypeDef; |
| yihui | 5:b8c02645e6af | 347 | |
| yihui | 5:b8c02645e6af | 348 | #define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */ |
| yihui | 5:b8c02645e6af | 349 | #define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */ |
| yihui | 5:b8c02645e6af | 350 | |
| yihui | 5:b8c02645e6af | 351 | #define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */ |
| yihui | 5:b8c02645e6af | 352 | #define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */ |
| yihui | 5:b8c02645e6af | 353 | |
| yihui | 5:b8c02645e6af | 354 | #define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */ |
| yihui | 5:b8c02645e6af | 355 | #define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */ |
| yihui | 5:b8c02645e6af | 356 | |
| yihui | 5:b8c02645e6af | 357 | #define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */ |
| yihui | 5:b8c02645e6af | 358 | #define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */ |
| yihui | 5:b8c02645e6af | 359 | |
| yihui | 5:b8c02645e6af | 360 | #define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */ |
| yihui | 5:b8c02645e6af | 361 | #define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */ |
| yihui | 5:b8c02645e6af | 362 | |
| yihui | 5:b8c02645e6af | 363 | #define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */ |
| yihui | 5:b8c02645e6af | 364 | #define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */ |
| yihui | 5:b8c02645e6af | 365 | |
| yihui | 5:b8c02645e6af | 366 | #define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */ |
| yihui | 5:b8c02645e6af | 367 | #define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */ |
| yihui | 5:b8c02645e6af | 368 | |
| yihui | 5:b8c02645e6af | 369 | #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */ |
| yihui | 5:b8c02645e6af | 370 | #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */ |
| yihui | 5:b8c02645e6af | 371 | |
| yihui | 5:b8c02645e6af | 372 | #define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */ |
| yihui | 5:b8c02645e6af | 373 | #define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */ |
| yihui | 5:b8c02645e6af | 374 | |
| yihui | 5:b8c02645e6af | 375 | #define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */ |
| yihui | 5:b8c02645e6af | 376 | #define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */ |
| yihui | 5:b8c02645e6af | 377 | |
| yihui | 5:b8c02645e6af | 378 | #define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */ |
| yihui | 5:b8c02645e6af | 379 | #define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */ |
| yihui | 5:b8c02645e6af | 380 | |
| yihui | 5:b8c02645e6af | 381 | #define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */ |
| yihui | 5:b8c02645e6af | 382 | #define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */ |
| yihui | 5:b8c02645e6af | 383 | |
| yihui | 5:b8c02645e6af | 384 | |
| yihui | 5:b8c02645e6af | 385 | /*-------------------- General Purpose Input Output (GPIO) -------------------*/ |
| yihui | 5:b8c02645e6af | 386 | typedef struct |
| yihui | 5:b8c02645e6af | 387 | { |
| yihui | 5:b8c02645e6af | 388 | __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ |
| yihui | 5:b8c02645e6af | 389 | __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ |
| yihui | 5:b8c02645e6af | 390 | uint32_t RESERVED0[2]; |
| yihui | 5:b8c02645e6af | 391 | __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ |
| yihui | 5:b8c02645e6af | 392 | __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ |
| yihui | 5:b8c02645e6af | 393 | __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ |
| yihui | 5:b8c02645e6af | 394 | __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ |
| yihui | 5:b8c02645e6af | 395 | __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ |
| yihui | 5:b8c02645e6af | 396 | __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ |
| yihui | 5:b8c02645e6af | 397 | __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ |
| yihui | 5:b8c02645e6af | 398 | __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ |
| yihui | 5:b8c02645e6af | 399 | __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ |
| yihui | 5:b8c02645e6af | 400 | __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ |
| yihui | 5:b8c02645e6af | 401 | union { |
| yihui | 5:b8c02645e6af | 402 | __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ |
| yihui | 5:b8c02645e6af | 403 | __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ |
| yihui | 5:b8c02645e6af | 404 | }; |
| yihui | 5:b8c02645e6af | 405 | uint32_t RESERVED1[241]; |
| yihui | 5:b8c02645e6af | 406 | __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ |
| yihui | 5:b8c02645e6af | 407 | __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ |
| yihui | 5:b8c02645e6af | 408 | } CMSDK_GPIO_TypeDef; |
| yihui | 5:b8c02645e6af | 409 | |
| yihui | 5:b8c02645e6af | 410 | #define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */ |
| yihui | 5:b8c02645e6af | 411 | #define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */ |
| yihui | 5:b8c02645e6af | 412 | |
| yihui | 5:b8c02645e6af | 413 | #define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */ |
| yihui | 5:b8c02645e6af | 414 | #define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */ |
| yihui | 5:b8c02645e6af | 415 | |
| yihui | 5:b8c02645e6af | 416 | #define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ |
| yihui | 5:b8c02645e6af | 417 | #define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ |
| yihui | 5:b8c02645e6af | 418 | |
| yihui | 5:b8c02645e6af | 419 | #define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ |
| yihui | 5:b8c02645e6af | 420 | #define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ |
| yihui | 5:b8c02645e6af | 421 | |
| yihui | 5:b8c02645e6af | 422 | #define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ |
| yihui | 5:b8c02645e6af | 423 | #define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ |
| yihui | 5:b8c02645e6af | 424 | |
| yihui | 5:b8c02645e6af | 425 | #define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ |
| yihui | 5:b8c02645e6af | 426 | #define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ |
| yihui | 5:b8c02645e6af | 427 | |
| yihui | 5:b8c02645e6af | 428 | #define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ |
| yihui | 5:b8c02645e6af | 429 | #define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ |
| yihui | 5:b8c02645e6af | 430 | |
| yihui | 5:b8c02645e6af | 431 | #define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ |
| yihui | 5:b8c02645e6af | 432 | #define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ |
| yihui | 5:b8c02645e6af | 433 | |
| yihui | 5:b8c02645e6af | 434 | #define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ |
| yihui | 5:b8c02645e6af | 435 | #define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ |
| yihui | 5:b8c02645e6af | 436 | |
| yihui | 5:b8c02645e6af | 437 | #define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ |
| yihui | 5:b8c02645e6af | 438 | #define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ |
| yihui | 5:b8c02645e6af | 439 | |
| yihui | 5:b8c02645e6af | 440 | #define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ |
| yihui | 5:b8c02645e6af | 441 | #define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ |
| yihui | 5:b8c02645e6af | 442 | |
| yihui | 5:b8c02645e6af | 443 | #define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ |
| yihui | 5:b8c02645e6af | 444 | #define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ |
| yihui | 5:b8c02645e6af | 445 | |
| yihui | 5:b8c02645e6af | 446 | #define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */ |
| yihui | 5:b8c02645e6af | 447 | #define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */ |
| yihui | 5:b8c02645e6af | 448 | |
| yihui | 5:b8c02645e6af | 449 | #define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */ |
| yihui | 5:b8c02645e6af | 450 | #define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */ |
| yihui | 5:b8c02645e6af | 451 | |
| yihui | 5:b8c02645e6af | 452 | #define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */ |
| yihui | 5:b8c02645e6af | 453 | #define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */ |
| yihui | 5:b8c02645e6af | 454 | |
| yihui | 5:b8c02645e6af | 455 | #define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */ |
| yihui | 5:b8c02645e6af | 456 | #define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */ |
| yihui | 5:b8c02645e6af | 457 | |
| yihui | 5:b8c02645e6af | 458 | |
| yihui | 5:b8c02645e6af | 459 | /*------------- System Control (SYSCON) --------------------------------------*/ |
| yihui | 5:b8c02645e6af | 460 | typedef struct |
| yihui | 5:b8c02645e6af | 461 | { |
| yihui | 5:b8c02645e6af | 462 | __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ |
| yihui | 5:b8c02645e6af | 463 | __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ |
| yihui | 5:b8c02645e6af | 464 | __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ |
| yihui | 5:b8c02645e6af | 465 | __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ |
| yihui | 5:b8c02645e6af | 466 | __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ |
| yihui | 5:b8c02645e6af | 467 | uint32_t RESERVED0[3]; |
| yihui | 5:b8c02645e6af | 468 | __IO uint32_t AHBPER0SET; /* Offset: 0x020 (R/W)AHB peripheral access control set */ |
| yihui | 5:b8c02645e6af | 469 | __IO uint32_t AHBPER0CLR; /* Offset: 0x024 (R/W)AHB peripheral access control clear */ |
| yihui | 5:b8c02645e6af | 470 | uint32_t RESERVED1[2]; |
| yihui | 5:b8c02645e6af | 471 | __IO uint32_t APBPER0SET; /* Offset: 0x030 (R/W)APB peripheral access control set */ |
| yihui | 5:b8c02645e6af | 472 | __IO uint32_t APBPER0CLR; /* Offset: 0x034 (R/W)APB peripheral access control clear */ |
| yihui | 5:b8c02645e6af | 473 | uint32_t RESERVED2[2]; |
| yihui | 5:b8c02645e6af | 474 | __IO uint32_t MAINCLK; /* Offset: 0x040 (R/W) Main Clock Control Register */ |
| yihui | 5:b8c02645e6af | 475 | __IO uint32_t AUXCLK; /* Offset: 0x044 (R/W) Auxiliary / RTC Control Register */ |
| yihui | 5:b8c02645e6af | 476 | __IO uint32_t PLLCTRL; /* Offset: 0x048 (R/W) PLL Control Register */ |
| yihui | 5:b8c02645e6af | 477 | __IO uint32_t PLLSTATUS; /* Offset: 0x04C (R/W) PLL Status Register */ |
| yihui | 5:b8c02645e6af | 478 | __IO uint32_t SLEEPCFG; /* Offset: 0x050 (R/W) Sleep Control Register */ |
| yihui | 5:b8c02645e6af | 479 | __IO uint32_t FLASHAUXCFG; /* Offset: 0x054 (R/W) Flash auxiliary settings Control Register */ |
| yihui | 5:b8c02645e6af | 480 | uint32_t RESERVED3[10]; |
| yihui | 5:b8c02645e6af | 481 | __IO uint32_t AHBCLKCFG0SET; /* Offset: 0x080 (R/W) AHB Peripheral Clock set in Active state */ |
| yihui | 5:b8c02645e6af | 482 | __IO uint32_t AHBCLKCFG0CLR; /* Offset: 0x084 (R/W) AHB Peripheral Clock clear in Active state */ |
| yihui | 5:b8c02645e6af | 483 | __IO uint32_t AHBCLKCFG1SET; /* Offset: 0x088 (R/W) AHB Peripheral Clock set in Sleep state */ |
| yihui | 5:b8c02645e6af | 484 | __IO uint32_t AHBCLKCFG1CLR; /* Offset: 0x08C (R/W) AHB Peripheral Clock clear in Sleep state */ |
| yihui | 5:b8c02645e6af | 485 | __IO uint32_t AHBCLKCFG2SET; /* Offset: 0x090 (R/W) AHB Peripheral Clock set in Deep Sleep state */ |
| yihui | 5:b8c02645e6af | 486 | __IO uint32_t AHBCLKCFG2CLR; /* Offset: 0x094 (R/W) AHB Peripheral Clock clear in Deep Sleep state */ |
| yihui | 5:b8c02645e6af | 487 | uint32_t RESERVED4[2]; |
| yihui | 5:b8c02645e6af | 488 | __IO uint32_t APBCLKCFG0SET; /* Offset: 0x0A0 (R/W) APB Peripheral Clock set in Active state */ |
| yihui | 5:b8c02645e6af | 489 | __IO uint32_t APBCLKCFG0CLR; /* Offset: 0x0A4 (R/W) APB Peripheral Clock clear in Active state */ |
| yihui | 5:b8c02645e6af | 490 | __IO uint32_t APBCLKCFG1SET; /* Offset: 0x0A8 (R/W) APB Peripheral Clock set in Sleep state */ |
| yihui | 5:b8c02645e6af | 491 | __IO uint32_t APBCLKCFG1CLR; /* Offset: 0x0AC (R/W) APB Peripheral Clock clear in Sleep state */ |
| yihui | 5:b8c02645e6af | 492 | __IO uint32_t APBCLKCFG2SET; /* Offset: 0x0B0 (R/W) APB Peripheral Clock set in Deep Sleep state */ |
| yihui | 5:b8c02645e6af | 493 | __IO uint32_t APBCLKCFG2CLR; /* Offset: 0x0B4 (R/W) APB Peripheral Clock clear in Deep Sleep state */ |
| yihui | 5:b8c02645e6af | 494 | uint32_t RESERVED5[2]; |
| yihui | 5:b8c02645e6af | 495 | __IO uint32_t AHBPRST0SET; /* Offset: 0x0C0 (R/W) AHB Peripheral reset select set */ |
| yihui | 5:b8c02645e6af | 496 | __IO uint32_t AHBPRST0CLR; /* Offset: 0x0C4 (R/W) AHB Peripheral reset select clear */ |
| yihui | 5:b8c02645e6af | 497 | __IO uint32_t APBPRST0SET; /* Offset: 0x0C8 (R/W) APB Peripheral reset select set */ |
| yihui | 5:b8c02645e6af | 498 | __IO uint32_t APBPRST0CLR; /* Offset: 0x0CC (R/W) APB Peripheral reset select clear */ |
| yihui | 5:b8c02645e6af | 499 | __IO uint32_t PWRDNCFG0SET; /* Offset: 0x0D0 (R/W) AHB Power down sleep wakeup source set */ |
| yihui | 5:b8c02645e6af | 500 | __IO uint32_t PWRDNCFG0CLR; /* Offset: 0x0D4 (R/W) AHB Power down sleep wakeup source clear */ |
| yihui | 5:b8c02645e6af | 501 | __IO uint32_t PWRDNCFG1SET; /* Offset: 0x0D8 (R/W) APB Power down sleep wakeup source set */ |
| yihui | 5:b8c02645e6af | 502 | __IO uint32_t PWRDNCFG1CLR; /* Offset: 0x0DC (R/W) APB Power down sleep wakeup source clear */ |
| yihui | 5:b8c02645e6af | 503 | __O uint32_t RTCRESET; /* Offset: 0x0E0 ( /W) RTC reset */ |
| yihui | 5:b8c02645e6af | 504 | __IO uint32_t EVENTCFG; /* Offset: 0x0E4 (R/W) Event interface Control Register */ |
| yihui | 5:b8c02645e6af | 505 | uint32_t RESERVED6[2]; |
| yihui | 5:b8c02645e6af | 506 | __IO uint32_t PWROVRIDE0; /* Offset: 0x0F0 (R/W) SRAM Power control overide */ |
| yihui | 5:b8c02645e6af | 507 | __IO uint32_t PWROVRIDE1; /* Offset: 0x0F4 (R/W) Embedded Flash Power control overide */ |
| yihui | 5:b8c02645e6af | 508 | __I uint32_t MEMORYSTATUS; /* Offset: 0x0F8 (R/ ) Memory Status Register */ |
| yihui | 5:b8c02645e6af | 509 | uint32_t RESERVED7[1]; |
| yihui | 5:b8c02645e6af | 510 | __IO uint32_t GPIOPADCFG0; /* Offset: 0x100 (R/W) IO pad settings */ |
| yihui | 5:b8c02645e6af | 511 | __IO uint32_t GPIOPADCFG1; /* Offset: 0x104 (R/W) IO pad settings */ |
| yihui | 5:b8c02645e6af | 512 | __IO uint32_t TESTMODECFG; /* Offset: 0x108 (R/W) Testmode boot bypass */ |
| yihui | 5:b8c02645e6af | 513 | } CMSDK_SYSCON_TypeDef; |
| yihui | 5:b8c02645e6af | 514 | |
| yihui | 5:b8c02645e6af | 515 | #define CMSDK_SYSCON_REMAP_Pos 0 |
| yihui | 5:b8c02645e6af | 516 | #define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */ |
| yihui | 5:b8c02645e6af | 517 | |
| yihui | 5:b8c02645e6af | 518 | #define CMSDK_SYSCON_PMUCTRL_EN_Pos 0 |
| yihui | 5:b8c02645e6af | 519 | #define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */ |
| yihui | 5:b8c02645e6af | 520 | |
| yihui | 5:b8c02645e6af | 521 | #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0 |
| yihui | 5:b8c02645e6af | 522 | #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */ |
| yihui | 5:b8c02645e6af | 523 | |
| yihui | 5:b8c02645e6af | 524 | #define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24 |
| yihui | 5:b8c02645e6af | 525 | #define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */ |
| yihui | 5:b8c02645e6af | 526 | |
| yihui | 5:b8c02645e6af | 527 | #define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16 |
| yihui | 5:b8c02645e6af | 528 | #define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */ |
| yihui | 5:b8c02645e6af | 529 | |
| yihui | 5:b8c02645e6af | 530 | #define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8 |
| yihui | 5:b8c02645e6af | 531 | #define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */ |
| yihui | 5:b8c02645e6af | 532 | |
| yihui | 5:b8c02645e6af | 533 | #define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0 |
| yihui | 5:b8c02645e6af | 534 | #define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */ |
| yihui | 5:b8c02645e6af | 535 | |
| yihui | 5:b8c02645e6af | 536 | #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0 |
| yihui | 5:b8c02645e6af | 537 | #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */ |
| yihui | 5:b8c02645e6af | 538 | |
| yihui | 5:b8c02645e6af | 539 | #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1 |
| yihui | 5:b8c02645e6af | 540 | #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */ |
| yihui | 5:b8c02645e6af | 541 | |
| yihui | 5:b8c02645e6af | 542 | #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2 |
| yihui | 5:b8c02645e6af | 543 | #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */ |
| yihui | 5:b8c02645e6af | 544 | |
| yihui | 5:b8c02645e6af | 545 | |
| yihui | 5:b8c02645e6af | 546 | /*------------- PL230 uDMA (PL230) --------------------------------------*/ |
| yihui | 5:b8c02645e6af | 547 | typedef struct |
| yihui | 5:b8c02645e6af | 548 | { |
| yihui | 5:b8c02645e6af | 549 | __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ |
| yihui | 5:b8c02645e6af | 550 | __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ |
| yihui | 5:b8c02645e6af | 551 | __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ |
| yihui | 5:b8c02645e6af | 552 | __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ |
| yihui | 5:b8c02645e6af | 553 | __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ |
| yihui | 5:b8c02645e6af | 554 | __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ |
| yihui | 5:b8c02645e6af | 555 | __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ |
| yihui | 5:b8c02645e6af | 556 | __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ |
| yihui | 5:b8c02645e6af | 557 | __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ |
| yihui | 5:b8c02645e6af | 558 | __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ |
| yihui | 5:b8c02645e6af | 559 | __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ |
| yihui | 5:b8c02645e6af | 560 | __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ |
| yihui | 5:b8c02645e6af | 561 | __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ |
| yihui | 5:b8c02645e6af | 562 | __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ |
| yihui | 5:b8c02645e6af | 563 | __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ |
| yihui | 5:b8c02645e6af | 564 | __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ |
| yihui | 5:b8c02645e6af | 565 | uint32_t RESERVED0[3]; |
| yihui | 5:b8c02645e6af | 566 | __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */ |
| yihui | 5:b8c02645e6af | 567 | |
| yihui | 5:b8c02645e6af | 568 | } CMSDK_PL230_TypeDef; |
| yihui | 5:b8c02645e6af | 569 | |
| yihui | 5:b8c02645e6af | 570 | #define PL230_DMA_CHNL_BITS 0 |
| yihui | 5:b8c02645e6af | 571 | |
| yihui | 5:b8c02645e6af | 572 | #define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */ |
| yihui | 5:b8c02645e6af | 573 | #define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */ |
| yihui | 5:b8c02645e6af | 574 | |
| yihui | 5:b8c02645e6af | 575 | #define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */ |
| yihui | 5:b8c02645e6af | 576 | #define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */ |
| yihui | 5:b8c02645e6af | 577 | |
| yihui | 5:b8c02645e6af | 578 | #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */ |
| yihui | 5:b8c02645e6af | 579 | #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */ |
| yihui | 5:b8c02645e6af | 580 | |
| yihui | 5:b8c02645e6af | 581 | #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */ |
| yihui | 5:b8c02645e6af | 582 | #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */ |
| yihui | 5:b8c02645e6af | 583 | |
| yihui | 5:b8c02645e6af | 584 | #define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */ |
| yihui | 5:b8c02645e6af | 585 | #define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */ |
| yihui | 5:b8c02645e6af | 586 | |
| yihui | 5:b8c02645e6af | 587 | #define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */ |
| yihui | 5:b8c02645e6af | 588 | #define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */ |
| yihui | 5:b8c02645e6af | 589 | |
| yihui | 5:b8c02645e6af | 590 | #define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */ |
| yihui | 5:b8c02645e6af | 591 | #define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */ |
| yihui | 5:b8c02645e6af | 592 | |
| yihui | 5:b8c02645e6af | 593 | #define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */ |
| yihui | 5:b8c02645e6af | 594 | #define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */ |
| yihui | 5:b8c02645e6af | 595 | |
| yihui | 5:b8c02645e6af | 596 | #define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */ |
| yihui | 5:b8c02645e6af | 597 | #define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */ |
| yihui | 5:b8c02645e6af | 598 | |
| yihui | 5:b8c02645e6af | 599 | #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */ |
| yihui | 5:b8c02645e6af | 600 | #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */ |
| yihui | 5:b8c02645e6af | 601 | |
| yihui | 5:b8c02645e6af | 602 | #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */ |
| yihui | 5:b8c02645e6af | 603 | #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */ |
| yihui | 5:b8c02645e6af | 604 | |
| yihui | 5:b8c02645e6af | 605 | #define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */ |
| yihui | 5:b8c02645e6af | 606 | #define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */ |
| yihui | 5:b8c02645e6af | 607 | |
| yihui | 5:b8c02645e6af | 608 | #define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */ |
| yihui | 5:b8c02645e6af | 609 | #define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */ |
| yihui | 5:b8c02645e6af | 610 | |
| yihui | 5:b8c02645e6af | 611 | #define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */ |
| yihui | 5:b8c02645e6af | 612 | #define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */ |
| yihui | 5:b8c02645e6af | 613 | |
| yihui | 5:b8c02645e6af | 614 | #define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */ |
| yihui | 5:b8c02645e6af | 615 | #define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */ |
| yihui | 5:b8c02645e6af | 616 | |
| yihui | 5:b8c02645e6af | 617 | #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */ |
| yihui | 5:b8c02645e6af | 618 | #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */ |
| yihui | 5:b8c02645e6af | 619 | |
| yihui | 5:b8c02645e6af | 620 | #define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */ |
| yihui | 5:b8c02645e6af | 621 | #define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */ |
| yihui | 5:b8c02645e6af | 622 | |
| yihui | 5:b8c02645e6af | 623 | #define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */ |
| yihui | 5:b8c02645e6af | 624 | #define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */ |
| yihui | 5:b8c02645e6af | 625 | |
| yihui | 5:b8c02645e6af | 626 | #define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */ |
| yihui | 5:b8c02645e6af | 627 | #define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */ |
| yihui | 5:b8c02645e6af | 628 | |
| yihui | 5:b8c02645e6af | 629 | #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */ |
| yihui | 5:b8c02645e6af | 630 | #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */ |
| yihui | 5:b8c02645e6af | 631 | |
| yihui | 5:b8c02645e6af | 632 | #define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */ |
| yihui | 5:b8c02645e6af | 633 | #define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */ |
| yihui | 5:b8c02645e6af | 634 | |
| yihui | 5:b8c02645e6af | 635 | #define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */ |
| yihui | 5:b8c02645e6af | 636 | #define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */ |
| yihui | 5:b8c02645e6af | 637 | |
| yihui | 5:b8c02645e6af | 638 | #define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */ |
| yihui | 5:b8c02645e6af | 639 | #define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */ |
| yihui | 5:b8c02645e6af | 640 | |
| yihui | 5:b8c02645e6af | 641 | |
| yihui | 5:b8c02645e6af | 642 | /*------------------- Watchdog ----------------------------------------------*/ |
| yihui | 5:b8c02645e6af | 643 | typedef struct |
| yihui | 5:b8c02645e6af | 644 | { |
| yihui | 5:b8c02645e6af | 645 | |
| yihui | 5:b8c02645e6af | 646 | __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ |
| yihui | 5:b8c02645e6af | 647 | __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ |
| yihui | 5:b8c02645e6af | 648 | __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ |
| yihui | 5:b8c02645e6af | 649 | __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ |
| yihui | 5:b8c02645e6af | 650 | __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ |
| yihui | 5:b8c02645e6af | 651 | __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ |
| yihui | 5:b8c02645e6af | 652 | uint32_t RESERVED0[762]; |
| yihui | 5:b8c02645e6af | 653 | __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ |
| yihui | 5:b8c02645e6af | 654 | uint32_t RESERVED1[191]; |
| yihui | 5:b8c02645e6af | 655 | __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ |
| yihui | 5:b8c02645e6af | 656 | __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ |
| yihui | 5:b8c02645e6af | 657 | }CMSDK_WATCHDOG_TypeDef; |
| yihui | 5:b8c02645e6af | 658 | |
| yihui | 5:b8c02645e6af | 659 | #define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ |
| yihui | 5:b8c02645e6af | 660 | #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */ |
| yihui | 5:b8c02645e6af | 661 | |
| yihui | 5:b8c02645e6af | 662 | #define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */ |
| yihui | 5:b8c02645e6af | 663 | #define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */ |
| yihui | 5:b8c02645e6af | 664 | |
| yihui | 5:b8c02645e6af | 665 | #define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */ |
| yihui | 5:b8c02645e6af | 666 | #define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */ |
| yihui | 5:b8c02645e6af | 667 | |
| yihui | 5:b8c02645e6af | 668 | #define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */ |
| yihui | 5:b8c02645e6af | 669 | #define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */ |
| yihui | 5:b8c02645e6af | 670 | |
| yihui | 5:b8c02645e6af | 671 | #define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */ |
| yihui | 5:b8c02645e6af | 672 | #define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */ |
| yihui | 5:b8c02645e6af | 673 | |
| yihui | 5:b8c02645e6af | 674 | #define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */ |
| yihui | 5:b8c02645e6af | 675 | #define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */ |
| yihui | 5:b8c02645e6af | 676 | |
| yihui | 5:b8c02645e6af | 677 | #define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */ |
| yihui | 5:b8c02645e6af | 678 | #define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */ |
| yihui | 5:b8c02645e6af | 679 | |
| yihui | 5:b8c02645e6af | 680 | #define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */ |
| yihui | 5:b8c02645e6af | 681 | #define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */ |
| yihui | 5:b8c02645e6af | 682 | |
| yihui | 5:b8c02645e6af | 683 | #define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */ |
| yihui | 5:b8c02645e6af | 684 | #define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */ |
| yihui | 5:b8c02645e6af | 685 | |
| yihui | 5:b8c02645e6af | 686 | #define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */ |
| yihui | 5:b8c02645e6af | 687 | #define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */ |
| yihui | 5:b8c02645e6af | 688 | |
| yihui | 5:b8c02645e6af | 689 | |
| yihui | 5:b8c02645e6af | 690 | |
| yihui | 5:b8c02645e6af | 691 | /* -------------------- End of section using anonymous unions ------------------- */ |
| yihui | 5:b8c02645e6af | 692 | #if defined ( __CC_ARM ) |
| yihui | 5:b8c02645e6af | 693 | #pragma pop |
| yihui | 5:b8c02645e6af | 694 | #elif defined(__ICCARM__) |
| yihui | 5:b8c02645e6af | 695 | /* leave anonymous unions enabled */ |
| yihui | 5:b8c02645e6af | 696 | #elif defined(__GNUC__) |
| yihui | 5:b8c02645e6af | 697 | /* anonymous unions are enabled by default */ |
| yihui | 5:b8c02645e6af | 698 | #elif defined(__TMS470__) |
| yihui | 5:b8c02645e6af | 699 | /* anonymous unions are enabled by default */ |
| yihui | 5:b8c02645e6af | 700 | #elif defined(__TASKING__) |
| yihui | 5:b8c02645e6af | 701 | #pragma warning restore |
| yihui | 5:b8c02645e6af | 702 | #else |
| yihui | 5:b8c02645e6af | 703 | #warning Not supported compiler type |
| yihui | 5:b8c02645e6af | 704 | #endif |
| yihui | 5:b8c02645e6af | 705 | |
| yihui | 5:b8c02645e6af | 706 | |
| yihui | 5:b8c02645e6af | 707 | |
| yihui | 5:b8c02645e6af | 708 | |
| yihui | 5:b8c02645e6af | 709 | /* ================================================================================ */ |
| yihui | 5:b8c02645e6af | 710 | /* ================ Peripheral memory map ================ */ |
| yihui | 5:b8c02645e6af | 711 | /* ================================================================================ */ |
| yihui | 5:b8c02645e6af | 712 | |
| yihui | 5:b8c02645e6af | 713 | /* Peripheral and SRAM base address */ |
| yihui | 5:b8c02645e6af | 714 | #define CMSDK_FLASH_BASE (0x00000000UL) |
| yihui | 5:b8c02645e6af | 715 | #define CMSDK_SRAM_BASE (0x20000000UL) |
| yihui | 5:b8c02645e6af | 716 | #define CMSDK_PERIPH_BASE (0x40000000UL) |
| yihui | 5:b8c02645e6af | 717 | |
| yihui | 5:b8c02645e6af | 718 | #define CMSDK_RAM_BASE (0x20000000UL) |
| yihui | 5:b8c02645e6af | 719 | #define CMSDK_APB_BASE (0x40000000UL) |
| yihui | 5:b8c02645e6af | 720 | #define CMSDK_AHB_BASE (0x40010000UL) |
| yihui | 5:b8c02645e6af | 721 | |
| yihui | 5:b8c02645e6af | 722 | /* APB peripherals */ |
| yihui | 5:b8c02645e6af | 723 | #define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL) |
| yihui | 5:b8c02645e6af | 724 | #define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL) |
| yihui | 5:b8c02645e6af | 725 | #define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL) |
| yihui | 5:b8c02645e6af | 726 | #define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE) |
| yihui | 5:b8c02645e6af | 727 | #define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL) |
| yihui | 5:b8c02645e6af | 728 | #define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x5000UL) |
| yihui | 5:b8c02645e6af | 729 | #define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x4000UL) |
| yihui | 5:b8c02645e6af | 730 | #define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL) |
| yihui | 5:b8c02645e6af | 731 | #define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL) |
| yihui | 5:b8c02645e6af | 732 | #define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL) |
| yihui | 5:b8c02645e6af | 733 | #define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL) |
| yihui | 5:b8c02645e6af | 734 | |
| yihui | 5:b8c02645e6af | 735 | /* AHB peripherals */ |
| yihui | 5:b8c02645e6af | 736 | #define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL) |
| yihui | 5:b8c02645e6af | 737 | #define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL) |
| yihui | 5:b8c02645e6af | 738 | #define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL) |
| yihui | 5:b8c02645e6af | 739 | #define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL) |
| yihui | 5:b8c02645e6af | 740 | #define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL) |
| yihui | 5:b8c02645e6af | 741 | |
| yihui | 5:b8c02645e6af | 742 | |
| yihui | 5:b8c02645e6af | 743 | /* ================================================================================ */ |
| yihui | 5:b8c02645e6af | 744 | /* ================ Peripheral declaration ================ */ |
| yihui | 5:b8c02645e6af | 745 | /* ================================================================================ */ |
| yihui | 5:b8c02645e6af | 746 | |
| yihui | 5:b8c02645e6af | 747 | #define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE ) |
| yihui | 5:b8c02645e6af | 748 | #define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE ) |
| yihui | 5:b8c02645e6af | 749 | #define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE ) |
| yihui | 5:b8c02645e6af | 750 | #define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE ) |
| yihui | 5:b8c02645e6af | 751 | #define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE ) |
| yihui | 5:b8c02645e6af | 752 | #define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE ) |
| yihui | 5:b8c02645e6af | 753 | #define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE ) |
| yihui | 5:b8c02645e6af | 754 | #define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE ) |
| yihui | 5:b8c02645e6af | 755 | #define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE ) |
| yihui | 5:b8c02645e6af | 756 | #define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE ) |
| yihui | 5:b8c02645e6af | 757 | #define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE ) |
| yihui | 5:b8c02645e6af | 758 | #define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE ) |
| yihui | 5:b8c02645e6af | 759 | #define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE ) |
| yihui | 5:b8c02645e6af | 760 | #define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE ) |
| yihui | 5:b8c02645e6af | 761 | #define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE ) |
| yihui | 5:b8c02645e6af | 762 | #define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE ) |
| yihui | 5:b8c02645e6af | 763 | |
| yihui | 5:b8c02645e6af | 764 | |
| yihui | 5:b8c02645e6af | 765 | #ifdef __cplusplus |
| yihui | 5:b8c02645e6af | 766 | } |
| yihui | 5:b8c02645e6af | 767 | #endif |
| yihui | 5:b8c02645e6af | 768 | |
| yihui | 5:b8c02645e6af | 769 | #endif /* CMSDK_BEID_H */ |