Yihui Xiong / BLE_NODE_TEST

Test code for Grove Node BLE

Dependencies:   BLE_API nRF51822

Fork of BLE_LoopbackUART by Bluetooth Low Energy

mbed-src/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/spi_api.c@10:22480ac31879, 2014-11-27 (annotated)

Committer:
yihui
Date:
Thu Nov 27 09:30:36 2014 +0000
Revision:
10:22480ac31879
Parent:
9:05f0b5a3a70a 
change to new revision hardware

Who changed what in which revision?

UserRevisionLine numberNew contents of line
yihui 9:05f0b5a3a70a 1 /* mbed Microcontroller Library
yihui 9:05f0b5a3a70a 2 * Copyright (c) 2013 Nordic Semiconductor
yihui 9:05f0b5a3a70a 3 *
yihui 9:05f0b5a3a70a 4 * Licensed under the Apache License, Version 2.0 (the "License");
yihui 9:05f0b5a3a70a 5 * you may not use this file except in compliance with the License.
yihui 9:05f0b5a3a70a 6 * You may obtain a copy of the License at
yihui 9:05f0b5a3a70a 7 *
yihui 9:05f0b5a3a70a 8 * http://www.apache.org/licenses/LICENSE-2.0
yihui 9:05f0b5a3a70a 9 *
yihui 9:05f0b5a3a70a 10 * Unless required by applicable law or agreed to in writing, software
yihui 9:05f0b5a3a70a 11 * distributed under the License is distributed on an "AS IS" BASIS,
yihui 9:05f0b5a3a70a 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
yihui 9:05f0b5a3a70a 13 * See the License for the specific language governing permissions and
yihui 9:05f0b5a3a70a 14 * limitations under the License.
yihui 9:05f0b5a3a70a 15 */
yihui 9:05f0b5a3a70a 16 //#include <math.h>
yihui 9:05f0b5a3a70a 17 #include "mbed_assert.h"
yihui 9:05f0b5a3a70a 18 #include "spi_api.h"
yihui 9:05f0b5a3a70a 19 #include "cmsis.h"
yihui 9:05f0b5a3a70a 20 #include "pinmap.h"
yihui 9:05f0b5a3a70a 21 #include "mbed_error.h"
yihui 9:05f0b5a3a70a 22
yihui 9:05f0b5a3a70a 23 static const PinMap PinMap_SPI_SCLK[] = {
yihui 9:05f0b5a3a70a 24 {SPI_PSELSCK0, SPI_0, 0x01},
yihui 9:05f0b5a3a70a 25 {SPI_PSELSCK1, SPI_1, 0x02},
yihui 9:05f0b5a3a70a 26 {SPIS_PSELSCK, SPIS, 0x03},
yihui 9:05f0b5a3a70a 27 {NC, NC, 0}
yihui 9:05f0b5a3a70a 28 };
yihui 9:05f0b5a3a70a 29
yihui 9:05f0b5a3a70a 30 static const PinMap PinMap_SPI_MOSI[] = {
yihui 9:05f0b5a3a70a 31 {SPI_PSELMOSI0, SPI_0, 0x01},
yihui 9:05f0b5a3a70a 32 {SPI_PSELMOSI1, SPI_1, 0x02},
yihui 9:05f0b5a3a70a 33 {SPIS_PSELMOSI, SPIS, 0x03},
yihui 9:05f0b5a3a70a 34 {NC, NC, 0}
yihui 9:05f0b5a3a70a 35 };
yihui 9:05f0b5a3a70a 36
yihui 9:05f0b5a3a70a 37 static const PinMap PinMap_SPI_MISO[] = {
yihui 9:05f0b5a3a70a 38 {SPI_PSELMISO0, SPI_0, 0x01},
yihui 9:05f0b5a3a70a 39 {SPI_PSELMISO1, SPI_1, 0x02},
yihui 9:05f0b5a3a70a 40 {SPIS_PSELMISO, SPIS, 0x03},
yihui 9:05f0b5a3a70a 41 {NC, NC, 0}
yihui 9:05f0b5a3a70a 42 };
yihui 9:05f0b5a3a70a 43
yihui 9:05f0b5a3a70a 44 static const PinMap PinMap_SPI_SSEL[] = {
yihui 9:05f0b5a3a70a 45 {SPIS_PSELSS, SPIS, 0x03},
yihui 9:05f0b5a3a70a 46 {NC, NC, 0}
yihui 9:05f0b5a3a70a 47 };
yihui 9:05f0b5a3a70a 48 // {SPI_PSELSS0 , SPI_0, 0x01},
yihui 9:05f0b5a3a70a 49 #define SPIS_MESSAGE_SIZE 1
yihui 9:05f0b5a3a70a 50 volatile uint8_t m_tx_buf[SPIS_MESSAGE_SIZE] = {0};
yihui 9:05f0b5a3a70a 51 volatile uint8_t m_rx_buf[SPIS_MESSAGE_SIZE] = {0};
yihui 9:05f0b5a3a70a 52
yihui 9:05f0b5a3a70a 53
yihui 9:05f0b5a3a70a 54 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
yihui 9:05f0b5a3a70a 55 {
yihui 9:05f0b5a3a70a 56 // determine the SPI to use
yihui 9:05f0b5a3a70a 57 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
yihui 9:05f0b5a3a70a 58 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
yihui 9:05f0b5a3a70a 59 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
yihui 9:05f0b5a3a70a 60 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
yihui 9:05f0b5a3a70a 61 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
yihui 9:05f0b5a3a70a 62 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
yihui 9:05f0b5a3a70a 63 SPIName spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
yihui 9:05f0b5a3a70a 64 //SPIName
yihui 9:05f0b5a3a70a 65 if (ssel==NC) {
yihui 9:05f0b5a3a70a 66 obj->spi = (NRF_SPI_Type *)spi;
yihui 9:05f0b5a3a70a 67 obj->spis = (NRF_SPIS_Type *)NC;
yihui 9:05f0b5a3a70a 68 } else {
yihui 9:05f0b5a3a70a 69 obj->spi = (NRF_SPI_Type *)NC;
yihui 9:05f0b5a3a70a 70 obj->spis = (NRF_SPIS_Type *)spi;
yihui 9:05f0b5a3a70a 71 }
yihui 9:05f0b5a3a70a 72 MBED_ASSERT((int)obj->spi != NC || (int)obj->spis != NC);
yihui 9:05f0b5a3a70a 73
yihui 9:05f0b5a3a70a 74 // pin out the spi pins
yihui 9:05f0b5a3a70a 75 if (ssel != NC) { //slave
yihui 9:05f0b5a3a70a 76 obj->spis->POWER = 0;
yihui 9:05f0b5a3a70a 77 obj->spis->POWER = 1;
yihui 9:05f0b5a3a70a 78
yihui 9:05f0b5a3a70a 79 NRF_GPIO->PIN_CNF[mosi] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
yihui 9:05f0b5a3a70a 80 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
yihui 9:05f0b5a3a70a 81 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
yihui 9:05f0b5a3a70a 82 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
yihui 9:05f0b5a3a70a 83 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
yihui 9:05f0b5a3a70a 84 NRF_GPIO->PIN_CNF[miso] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
yihui 9:05f0b5a3a70a 85 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
yihui 9:05f0b5a3a70a 86 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
yihui 9:05f0b5a3a70a 87 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
yihui 9:05f0b5a3a70a 88 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
yihui 9:05f0b5a3a70a 89 NRF_GPIO->PIN_CNF[sclk] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
yihui 9:05f0b5a3a70a 90 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
yihui 9:05f0b5a3a70a 91 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
yihui 9:05f0b5a3a70a 92 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
yihui 9:05f0b5a3a70a 93 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
yihui 9:05f0b5a3a70a 94 NRF_GPIO->PIN_CNF[ssel] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
yihui 9:05f0b5a3a70a 95 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
yihui 9:05f0b5a3a70a 96 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
yihui 9:05f0b5a3a70a 97 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
yihui 9:05f0b5a3a70a 98 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
yihui 9:05f0b5a3a70a 99
yihui 9:05f0b5a3a70a 100 obj->spis->PSELMOSI = mosi;
yihui 9:05f0b5a3a70a 101 obj->spis->PSELMISO = miso;
yihui 9:05f0b5a3a70a 102 obj->spis->PSELSCK = sclk;
yihui 9:05f0b5a3a70a 103 obj->spis->PSELCSN = ssel;
yihui 9:05f0b5a3a70a 104
yihui 9:05f0b5a3a70a 105 obj->spis->EVENTS_END = 0;
yihui 9:05f0b5a3a70a 106 obj->spis->EVENTS_ACQUIRED = 0;
yihui 9:05f0b5a3a70a 107 obj->spis->MAXRX = SPIS_MESSAGE_SIZE;
yihui 9:05f0b5a3a70a 108 obj->spis->MAXTX = SPIS_MESSAGE_SIZE;
yihui 9:05f0b5a3a70a 109 obj->spis->TXDPTR = (uint32_t)&m_tx_buf[0];
yihui 9:05f0b5a3a70a 110 obj->spis->RXDPTR = (uint32_t)&m_rx_buf[0];
yihui 9:05f0b5a3a70a 111 obj->spis->SHORTS = (SPIS_SHORTS_END_ACQUIRE_Enabled << SPIS_SHORTS_END_ACQUIRE_Pos);
yihui 9:05f0b5a3a70a 112
yihui 9:05f0b5a3a70a 113 spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
yihui 9:05f0b5a3a70a 114 } else { //master
yihui 9:05f0b5a3a70a 115 obj->spi->POWER = 0;
yihui 9:05f0b5a3a70a 116 obj->spi->POWER = 1;
yihui 9:05f0b5a3a70a 117
yihui 9:05f0b5a3a70a 118 //NRF_GPIO->DIR |= (1<<mosi);
yihui 9:05f0b5a3a70a 119 NRF_GPIO->PIN_CNF[mosi] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
yihui 9:05f0b5a3a70a 120 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
yihui 9:05f0b5a3a70a 121 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
yihui 9:05f0b5a3a70a 122 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
yihui 9:05f0b5a3a70a 123 | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
yihui 9:05f0b5a3a70a 124 obj->spi->PSELMOSI = mosi;
yihui 9:05f0b5a3a70a 125
yihui 9:05f0b5a3a70a 126 NRF_GPIO->PIN_CNF[sclk] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
yihui 9:05f0b5a3a70a 127 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
yihui 9:05f0b5a3a70a 128 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
yihui 9:05f0b5a3a70a 129 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
yihui 9:05f0b5a3a70a 130 | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
yihui 9:05f0b5a3a70a 131 obj->spi->PSELSCK = sclk;
yihui 9:05f0b5a3a70a 132
yihui 9:05f0b5a3a70a 133 //NRF_GPIO->DIR &= ~(1<<miso);
yihui 9:05f0b5a3a70a 134 NRF_GPIO->PIN_CNF[miso] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
yihui 9:05f0b5a3a70a 135 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
yihui 9:05f0b5a3a70a 136 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
yihui 9:05f0b5a3a70a 137 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
yihui 9:05f0b5a3a70a 138 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
yihui 9:05f0b5a3a70a 139
yihui 9:05f0b5a3a70a 140 obj->spi->PSELMISO = miso;
yihui 9:05f0b5a3a70a 141
yihui 9:05f0b5a3a70a 142 obj->spi->EVENTS_READY = 0U;
yihui 9:05f0b5a3a70a 143
yihui 9:05f0b5a3a70a 144 spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
yihui 9:05f0b5a3a70a 145 spi_frequency(obj, 1000000);
yihui 9:05f0b5a3a70a 146 }
yihui 9:05f0b5a3a70a 147 }
yihui 9:05f0b5a3a70a 148
yihui 9:05f0b5a3a70a 149 void spi_free(spi_t *obj) {
yihui 9:05f0b5a3a70a 150 }
yihui 9:05f0b5a3a70a 151
yihui 9:05f0b5a3a70a 152 static inline void spi_disable(spi_t *obj, int slave)
yihui 9:05f0b5a3a70a 153 {
yihui 9:05f0b5a3a70a 154 if (slave) {
yihui 9:05f0b5a3a70a 155 obj->spis->ENABLE = (SPIS_ENABLE_ENABLE_Disabled << SPIS_ENABLE_ENABLE_Pos);
yihui 9:05f0b5a3a70a 156 } else {
yihui 9:05f0b5a3a70a 157 obj->spi->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos);
yihui 9:05f0b5a3a70a 158 }
yihui 9:05f0b5a3a70a 159 }
yihui 9:05f0b5a3a70a 160
yihui 9:05f0b5a3a70a 161 static inline void spi_enable(spi_t *obj, int slave)
yihui 9:05f0b5a3a70a 162 {
yihui 9:05f0b5a3a70a 163 if (slave) {
yihui 9:05f0b5a3a70a 164 obj->spis->ENABLE = (SPIS_ENABLE_ENABLE_Enabled << SPIS_ENABLE_ENABLE_Pos);
yihui 9:05f0b5a3a70a 165 } else {
yihui 9:05f0b5a3a70a 166 obj->spi->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos);
yihui 9:05f0b5a3a70a 167 }
yihui 9:05f0b5a3a70a 168 }
yihui 9:05f0b5a3a70a 169
yihui 9:05f0b5a3a70a 170 void spi_format(spi_t *obj, int bits, int mode, int slave)
yihui 9:05f0b5a3a70a 171 {
yihui 9:05f0b5a3a70a 172 uint32_t config_mode = 0;
yihui 9:05f0b5a3a70a 173 spi_disable(obj, slave);
yihui 9:05f0b5a3a70a 174
yihui 9:05f0b5a3a70a 175 if (bits != 8) {
yihui 9:05f0b5a3a70a 176 error("Only 8bits SPI supported");
yihui 9:05f0b5a3a70a 177 }
yihui 9:05f0b5a3a70a 178
yihui 9:05f0b5a3a70a 179 switch (mode) {
yihui 9:05f0b5a3a70a 180 case 0:
yihui 9:05f0b5a3a70a 181 config_mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
yihui 9:05f0b5a3a70a 182 break;
yihui 9:05f0b5a3a70a 183 case 1:
yihui 9:05f0b5a3a70a 184 config_mode = (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
yihui 9:05f0b5a3a70a 185 break;
yihui 9:05f0b5a3a70a 186 case 2:
yihui 9:05f0b5a3a70a 187 config_mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
yihui 9:05f0b5a3a70a 188 break;
yihui 9:05f0b5a3a70a 189 case 3:
yihui 9:05f0b5a3a70a 190 config_mode = (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
yihui 9:05f0b5a3a70a 191 break;
yihui 9:05f0b5a3a70a 192 default:
yihui 9:05f0b5a3a70a 193 error("SPI format error");
yihui 9:05f0b5a3a70a 194 break;
yihui 9:05f0b5a3a70a 195 }
yihui 9:05f0b5a3a70a 196 //default to msb first
yihui 9:05f0b5a3a70a 197 if (slave) {
yihui 9:05f0b5a3a70a 198 obj->spis->CONFIG = (config_mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos));
yihui 9:05f0b5a3a70a 199 } else {
yihui 9:05f0b5a3a70a 200 obj->spi->CONFIG = (config_mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos));
yihui 9:05f0b5a3a70a 201 }
yihui 9:05f0b5a3a70a 202
yihui 9:05f0b5a3a70a 203 spi_enable(obj, slave);
yihui 9:05f0b5a3a70a 204 }
yihui 9:05f0b5a3a70a 205
yihui 9:05f0b5a3a70a 206 void spi_frequency(spi_t *obj, int hz)
yihui 9:05f0b5a3a70a 207 {
yihui 9:05f0b5a3a70a 208 if ((int)obj->spi==NC) {
yihui 9:05f0b5a3a70a 209 return;
yihui 9:05f0b5a3a70a 210 }
yihui 9:05f0b5a3a70a 211 spi_disable(obj, 0);
yihui 9:05f0b5a3a70a 212
yihui 9:05f0b5a3a70a 213 if (hz<250000) { //125Kbps
yihui 9:05f0b5a3a70a 214 obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_K125;
yihui 9:05f0b5a3a70a 215 } else if (hz<500000) { //250Kbps
yihui 9:05f0b5a3a70a 216 obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_K250;
yihui 9:05f0b5a3a70a 217 } else if (hz<1000000) { //500Kbps
yihui 9:05f0b5a3a70a 218 obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_K500;
yihui 9:05f0b5a3a70a 219 } else if (hz<2000000) { //1Mbps
yihui 9:05f0b5a3a70a 220 obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_M1;
yihui 9:05f0b5a3a70a 221 } else if (hz<4000000) { //2Mbps
yihui 9:05f0b5a3a70a 222 obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_M2;
yihui 9:05f0b5a3a70a 223 } else if (hz<8000000) { //4Mbps
yihui 9:05f0b5a3a70a 224 obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_M4;
yihui 9:05f0b5a3a70a 225 } else { //8Mbps
yihui 9:05f0b5a3a70a 226 obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_M8;
yihui 9:05f0b5a3a70a 227 }
yihui 9:05f0b5a3a70a 228
yihui 9:05f0b5a3a70a 229 spi_enable(obj, 0);
yihui 9:05f0b5a3a70a 230 }
yihui 9:05f0b5a3a70a 231
yihui 9:05f0b5a3a70a 232 static inline int spi_readable(spi_t *obj)
yihui 9:05f0b5a3a70a 233 {
yihui 9:05f0b5a3a70a 234 return (obj->spi->EVENTS_READY == 1);
yihui 9:05f0b5a3a70a 235 }
yihui 9:05f0b5a3a70a 236
yihui 9:05f0b5a3a70a 237 static inline int spi_writeable(spi_t *obj)
yihui 9:05f0b5a3a70a 238 {
yihui 9:05f0b5a3a70a 239 return (obj->spi->EVENTS_READY == 0);
yihui 9:05f0b5a3a70a 240 }
yihui 9:05f0b5a3a70a 241
yihui 9:05f0b5a3a70a 242 static inline int spi_read(spi_t *obj)
yihui 9:05f0b5a3a70a 243 {
yihui 9:05f0b5a3a70a 244 while (!spi_readable(obj)) {
yihui 9:05f0b5a3a70a 245 }
yihui 9:05f0b5a3a70a 246
yihui 9:05f0b5a3a70a 247 obj->spi->EVENTS_READY = 0;
yihui 9:05f0b5a3a70a 248 return (int)obj->spi->RXD;
yihui 9:05f0b5a3a70a 249 }
yihui 9:05f0b5a3a70a 250
yihui 9:05f0b5a3a70a 251 int spi_master_write(spi_t *obj, int value)
yihui 9:05f0b5a3a70a 252 {
yihui 9:05f0b5a3a70a 253 while (!spi_writeable(obj)) {
yihui 9:05f0b5a3a70a 254 }
yihui 9:05f0b5a3a70a 255 obj->spi->TXD = (uint32_t)value;
yihui 9:05f0b5a3a70a 256 return spi_read(obj);
yihui 9:05f0b5a3a70a 257 }
yihui 9:05f0b5a3a70a 258
yihui 9:05f0b5a3a70a 259 //static inline int spis_writeable(spi_t *obj) {
yihui 9:05f0b5a3a70a 260 // return (obj->spis->EVENTS_ACQUIRED==1);
yihui 9:05f0b5a3a70a 261 //}
yihui 9:05f0b5a3a70a 262
yihui 9:05f0b5a3a70a 263 int spi_slave_receive(spi_t *obj)
yihui 9:05f0b5a3a70a 264 {
yihui 9:05f0b5a3a70a 265 return obj->spis->EVENTS_END;
yihui 9:05f0b5a3a70a 266 }
yihui 9:05f0b5a3a70a 267
yihui 9:05f0b5a3a70a 268 int spi_slave_read(spi_t *obj)
yihui 9:05f0b5a3a70a 269 {
yihui 9:05f0b5a3a70a 270 return m_rx_buf[0];
yihui 9:05f0b5a3a70a 271 }
yihui 9:05f0b5a3a70a 272
yihui 9:05f0b5a3a70a 273 void spi_slave_write(spi_t *obj, int value)
yihui 9:05f0b5a3a70a 274 {
yihui 9:05f0b5a3a70a 275 m_tx_buf[0] = value & 0xFF;
yihui 9:05f0b5a3a70a 276 obj->spis->TASKS_RELEASE = 1;
yihui 9:05f0b5a3a70a 277 obj->spis->EVENTS_ACQUIRED = 0;
yihui 9:05f0b5a3a70a 278 obj->spis->EVENTS_END = 0;
yihui 9:05f0b5a3a70a 279 }