Yihui Xiong / BLE_NODE_TEST

Test code for Grove Node BLE

Dependencies:   BLE_API nRF51822

Fork of BLE_LoopbackUART by Bluetooth Low Energy

mbed-src/targets/cmsis/core_cmInstr.h@10:22480ac31879, 2014-11-27 (annotated)

Committer:
yihui
Date:
Thu Nov 27 09:30:36 2014 +0000
Revision:
10:22480ac31879
Parent:
9:05f0b5a3a70a 
change to new revision hardware

Who changed what in which revision?

UserRevisionLine numberNew contents of line
yihui 9:05f0b5a3a70a 1 /**************************************************************************//**
yihui 9:05f0b5a3a70a 2 * @file core_cmInstr.h
yihui 9:05f0b5a3a70a 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
yihui 9:05f0b5a3a70a 4 * @version V3.20
yihui 9:05f0b5a3a70a 5 * @date 05. March 2013
yihui 9:05f0b5a3a70a 6 *
yihui 9:05f0b5a3a70a 7 * @note
yihui 9:05f0b5a3a70a 8 *
yihui 9:05f0b5a3a70a 9 ******************************************************************************/
yihui 9:05f0b5a3a70a 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
yihui 9:05f0b5a3a70a 11
yihui 9:05f0b5a3a70a 12 All rights reserved.
yihui 9:05f0b5a3a70a 13 Redistribution and use in source and binary forms, with or without
yihui 9:05f0b5a3a70a 14 modification, are permitted provided that the following conditions are met:
yihui 9:05f0b5a3a70a 15 - Redistributions of source code must retain the above copyright
yihui 9:05f0b5a3a70a 16 notice, this list of conditions and the following disclaimer.
yihui 9:05f0b5a3a70a 17 - Redistributions in binary form must reproduce the above copyright
yihui 9:05f0b5a3a70a 18 notice, this list of conditions and the following disclaimer in the
yihui 9:05f0b5a3a70a 19 documentation and/or other materials provided with the distribution.
yihui 9:05f0b5a3a70a 20 - Neither the name of ARM nor the names of its contributors may be used
yihui 9:05f0b5a3a70a 21 to endorse or promote products derived from this software without
yihui 9:05f0b5a3a70a 22 specific prior written permission.
yihui 9:05f0b5a3a70a 23 *
yihui 9:05f0b5a3a70a 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
yihui 9:05f0b5a3a70a 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
yihui 9:05f0b5a3a70a 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
yihui 9:05f0b5a3a70a 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
yihui 9:05f0b5a3a70a 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
yihui 9:05f0b5a3a70a 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
yihui 9:05f0b5a3a70a 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
yihui 9:05f0b5a3a70a 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
yihui 9:05f0b5a3a70a 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
yihui 9:05f0b5a3a70a 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
yihui 9:05f0b5a3a70a 34 POSSIBILITY OF SUCH DAMAGE.
yihui 9:05f0b5a3a70a 35 ---------------------------------------------------------------------------*/
yihui 9:05f0b5a3a70a 36
yihui 9:05f0b5a3a70a 37
yihui 9:05f0b5a3a70a 38 #ifndef __CORE_CMINSTR_H
yihui 9:05f0b5a3a70a 39 #define __CORE_CMINSTR_H
yihui 9:05f0b5a3a70a 40
yihui 9:05f0b5a3a70a 41
yihui 9:05f0b5a3a70a 42 /* ########################## Core Instruction Access ######################### */
yihui 9:05f0b5a3a70a 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
yihui 9:05f0b5a3a70a 44 Access to dedicated instructions
yihui 9:05f0b5a3a70a 45 @{
yihui 9:05f0b5a3a70a 46 */
yihui 9:05f0b5a3a70a 47
yihui 9:05f0b5a3a70a 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
yihui 9:05f0b5a3a70a 49 /* ARM armcc specific functions */
yihui 9:05f0b5a3a70a 50
yihui 9:05f0b5a3a70a 51 #if (__ARMCC_VERSION < 400677)
yihui 9:05f0b5a3a70a 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
yihui 9:05f0b5a3a70a 53 #endif
yihui 9:05f0b5a3a70a 54
yihui 9:05f0b5a3a70a 55
yihui 9:05f0b5a3a70a 56 /** \brief No Operation
yihui 9:05f0b5a3a70a 57
yihui 9:05f0b5a3a70a 58 No Operation does nothing. This instruction can be used for code alignment purposes.
yihui 9:05f0b5a3a70a 59 */
yihui 9:05f0b5a3a70a 60 #define __NOP __nop
yihui 9:05f0b5a3a70a 61
yihui 9:05f0b5a3a70a 62
yihui 9:05f0b5a3a70a 63 /** \brief Wait For Interrupt
yihui 9:05f0b5a3a70a 64
yihui 9:05f0b5a3a70a 65 Wait For Interrupt is a hint instruction that suspends execution
yihui 9:05f0b5a3a70a 66 until one of a number of events occurs.
yihui 9:05f0b5a3a70a 67 */
yihui 9:05f0b5a3a70a 68 #define __WFI __wfi
yihui 9:05f0b5a3a70a 69
yihui 9:05f0b5a3a70a 70
yihui 9:05f0b5a3a70a 71 /** \brief Wait For Event
yihui 9:05f0b5a3a70a 72
yihui 9:05f0b5a3a70a 73 Wait For Event is a hint instruction that permits the processor to enter
yihui 9:05f0b5a3a70a 74 a low-power state until one of a number of events occurs.
yihui 9:05f0b5a3a70a 75 */
yihui 9:05f0b5a3a70a 76 #define __WFE __wfe
yihui 9:05f0b5a3a70a 77
yihui 9:05f0b5a3a70a 78
yihui 9:05f0b5a3a70a 79 /** \brief Send Event
yihui 9:05f0b5a3a70a 80
yihui 9:05f0b5a3a70a 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
yihui 9:05f0b5a3a70a 82 */
yihui 9:05f0b5a3a70a 83 #define __SEV __sev
yihui 9:05f0b5a3a70a 84
yihui 9:05f0b5a3a70a 85
yihui 9:05f0b5a3a70a 86 /** \brief Instruction Synchronization Barrier
yihui 9:05f0b5a3a70a 87
yihui 9:05f0b5a3a70a 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
yihui 9:05f0b5a3a70a 89 so that all instructions following the ISB are fetched from cache or
yihui 9:05f0b5a3a70a 90 memory, after the instruction has been completed.
yihui 9:05f0b5a3a70a 91 */
yihui 9:05f0b5a3a70a 92 #define __ISB() __isb(0xF)
yihui 9:05f0b5a3a70a 93
yihui 9:05f0b5a3a70a 94
yihui 9:05f0b5a3a70a 95 /** \brief Data Synchronization Barrier
yihui 9:05f0b5a3a70a 96
yihui 9:05f0b5a3a70a 97 This function acts as a special kind of Data Memory Barrier.
yihui 9:05f0b5a3a70a 98 It completes when all explicit memory accesses before this instruction complete.
yihui 9:05f0b5a3a70a 99 */
yihui 9:05f0b5a3a70a 100 #define __DSB() __dsb(0xF)
yihui 9:05f0b5a3a70a 101
yihui 9:05f0b5a3a70a 102
yihui 9:05f0b5a3a70a 103 /** \brief Data Memory Barrier
yihui 9:05f0b5a3a70a 104
yihui 9:05f0b5a3a70a 105 This function ensures the apparent order of the explicit memory operations before
yihui 9:05f0b5a3a70a 106 and after the instruction, without ensuring their completion.
yihui 9:05f0b5a3a70a 107 */
yihui 9:05f0b5a3a70a 108 #define __DMB() __dmb(0xF)
yihui 9:05f0b5a3a70a 109
yihui 9:05f0b5a3a70a 110
yihui 9:05f0b5a3a70a 111 /** \brief Reverse byte order (32 bit)
yihui 9:05f0b5a3a70a 112
yihui 9:05f0b5a3a70a 113 This function reverses the byte order in integer value.
yihui 9:05f0b5a3a70a 114
yihui 9:05f0b5a3a70a 115 \param [in] value Value to reverse
yihui 9:05f0b5a3a70a 116 \return Reversed value
yihui 9:05f0b5a3a70a 117 */
yihui 9:05f0b5a3a70a 118 #define __REV __rev
yihui 9:05f0b5a3a70a 119
yihui 9:05f0b5a3a70a 120
yihui 9:05f0b5a3a70a 121 /** \brief Reverse byte order (16 bit)
yihui 9:05f0b5a3a70a 122
yihui 9:05f0b5a3a70a 123 This function reverses the byte order in two unsigned short values.
yihui 9:05f0b5a3a70a 124
yihui 9:05f0b5a3a70a 125 \param [in] value Value to reverse
yihui 9:05f0b5a3a70a 126 \return Reversed value
yihui 9:05f0b5a3a70a 127 */
yihui 9:05f0b5a3a70a 128 #ifndef __NO_EMBEDDED_ASM
yihui 9:05f0b5a3a70a 129 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
yihui 9:05f0b5a3a70a 130 {
yihui 9:05f0b5a3a70a 131 rev16 r0, r0
yihui 9:05f0b5a3a70a 132 bx lr
yihui 9:05f0b5a3a70a 133 }
yihui 9:05f0b5a3a70a 134 #endif
yihui 9:05f0b5a3a70a 135
yihui 9:05f0b5a3a70a 136 /** \brief Reverse byte order in signed short value
yihui 9:05f0b5a3a70a 137
yihui 9:05f0b5a3a70a 138 This function reverses the byte order in a signed short value with sign extension to integer.
yihui 9:05f0b5a3a70a 139
yihui 9:05f0b5a3a70a 140 \param [in] value Value to reverse
yihui 9:05f0b5a3a70a 141 \return Reversed value
yihui 9:05f0b5a3a70a 142 */
yihui 9:05f0b5a3a70a 143 #ifndef __NO_EMBEDDED_ASM
yihui 9:05f0b5a3a70a 144 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
yihui 9:05f0b5a3a70a 145 {
yihui 9:05f0b5a3a70a 146 revsh r0, r0
yihui 9:05f0b5a3a70a 147 bx lr
yihui 9:05f0b5a3a70a 148 }
yihui 9:05f0b5a3a70a 149 #endif
yihui 9:05f0b5a3a70a 150
yihui 9:05f0b5a3a70a 151
yihui 9:05f0b5a3a70a 152 /** \brief Rotate Right in unsigned value (32 bit)
yihui 9:05f0b5a3a70a 153
yihui 9:05f0b5a3a70a 154 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
yihui 9:05f0b5a3a70a 155
yihui 9:05f0b5a3a70a 156 \param [in] value Value to rotate
yihui 9:05f0b5a3a70a 157 \param [in] value Number of Bits to rotate
yihui 9:05f0b5a3a70a 158 \return Rotated value
yihui 9:05f0b5a3a70a 159 */
yihui 9:05f0b5a3a70a 160 #define __ROR __ror
yihui 9:05f0b5a3a70a 161
yihui 9:05f0b5a3a70a 162
yihui 9:05f0b5a3a70a 163 /** \brief Breakpoint
yihui 9:05f0b5a3a70a 164
yihui 9:05f0b5a3a70a 165 This function causes the processor to enter Debug state.
yihui 9:05f0b5a3a70a 166 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
yihui 9:05f0b5a3a70a 167
yihui 9:05f0b5a3a70a 168 \param [in] value is ignored by the processor.
yihui 9:05f0b5a3a70a 169 If required, a debugger can use it to store additional information about the breakpoint.
yihui 9:05f0b5a3a70a 170 */
yihui 9:05f0b5a3a70a 171 #define __BKPT(value) __breakpoint(value)
yihui 9:05f0b5a3a70a 172
yihui 9:05f0b5a3a70a 173
yihui 9:05f0b5a3a70a 174 #if (__CORTEX_M >= 0x03)
yihui 9:05f0b5a3a70a 175
yihui 9:05f0b5a3a70a 176 /** \brief Reverse bit order of value
yihui 9:05f0b5a3a70a 177
yihui 9:05f0b5a3a70a 178 This function reverses the bit order of the given value.
yihui 9:05f0b5a3a70a 179
yihui 9:05f0b5a3a70a 180 \param [in] value Value to reverse
yihui 9:05f0b5a3a70a 181 \return Reversed value
yihui 9:05f0b5a3a70a 182 */
yihui 9:05f0b5a3a70a 183 #define __RBIT __rbit
yihui 9:05f0b5a3a70a 184
yihui 9:05f0b5a3a70a 185
yihui 9:05f0b5a3a70a 186 /** \brief LDR Exclusive (8 bit)
yihui 9:05f0b5a3a70a 187
yihui 9:05f0b5a3a70a 188 This function performs a exclusive LDR command for 8 bit value.
yihui 9:05f0b5a3a70a 189
yihui 9:05f0b5a3a70a 190 \param [in] ptr Pointer to data
yihui 9:05f0b5a3a70a 191 \return value of type uint8_t at (*ptr)
yihui 9:05f0b5a3a70a 192 */
yihui 9:05f0b5a3a70a 193 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
yihui 9:05f0b5a3a70a 194
yihui 9:05f0b5a3a70a 195
yihui 9:05f0b5a3a70a 196 /** \brief LDR Exclusive (16 bit)
yihui 9:05f0b5a3a70a 197
yihui 9:05f0b5a3a70a 198 This function performs a exclusive LDR command for 16 bit values.
yihui 9:05f0b5a3a70a 199
yihui 9:05f0b5a3a70a 200 \param [in] ptr Pointer to data
yihui 9:05f0b5a3a70a 201 \return value of type uint16_t at (*ptr)
yihui 9:05f0b5a3a70a 202 */
yihui 9:05f0b5a3a70a 203 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
yihui 9:05f0b5a3a70a 204
yihui 9:05f0b5a3a70a 205
yihui 9:05f0b5a3a70a 206 /** \brief LDR Exclusive (32 bit)
yihui 9:05f0b5a3a70a 207
yihui 9:05f0b5a3a70a 208 This function performs a exclusive LDR command for 32 bit values.
yihui 9:05f0b5a3a70a 209
yihui 9:05f0b5a3a70a 210 \param [in] ptr Pointer to data
yihui 9:05f0b5a3a70a 211 \return value of type uint32_t at (*ptr)
yihui 9:05f0b5a3a70a 212 */
yihui 9:05f0b5a3a70a 213 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
yihui 9:05f0b5a3a70a 214
yihui 9:05f0b5a3a70a 215
yihui 9:05f0b5a3a70a 216 /** \brief STR Exclusive (8 bit)
yihui 9:05f0b5a3a70a 217
yihui 9:05f0b5a3a70a 218 This function performs a exclusive STR command for 8 bit values.
yihui 9:05f0b5a3a70a 219
yihui 9:05f0b5a3a70a 220 \param [in] value Value to store
yihui 9:05f0b5a3a70a 221 \param [in] ptr Pointer to location
yihui 9:05f0b5a3a70a 222 \return 0 Function succeeded
yihui 9:05f0b5a3a70a 223 \return 1 Function failed
yihui 9:05f0b5a3a70a 224 */
yihui 9:05f0b5a3a70a 225 #define __STREXB(value, ptr) __strex(value, ptr)
yihui 9:05f0b5a3a70a 226
yihui 9:05f0b5a3a70a 227
yihui 9:05f0b5a3a70a 228 /** \brief STR Exclusive (16 bit)
yihui 9:05f0b5a3a70a 229
yihui 9:05f0b5a3a70a 230 This function performs a exclusive STR command for 16 bit values.
yihui 9:05f0b5a3a70a 231
yihui 9:05f0b5a3a70a 232 \param [in] value Value to store
yihui 9:05f0b5a3a70a 233 \param [in] ptr Pointer to location
yihui 9:05f0b5a3a70a 234 \return 0 Function succeeded
yihui 9:05f0b5a3a70a 235 \return 1 Function failed
yihui 9:05f0b5a3a70a 236 */
yihui 9:05f0b5a3a70a 237 #define __STREXH(value, ptr) __strex(value, ptr)
yihui 9:05f0b5a3a70a 238
yihui 9:05f0b5a3a70a 239
yihui 9:05f0b5a3a70a 240 /** \brief STR Exclusive (32 bit)
yihui 9:05f0b5a3a70a 241
yihui 9:05f0b5a3a70a 242 This function performs a exclusive STR command for 32 bit values.
yihui 9:05f0b5a3a70a 243
yihui 9:05f0b5a3a70a 244 \param [in] value Value to store
yihui 9:05f0b5a3a70a 245 \param [in] ptr Pointer to location
yihui 9:05f0b5a3a70a 246 \return 0 Function succeeded
yihui 9:05f0b5a3a70a 247 \return 1 Function failed
yihui 9:05f0b5a3a70a 248 */
yihui 9:05f0b5a3a70a 249 #define __STREXW(value, ptr) __strex(value, ptr)
yihui 9:05f0b5a3a70a 250
yihui 9:05f0b5a3a70a 251
yihui 9:05f0b5a3a70a 252 /** \brief Remove the exclusive lock
yihui 9:05f0b5a3a70a 253
yihui 9:05f0b5a3a70a 254 This function removes the exclusive lock which is created by LDREX.
yihui 9:05f0b5a3a70a 255
yihui 9:05f0b5a3a70a 256 */
yihui 9:05f0b5a3a70a 257 #define __CLREX __clrex
yihui 9:05f0b5a3a70a 258
yihui 9:05f0b5a3a70a 259
yihui 9:05f0b5a3a70a 260 /** \brief Signed Saturate
yihui 9:05f0b5a3a70a 261
yihui 9:05f0b5a3a70a 262 This function saturates a signed value.
yihui 9:05f0b5a3a70a 263
yihui 9:05f0b5a3a70a 264 \param [in] value Value to be saturated
yihui 9:05f0b5a3a70a 265 \param [in] sat Bit position to saturate to (1..32)
yihui 9:05f0b5a3a70a 266 \return Saturated value
yihui 9:05f0b5a3a70a 267 */
yihui 9:05f0b5a3a70a 268 #define __SSAT __ssat
yihui 9:05f0b5a3a70a 269
yihui 9:05f0b5a3a70a 270
yihui 9:05f0b5a3a70a 271 /** \brief Unsigned Saturate
yihui 9:05f0b5a3a70a 272
yihui 9:05f0b5a3a70a 273 This function saturates an unsigned value.
yihui 9:05f0b5a3a70a 274
yihui 9:05f0b5a3a70a 275 \param [in] value Value to be saturated
yihui 9:05f0b5a3a70a 276 \param [in] sat Bit position to saturate to (0..31)
yihui 9:05f0b5a3a70a 277 \return Saturated value
yihui 9:05f0b5a3a70a 278 */
yihui 9:05f0b5a3a70a 279 #define __USAT __usat
yihui 9:05f0b5a3a70a 280
yihui 9:05f0b5a3a70a 281
yihui 9:05f0b5a3a70a 282 /** \brief Count leading zeros
yihui 9:05f0b5a3a70a 283
yihui 9:05f0b5a3a70a 284 This function counts the number of leading zeros of a data value.
yihui 9:05f0b5a3a70a 285
yihui 9:05f0b5a3a70a 286 \param [in] value Value to count the leading zeros
yihui 9:05f0b5a3a70a 287 \return number of leading zeros in value
yihui 9:05f0b5a3a70a 288 */
yihui 9:05f0b5a3a70a 289 #define __CLZ __clz
yihui 9:05f0b5a3a70a 290
yihui 9:05f0b5a3a70a 291 #endif /* (__CORTEX_M >= 0x03) */
yihui 9:05f0b5a3a70a 292
yihui 9:05f0b5a3a70a 293
yihui 9:05f0b5a3a70a 294
yihui 9:05f0b5a3a70a 295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
yihui 9:05f0b5a3a70a 296 /* IAR iccarm specific functions */
yihui 9:05f0b5a3a70a 297
yihui 9:05f0b5a3a70a 298 #include <cmsis_iar.h>
yihui 9:05f0b5a3a70a 299
yihui 9:05f0b5a3a70a 300
yihui 9:05f0b5a3a70a 301 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
yihui 9:05f0b5a3a70a 302 /* TI CCS specific functions */
yihui 9:05f0b5a3a70a 303
yihui 9:05f0b5a3a70a 304 #include <cmsis_ccs.h>
yihui 9:05f0b5a3a70a 305
yihui 9:05f0b5a3a70a 306
yihui 9:05f0b5a3a70a 307 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
yihui 9:05f0b5a3a70a 308 /* GNU gcc specific functions */
yihui 9:05f0b5a3a70a 309
yihui 9:05f0b5a3a70a 310 /* Define macros for porting to both thumb1 and thumb2.
yihui 9:05f0b5a3a70a 311 * For thumb1, use low register (r0-r7), specified by constrant "l"
yihui 9:05f0b5a3a70a 312 * Otherwise, use general registers, specified by constrant "r" */
yihui 9:05f0b5a3a70a 313 #if defined (__thumb__) && !defined (__thumb2__)
yihui 9:05f0b5a3a70a 314 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
yihui 9:05f0b5a3a70a 315 #define __CMSIS_GCC_USE_REG(r) "l" (r)
yihui 9:05f0b5a3a70a 316 #else
yihui 9:05f0b5a3a70a 317 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
yihui 9:05f0b5a3a70a 318 #define __CMSIS_GCC_USE_REG(r) "r" (r)
yihui 9:05f0b5a3a70a 319 #endif
yihui 9:05f0b5a3a70a 320
yihui 9:05f0b5a3a70a 321 /** \brief No Operation
yihui 9:05f0b5a3a70a 322
yihui 9:05f0b5a3a70a 323 No Operation does nothing. This instruction can be used for code alignment purposes.
yihui 9:05f0b5a3a70a 324 */
yihui 9:05f0b5a3a70a 325 __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
yihui 9:05f0b5a3a70a 326 {
yihui 9:05f0b5a3a70a 327 __ASM volatile ("nop");
yihui 9:05f0b5a3a70a 328 }
yihui 9:05f0b5a3a70a 329
yihui 9:05f0b5a3a70a 330
yihui 9:05f0b5a3a70a 331 /** \brief Wait For Interrupt
yihui 9:05f0b5a3a70a 332
yihui 9:05f0b5a3a70a 333 Wait For Interrupt is a hint instruction that suspends execution
yihui 9:05f0b5a3a70a 334 until one of a number of events occurs.
yihui 9:05f0b5a3a70a 335 */
yihui 9:05f0b5a3a70a 336 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
yihui 9:05f0b5a3a70a 337 {
yihui 9:05f0b5a3a70a 338 __ASM volatile ("wfi");
yihui 9:05f0b5a3a70a 339 }
yihui 9:05f0b5a3a70a 340
yihui 9:05f0b5a3a70a 341
yihui 9:05f0b5a3a70a 342 /** \brief Wait For Event
yihui 9:05f0b5a3a70a 343
yihui 9:05f0b5a3a70a 344 Wait For Event is a hint instruction that permits the processor to enter
yihui 9:05f0b5a3a70a 345 a low-power state until one of a number of events occurs.
yihui 9:05f0b5a3a70a 346 */
yihui 9:05f0b5a3a70a 347 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
yihui 9:05f0b5a3a70a 348 {
yihui 9:05f0b5a3a70a 349 __ASM volatile ("wfe");
yihui 9:05f0b5a3a70a 350 }
yihui 9:05f0b5a3a70a 351
yihui 9:05f0b5a3a70a 352
yihui 9:05f0b5a3a70a 353 /** \brief Send Event
yihui 9:05f0b5a3a70a 354
yihui 9:05f0b5a3a70a 355 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
yihui 9:05f0b5a3a70a 356 */
yihui 9:05f0b5a3a70a 357 __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
yihui 9:05f0b5a3a70a 358 {
yihui 9:05f0b5a3a70a 359 __ASM volatile ("sev");
yihui 9:05f0b5a3a70a 360 }
yihui 9:05f0b5a3a70a 361
yihui 9:05f0b5a3a70a 362
yihui 9:05f0b5a3a70a 363 /** \brief Instruction Synchronization Barrier
yihui 9:05f0b5a3a70a 364
yihui 9:05f0b5a3a70a 365 Instruction Synchronization Barrier flushes the pipeline in the processor,
yihui 9:05f0b5a3a70a 366 so that all instructions following the ISB are fetched from cache or
yihui 9:05f0b5a3a70a 367 memory, after the instruction has been completed.
yihui 9:05f0b5a3a70a 368 */
yihui 9:05f0b5a3a70a 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
yihui 9:05f0b5a3a70a 370 {
yihui 9:05f0b5a3a70a 371 __ASM volatile ("isb");
yihui 9:05f0b5a3a70a 372 }
yihui 9:05f0b5a3a70a 373
yihui 9:05f0b5a3a70a 374
yihui 9:05f0b5a3a70a 375 /** \brief Data Synchronization Barrier
yihui 9:05f0b5a3a70a 376
yihui 9:05f0b5a3a70a 377 This function acts as a special kind of Data Memory Barrier.
yihui 9:05f0b5a3a70a 378 It completes when all explicit memory accesses before this instruction complete.
yihui 9:05f0b5a3a70a 379 */
yihui 9:05f0b5a3a70a 380 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
yihui 9:05f0b5a3a70a 381 {
yihui 9:05f0b5a3a70a 382 __ASM volatile ("dsb");
yihui 9:05f0b5a3a70a 383 }
yihui 9:05f0b5a3a70a 384
yihui 9:05f0b5a3a70a 385
yihui 9:05f0b5a3a70a 386 /** \brief Data Memory Barrier
yihui 9:05f0b5a3a70a 387
yihui 9:05f0b5a3a70a 388 This function ensures the apparent order of the explicit memory operations before
yihui 9:05f0b5a3a70a 389 and after the instruction, without ensuring their completion.
yihui 9:05f0b5a3a70a 390 */
yihui 9:05f0b5a3a70a 391 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
yihui 9:05f0b5a3a70a 392 {
yihui 9:05f0b5a3a70a 393 __ASM volatile ("dmb");
yihui 9:05f0b5a3a70a 394 }
yihui 9:05f0b5a3a70a 395
yihui 9:05f0b5a3a70a 396
yihui 9:05f0b5a3a70a 397 /** \brief Reverse byte order (32 bit)
yihui 9:05f0b5a3a70a 398
yihui 9:05f0b5a3a70a 399 This function reverses the byte order in integer value.
yihui 9:05f0b5a3a70a 400
yihui 9:05f0b5a3a70a 401 \param [in] value Value to reverse
yihui 9:05f0b5a3a70a 402 \return Reversed value
yihui 9:05f0b5a3a70a 403 */
yihui 9:05f0b5a3a70a 404 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
yihui 9:05f0b5a3a70a 405 {
yihui 9:05f0b5a3a70a 406 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
yihui 9:05f0b5a3a70a 407 return __builtin_bswap32(value);
yihui 9:05f0b5a3a70a 408 #else
yihui 9:05f0b5a3a70a 409 uint32_t result;
yihui 9:05f0b5a3a70a 410
yihui 9:05f0b5a3a70a 411 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
yihui 9:05f0b5a3a70a 412 return(result);
yihui 9:05f0b5a3a70a 413 #endif
yihui 9:05f0b5a3a70a 414 }
yihui 9:05f0b5a3a70a 415
yihui 9:05f0b5a3a70a 416
yihui 9:05f0b5a3a70a 417 /** \brief Reverse byte order (16 bit)
yihui 9:05f0b5a3a70a 418
yihui 9:05f0b5a3a70a 419 This function reverses the byte order in two unsigned short values.
yihui 9:05f0b5a3a70a 420
yihui 9:05f0b5a3a70a 421 \param [in] value Value to reverse
yihui 9:05f0b5a3a70a 422 \return Reversed value
yihui 9:05f0b5a3a70a 423 */
yihui 9:05f0b5a3a70a 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
yihui 9:05f0b5a3a70a 425 {
yihui 9:05f0b5a3a70a 426 uint32_t result;
yihui 9:05f0b5a3a70a 427
yihui 9:05f0b5a3a70a 428 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
yihui 9:05f0b5a3a70a 429 return(result);
yihui 9:05f0b5a3a70a 430 }
yihui 9:05f0b5a3a70a 431
yihui 9:05f0b5a3a70a 432
yihui 9:05f0b5a3a70a 433 /** \brief Reverse byte order in signed short value
yihui 9:05f0b5a3a70a 434
yihui 9:05f0b5a3a70a 435 This function reverses the byte order in a signed short value with sign extension to integer.
yihui 9:05f0b5a3a70a 436
yihui 9:05f0b5a3a70a 437 \param [in] value Value to reverse
yihui 9:05f0b5a3a70a 438 \return Reversed value
yihui 9:05f0b5a3a70a 439 */
yihui 9:05f0b5a3a70a 440 __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
yihui 9:05f0b5a3a70a 441 {
yihui 9:05f0b5a3a70a 442 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
yihui 9:05f0b5a3a70a 443 return (short)__builtin_bswap16(value);
yihui 9:05f0b5a3a70a 444 #else
yihui 9:05f0b5a3a70a 445 uint32_t result;
yihui 9:05f0b5a3a70a 446
yihui 9:05f0b5a3a70a 447 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
yihui 9:05f0b5a3a70a 448 return(result);
yihui 9:05f0b5a3a70a 449 #endif
yihui 9:05f0b5a3a70a 450 }
yihui 9:05f0b5a3a70a 451
yihui 9:05f0b5a3a70a 452
yihui 9:05f0b5a3a70a 453 /** \brief Rotate Right in unsigned value (32 bit)
yihui 9:05f0b5a3a70a 454
yihui 9:05f0b5a3a70a 455 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
yihui 9:05f0b5a3a70a 456
yihui 9:05f0b5a3a70a 457 \param [in] value Value to rotate
yihui 9:05f0b5a3a70a 458 \param [in] value Number of Bits to rotate
yihui 9:05f0b5a3a70a 459 \return Rotated value
yihui 9:05f0b5a3a70a 460 */
yihui 9:05f0b5a3a70a 461 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 462 {
yihui 9:05f0b5a3a70a 463 return (op1 >> op2) | (op1 << (32 - op2));
yihui 9:05f0b5a3a70a 464 }
yihui 9:05f0b5a3a70a 465
yihui 9:05f0b5a3a70a 466
yihui 9:05f0b5a3a70a 467 /** \brief Breakpoint
yihui 9:05f0b5a3a70a 468
yihui 9:05f0b5a3a70a 469 This function causes the processor to enter Debug state.
yihui 9:05f0b5a3a70a 470 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
yihui 9:05f0b5a3a70a 471
yihui 9:05f0b5a3a70a 472 \param [in] value is ignored by the processor.
yihui 9:05f0b5a3a70a 473 If required, a debugger can use it to store additional information about the breakpoint.
yihui 9:05f0b5a3a70a 474 */
yihui 9:05f0b5a3a70a 475 #define __BKPT(value) __ASM volatile ("bkpt "#value)
yihui 9:05f0b5a3a70a 476
yihui 9:05f0b5a3a70a 477
yihui 9:05f0b5a3a70a 478 #if (__CORTEX_M >= 0x03)
yihui 9:05f0b5a3a70a 479
yihui 9:05f0b5a3a70a 480 /** \brief Reverse bit order of value
yihui 9:05f0b5a3a70a 481
yihui 9:05f0b5a3a70a 482 This function reverses the bit order of the given value.
yihui 9:05f0b5a3a70a 483
yihui 9:05f0b5a3a70a 484 \param [in] value Value to reverse
yihui 9:05f0b5a3a70a 485 \return Reversed value
yihui 9:05f0b5a3a70a 486 */
yihui 9:05f0b5a3a70a 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
yihui 9:05f0b5a3a70a 488 {
yihui 9:05f0b5a3a70a 489 uint32_t result;
yihui 9:05f0b5a3a70a 490
yihui 9:05f0b5a3a70a 491 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
yihui 9:05f0b5a3a70a 492 return(result);
yihui 9:05f0b5a3a70a 493 }
yihui 9:05f0b5a3a70a 494
yihui 9:05f0b5a3a70a 495
yihui 9:05f0b5a3a70a 496 /** \brief LDR Exclusive (8 bit)
yihui 9:05f0b5a3a70a 497
yihui 9:05f0b5a3a70a 498 This function performs a exclusive LDR command for 8 bit value.
yihui 9:05f0b5a3a70a 499
yihui 9:05f0b5a3a70a 500 \param [in] ptr Pointer to data
yihui 9:05f0b5a3a70a 501 \return value of type uint8_t at (*ptr)
yihui 9:05f0b5a3a70a 502 */
yihui 9:05f0b5a3a70a 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
yihui 9:05f0b5a3a70a 504 {
yihui 9:05f0b5a3a70a 505 uint32_t result;
yihui 9:05f0b5a3a70a 506
yihui 9:05f0b5a3a70a 507 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
yihui 9:05f0b5a3a70a 508 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
yihui 9:05f0b5a3a70a 509 #else
yihui 9:05f0b5a3a70a 510 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
yihui 9:05f0b5a3a70a 511 accepted by assembler. So has to use following less efficient pattern.
yihui 9:05f0b5a3a70a 512 */
yihui 9:05f0b5a3a70a 513 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
yihui 9:05f0b5a3a70a 514 #endif
yihui 9:05f0b5a3a70a 515 return(result);
yihui 9:05f0b5a3a70a 516 }
yihui 9:05f0b5a3a70a 517
yihui 9:05f0b5a3a70a 518
yihui 9:05f0b5a3a70a 519 /** \brief LDR Exclusive (16 bit)
yihui 9:05f0b5a3a70a 520
yihui 9:05f0b5a3a70a 521 This function performs a exclusive LDR command for 16 bit values.
yihui 9:05f0b5a3a70a 522
yihui 9:05f0b5a3a70a 523 \param [in] ptr Pointer to data
yihui 9:05f0b5a3a70a 524 \return value of type uint16_t at (*ptr)
yihui 9:05f0b5a3a70a 525 */
yihui 9:05f0b5a3a70a 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
yihui 9:05f0b5a3a70a 527 {
yihui 9:05f0b5a3a70a 528 uint32_t result;
yihui 9:05f0b5a3a70a 529
yihui 9:05f0b5a3a70a 530 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
yihui 9:05f0b5a3a70a 531 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
yihui 9:05f0b5a3a70a 532 #else
yihui 9:05f0b5a3a70a 533 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
yihui 9:05f0b5a3a70a 534 accepted by assembler. So has to use following less efficient pattern.
yihui 9:05f0b5a3a70a 535 */
yihui 9:05f0b5a3a70a 536 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
yihui 9:05f0b5a3a70a 537 #endif
yihui 9:05f0b5a3a70a 538 return(result);
yihui 9:05f0b5a3a70a 539 }
yihui 9:05f0b5a3a70a 540
yihui 9:05f0b5a3a70a 541
yihui 9:05f0b5a3a70a 542 /** \brief LDR Exclusive (32 bit)
yihui 9:05f0b5a3a70a 543
yihui 9:05f0b5a3a70a 544 This function performs a exclusive LDR command for 32 bit values.
yihui 9:05f0b5a3a70a 545
yihui 9:05f0b5a3a70a 546 \param [in] ptr Pointer to data
yihui 9:05f0b5a3a70a 547 \return value of type uint32_t at (*ptr)
yihui 9:05f0b5a3a70a 548 */
yihui 9:05f0b5a3a70a 549 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
yihui 9:05f0b5a3a70a 550 {
yihui 9:05f0b5a3a70a 551 uint32_t result;
yihui 9:05f0b5a3a70a 552
yihui 9:05f0b5a3a70a 553 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
yihui 9:05f0b5a3a70a 554 return(result);
yihui 9:05f0b5a3a70a 555 }
yihui 9:05f0b5a3a70a 556
yihui 9:05f0b5a3a70a 557
yihui 9:05f0b5a3a70a 558 /** \brief STR Exclusive (8 bit)
yihui 9:05f0b5a3a70a 559
yihui 9:05f0b5a3a70a 560 This function performs a exclusive STR command for 8 bit values.
yihui 9:05f0b5a3a70a 561
yihui 9:05f0b5a3a70a 562 \param [in] value Value to store
yihui 9:05f0b5a3a70a 563 \param [in] ptr Pointer to location
yihui 9:05f0b5a3a70a 564 \return 0 Function succeeded
yihui 9:05f0b5a3a70a 565 \return 1 Function failed
yihui 9:05f0b5a3a70a 566 */
yihui 9:05f0b5a3a70a 567 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
yihui 9:05f0b5a3a70a 568 {
yihui 9:05f0b5a3a70a 569 uint32_t result;
yihui 9:05f0b5a3a70a 570
yihui 9:05f0b5a3a70a 571 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
yihui 9:05f0b5a3a70a 572 return(result);
yihui 9:05f0b5a3a70a 573 }
yihui 9:05f0b5a3a70a 574
yihui 9:05f0b5a3a70a 575
yihui 9:05f0b5a3a70a 576 /** \brief STR Exclusive (16 bit)
yihui 9:05f0b5a3a70a 577
yihui 9:05f0b5a3a70a 578 This function performs a exclusive STR command for 16 bit values.
yihui 9:05f0b5a3a70a 579
yihui 9:05f0b5a3a70a 580 \param [in] value Value to store
yihui 9:05f0b5a3a70a 581 \param [in] ptr Pointer to location
yihui 9:05f0b5a3a70a 582 \return 0 Function succeeded
yihui 9:05f0b5a3a70a 583 \return 1 Function failed
yihui 9:05f0b5a3a70a 584 */
yihui 9:05f0b5a3a70a 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
yihui 9:05f0b5a3a70a 586 {
yihui 9:05f0b5a3a70a 587 uint32_t result;
yihui 9:05f0b5a3a70a 588
yihui 9:05f0b5a3a70a 589 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
yihui 9:05f0b5a3a70a 590 return(result);
yihui 9:05f0b5a3a70a 591 }
yihui 9:05f0b5a3a70a 592
yihui 9:05f0b5a3a70a 593
yihui 9:05f0b5a3a70a 594 /** \brief STR Exclusive (32 bit)
yihui 9:05f0b5a3a70a 595
yihui 9:05f0b5a3a70a 596 This function performs a exclusive STR command for 32 bit values.
yihui 9:05f0b5a3a70a 597
yihui 9:05f0b5a3a70a 598 \param [in] value Value to store
yihui 9:05f0b5a3a70a 599 \param [in] ptr Pointer to location
yihui 9:05f0b5a3a70a 600 \return 0 Function succeeded
yihui 9:05f0b5a3a70a 601 \return 1 Function failed
yihui 9:05f0b5a3a70a 602 */
yihui 9:05f0b5a3a70a 603 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
yihui 9:05f0b5a3a70a 604 {
yihui 9:05f0b5a3a70a 605 uint32_t result;
yihui 9:05f0b5a3a70a 606
yihui 9:05f0b5a3a70a 607 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
yihui 9:05f0b5a3a70a 608 return(result);
yihui 9:05f0b5a3a70a 609 }
yihui 9:05f0b5a3a70a 610
yihui 9:05f0b5a3a70a 611
yihui 9:05f0b5a3a70a 612 /** \brief Remove the exclusive lock
yihui 9:05f0b5a3a70a 613
yihui 9:05f0b5a3a70a 614 This function removes the exclusive lock which is created by LDREX.
yihui 9:05f0b5a3a70a 615
yihui 9:05f0b5a3a70a 616 */
yihui 9:05f0b5a3a70a 617 __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
yihui 9:05f0b5a3a70a 618 {
yihui 9:05f0b5a3a70a 619 __ASM volatile ("clrex" ::: "memory");
yihui 9:05f0b5a3a70a 620 }
yihui 9:05f0b5a3a70a 621
yihui 9:05f0b5a3a70a 622
yihui 9:05f0b5a3a70a 623 /** \brief Signed Saturate
yihui 9:05f0b5a3a70a 624
yihui 9:05f0b5a3a70a 625 This function saturates a signed value.
yihui 9:05f0b5a3a70a 626
yihui 9:05f0b5a3a70a 627 \param [in] value Value to be saturated
yihui 9:05f0b5a3a70a 628 \param [in] sat Bit position to saturate to (1..32)
yihui 9:05f0b5a3a70a 629 \return Saturated value
yihui 9:05f0b5a3a70a 630 */
yihui 9:05f0b5a3a70a 631 #define __SSAT(ARG1,ARG2) \
yihui 9:05f0b5a3a70a 632 ({ \
yihui 9:05f0b5a3a70a 633 uint32_t __RES, __ARG1 = (ARG1); \
yihui 9:05f0b5a3a70a 634 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
yihui 9:05f0b5a3a70a 635 __RES; \
yihui 9:05f0b5a3a70a 636 })
yihui 9:05f0b5a3a70a 637
yihui 9:05f0b5a3a70a 638
yihui 9:05f0b5a3a70a 639 /** \brief Unsigned Saturate
yihui 9:05f0b5a3a70a 640
yihui 9:05f0b5a3a70a 641 This function saturates an unsigned value.
yihui 9:05f0b5a3a70a 642
yihui 9:05f0b5a3a70a 643 \param [in] value Value to be saturated
yihui 9:05f0b5a3a70a 644 \param [in] sat Bit position to saturate to (0..31)
yihui 9:05f0b5a3a70a 645 \return Saturated value
yihui 9:05f0b5a3a70a 646 */
yihui 9:05f0b5a3a70a 647 #define __USAT(ARG1,ARG2) \
yihui 9:05f0b5a3a70a 648 ({ \
yihui 9:05f0b5a3a70a 649 uint32_t __RES, __ARG1 = (ARG1); \
yihui 9:05f0b5a3a70a 650 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
yihui 9:05f0b5a3a70a 651 __RES; \
yihui 9:05f0b5a3a70a 652 })
yihui 9:05f0b5a3a70a 653
yihui 9:05f0b5a3a70a 654
yihui 9:05f0b5a3a70a 655 /** \brief Count leading zeros
yihui 9:05f0b5a3a70a 656
yihui 9:05f0b5a3a70a 657 This function counts the number of leading zeros of a data value.
yihui 9:05f0b5a3a70a 658
yihui 9:05f0b5a3a70a 659 \param [in] value Value to count the leading zeros
yihui 9:05f0b5a3a70a 660 \return number of leading zeros in value
yihui 9:05f0b5a3a70a 661 */
yihui 9:05f0b5a3a70a 662 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
yihui 9:05f0b5a3a70a 663 {
yihui 9:05f0b5a3a70a 664 uint32_t result;
yihui 9:05f0b5a3a70a 665
yihui 9:05f0b5a3a70a 666 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
yihui 9:05f0b5a3a70a 667 return(result);
yihui 9:05f0b5a3a70a 668 }
yihui 9:05f0b5a3a70a 669
yihui 9:05f0b5a3a70a 670 #endif /* (__CORTEX_M >= 0x03) */
yihui 9:05f0b5a3a70a 671
yihui 9:05f0b5a3a70a 672
yihui 9:05f0b5a3a70a 673
yihui 9:05f0b5a3a70a 674
yihui 9:05f0b5a3a70a 675 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
yihui 9:05f0b5a3a70a 676 /* TASKING carm specific functions */
yihui 9:05f0b5a3a70a 677
yihui 9:05f0b5a3a70a 678 /*
yihui 9:05f0b5a3a70a 679 * The CMSIS functions have been implemented as intrinsics in the compiler.
yihui 9:05f0b5a3a70a 680 * Please use "carm -?i" to get an up to date list of all intrinsics,
yihui 9:05f0b5a3a70a 681 * Including the CMSIS ones.
yihui 9:05f0b5a3a70a 682 */
yihui 9:05f0b5a3a70a 683
yihui 9:05f0b5a3a70a 684 #endif
yihui 9:05f0b5a3a70a 685
yihui 9:05f0b5a3a70a 686 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
yihui 9:05f0b5a3a70a 687
yihui 9:05f0b5a3a70a 688 #endif /* __CORE_CMINSTR_H */