Yihui Xiong / BLE_NODE_TEST

Test code for Grove Node BLE

Dependencies:   BLE_API nRF51822

Fork of BLE_LoopbackUART by Bluetooth Low Energy

mbed-src/targets/cmsis/core_cmFunc.h@10:22480ac31879, 2014-11-27 (annotated)

Committer:
yihui
Date:
Thu Nov 27 09:30:36 2014 +0000
Revision:
10:22480ac31879
Parent:
9:05f0b5a3a70a 
change to new revision hardware

Who changed what in which revision?

UserRevisionLine numberNew contents of line
yihui 9:05f0b5a3a70a 1 /**************************************************************************//**
yihui 9:05f0b5a3a70a 2 * @file core_cmFunc.h
yihui 9:05f0b5a3a70a 3 * @brief CMSIS Cortex-M Core Function Access Header File
yihui 9:05f0b5a3a70a 4 * @version V3.20
yihui 9:05f0b5a3a70a 5 * @date 25. February 2013
yihui 9:05f0b5a3a70a 6 *
yihui 9:05f0b5a3a70a 7 * @note
yihui 9:05f0b5a3a70a 8 *
yihui 9:05f0b5a3a70a 9 ******************************************************************************/
yihui 9:05f0b5a3a70a 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
yihui 9:05f0b5a3a70a 11
yihui 9:05f0b5a3a70a 12 All rights reserved.
yihui 9:05f0b5a3a70a 13 Redistribution and use in source and binary forms, with or without
yihui 9:05f0b5a3a70a 14 modification, are permitted provided that the following conditions are met:
yihui 9:05f0b5a3a70a 15 - Redistributions of source code must retain the above copyright
yihui 9:05f0b5a3a70a 16 notice, this list of conditions and the following disclaimer.
yihui 9:05f0b5a3a70a 17 - Redistributions in binary form must reproduce the above copyright
yihui 9:05f0b5a3a70a 18 notice, this list of conditions and the following disclaimer in the
yihui 9:05f0b5a3a70a 19 documentation and/or other materials provided with the distribution.
yihui 9:05f0b5a3a70a 20 - Neither the name of ARM nor the names of its contributors may be used
yihui 9:05f0b5a3a70a 21 to endorse or promote products derived from this software without
yihui 9:05f0b5a3a70a 22 specific prior written permission.
yihui 9:05f0b5a3a70a 23 *
yihui 9:05f0b5a3a70a 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
yihui 9:05f0b5a3a70a 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
yihui 9:05f0b5a3a70a 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
yihui 9:05f0b5a3a70a 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
yihui 9:05f0b5a3a70a 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
yihui 9:05f0b5a3a70a 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
yihui 9:05f0b5a3a70a 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
yihui 9:05f0b5a3a70a 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
yihui 9:05f0b5a3a70a 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
yihui 9:05f0b5a3a70a 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
yihui 9:05f0b5a3a70a 34 POSSIBILITY OF SUCH DAMAGE.
yihui 9:05f0b5a3a70a 35 ---------------------------------------------------------------------------*/
yihui 9:05f0b5a3a70a 36
yihui 9:05f0b5a3a70a 37
yihui 9:05f0b5a3a70a 38 #ifndef __CORE_CMFUNC_H
yihui 9:05f0b5a3a70a 39 #define __CORE_CMFUNC_H
yihui 9:05f0b5a3a70a 40
yihui 9:05f0b5a3a70a 41
yihui 9:05f0b5a3a70a 42 /* ########################### Core Function Access ########################### */
yihui 9:05f0b5a3a70a 43 /** \ingroup CMSIS_Core_FunctionInterface
yihui 9:05f0b5a3a70a 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
yihui 9:05f0b5a3a70a 45 @{
yihui 9:05f0b5a3a70a 46 */
yihui 9:05f0b5a3a70a 47
yihui 9:05f0b5a3a70a 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
yihui 9:05f0b5a3a70a 49 /* ARM armcc specific functions */
yihui 9:05f0b5a3a70a 50
yihui 9:05f0b5a3a70a 51 #if (__ARMCC_VERSION < 400677)
yihui 9:05f0b5a3a70a 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
yihui 9:05f0b5a3a70a 53 #endif
yihui 9:05f0b5a3a70a 54
yihui 9:05f0b5a3a70a 55 /* intrinsic void __enable_irq(); */
yihui 9:05f0b5a3a70a 56 /* intrinsic void __disable_irq(); */
yihui 9:05f0b5a3a70a 57
yihui 9:05f0b5a3a70a 58 /** \brief Get Control Register
yihui 9:05f0b5a3a70a 59
yihui 9:05f0b5a3a70a 60 This function returns the content of the Control Register.
yihui 9:05f0b5a3a70a 61
yihui 9:05f0b5a3a70a 62 \return Control Register value
yihui 9:05f0b5a3a70a 63 */
yihui 9:05f0b5a3a70a 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
yihui 9:05f0b5a3a70a 65 {
yihui 9:05f0b5a3a70a 66 register uint32_t __regControl __ASM("control");
yihui 9:05f0b5a3a70a 67 return(__regControl);
yihui 9:05f0b5a3a70a 68 }
yihui 9:05f0b5a3a70a 69
yihui 9:05f0b5a3a70a 70
yihui 9:05f0b5a3a70a 71 /** \brief Set Control Register
yihui 9:05f0b5a3a70a 72
yihui 9:05f0b5a3a70a 73 This function writes the given value to the Control Register.
yihui 9:05f0b5a3a70a 74
yihui 9:05f0b5a3a70a 75 \param [in] control Control Register value to set
yihui 9:05f0b5a3a70a 76 */
yihui 9:05f0b5a3a70a 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
yihui 9:05f0b5a3a70a 78 {
yihui 9:05f0b5a3a70a 79 register uint32_t __regControl __ASM("control");
yihui 9:05f0b5a3a70a 80 __regControl = control;
yihui 9:05f0b5a3a70a 81 }
yihui 9:05f0b5a3a70a 82
yihui 9:05f0b5a3a70a 83
yihui 9:05f0b5a3a70a 84 /** \brief Get IPSR Register
yihui 9:05f0b5a3a70a 85
yihui 9:05f0b5a3a70a 86 This function returns the content of the IPSR Register.
yihui 9:05f0b5a3a70a 87
yihui 9:05f0b5a3a70a 88 \return IPSR Register value
yihui 9:05f0b5a3a70a 89 */
yihui 9:05f0b5a3a70a 90 __STATIC_INLINE uint32_t __get_IPSR(void)
yihui 9:05f0b5a3a70a 91 {
yihui 9:05f0b5a3a70a 92 register uint32_t __regIPSR __ASM("ipsr");
yihui 9:05f0b5a3a70a 93 return(__regIPSR);
yihui 9:05f0b5a3a70a 94 }
yihui 9:05f0b5a3a70a 95
yihui 9:05f0b5a3a70a 96
yihui 9:05f0b5a3a70a 97 /** \brief Get APSR Register
yihui 9:05f0b5a3a70a 98
yihui 9:05f0b5a3a70a 99 This function returns the content of the APSR Register.
yihui 9:05f0b5a3a70a 100
yihui 9:05f0b5a3a70a 101 \return APSR Register value
yihui 9:05f0b5a3a70a 102 */
yihui 9:05f0b5a3a70a 103 __STATIC_INLINE uint32_t __get_APSR(void)
yihui 9:05f0b5a3a70a 104 {
yihui 9:05f0b5a3a70a 105 register uint32_t __regAPSR __ASM("apsr");
yihui 9:05f0b5a3a70a 106 return(__regAPSR);
yihui 9:05f0b5a3a70a 107 }
yihui 9:05f0b5a3a70a 108
yihui 9:05f0b5a3a70a 109
yihui 9:05f0b5a3a70a 110 /** \brief Get xPSR Register
yihui 9:05f0b5a3a70a 111
yihui 9:05f0b5a3a70a 112 This function returns the content of the xPSR Register.
yihui 9:05f0b5a3a70a 113
yihui 9:05f0b5a3a70a 114 \return xPSR Register value
yihui 9:05f0b5a3a70a 115 */
yihui 9:05f0b5a3a70a 116 __STATIC_INLINE uint32_t __get_xPSR(void)
yihui 9:05f0b5a3a70a 117 {
yihui 9:05f0b5a3a70a 118 register uint32_t __regXPSR __ASM("xpsr");
yihui 9:05f0b5a3a70a 119 return(__regXPSR);
yihui 9:05f0b5a3a70a 120 }
yihui 9:05f0b5a3a70a 121
yihui 9:05f0b5a3a70a 122
yihui 9:05f0b5a3a70a 123 /** \brief Get Process Stack Pointer
yihui 9:05f0b5a3a70a 124
yihui 9:05f0b5a3a70a 125 This function returns the current value of the Process Stack Pointer (PSP).
yihui 9:05f0b5a3a70a 126
yihui 9:05f0b5a3a70a 127 \return PSP Register value
yihui 9:05f0b5a3a70a 128 */
yihui 9:05f0b5a3a70a 129 __STATIC_INLINE uint32_t __get_PSP(void)
yihui 9:05f0b5a3a70a 130 {
yihui 9:05f0b5a3a70a 131 register uint32_t __regProcessStackPointer __ASM("psp");
yihui 9:05f0b5a3a70a 132 return(__regProcessStackPointer);
yihui 9:05f0b5a3a70a 133 }
yihui 9:05f0b5a3a70a 134
yihui 9:05f0b5a3a70a 135
yihui 9:05f0b5a3a70a 136 /** \brief Set Process Stack Pointer
yihui 9:05f0b5a3a70a 137
yihui 9:05f0b5a3a70a 138 This function assigns the given value to the Process Stack Pointer (PSP).
yihui 9:05f0b5a3a70a 139
yihui 9:05f0b5a3a70a 140 \param [in] topOfProcStack Process Stack Pointer value to set
yihui 9:05f0b5a3a70a 141 */
yihui 9:05f0b5a3a70a 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
yihui 9:05f0b5a3a70a 143 {
yihui 9:05f0b5a3a70a 144 register uint32_t __regProcessStackPointer __ASM("psp");
yihui 9:05f0b5a3a70a 145 __regProcessStackPointer = topOfProcStack;
yihui 9:05f0b5a3a70a 146 }
yihui 9:05f0b5a3a70a 147
yihui 9:05f0b5a3a70a 148
yihui 9:05f0b5a3a70a 149 /** \brief Get Main Stack Pointer
yihui 9:05f0b5a3a70a 150
yihui 9:05f0b5a3a70a 151 This function returns the current value of the Main Stack Pointer (MSP).
yihui 9:05f0b5a3a70a 152
yihui 9:05f0b5a3a70a 153 \return MSP Register value
yihui 9:05f0b5a3a70a 154 */
yihui 9:05f0b5a3a70a 155 __STATIC_INLINE uint32_t __get_MSP(void)
yihui 9:05f0b5a3a70a 156 {
yihui 9:05f0b5a3a70a 157 register uint32_t __regMainStackPointer __ASM("msp");
yihui 9:05f0b5a3a70a 158 return(__regMainStackPointer);
yihui 9:05f0b5a3a70a 159 }
yihui 9:05f0b5a3a70a 160
yihui 9:05f0b5a3a70a 161
yihui 9:05f0b5a3a70a 162 /** \brief Set Main Stack Pointer
yihui 9:05f0b5a3a70a 163
yihui 9:05f0b5a3a70a 164 This function assigns the given value to the Main Stack Pointer (MSP).
yihui 9:05f0b5a3a70a 165
yihui 9:05f0b5a3a70a 166 \param [in] topOfMainStack Main Stack Pointer value to set
yihui 9:05f0b5a3a70a 167 */
yihui 9:05f0b5a3a70a 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
yihui 9:05f0b5a3a70a 169 {
yihui 9:05f0b5a3a70a 170 register uint32_t __regMainStackPointer __ASM("msp");
yihui 9:05f0b5a3a70a 171 __regMainStackPointer = topOfMainStack;
yihui 9:05f0b5a3a70a 172 }
yihui 9:05f0b5a3a70a 173
yihui 9:05f0b5a3a70a 174
yihui 9:05f0b5a3a70a 175 /** \brief Get Priority Mask
yihui 9:05f0b5a3a70a 176
yihui 9:05f0b5a3a70a 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
yihui 9:05f0b5a3a70a 178
yihui 9:05f0b5a3a70a 179 \return Priority Mask value
yihui 9:05f0b5a3a70a 180 */
yihui 9:05f0b5a3a70a 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
yihui 9:05f0b5a3a70a 182 {
yihui 9:05f0b5a3a70a 183 register uint32_t __regPriMask __ASM("primask");
yihui 9:05f0b5a3a70a 184 return(__regPriMask);
yihui 9:05f0b5a3a70a 185 }
yihui 9:05f0b5a3a70a 186
yihui 9:05f0b5a3a70a 187
yihui 9:05f0b5a3a70a 188 /** \brief Set Priority Mask
yihui 9:05f0b5a3a70a 189
yihui 9:05f0b5a3a70a 190 This function assigns the given value to the Priority Mask Register.
yihui 9:05f0b5a3a70a 191
yihui 9:05f0b5a3a70a 192 \param [in] priMask Priority Mask
yihui 9:05f0b5a3a70a 193 */
yihui 9:05f0b5a3a70a 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
yihui 9:05f0b5a3a70a 195 {
yihui 9:05f0b5a3a70a 196 register uint32_t __regPriMask __ASM("primask");
yihui 9:05f0b5a3a70a 197 __regPriMask = (priMask);
yihui 9:05f0b5a3a70a 198 }
yihui 9:05f0b5a3a70a 199
yihui 9:05f0b5a3a70a 200
yihui 9:05f0b5a3a70a 201 #if (__CORTEX_M >= 0x03)
yihui 9:05f0b5a3a70a 202
yihui 9:05f0b5a3a70a 203 /** \brief Enable FIQ
yihui 9:05f0b5a3a70a 204
yihui 9:05f0b5a3a70a 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
yihui 9:05f0b5a3a70a 206 Can only be executed in Privileged modes.
yihui 9:05f0b5a3a70a 207 */
yihui 9:05f0b5a3a70a 208 #define __enable_fault_irq __enable_fiq
yihui 9:05f0b5a3a70a 209
yihui 9:05f0b5a3a70a 210
yihui 9:05f0b5a3a70a 211 /** \brief Disable FIQ
yihui 9:05f0b5a3a70a 212
yihui 9:05f0b5a3a70a 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
yihui 9:05f0b5a3a70a 214 Can only be executed in Privileged modes.
yihui 9:05f0b5a3a70a 215 */
yihui 9:05f0b5a3a70a 216 #define __disable_fault_irq __disable_fiq
yihui 9:05f0b5a3a70a 217
yihui 9:05f0b5a3a70a 218
yihui 9:05f0b5a3a70a 219 /** \brief Get Base Priority
yihui 9:05f0b5a3a70a 220
yihui 9:05f0b5a3a70a 221 This function returns the current value of the Base Priority register.
yihui 9:05f0b5a3a70a 222
yihui 9:05f0b5a3a70a 223 \return Base Priority register value
yihui 9:05f0b5a3a70a 224 */
yihui 9:05f0b5a3a70a 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
yihui 9:05f0b5a3a70a 226 {
yihui 9:05f0b5a3a70a 227 register uint32_t __regBasePri __ASM("basepri");
yihui 9:05f0b5a3a70a 228 return(__regBasePri);
yihui 9:05f0b5a3a70a 229 }
yihui 9:05f0b5a3a70a 230
yihui 9:05f0b5a3a70a 231
yihui 9:05f0b5a3a70a 232 /** \brief Set Base Priority
yihui 9:05f0b5a3a70a 233
yihui 9:05f0b5a3a70a 234 This function assigns the given value to the Base Priority register.
yihui 9:05f0b5a3a70a 235
yihui 9:05f0b5a3a70a 236 \param [in] basePri Base Priority value to set
yihui 9:05f0b5a3a70a 237 */
yihui 9:05f0b5a3a70a 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
yihui 9:05f0b5a3a70a 239 {
yihui 9:05f0b5a3a70a 240 register uint32_t __regBasePri __ASM("basepri");
yihui 9:05f0b5a3a70a 241 __regBasePri = (basePri & 0xff);
yihui 9:05f0b5a3a70a 242 }
yihui 9:05f0b5a3a70a 243
yihui 9:05f0b5a3a70a 244
yihui 9:05f0b5a3a70a 245 /** \brief Get Fault Mask
yihui 9:05f0b5a3a70a 246
yihui 9:05f0b5a3a70a 247 This function returns the current value of the Fault Mask register.
yihui 9:05f0b5a3a70a 248
yihui 9:05f0b5a3a70a 249 \return Fault Mask register value
yihui 9:05f0b5a3a70a 250 */
yihui 9:05f0b5a3a70a 251 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
yihui 9:05f0b5a3a70a 252 {
yihui 9:05f0b5a3a70a 253 register uint32_t __regFaultMask __ASM("faultmask");
yihui 9:05f0b5a3a70a 254 return(__regFaultMask);
yihui 9:05f0b5a3a70a 255 }
yihui 9:05f0b5a3a70a 256
yihui 9:05f0b5a3a70a 257
yihui 9:05f0b5a3a70a 258 /** \brief Set Fault Mask
yihui 9:05f0b5a3a70a 259
yihui 9:05f0b5a3a70a 260 This function assigns the given value to the Fault Mask register.
yihui 9:05f0b5a3a70a 261
yihui 9:05f0b5a3a70a 262 \param [in] faultMask Fault Mask value to set
yihui 9:05f0b5a3a70a 263 */
yihui 9:05f0b5a3a70a 264 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
yihui 9:05f0b5a3a70a 265 {
yihui 9:05f0b5a3a70a 266 register uint32_t __regFaultMask __ASM("faultmask");
yihui 9:05f0b5a3a70a 267 __regFaultMask = (faultMask & (uint32_t)1);
yihui 9:05f0b5a3a70a 268 }
yihui 9:05f0b5a3a70a 269
yihui 9:05f0b5a3a70a 270 #endif /* (__CORTEX_M >= 0x03) */
yihui 9:05f0b5a3a70a 271
yihui 9:05f0b5a3a70a 272
yihui 9:05f0b5a3a70a 273 #if (__CORTEX_M == 0x04)
yihui 9:05f0b5a3a70a 274
yihui 9:05f0b5a3a70a 275 /** \brief Get FPSCR
yihui 9:05f0b5a3a70a 276
yihui 9:05f0b5a3a70a 277 This function returns the current value of the Floating Point Status/Control register.
yihui 9:05f0b5a3a70a 278
yihui 9:05f0b5a3a70a 279 \return Floating Point Status/Control register value
yihui 9:05f0b5a3a70a 280 */
yihui 9:05f0b5a3a70a 281 __STATIC_INLINE uint32_t __get_FPSCR(void)
yihui 9:05f0b5a3a70a 282 {
yihui 9:05f0b5a3a70a 283 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
yihui 9:05f0b5a3a70a 284 register uint32_t __regfpscr __ASM("fpscr");
yihui 9:05f0b5a3a70a 285 return(__regfpscr);
yihui 9:05f0b5a3a70a 286 #else
yihui 9:05f0b5a3a70a 287 return(0);
yihui 9:05f0b5a3a70a 288 #endif
yihui 9:05f0b5a3a70a 289 }
yihui 9:05f0b5a3a70a 290
yihui 9:05f0b5a3a70a 291
yihui 9:05f0b5a3a70a 292 /** \brief Set FPSCR
yihui 9:05f0b5a3a70a 293
yihui 9:05f0b5a3a70a 294 This function assigns the given value to the Floating Point Status/Control register.
yihui 9:05f0b5a3a70a 295
yihui 9:05f0b5a3a70a 296 \param [in] fpscr Floating Point Status/Control value to set
yihui 9:05f0b5a3a70a 297 */
yihui 9:05f0b5a3a70a 298 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
yihui 9:05f0b5a3a70a 299 {
yihui 9:05f0b5a3a70a 300 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
yihui 9:05f0b5a3a70a 301 register uint32_t __regfpscr __ASM("fpscr");
yihui 9:05f0b5a3a70a 302 __regfpscr = (fpscr);
yihui 9:05f0b5a3a70a 303 #endif
yihui 9:05f0b5a3a70a 304 }
yihui 9:05f0b5a3a70a 305
yihui 9:05f0b5a3a70a 306 #endif /* (__CORTEX_M == 0x04) */
yihui 9:05f0b5a3a70a 307
yihui 9:05f0b5a3a70a 308
yihui 9:05f0b5a3a70a 309 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
yihui 9:05f0b5a3a70a 310 /* IAR iccarm specific functions */
yihui 9:05f0b5a3a70a 311
yihui 9:05f0b5a3a70a 312 #include <cmsis_iar.h>
yihui 9:05f0b5a3a70a 313
yihui 9:05f0b5a3a70a 314
yihui 9:05f0b5a3a70a 315 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
yihui 9:05f0b5a3a70a 316 /* TI CCS specific functions */
yihui 9:05f0b5a3a70a 317
yihui 9:05f0b5a3a70a 318 #include <cmsis_ccs.h>
yihui 9:05f0b5a3a70a 319
yihui 9:05f0b5a3a70a 320
yihui 9:05f0b5a3a70a 321 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
yihui 9:05f0b5a3a70a 322 /* GNU gcc specific functions */
yihui 9:05f0b5a3a70a 323
yihui 9:05f0b5a3a70a 324 /** \brief Enable IRQ Interrupts
yihui 9:05f0b5a3a70a 325
yihui 9:05f0b5a3a70a 326 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
yihui 9:05f0b5a3a70a 327 Can only be executed in Privileged modes.
yihui 9:05f0b5a3a70a 328 */
yihui 9:05f0b5a3a70a 329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
yihui 9:05f0b5a3a70a 330 {
yihui 9:05f0b5a3a70a 331 __ASM volatile ("cpsie i" : : : "memory");
yihui 9:05f0b5a3a70a 332 }
yihui 9:05f0b5a3a70a 333
yihui 9:05f0b5a3a70a 334
yihui 9:05f0b5a3a70a 335 /** \brief Disable IRQ Interrupts
yihui 9:05f0b5a3a70a 336
yihui 9:05f0b5a3a70a 337 This function disables IRQ interrupts by setting the I-bit in the CPSR.
yihui 9:05f0b5a3a70a 338 Can only be executed in Privileged modes.
yihui 9:05f0b5a3a70a 339 */
yihui 9:05f0b5a3a70a 340 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
yihui 9:05f0b5a3a70a 341 {
yihui 9:05f0b5a3a70a 342 __ASM volatile ("cpsid i" : : : "memory");
yihui 9:05f0b5a3a70a 343 }
yihui 9:05f0b5a3a70a 344
yihui 9:05f0b5a3a70a 345
yihui 9:05f0b5a3a70a 346 /** \brief Get Control Register
yihui 9:05f0b5a3a70a 347
yihui 9:05f0b5a3a70a 348 This function returns the content of the Control Register.
yihui 9:05f0b5a3a70a 349
yihui 9:05f0b5a3a70a 350 \return Control Register value
yihui 9:05f0b5a3a70a 351 */
yihui 9:05f0b5a3a70a 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
yihui 9:05f0b5a3a70a 353 {
yihui 9:05f0b5a3a70a 354 uint32_t result;
yihui 9:05f0b5a3a70a 355
yihui 9:05f0b5a3a70a 356 __ASM volatile ("MRS %0, control" : "=r" (result) );
yihui 9:05f0b5a3a70a 357 return(result);
yihui 9:05f0b5a3a70a 358 }
yihui 9:05f0b5a3a70a 359
yihui 9:05f0b5a3a70a 360
yihui 9:05f0b5a3a70a 361 /** \brief Set Control Register
yihui 9:05f0b5a3a70a 362
yihui 9:05f0b5a3a70a 363 This function writes the given value to the Control Register.
yihui 9:05f0b5a3a70a 364
yihui 9:05f0b5a3a70a 365 \param [in] control Control Register value to set
yihui 9:05f0b5a3a70a 366 */
yihui 9:05f0b5a3a70a 367 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
yihui 9:05f0b5a3a70a 368 {
yihui 9:05f0b5a3a70a 369 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
yihui 9:05f0b5a3a70a 370 }
yihui 9:05f0b5a3a70a 371
yihui 9:05f0b5a3a70a 372
yihui 9:05f0b5a3a70a 373 /** \brief Get IPSR Register
yihui 9:05f0b5a3a70a 374
yihui 9:05f0b5a3a70a 375 This function returns the content of the IPSR Register.
yihui 9:05f0b5a3a70a 376
yihui 9:05f0b5a3a70a 377 \return IPSR Register value
yihui 9:05f0b5a3a70a 378 */
yihui 9:05f0b5a3a70a 379 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
yihui 9:05f0b5a3a70a 380 {
yihui 9:05f0b5a3a70a 381 uint32_t result;
yihui 9:05f0b5a3a70a 382
yihui 9:05f0b5a3a70a 383 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
yihui 9:05f0b5a3a70a 384 return(result);
yihui 9:05f0b5a3a70a 385 }
yihui 9:05f0b5a3a70a 386
yihui 9:05f0b5a3a70a 387
yihui 9:05f0b5a3a70a 388 /** \brief Get APSR Register
yihui 9:05f0b5a3a70a 389
yihui 9:05f0b5a3a70a 390 This function returns the content of the APSR Register.
yihui 9:05f0b5a3a70a 391
yihui 9:05f0b5a3a70a 392 \return APSR Register value
yihui 9:05f0b5a3a70a 393 */
yihui 9:05f0b5a3a70a 394 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
yihui 9:05f0b5a3a70a 395 {
yihui 9:05f0b5a3a70a 396 uint32_t result;
yihui 9:05f0b5a3a70a 397
yihui 9:05f0b5a3a70a 398 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
yihui 9:05f0b5a3a70a 399 return(result);
yihui 9:05f0b5a3a70a 400 }
yihui 9:05f0b5a3a70a 401
yihui 9:05f0b5a3a70a 402
yihui 9:05f0b5a3a70a 403 /** \brief Get xPSR Register
yihui 9:05f0b5a3a70a 404
yihui 9:05f0b5a3a70a 405 This function returns the content of the xPSR Register.
yihui 9:05f0b5a3a70a 406
yihui 9:05f0b5a3a70a 407 \return xPSR Register value
yihui 9:05f0b5a3a70a 408 */
yihui 9:05f0b5a3a70a 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
yihui 9:05f0b5a3a70a 410 {
yihui 9:05f0b5a3a70a 411 uint32_t result;
yihui 9:05f0b5a3a70a 412
yihui 9:05f0b5a3a70a 413 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
yihui 9:05f0b5a3a70a 414 return(result);
yihui 9:05f0b5a3a70a 415 }
yihui 9:05f0b5a3a70a 416
yihui 9:05f0b5a3a70a 417
yihui 9:05f0b5a3a70a 418 /** \brief Get Process Stack Pointer
yihui 9:05f0b5a3a70a 419
yihui 9:05f0b5a3a70a 420 This function returns the current value of the Process Stack Pointer (PSP).
yihui 9:05f0b5a3a70a 421
yihui 9:05f0b5a3a70a 422 \return PSP Register value
yihui 9:05f0b5a3a70a 423 */
yihui 9:05f0b5a3a70a 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
yihui 9:05f0b5a3a70a 425 {
yihui 9:05f0b5a3a70a 426 register uint32_t result;
yihui 9:05f0b5a3a70a 427
yihui 9:05f0b5a3a70a 428 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
yihui 9:05f0b5a3a70a 429 return(result);
yihui 9:05f0b5a3a70a 430 }
yihui 9:05f0b5a3a70a 431
yihui 9:05f0b5a3a70a 432
yihui 9:05f0b5a3a70a 433 /** \brief Set Process Stack Pointer
yihui 9:05f0b5a3a70a 434
yihui 9:05f0b5a3a70a 435 This function assigns the given value to the Process Stack Pointer (PSP).
yihui 9:05f0b5a3a70a 436
yihui 9:05f0b5a3a70a 437 \param [in] topOfProcStack Process Stack Pointer value to set
yihui 9:05f0b5a3a70a 438 */
yihui 9:05f0b5a3a70a 439 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
yihui 9:05f0b5a3a70a 440 {
yihui 9:05f0b5a3a70a 441 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
yihui 9:05f0b5a3a70a 442 }
yihui 9:05f0b5a3a70a 443
yihui 9:05f0b5a3a70a 444
yihui 9:05f0b5a3a70a 445 /** \brief Get Main Stack Pointer
yihui 9:05f0b5a3a70a 446
yihui 9:05f0b5a3a70a 447 This function returns the current value of the Main Stack Pointer (MSP).
yihui 9:05f0b5a3a70a 448
yihui 9:05f0b5a3a70a 449 \return MSP Register value
yihui 9:05f0b5a3a70a 450 */
yihui 9:05f0b5a3a70a 451 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
yihui 9:05f0b5a3a70a 452 {
yihui 9:05f0b5a3a70a 453 register uint32_t result;
yihui 9:05f0b5a3a70a 454
yihui 9:05f0b5a3a70a 455 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
yihui 9:05f0b5a3a70a 456 return(result);
yihui 9:05f0b5a3a70a 457 }
yihui 9:05f0b5a3a70a 458
yihui 9:05f0b5a3a70a 459
yihui 9:05f0b5a3a70a 460 /** \brief Set Main Stack Pointer
yihui 9:05f0b5a3a70a 461
yihui 9:05f0b5a3a70a 462 This function assigns the given value to the Main Stack Pointer (MSP).
yihui 9:05f0b5a3a70a 463
yihui 9:05f0b5a3a70a 464 \param [in] topOfMainStack Main Stack Pointer value to set
yihui 9:05f0b5a3a70a 465 */
yihui 9:05f0b5a3a70a 466 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
yihui 9:05f0b5a3a70a 467 {
yihui 9:05f0b5a3a70a 468 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
yihui 9:05f0b5a3a70a 469 }
yihui 9:05f0b5a3a70a 470
yihui 9:05f0b5a3a70a 471
yihui 9:05f0b5a3a70a 472 /** \brief Get Priority Mask
yihui 9:05f0b5a3a70a 473
yihui 9:05f0b5a3a70a 474 This function returns the current state of the priority mask bit from the Priority Mask Register.
yihui 9:05f0b5a3a70a 475
yihui 9:05f0b5a3a70a 476 \return Priority Mask value
yihui 9:05f0b5a3a70a 477 */
yihui 9:05f0b5a3a70a 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
yihui 9:05f0b5a3a70a 479 {
yihui 9:05f0b5a3a70a 480 uint32_t result;
yihui 9:05f0b5a3a70a 481
yihui 9:05f0b5a3a70a 482 __ASM volatile ("MRS %0, primask" : "=r" (result) );
yihui 9:05f0b5a3a70a 483 return(result);
yihui 9:05f0b5a3a70a 484 }
yihui 9:05f0b5a3a70a 485
yihui 9:05f0b5a3a70a 486
yihui 9:05f0b5a3a70a 487 /** \brief Set Priority Mask
yihui 9:05f0b5a3a70a 488
yihui 9:05f0b5a3a70a 489 This function assigns the given value to the Priority Mask Register.
yihui 9:05f0b5a3a70a 490
yihui 9:05f0b5a3a70a 491 \param [in] priMask Priority Mask
yihui 9:05f0b5a3a70a 492 */
yihui 9:05f0b5a3a70a 493 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
yihui 9:05f0b5a3a70a 494 {
yihui 9:05f0b5a3a70a 495 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
yihui 9:05f0b5a3a70a 496 }
yihui 9:05f0b5a3a70a 497
yihui 9:05f0b5a3a70a 498
yihui 9:05f0b5a3a70a 499 #if (__CORTEX_M >= 0x03)
yihui 9:05f0b5a3a70a 500
yihui 9:05f0b5a3a70a 501 /** \brief Enable FIQ
yihui 9:05f0b5a3a70a 502
yihui 9:05f0b5a3a70a 503 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
yihui 9:05f0b5a3a70a 504 Can only be executed in Privileged modes.
yihui 9:05f0b5a3a70a 505 */
yihui 9:05f0b5a3a70a 506 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
yihui 9:05f0b5a3a70a 507 {
yihui 9:05f0b5a3a70a 508 __ASM volatile ("cpsie f" : : : "memory");
yihui 9:05f0b5a3a70a 509 }
yihui 9:05f0b5a3a70a 510
yihui 9:05f0b5a3a70a 511
yihui 9:05f0b5a3a70a 512 /** \brief Disable FIQ
yihui 9:05f0b5a3a70a 513
yihui 9:05f0b5a3a70a 514 This function disables FIQ interrupts by setting the F-bit in the CPSR.
yihui 9:05f0b5a3a70a 515 Can only be executed in Privileged modes.
yihui 9:05f0b5a3a70a 516 */
yihui 9:05f0b5a3a70a 517 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
yihui 9:05f0b5a3a70a 518 {
yihui 9:05f0b5a3a70a 519 __ASM volatile ("cpsid f" : : : "memory");
yihui 9:05f0b5a3a70a 520 }
yihui 9:05f0b5a3a70a 521
yihui 9:05f0b5a3a70a 522
yihui 9:05f0b5a3a70a 523 /** \brief Get Base Priority
yihui 9:05f0b5a3a70a 524
yihui 9:05f0b5a3a70a 525 This function returns the current value of the Base Priority register.
yihui 9:05f0b5a3a70a 526
yihui 9:05f0b5a3a70a 527 \return Base Priority register value
yihui 9:05f0b5a3a70a 528 */
yihui 9:05f0b5a3a70a 529 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
yihui 9:05f0b5a3a70a 530 {
yihui 9:05f0b5a3a70a 531 uint32_t result;
yihui 9:05f0b5a3a70a 532
yihui 9:05f0b5a3a70a 533 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
yihui 9:05f0b5a3a70a 534 return(result);
yihui 9:05f0b5a3a70a 535 }
yihui 9:05f0b5a3a70a 536
yihui 9:05f0b5a3a70a 537
yihui 9:05f0b5a3a70a 538 /** \brief Set Base Priority
yihui 9:05f0b5a3a70a 539
yihui 9:05f0b5a3a70a 540 This function assigns the given value to the Base Priority register.
yihui 9:05f0b5a3a70a 541
yihui 9:05f0b5a3a70a 542 \param [in] basePri Base Priority value to set
yihui 9:05f0b5a3a70a 543 */
yihui 9:05f0b5a3a70a 544 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
yihui 9:05f0b5a3a70a 545 {
yihui 9:05f0b5a3a70a 546 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
yihui 9:05f0b5a3a70a 547 }
yihui 9:05f0b5a3a70a 548
yihui 9:05f0b5a3a70a 549
yihui 9:05f0b5a3a70a 550 /** \brief Get Fault Mask
yihui 9:05f0b5a3a70a 551
yihui 9:05f0b5a3a70a 552 This function returns the current value of the Fault Mask register.
yihui 9:05f0b5a3a70a 553
yihui 9:05f0b5a3a70a 554 \return Fault Mask register value
yihui 9:05f0b5a3a70a 555 */
yihui 9:05f0b5a3a70a 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
yihui 9:05f0b5a3a70a 557 {
yihui 9:05f0b5a3a70a 558 uint32_t result;
yihui 9:05f0b5a3a70a 559
yihui 9:05f0b5a3a70a 560 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
yihui 9:05f0b5a3a70a 561 return(result);
yihui 9:05f0b5a3a70a 562 }
yihui 9:05f0b5a3a70a 563
yihui 9:05f0b5a3a70a 564
yihui 9:05f0b5a3a70a 565 /** \brief Set Fault Mask
yihui 9:05f0b5a3a70a 566
yihui 9:05f0b5a3a70a 567 This function assigns the given value to the Fault Mask register.
yihui 9:05f0b5a3a70a 568
yihui 9:05f0b5a3a70a 569 \param [in] faultMask Fault Mask value to set
yihui 9:05f0b5a3a70a 570 */
yihui 9:05f0b5a3a70a 571 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
yihui 9:05f0b5a3a70a 572 {
yihui 9:05f0b5a3a70a 573 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
yihui 9:05f0b5a3a70a 574 }
yihui 9:05f0b5a3a70a 575
yihui 9:05f0b5a3a70a 576 #endif /* (__CORTEX_M >= 0x03) */
yihui 9:05f0b5a3a70a 577
yihui 9:05f0b5a3a70a 578
yihui 9:05f0b5a3a70a 579 #if (__CORTEX_M == 0x04)
yihui 9:05f0b5a3a70a 580
yihui 9:05f0b5a3a70a 581 /** \brief Get FPSCR
yihui 9:05f0b5a3a70a 582
yihui 9:05f0b5a3a70a 583 This function returns the current value of the Floating Point Status/Control register.
yihui 9:05f0b5a3a70a 584
yihui 9:05f0b5a3a70a 585 \return Floating Point Status/Control register value
yihui 9:05f0b5a3a70a 586 */
yihui 9:05f0b5a3a70a 587 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
yihui 9:05f0b5a3a70a 588 {
yihui 9:05f0b5a3a70a 589 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
yihui 9:05f0b5a3a70a 590 uint32_t result;
yihui 9:05f0b5a3a70a 591
yihui 9:05f0b5a3a70a 592 /* Empty asm statement works as a scheduling barrier */
yihui 9:05f0b5a3a70a 593 __ASM volatile ("");
yihui 9:05f0b5a3a70a 594 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
yihui 9:05f0b5a3a70a 595 __ASM volatile ("");
yihui 9:05f0b5a3a70a 596 return(result);
yihui 9:05f0b5a3a70a 597 #else
yihui 9:05f0b5a3a70a 598 return(0);
yihui 9:05f0b5a3a70a 599 #endif
yihui 9:05f0b5a3a70a 600 }
yihui 9:05f0b5a3a70a 601
yihui 9:05f0b5a3a70a 602
yihui 9:05f0b5a3a70a 603 /** \brief Set FPSCR
yihui 9:05f0b5a3a70a 604
yihui 9:05f0b5a3a70a 605 This function assigns the given value to the Floating Point Status/Control register.
yihui 9:05f0b5a3a70a 606
yihui 9:05f0b5a3a70a 607 \param [in] fpscr Floating Point Status/Control value to set
yihui 9:05f0b5a3a70a 608 */
yihui 9:05f0b5a3a70a 609 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
yihui 9:05f0b5a3a70a 610 {
yihui 9:05f0b5a3a70a 611 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
yihui 9:05f0b5a3a70a 612 /* Empty asm statement works as a scheduling barrier */
yihui 9:05f0b5a3a70a 613 __ASM volatile ("");
yihui 9:05f0b5a3a70a 614 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
yihui 9:05f0b5a3a70a 615 __ASM volatile ("");
yihui 9:05f0b5a3a70a 616 #endif
yihui 9:05f0b5a3a70a 617 }
yihui 9:05f0b5a3a70a 618
yihui 9:05f0b5a3a70a 619 #endif /* (__CORTEX_M == 0x04) */
yihui 9:05f0b5a3a70a 620
yihui 9:05f0b5a3a70a 621
yihui 9:05f0b5a3a70a 622 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
yihui 9:05f0b5a3a70a 623 /* TASKING carm specific functions */
yihui 9:05f0b5a3a70a 624
yihui 9:05f0b5a3a70a 625 /*
yihui 9:05f0b5a3a70a 626 * The CMSIS functions have been implemented as intrinsics in the compiler.
yihui 9:05f0b5a3a70a 627 * Please use "carm -?i" to get an up to date list of all instrinsics,
yihui 9:05f0b5a3a70a 628 * Including the CMSIS ones.
yihui 9:05f0b5a3a70a 629 */
yihui 9:05f0b5a3a70a 630
yihui 9:05f0b5a3a70a 631 #endif
yihui 9:05f0b5a3a70a 632
yihui 9:05f0b5a3a70a 633 /*@} end of CMSIS_Core_RegAccFunctions */
yihui 9:05f0b5a3a70a 634
yihui 9:05f0b5a3a70a 635
yihui 9:05f0b5a3a70a 636 #endif /* __CORE_CMFUNC_H */