Yihui Xiong / BLE_NODE_TEST

Test code for Grove Node BLE

Dependencies:   BLE_API nRF51822

Fork of BLE_LoopbackUART by Bluetooth Low Energy

mbed-src/targets/cmsis/core_cm4_simd.h@10:22480ac31879, 2014-11-27 (annotated)

Committer:
yihui
Date:
Thu Nov 27 09:30:36 2014 +0000
Revision:
10:22480ac31879
Parent:
9:05f0b5a3a70a 
change to new revision hardware

Who changed what in which revision?

UserRevisionLine numberNew contents of line
yihui 9:05f0b5a3a70a 1 /**************************************************************************//**
yihui 9:05f0b5a3a70a 2 * @file core_cm4_simd.h
yihui 9:05f0b5a3a70a 3 * @brief CMSIS Cortex-M4 SIMD Header File
yihui 9:05f0b5a3a70a 4 * @version V3.20
yihui 9:05f0b5a3a70a 5 * @date 25. February 2013
yihui 9:05f0b5a3a70a 6 *
yihui 9:05f0b5a3a70a 7 * @note
yihui 9:05f0b5a3a70a 8 *
yihui 9:05f0b5a3a70a 9 ******************************************************************************/
yihui 9:05f0b5a3a70a 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
yihui 9:05f0b5a3a70a 11
yihui 9:05f0b5a3a70a 12 All rights reserved.
yihui 9:05f0b5a3a70a 13 Redistribution and use in source and binary forms, with or without
yihui 9:05f0b5a3a70a 14 modification, are permitted provided that the following conditions are met:
yihui 9:05f0b5a3a70a 15 - Redistributions of source code must retain the above copyright
yihui 9:05f0b5a3a70a 16 notice, this list of conditions and the following disclaimer.
yihui 9:05f0b5a3a70a 17 - Redistributions in binary form must reproduce the above copyright
yihui 9:05f0b5a3a70a 18 notice, this list of conditions and the following disclaimer in the
yihui 9:05f0b5a3a70a 19 documentation and/or other materials provided with the distribution.
yihui 9:05f0b5a3a70a 20 - Neither the name of ARM nor the names of its contributors may be used
yihui 9:05f0b5a3a70a 21 to endorse or promote products derived from this software without
yihui 9:05f0b5a3a70a 22 specific prior written permission.
yihui 9:05f0b5a3a70a 23 *
yihui 9:05f0b5a3a70a 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
yihui 9:05f0b5a3a70a 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
yihui 9:05f0b5a3a70a 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
yihui 9:05f0b5a3a70a 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
yihui 9:05f0b5a3a70a 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
yihui 9:05f0b5a3a70a 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
yihui 9:05f0b5a3a70a 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
yihui 9:05f0b5a3a70a 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
yihui 9:05f0b5a3a70a 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
yihui 9:05f0b5a3a70a 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
yihui 9:05f0b5a3a70a 34 POSSIBILITY OF SUCH DAMAGE.
yihui 9:05f0b5a3a70a 35 ---------------------------------------------------------------------------*/
yihui 9:05f0b5a3a70a 36
yihui 9:05f0b5a3a70a 37
yihui 9:05f0b5a3a70a 38 #ifdef __cplusplus
yihui 9:05f0b5a3a70a 39 extern "C" {
yihui 9:05f0b5a3a70a 40 #endif
yihui 9:05f0b5a3a70a 41
yihui 9:05f0b5a3a70a 42 #ifndef __CORE_CM4_SIMD_H
yihui 9:05f0b5a3a70a 43 #define __CORE_CM4_SIMD_H
yihui 9:05f0b5a3a70a 44
yihui 9:05f0b5a3a70a 45
yihui 9:05f0b5a3a70a 46 /*******************************************************************************
yihui 9:05f0b5a3a70a 47 * Hardware Abstraction Layer
yihui 9:05f0b5a3a70a 48 ******************************************************************************/
yihui 9:05f0b5a3a70a 49
yihui 9:05f0b5a3a70a 50
yihui 9:05f0b5a3a70a 51 /* ################### Compiler specific Intrinsics ########################### */
yihui 9:05f0b5a3a70a 52 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
yihui 9:05f0b5a3a70a 53 Access to dedicated SIMD instructions
yihui 9:05f0b5a3a70a 54 @{
yihui 9:05f0b5a3a70a 55 */
yihui 9:05f0b5a3a70a 56
yihui 9:05f0b5a3a70a 57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
yihui 9:05f0b5a3a70a 58 /* ARM armcc specific functions */
yihui 9:05f0b5a3a70a 59
yihui 9:05f0b5a3a70a 60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
yihui 9:05f0b5a3a70a 61 #define __SADD8 __sadd8
yihui 9:05f0b5a3a70a 62 #define __QADD8 __qadd8
yihui 9:05f0b5a3a70a 63 #define __SHADD8 __shadd8
yihui 9:05f0b5a3a70a 64 #define __UADD8 __uadd8
yihui 9:05f0b5a3a70a 65 #define __UQADD8 __uqadd8
yihui 9:05f0b5a3a70a 66 #define __UHADD8 __uhadd8
yihui 9:05f0b5a3a70a 67 #define __SSUB8 __ssub8
yihui 9:05f0b5a3a70a 68 #define __QSUB8 __qsub8
yihui 9:05f0b5a3a70a 69 #define __SHSUB8 __shsub8
yihui 9:05f0b5a3a70a 70 #define __USUB8 __usub8
yihui 9:05f0b5a3a70a 71 #define __UQSUB8 __uqsub8
yihui 9:05f0b5a3a70a 72 #define __UHSUB8 __uhsub8
yihui 9:05f0b5a3a70a 73 #define __SADD16 __sadd16
yihui 9:05f0b5a3a70a 74 #define __QADD16 __qadd16
yihui 9:05f0b5a3a70a 75 #define __SHADD16 __shadd16
yihui 9:05f0b5a3a70a 76 #define __UADD16 __uadd16
yihui 9:05f0b5a3a70a 77 #define __UQADD16 __uqadd16
yihui 9:05f0b5a3a70a 78 #define __UHADD16 __uhadd16
yihui 9:05f0b5a3a70a 79 #define __SSUB16 __ssub16
yihui 9:05f0b5a3a70a 80 #define __QSUB16 __qsub16
yihui 9:05f0b5a3a70a 81 #define __SHSUB16 __shsub16
yihui 9:05f0b5a3a70a 82 #define __USUB16 __usub16
yihui 9:05f0b5a3a70a 83 #define __UQSUB16 __uqsub16
yihui 9:05f0b5a3a70a 84 #define __UHSUB16 __uhsub16
yihui 9:05f0b5a3a70a 85 #define __SASX __sasx
yihui 9:05f0b5a3a70a 86 #define __QASX __qasx
yihui 9:05f0b5a3a70a 87 #define __SHASX __shasx
yihui 9:05f0b5a3a70a 88 #define __UASX __uasx
yihui 9:05f0b5a3a70a 89 #define __UQASX __uqasx
yihui 9:05f0b5a3a70a 90 #define __UHASX __uhasx
yihui 9:05f0b5a3a70a 91 #define __SSAX __ssax
yihui 9:05f0b5a3a70a 92 #define __QSAX __qsax
yihui 9:05f0b5a3a70a 93 #define __SHSAX __shsax
yihui 9:05f0b5a3a70a 94 #define __USAX __usax
yihui 9:05f0b5a3a70a 95 #define __UQSAX __uqsax
yihui 9:05f0b5a3a70a 96 #define __UHSAX __uhsax
yihui 9:05f0b5a3a70a 97 #define __USAD8 __usad8
yihui 9:05f0b5a3a70a 98 #define __USADA8 __usada8
yihui 9:05f0b5a3a70a 99 #define __SSAT16 __ssat16
yihui 9:05f0b5a3a70a 100 #define __USAT16 __usat16
yihui 9:05f0b5a3a70a 101 #define __UXTB16 __uxtb16
yihui 9:05f0b5a3a70a 102 #define __UXTAB16 __uxtab16
yihui 9:05f0b5a3a70a 103 #define __SXTB16 __sxtb16
yihui 9:05f0b5a3a70a 104 #define __SXTAB16 __sxtab16
yihui 9:05f0b5a3a70a 105 #define __SMUAD __smuad
yihui 9:05f0b5a3a70a 106 #define __SMUADX __smuadx
yihui 9:05f0b5a3a70a 107 #define __SMLAD __smlad
yihui 9:05f0b5a3a70a 108 #define __SMLADX __smladx
yihui 9:05f0b5a3a70a 109 #define __SMLALD __smlald
yihui 9:05f0b5a3a70a 110 #define __SMLALDX __smlaldx
yihui 9:05f0b5a3a70a 111 #define __SMUSD __smusd
yihui 9:05f0b5a3a70a 112 #define __SMUSDX __smusdx
yihui 9:05f0b5a3a70a 113 #define __SMLSD __smlsd
yihui 9:05f0b5a3a70a 114 #define __SMLSDX __smlsdx
yihui 9:05f0b5a3a70a 115 #define __SMLSLD __smlsld
yihui 9:05f0b5a3a70a 116 #define __SMLSLDX __smlsldx
yihui 9:05f0b5a3a70a 117 #define __SEL __sel
yihui 9:05f0b5a3a70a 118 #define __QADD __qadd
yihui 9:05f0b5a3a70a 119 #define __QSUB __qsub
yihui 9:05f0b5a3a70a 120
yihui 9:05f0b5a3a70a 121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
yihui 9:05f0b5a3a70a 122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
yihui 9:05f0b5a3a70a 123
yihui 9:05f0b5a3a70a 124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
yihui 9:05f0b5a3a70a 125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
yihui 9:05f0b5a3a70a 126
yihui 9:05f0b5a3a70a 127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
yihui 9:05f0b5a3a70a 128 ((int64_t)(ARG3) << 32) ) >> 32))
yihui 9:05f0b5a3a70a 129
yihui 9:05f0b5a3a70a 130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
yihui 9:05f0b5a3a70a 131
yihui 9:05f0b5a3a70a 132
yihui 9:05f0b5a3a70a 133
yihui 9:05f0b5a3a70a 134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
yihui 9:05f0b5a3a70a 135 /* IAR iccarm specific functions */
yihui 9:05f0b5a3a70a 136
yihui 9:05f0b5a3a70a 137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
yihui 9:05f0b5a3a70a 138 #include <cmsis_iar.h>
yihui 9:05f0b5a3a70a 139
yihui 9:05f0b5a3a70a 140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
yihui 9:05f0b5a3a70a 141
yihui 9:05f0b5a3a70a 142
yihui 9:05f0b5a3a70a 143
yihui 9:05f0b5a3a70a 144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
yihui 9:05f0b5a3a70a 145 /* TI CCS specific functions */
yihui 9:05f0b5a3a70a 146
yihui 9:05f0b5a3a70a 147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
yihui 9:05f0b5a3a70a 148 #include <cmsis_ccs.h>
yihui 9:05f0b5a3a70a 149
yihui 9:05f0b5a3a70a 150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
yihui 9:05f0b5a3a70a 151
yihui 9:05f0b5a3a70a 152
yihui 9:05f0b5a3a70a 153
yihui 9:05f0b5a3a70a 154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
yihui 9:05f0b5a3a70a 155 /* GNU gcc specific functions */
yihui 9:05f0b5a3a70a 156
yihui 9:05f0b5a3a70a 157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
yihui 9:05f0b5a3a70a 158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 159 {
yihui 9:05f0b5a3a70a 160 uint32_t result;
yihui 9:05f0b5a3a70a 161
yihui 9:05f0b5a3a70a 162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 163 return(result);
yihui 9:05f0b5a3a70a 164 }
yihui 9:05f0b5a3a70a 165
yihui 9:05f0b5a3a70a 166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 167 {
yihui 9:05f0b5a3a70a 168 uint32_t result;
yihui 9:05f0b5a3a70a 169
yihui 9:05f0b5a3a70a 170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 171 return(result);
yihui 9:05f0b5a3a70a 172 }
yihui 9:05f0b5a3a70a 173
yihui 9:05f0b5a3a70a 174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 175 {
yihui 9:05f0b5a3a70a 176 uint32_t result;
yihui 9:05f0b5a3a70a 177
yihui 9:05f0b5a3a70a 178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 179 return(result);
yihui 9:05f0b5a3a70a 180 }
yihui 9:05f0b5a3a70a 181
yihui 9:05f0b5a3a70a 182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 183 {
yihui 9:05f0b5a3a70a 184 uint32_t result;
yihui 9:05f0b5a3a70a 185
yihui 9:05f0b5a3a70a 186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 187 return(result);
yihui 9:05f0b5a3a70a 188 }
yihui 9:05f0b5a3a70a 189
yihui 9:05f0b5a3a70a 190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 191 {
yihui 9:05f0b5a3a70a 192 uint32_t result;
yihui 9:05f0b5a3a70a 193
yihui 9:05f0b5a3a70a 194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 195 return(result);
yihui 9:05f0b5a3a70a 196 }
yihui 9:05f0b5a3a70a 197
yihui 9:05f0b5a3a70a 198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 199 {
yihui 9:05f0b5a3a70a 200 uint32_t result;
yihui 9:05f0b5a3a70a 201
yihui 9:05f0b5a3a70a 202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 203 return(result);
yihui 9:05f0b5a3a70a 204 }
yihui 9:05f0b5a3a70a 205
yihui 9:05f0b5a3a70a 206
yihui 9:05f0b5a3a70a 207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 208 {
yihui 9:05f0b5a3a70a 209 uint32_t result;
yihui 9:05f0b5a3a70a 210
yihui 9:05f0b5a3a70a 211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 212 return(result);
yihui 9:05f0b5a3a70a 213 }
yihui 9:05f0b5a3a70a 214
yihui 9:05f0b5a3a70a 215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 216 {
yihui 9:05f0b5a3a70a 217 uint32_t result;
yihui 9:05f0b5a3a70a 218
yihui 9:05f0b5a3a70a 219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 220 return(result);
yihui 9:05f0b5a3a70a 221 }
yihui 9:05f0b5a3a70a 222
yihui 9:05f0b5a3a70a 223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 224 {
yihui 9:05f0b5a3a70a 225 uint32_t result;
yihui 9:05f0b5a3a70a 226
yihui 9:05f0b5a3a70a 227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 228 return(result);
yihui 9:05f0b5a3a70a 229 }
yihui 9:05f0b5a3a70a 230
yihui 9:05f0b5a3a70a 231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 232 {
yihui 9:05f0b5a3a70a 233 uint32_t result;
yihui 9:05f0b5a3a70a 234
yihui 9:05f0b5a3a70a 235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 236 return(result);
yihui 9:05f0b5a3a70a 237 }
yihui 9:05f0b5a3a70a 238
yihui 9:05f0b5a3a70a 239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 240 {
yihui 9:05f0b5a3a70a 241 uint32_t result;
yihui 9:05f0b5a3a70a 242
yihui 9:05f0b5a3a70a 243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 244 return(result);
yihui 9:05f0b5a3a70a 245 }
yihui 9:05f0b5a3a70a 246
yihui 9:05f0b5a3a70a 247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 248 {
yihui 9:05f0b5a3a70a 249 uint32_t result;
yihui 9:05f0b5a3a70a 250
yihui 9:05f0b5a3a70a 251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 252 return(result);
yihui 9:05f0b5a3a70a 253 }
yihui 9:05f0b5a3a70a 254
yihui 9:05f0b5a3a70a 255
yihui 9:05f0b5a3a70a 256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 257 {
yihui 9:05f0b5a3a70a 258 uint32_t result;
yihui 9:05f0b5a3a70a 259
yihui 9:05f0b5a3a70a 260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 261 return(result);
yihui 9:05f0b5a3a70a 262 }
yihui 9:05f0b5a3a70a 263
yihui 9:05f0b5a3a70a 264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 265 {
yihui 9:05f0b5a3a70a 266 uint32_t result;
yihui 9:05f0b5a3a70a 267
yihui 9:05f0b5a3a70a 268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 269 return(result);
yihui 9:05f0b5a3a70a 270 }
yihui 9:05f0b5a3a70a 271
yihui 9:05f0b5a3a70a 272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 273 {
yihui 9:05f0b5a3a70a 274 uint32_t result;
yihui 9:05f0b5a3a70a 275
yihui 9:05f0b5a3a70a 276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 277 return(result);
yihui 9:05f0b5a3a70a 278 }
yihui 9:05f0b5a3a70a 279
yihui 9:05f0b5a3a70a 280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 281 {
yihui 9:05f0b5a3a70a 282 uint32_t result;
yihui 9:05f0b5a3a70a 283
yihui 9:05f0b5a3a70a 284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 285 return(result);
yihui 9:05f0b5a3a70a 286 }
yihui 9:05f0b5a3a70a 287
yihui 9:05f0b5a3a70a 288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 289 {
yihui 9:05f0b5a3a70a 290 uint32_t result;
yihui 9:05f0b5a3a70a 291
yihui 9:05f0b5a3a70a 292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 293 return(result);
yihui 9:05f0b5a3a70a 294 }
yihui 9:05f0b5a3a70a 295
yihui 9:05f0b5a3a70a 296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 297 {
yihui 9:05f0b5a3a70a 298 uint32_t result;
yihui 9:05f0b5a3a70a 299
yihui 9:05f0b5a3a70a 300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 301 return(result);
yihui 9:05f0b5a3a70a 302 }
yihui 9:05f0b5a3a70a 303
yihui 9:05f0b5a3a70a 304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 305 {
yihui 9:05f0b5a3a70a 306 uint32_t result;
yihui 9:05f0b5a3a70a 307
yihui 9:05f0b5a3a70a 308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 309 return(result);
yihui 9:05f0b5a3a70a 310 }
yihui 9:05f0b5a3a70a 311
yihui 9:05f0b5a3a70a 312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 313 {
yihui 9:05f0b5a3a70a 314 uint32_t result;
yihui 9:05f0b5a3a70a 315
yihui 9:05f0b5a3a70a 316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 317 return(result);
yihui 9:05f0b5a3a70a 318 }
yihui 9:05f0b5a3a70a 319
yihui 9:05f0b5a3a70a 320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 321 {
yihui 9:05f0b5a3a70a 322 uint32_t result;
yihui 9:05f0b5a3a70a 323
yihui 9:05f0b5a3a70a 324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 325 return(result);
yihui 9:05f0b5a3a70a 326 }
yihui 9:05f0b5a3a70a 327
yihui 9:05f0b5a3a70a 328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 329 {
yihui 9:05f0b5a3a70a 330 uint32_t result;
yihui 9:05f0b5a3a70a 331
yihui 9:05f0b5a3a70a 332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 333 return(result);
yihui 9:05f0b5a3a70a 334 }
yihui 9:05f0b5a3a70a 335
yihui 9:05f0b5a3a70a 336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 337 {
yihui 9:05f0b5a3a70a 338 uint32_t result;
yihui 9:05f0b5a3a70a 339
yihui 9:05f0b5a3a70a 340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 341 return(result);
yihui 9:05f0b5a3a70a 342 }
yihui 9:05f0b5a3a70a 343
yihui 9:05f0b5a3a70a 344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 345 {
yihui 9:05f0b5a3a70a 346 uint32_t result;
yihui 9:05f0b5a3a70a 347
yihui 9:05f0b5a3a70a 348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 349 return(result);
yihui 9:05f0b5a3a70a 350 }
yihui 9:05f0b5a3a70a 351
yihui 9:05f0b5a3a70a 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 353 {
yihui 9:05f0b5a3a70a 354 uint32_t result;
yihui 9:05f0b5a3a70a 355
yihui 9:05f0b5a3a70a 356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 357 return(result);
yihui 9:05f0b5a3a70a 358 }
yihui 9:05f0b5a3a70a 359
yihui 9:05f0b5a3a70a 360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 361 {
yihui 9:05f0b5a3a70a 362 uint32_t result;
yihui 9:05f0b5a3a70a 363
yihui 9:05f0b5a3a70a 364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 365 return(result);
yihui 9:05f0b5a3a70a 366 }
yihui 9:05f0b5a3a70a 367
yihui 9:05f0b5a3a70a 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 369 {
yihui 9:05f0b5a3a70a 370 uint32_t result;
yihui 9:05f0b5a3a70a 371
yihui 9:05f0b5a3a70a 372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 373 return(result);
yihui 9:05f0b5a3a70a 374 }
yihui 9:05f0b5a3a70a 375
yihui 9:05f0b5a3a70a 376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 377 {
yihui 9:05f0b5a3a70a 378 uint32_t result;
yihui 9:05f0b5a3a70a 379
yihui 9:05f0b5a3a70a 380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 381 return(result);
yihui 9:05f0b5a3a70a 382 }
yihui 9:05f0b5a3a70a 383
yihui 9:05f0b5a3a70a 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 385 {
yihui 9:05f0b5a3a70a 386 uint32_t result;
yihui 9:05f0b5a3a70a 387
yihui 9:05f0b5a3a70a 388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 389 return(result);
yihui 9:05f0b5a3a70a 390 }
yihui 9:05f0b5a3a70a 391
yihui 9:05f0b5a3a70a 392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 393 {
yihui 9:05f0b5a3a70a 394 uint32_t result;
yihui 9:05f0b5a3a70a 395
yihui 9:05f0b5a3a70a 396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 397 return(result);
yihui 9:05f0b5a3a70a 398 }
yihui 9:05f0b5a3a70a 399
yihui 9:05f0b5a3a70a 400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 401 {
yihui 9:05f0b5a3a70a 402 uint32_t result;
yihui 9:05f0b5a3a70a 403
yihui 9:05f0b5a3a70a 404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 405 return(result);
yihui 9:05f0b5a3a70a 406 }
yihui 9:05f0b5a3a70a 407
yihui 9:05f0b5a3a70a 408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 409 {
yihui 9:05f0b5a3a70a 410 uint32_t result;
yihui 9:05f0b5a3a70a 411
yihui 9:05f0b5a3a70a 412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 413 return(result);
yihui 9:05f0b5a3a70a 414 }
yihui 9:05f0b5a3a70a 415
yihui 9:05f0b5a3a70a 416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 417 {
yihui 9:05f0b5a3a70a 418 uint32_t result;
yihui 9:05f0b5a3a70a 419
yihui 9:05f0b5a3a70a 420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 421 return(result);
yihui 9:05f0b5a3a70a 422 }
yihui 9:05f0b5a3a70a 423
yihui 9:05f0b5a3a70a 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 425 {
yihui 9:05f0b5a3a70a 426 uint32_t result;
yihui 9:05f0b5a3a70a 427
yihui 9:05f0b5a3a70a 428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 429 return(result);
yihui 9:05f0b5a3a70a 430 }
yihui 9:05f0b5a3a70a 431
yihui 9:05f0b5a3a70a 432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 433 {
yihui 9:05f0b5a3a70a 434 uint32_t result;
yihui 9:05f0b5a3a70a 435
yihui 9:05f0b5a3a70a 436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 437 return(result);
yihui 9:05f0b5a3a70a 438 }
yihui 9:05f0b5a3a70a 439
yihui 9:05f0b5a3a70a 440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 441 {
yihui 9:05f0b5a3a70a 442 uint32_t result;
yihui 9:05f0b5a3a70a 443
yihui 9:05f0b5a3a70a 444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 445 return(result);
yihui 9:05f0b5a3a70a 446 }
yihui 9:05f0b5a3a70a 447
yihui 9:05f0b5a3a70a 448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 449 {
yihui 9:05f0b5a3a70a 450 uint32_t result;
yihui 9:05f0b5a3a70a 451
yihui 9:05f0b5a3a70a 452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 453 return(result);
yihui 9:05f0b5a3a70a 454 }
yihui 9:05f0b5a3a70a 455
yihui 9:05f0b5a3a70a 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
yihui 9:05f0b5a3a70a 457 {
yihui 9:05f0b5a3a70a 458 uint32_t result;
yihui 9:05f0b5a3a70a 459
yihui 9:05f0b5a3a70a 460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
yihui 9:05f0b5a3a70a 461 return(result);
yihui 9:05f0b5a3a70a 462 }
yihui 9:05f0b5a3a70a 463
yihui 9:05f0b5a3a70a 464 #define __SSAT16(ARG1,ARG2) \
yihui 9:05f0b5a3a70a 465 ({ \
yihui 9:05f0b5a3a70a 466 uint32_t __RES, __ARG1 = (ARG1); \
yihui 9:05f0b5a3a70a 467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
yihui 9:05f0b5a3a70a 468 __RES; \
yihui 9:05f0b5a3a70a 469 })
yihui 9:05f0b5a3a70a 470
yihui 9:05f0b5a3a70a 471 #define __USAT16(ARG1,ARG2) \
yihui 9:05f0b5a3a70a 472 ({ \
yihui 9:05f0b5a3a70a 473 uint32_t __RES, __ARG1 = (ARG1); \
yihui 9:05f0b5a3a70a 474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
yihui 9:05f0b5a3a70a 475 __RES; \
yihui 9:05f0b5a3a70a 476 })
yihui 9:05f0b5a3a70a 477
yihui 9:05f0b5a3a70a 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
yihui 9:05f0b5a3a70a 479 {
yihui 9:05f0b5a3a70a 480 uint32_t result;
yihui 9:05f0b5a3a70a 481
yihui 9:05f0b5a3a70a 482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
yihui 9:05f0b5a3a70a 483 return(result);
yihui 9:05f0b5a3a70a 484 }
yihui 9:05f0b5a3a70a 485
yihui 9:05f0b5a3a70a 486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 487 {
yihui 9:05f0b5a3a70a 488 uint32_t result;
yihui 9:05f0b5a3a70a 489
yihui 9:05f0b5a3a70a 490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 491 return(result);
yihui 9:05f0b5a3a70a 492 }
yihui 9:05f0b5a3a70a 493
yihui 9:05f0b5a3a70a 494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
yihui 9:05f0b5a3a70a 495 {
yihui 9:05f0b5a3a70a 496 uint32_t result;
yihui 9:05f0b5a3a70a 497
yihui 9:05f0b5a3a70a 498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
yihui 9:05f0b5a3a70a 499 return(result);
yihui 9:05f0b5a3a70a 500 }
yihui 9:05f0b5a3a70a 501
yihui 9:05f0b5a3a70a 502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 503 {
yihui 9:05f0b5a3a70a 504 uint32_t result;
yihui 9:05f0b5a3a70a 505
yihui 9:05f0b5a3a70a 506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 507 return(result);
yihui 9:05f0b5a3a70a 508 }
yihui 9:05f0b5a3a70a 509
yihui 9:05f0b5a3a70a 510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 511 {
yihui 9:05f0b5a3a70a 512 uint32_t result;
yihui 9:05f0b5a3a70a 513
yihui 9:05f0b5a3a70a 514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 515 return(result);
yihui 9:05f0b5a3a70a 516 }
yihui 9:05f0b5a3a70a 517
yihui 9:05f0b5a3a70a 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 519 {
yihui 9:05f0b5a3a70a 520 uint32_t result;
yihui 9:05f0b5a3a70a 521
yihui 9:05f0b5a3a70a 522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 523 return(result);
yihui 9:05f0b5a3a70a 524 }
yihui 9:05f0b5a3a70a 525
yihui 9:05f0b5a3a70a 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
yihui 9:05f0b5a3a70a 527 {
yihui 9:05f0b5a3a70a 528 uint32_t result;
yihui 9:05f0b5a3a70a 529
yihui 9:05f0b5a3a70a 530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
yihui 9:05f0b5a3a70a 531 return(result);
yihui 9:05f0b5a3a70a 532 }
yihui 9:05f0b5a3a70a 533
yihui 9:05f0b5a3a70a 534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
yihui 9:05f0b5a3a70a 535 {
yihui 9:05f0b5a3a70a 536 uint32_t result;
yihui 9:05f0b5a3a70a 537
yihui 9:05f0b5a3a70a 538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
yihui 9:05f0b5a3a70a 539 return(result);
yihui 9:05f0b5a3a70a 540 }
yihui 9:05f0b5a3a70a 541
yihui 9:05f0b5a3a70a 542 #define __SMLALD(ARG1,ARG2,ARG3) \
yihui 9:05f0b5a3a70a 543 ({ \
yihui 9:05f0b5a3a70a 544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
yihui 9:05f0b5a3a70a 545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
yihui 9:05f0b5a3a70a 546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
yihui 9:05f0b5a3a70a 547 })
yihui 9:05f0b5a3a70a 548
yihui 9:05f0b5a3a70a 549 #define __SMLALDX(ARG1,ARG2,ARG3) \
yihui 9:05f0b5a3a70a 550 ({ \
yihui 9:05f0b5a3a70a 551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
yihui 9:05f0b5a3a70a 552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
yihui 9:05f0b5a3a70a 553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
yihui 9:05f0b5a3a70a 554 })
yihui 9:05f0b5a3a70a 555
yihui 9:05f0b5a3a70a 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 557 {
yihui 9:05f0b5a3a70a 558 uint32_t result;
yihui 9:05f0b5a3a70a 559
yihui 9:05f0b5a3a70a 560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 561 return(result);
yihui 9:05f0b5a3a70a 562 }
yihui 9:05f0b5a3a70a 563
yihui 9:05f0b5a3a70a 564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 565 {
yihui 9:05f0b5a3a70a 566 uint32_t result;
yihui 9:05f0b5a3a70a 567
yihui 9:05f0b5a3a70a 568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 569 return(result);
yihui 9:05f0b5a3a70a 570 }
yihui 9:05f0b5a3a70a 571
yihui 9:05f0b5a3a70a 572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
yihui 9:05f0b5a3a70a 573 {
yihui 9:05f0b5a3a70a 574 uint32_t result;
yihui 9:05f0b5a3a70a 575
yihui 9:05f0b5a3a70a 576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
yihui 9:05f0b5a3a70a 577 return(result);
yihui 9:05f0b5a3a70a 578 }
yihui 9:05f0b5a3a70a 579
yihui 9:05f0b5a3a70a 580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
yihui 9:05f0b5a3a70a 581 {
yihui 9:05f0b5a3a70a 582 uint32_t result;
yihui 9:05f0b5a3a70a 583
yihui 9:05f0b5a3a70a 584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
yihui 9:05f0b5a3a70a 585 return(result);
yihui 9:05f0b5a3a70a 586 }
yihui 9:05f0b5a3a70a 587
yihui 9:05f0b5a3a70a 588 #define __SMLSLD(ARG1,ARG2,ARG3) \
yihui 9:05f0b5a3a70a 589 ({ \
yihui 9:05f0b5a3a70a 590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
yihui 9:05f0b5a3a70a 591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
yihui 9:05f0b5a3a70a 592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
yihui 9:05f0b5a3a70a 593 })
yihui 9:05f0b5a3a70a 594
yihui 9:05f0b5a3a70a 595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
yihui 9:05f0b5a3a70a 596 ({ \
yihui 9:05f0b5a3a70a 597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
yihui 9:05f0b5a3a70a 598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
yihui 9:05f0b5a3a70a 599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
yihui 9:05f0b5a3a70a 600 })
yihui 9:05f0b5a3a70a 601
yihui 9:05f0b5a3a70a 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 603 {
yihui 9:05f0b5a3a70a 604 uint32_t result;
yihui 9:05f0b5a3a70a 605
yihui 9:05f0b5a3a70a 606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 607 return(result);
yihui 9:05f0b5a3a70a 608 }
yihui 9:05f0b5a3a70a 609
yihui 9:05f0b5a3a70a 610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 611 {
yihui 9:05f0b5a3a70a 612 uint32_t result;
yihui 9:05f0b5a3a70a 613
yihui 9:05f0b5a3a70a 614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 615 return(result);
yihui 9:05f0b5a3a70a 616 }
yihui 9:05f0b5a3a70a 617
yihui 9:05f0b5a3a70a 618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
yihui 9:05f0b5a3a70a 619 {
yihui 9:05f0b5a3a70a 620 uint32_t result;
yihui 9:05f0b5a3a70a 621
yihui 9:05f0b5a3a70a 622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
yihui 9:05f0b5a3a70a 623 return(result);
yihui 9:05f0b5a3a70a 624 }
yihui 9:05f0b5a3a70a 625
yihui 9:05f0b5a3a70a 626 #define __PKHBT(ARG1,ARG2,ARG3) \
yihui 9:05f0b5a3a70a 627 ({ \
yihui 9:05f0b5a3a70a 628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
yihui 9:05f0b5a3a70a 629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
yihui 9:05f0b5a3a70a 630 __RES; \
yihui 9:05f0b5a3a70a 631 })
yihui 9:05f0b5a3a70a 632
yihui 9:05f0b5a3a70a 633 #define __PKHTB(ARG1,ARG2,ARG3) \
yihui 9:05f0b5a3a70a 634 ({ \
yihui 9:05f0b5a3a70a 635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
yihui 9:05f0b5a3a70a 636 if (ARG3 == 0) \
yihui 9:05f0b5a3a70a 637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
yihui 9:05f0b5a3a70a 638 else \
yihui 9:05f0b5a3a70a 639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
yihui 9:05f0b5a3a70a 640 __RES; \
yihui 9:05f0b5a3a70a 641 })
yihui 9:05f0b5a3a70a 642
yihui 9:05f0b5a3a70a 643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
yihui 9:05f0b5a3a70a 644 {
yihui 9:05f0b5a3a70a 645 int32_t result;
yihui 9:05f0b5a3a70a 646
yihui 9:05f0b5a3a70a 647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
yihui 9:05f0b5a3a70a 648 return(result);
yihui 9:05f0b5a3a70a 649 }
yihui 9:05f0b5a3a70a 650
yihui 9:05f0b5a3a70a 651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
yihui 9:05f0b5a3a70a 652
yihui 9:05f0b5a3a70a 653
yihui 9:05f0b5a3a70a 654
yihui 9:05f0b5a3a70a 655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
yihui 9:05f0b5a3a70a 656 /* TASKING carm specific functions */
yihui 9:05f0b5a3a70a 657
yihui 9:05f0b5a3a70a 658
yihui 9:05f0b5a3a70a 659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
yihui 9:05f0b5a3a70a 660 /* not yet supported */
yihui 9:05f0b5a3a70a 661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
yihui 9:05f0b5a3a70a 662
yihui 9:05f0b5a3a70a 663
yihui 9:05f0b5a3a70a 664 #endif
yihui 9:05f0b5a3a70a 665
yihui 9:05f0b5a3a70a 666 /*@} end of group CMSIS_SIMD_intrinsics */
yihui 9:05f0b5a3a70a 667
yihui 9:05f0b5a3a70a 668
yihui 9:05f0b5a3a70a 669 #endif /* __CORE_CM4_SIMD_H */
yihui 9:05f0b5a3a70a 670
yihui 9:05f0b5a3a70a 671 #ifdef __cplusplus
yihui 9:05f0b5a3a70a 672 }
yihui 9:05f0b5a3a70a 673 #endif