Yihui Xiong / BLE_NODE_TEST

Test code for Grove Node BLE

Dependencies:   BLE_API nRF51822

Fork of BLE_LoopbackUART by Bluetooth Low Energy

mbed-src/targets/cmsis/core_cm4.h@10:22480ac31879, 2014-11-27 (annotated)

Committer:
yihui
Date:
Thu Nov 27 09:30:36 2014 +0000
Revision:
10:22480ac31879
Parent:
9:05f0b5a3a70a 
change to new revision hardware

Who changed what in which revision?

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yihui 9:05f0b5a3a70a 1 /**************************************************************************//**
yihui 9:05f0b5a3a70a 2 * @file core_cm4.h
yihui 9:05f0b5a3a70a 3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
yihui 9:05f0b5a3a70a 4 * @version V3.20
yihui 9:05f0b5a3a70a 5 * @date 25. February 2013
yihui 9:05f0b5a3a70a 6 *
yihui 9:05f0b5a3a70a 7 * @note
yihui 9:05f0b5a3a70a 8 *
yihui 9:05f0b5a3a70a 9 ******************************************************************************/
yihui 9:05f0b5a3a70a 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
yihui 9:05f0b5a3a70a 11
yihui 9:05f0b5a3a70a 12 All rights reserved.
yihui 9:05f0b5a3a70a 13 Redistribution and use in source and binary forms, with or without
yihui 9:05f0b5a3a70a 14 modification, are permitted provided that the following conditions are met:
yihui 9:05f0b5a3a70a 15 - Redistributions of source code must retain the above copyright
yihui 9:05f0b5a3a70a 16 notice, this list of conditions and the following disclaimer.
yihui 9:05f0b5a3a70a 17 - Redistributions in binary form must reproduce the above copyright
yihui 9:05f0b5a3a70a 18 notice, this list of conditions and the following disclaimer in the
yihui 9:05f0b5a3a70a 19 documentation and/or other materials provided with the distribution.
yihui 9:05f0b5a3a70a 20 - Neither the name of ARM nor the names of its contributors may be used
yihui 9:05f0b5a3a70a 21 to endorse or promote products derived from this software without
yihui 9:05f0b5a3a70a 22 specific prior written permission.
yihui 9:05f0b5a3a70a 23 *
yihui 9:05f0b5a3a70a 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
yihui 9:05f0b5a3a70a 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
yihui 9:05f0b5a3a70a 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
yihui 9:05f0b5a3a70a 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
yihui 9:05f0b5a3a70a 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
yihui 9:05f0b5a3a70a 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
yihui 9:05f0b5a3a70a 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
yihui 9:05f0b5a3a70a 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
yihui 9:05f0b5a3a70a 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
yihui 9:05f0b5a3a70a 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
yihui 9:05f0b5a3a70a 34 POSSIBILITY OF SUCH DAMAGE.
yihui 9:05f0b5a3a70a 35 ---------------------------------------------------------------------------*/
yihui 9:05f0b5a3a70a 36
yihui 9:05f0b5a3a70a 37
yihui 9:05f0b5a3a70a 38 #if defined ( __ICCARM__ )
yihui 9:05f0b5a3a70a 39 #pragma system_include /* treat file as system include file for MISRA check */
yihui 9:05f0b5a3a70a 40 #endif
yihui 9:05f0b5a3a70a 41
yihui 9:05f0b5a3a70a 42 #ifdef __cplusplus
yihui 9:05f0b5a3a70a 43 extern "C" {
yihui 9:05f0b5a3a70a 44 #endif
yihui 9:05f0b5a3a70a 45
yihui 9:05f0b5a3a70a 46 #ifndef __CORE_CM4_H_GENERIC
yihui 9:05f0b5a3a70a 47 #define __CORE_CM4_H_GENERIC
yihui 9:05f0b5a3a70a 48
yihui 9:05f0b5a3a70a 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
yihui 9:05f0b5a3a70a 50 CMSIS violates the following MISRA-C:2004 rules:
yihui 9:05f0b5a3a70a 51
yihui 9:05f0b5a3a70a 52 \li Required Rule 8.5, object/function definition in header file.<br>
yihui 9:05f0b5a3a70a 53 Function definitions in header files are used to allow 'inlining'.
yihui 9:05f0b5a3a70a 54
yihui 9:05f0b5a3a70a 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
yihui 9:05f0b5a3a70a 56 Unions are used for effective representation of core registers.
yihui 9:05f0b5a3a70a 57
yihui 9:05f0b5a3a70a 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
yihui 9:05f0b5a3a70a 59 Function-like macros are used to allow more efficient code.
yihui 9:05f0b5a3a70a 60 */
yihui 9:05f0b5a3a70a 61
yihui 9:05f0b5a3a70a 62
yihui 9:05f0b5a3a70a 63 /*******************************************************************************
yihui 9:05f0b5a3a70a 64 * CMSIS definitions
yihui 9:05f0b5a3a70a 65 ******************************************************************************/
yihui 9:05f0b5a3a70a 66 /** \ingroup Cortex_M4
yihui 9:05f0b5a3a70a 67 @{
yihui 9:05f0b5a3a70a 68 */
yihui 9:05f0b5a3a70a 69
yihui 9:05f0b5a3a70a 70 /* CMSIS CM4 definitions */
yihui 9:05f0b5a3a70a 71 #define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
yihui 9:05f0b5a3a70a 72 #define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
yihui 9:05f0b5a3a70a 73 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
yihui 9:05f0b5a3a70a 74 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
yihui 9:05f0b5a3a70a 75
yihui 9:05f0b5a3a70a 76 #define __CORTEX_M (0x04) /*!< Cortex-M Core */
yihui 9:05f0b5a3a70a 77
yihui 9:05f0b5a3a70a 78
yihui 9:05f0b5a3a70a 79 #if defined ( __CC_ARM )
yihui 9:05f0b5a3a70a 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
yihui 9:05f0b5a3a70a 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
yihui 9:05f0b5a3a70a 82 #define __STATIC_INLINE static __inline
yihui 9:05f0b5a3a70a 83
yihui 9:05f0b5a3a70a 84 #elif defined ( __ICCARM__ )
yihui 9:05f0b5a3a70a 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
yihui 9:05f0b5a3a70a 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
yihui 9:05f0b5a3a70a 87 #define __STATIC_INLINE static inline
yihui 9:05f0b5a3a70a 88
yihui 9:05f0b5a3a70a 89 #elif defined ( __TMS470__ )
yihui 9:05f0b5a3a70a 90 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
yihui 9:05f0b5a3a70a 91 #define __STATIC_INLINE static inline
yihui 9:05f0b5a3a70a 92
yihui 9:05f0b5a3a70a 93 #elif defined ( __GNUC__ )
yihui 9:05f0b5a3a70a 94 #define __ASM __asm /*!< asm keyword for GNU Compiler */
yihui 9:05f0b5a3a70a 95 #define __INLINE inline /*!< inline keyword for GNU Compiler */
yihui 9:05f0b5a3a70a 96 #define __STATIC_INLINE static inline
yihui 9:05f0b5a3a70a 97
yihui 9:05f0b5a3a70a 98 #elif defined ( __TASKING__ )
yihui 9:05f0b5a3a70a 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
yihui 9:05f0b5a3a70a 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
yihui 9:05f0b5a3a70a 101 #define __STATIC_INLINE static inline
yihui 9:05f0b5a3a70a 102
yihui 9:05f0b5a3a70a 103 #endif
yihui 9:05f0b5a3a70a 104
yihui 9:05f0b5a3a70a 105 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
yihui 9:05f0b5a3a70a 106 */
yihui 9:05f0b5a3a70a 107 #if defined ( __CC_ARM )
yihui 9:05f0b5a3a70a 108 #if defined __TARGET_FPU_VFP
yihui 9:05f0b5a3a70a 109 #if (__FPU_PRESENT == 1)
yihui 9:05f0b5a3a70a 110 #define __FPU_USED 1
yihui 9:05f0b5a3a70a 111 #else
yihui 9:05f0b5a3a70a 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
yihui 9:05f0b5a3a70a 113 #define __FPU_USED 0
yihui 9:05f0b5a3a70a 114 #endif
yihui 9:05f0b5a3a70a 115 #else
yihui 9:05f0b5a3a70a 116 #define __FPU_USED 0
yihui 9:05f0b5a3a70a 117 #endif
yihui 9:05f0b5a3a70a 118
yihui 9:05f0b5a3a70a 119 #elif defined ( __ICCARM__ )
yihui 9:05f0b5a3a70a 120 #if defined __ARMVFP__
yihui 9:05f0b5a3a70a 121 #if (__FPU_PRESENT == 1)
yihui 9:05f0b5a3a70a 122 #define __FPU_USED 1
yihui 9:05f0b5a3a70a 123 #else
yihui 9:05f0b5a3a70a 124 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
yihui 9:05f0b5a3a70a 125 #define __FPU_USED 0
yihui 9:05f0b5a3a70a 126 #endif
yihui 9:05f0b5a3a70a 127 #else
yihui 9:05f0b5a3a70a 128 #define __FPU_USED 0
yihui 9:05f0b5a3a70a 129 #endif
yihui 9:05f0b5a3a70a 130
yihui 9:05f0b5a3a70a 131 #elif defined ( __TMS470__ )
yihui 9:05f0b5a3a70a 132 #if defined __TI_VFP_SUPPORT__
yihui 9:05f0b5a3a70a 133 #if (__FPU_PRESENT == 1)
yihui 9:05f0b5a3a70a 134 #define __FPU_USED 1
yihui 9:05f0b5a3a70a 135 #else
yihui 9:05f0b5a3a70a 136 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
yihui 9:05f0b5a3a70a 137 #define __FPU_USED 0
yihui 9:05f0b5a3a70a 138 #endif
yihui 9:05f0b5a3a70a 139 #else
yihui 9:05f0b5a3a70a 140 #define __FPU_USED 0
yihui 9:05f0b5a3a70a 141 #endif
yihui 9:05f0b5a3a70a 142
yihui 9:05f0b5a3a70a 143 #elif defined ( __GNUC__ )
yihui 9:05f0b5a3a70a 144 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
yihui 9:05f0b5a3a70a 145 #if (__FPU_PRESENT == 1)
yihui 9:05f0b5a3a70a 146 #define __FPU_USED 1
yihui 9:05f0b5a3a70a 147 #else
yihui 9:05f0b5a3a70a 148 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
yihui 9:05f0b5a3a70a 149 #define __FPU_USED 0
yihui 9:05f0b5a3a70a 150 #endif
yihui 9:05f0b5a3a70a 151 #else
yihui 9:05f0b5a3a70a 152 #define __FPU_USED 0
yihui 9:05f0b5a3a70a 153 #endif
yihui 9:05f0b5a3a70a 154
yihui 9:05f0b5a3a70a 155 #elif defined ( __TASKING__ )
yihui 9:05f0b5a3a70a 156 #if defined __FPU_VFP__
yihui 9:05f0b5a3a70a 157 #if (__FPU_PRESENT == 1)
yihui 9:05f0b5a3a70a 158 #define __FPU_USED 1
yihui 9:05f0b5a3a70a 159 #else
yihui 9:05f0b5a3a70a 160 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
yihui 9:05f0b5a3a70a 161 #define __FPU_USED 0
yihui 9:05f0b5a3a70a 162 #endif
yihui 9:05f0b5a3a70a 163 #else
yihui 9:05f0b5a3a70a 164 #define __FPU_USED 0
yihui 9:05f0b5a3a70a 165 #endif
yihui 9:05f0b5a3a70a 166 #endif
yihui 9:05f0b5a3a70a 167
yihui 9:05f0b5a3a70a 168 #include <stdint.h> /* standard types definitions */
yihui 9:05f0b5a3a70a 169 #include <core_cmInstr.h> /* Core Instruction Access */
yihui 9:05f0b5a3a70a 170 #include <core_cmFunc.h> /* Core Function Access */
yihui 9:05f0b5a3a70a 171 #include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
yihui 9:05f0b5a3a70a 172
yihui 9:05f0b5a3a70a 173 #endif /* __CORE_CM4_H_GENERIC */
yihui 9:05f0b5a3a70a 174
yihui 9:05f0b5a3a70a 175 #ifndef __CMSIS_GENERIC
yihui 9:05f0b5a3a70a 176
yihui 9:05f0b5a3a70a 177 #ifndef __CORE_CM4_H_DEPENDANT
yihui 9:05f0b5a3a70a 178 #define __CORE_CM4_H_DEPENDANT
yihui 9:05f0b5a3a70a 179
yihui 9:05f0b5a3a70a 180 /* check device defines and use defaults */
yihui 9:05f0b5a3a70a 181 #if defined __CHECK_DEVICE_DEFINES
yihui 9:05f0b5a3a70a 182 #ifndef __CM4_REV
yihui 9:05f0b5a3a70a 183 #define __CM4_REV 0x0000
yihui 9:05f0b5a3a70a 184 #warning "__CM4_REV not defined in device header file; using default!"
yihui 9:05f0b5a3a70a 185 #endif
yihui 9:05f0b5a3a70a 186
yihui 9:05f0b5a3a70a 187 #ifndef __FPU_PRESENT
yihui 9:05f0b5a3a70a 188 #define __FPU_PRESENT 0
yihui 9:05f0b5a3a70a 189 #warning "__FPU_PRESENT not defined in device header file; using default!"
yihui 9:05f0b5a3a70a 190 #endif
yihui 9:05f0b5a3a70a 191
yihui 9:05f0b5a3a70a 192 #ifndef __MPU_PRESENT
yihui 9:05f0b5a3a70a 193 #define __MPU_PRESENT 0
yihui 9:05f0b5a3a70a 194 #warning "__MPU_PRESENT not defined in device header file; using default!"
yihui 9:05f0b5a3a70a 195 #endif
yihui 9:05f0b5a3a70a 196
yihui 9:05f0b5a3a70a 197 #ifndef __NVIC_PRIO_BITS
yihui 9:05f0b5a3a70a 198 #define __NVIC_PRIO_BITS 4
yihui 9:05f0b5a3a70a 199 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
yihui 9:05f0b5a3a70a 200 #endif
yihui 9:05f0b5a3a70a 201
yihui 9:05f0b5a3a70a 202 #ifndef __Vendor_SysTickConfig
yihui 9:05f0b5a3a70a 203 #define __Vendor_SysTickConfig 0
yihui 9:05f0b5a3a70a 204 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
yihui 9:05f0b5a3a70a 205 #endif
yihui 9:05f0b5a3a70a 206 #endif
yihui 9:05f0b5a3a70a 207
yihui 9:05f0b5a3a70a 208 /* IO definitions (access restrictions to peripheral registers) */
yihui 9:05f0b5a3a70a 209 /**
yihui 9:05f0b5a3a70a 210 \defgroup CMSIS_glob_defs CMSIS Global Defines
yihui 9:05f0b5a3a70a 211
yihui 9:05f0b5a3a70a 212 <strong>IO Type Qualifiers</strong> are used
yihui 9:05f0b5a3a70a 213 \li to specify the access to peripheral variables.
yihui 9:05f0b5a3a70a 214 \li for automatic generation of peripheral register debug information.
yihui 9:05f0b5a3a70a 215 */
yihui 9:05f0b5a3a70a 216 #ifdef __cplusplus
yihui 9:05f0b5a3a70a 217 #define __I volatile /*!< Defines 'read only' permissions */
yihui 9:05f0b5a3a70a 218 #else
yihui 9:05f0b5a3a70a 219 #define __I volatile const /*!< Defines 'read only' permissions */
yihui 9:05f0b5a3a70a 220 #endif
yihui 9:05f0b5a3a70a 221 #define __O volatile /*!< Defines 'write only' permissions */
yihui 9:05f0b5a3a70a 222 #define __IO volatile /*!< Defines 'read / write' permissions */
yihui 9:05f0b5a3a70a 223
yihui 9:05f0b5a3a70a 224 /*@} end of group Cortex_M4 */
yihui 9:05f0b5a3a70a 225
yihui 9:05f0b5a3a70a 226
yihui 9:05f0b5a3a70a 227
yihui 9:05f0b5a3a70a 228 /*******************************************************************************
yihui 9:05f0b5a3a70a 229 * Register Abstraction
yihui 9:05f0b5a3a70a 230 Core Register contain:
yihui 9:05f0b5a3a70a 231 - Core Register
yihui 9:05f0b5a3a70a 232 - Core NVIC Register
yihui 9:05f0b5a3a70a 233 - Core SCB Register
yihui 9:05f0b5a3a70a 234 - Core SysTick Register
yihui 9:05f0b5a3a70a 235 - Core Debug Register
yihui 9:05f0b5a3a70a 236 - Core MPU Register
yihui 9:05f0b5a3a70a 237 - Core FPU Register
yihui 9:05f0b5a3a70a 238 ******************************************************************************/
yihui 9:05f0b5a3a70a 239 /** \defgroup CMSIS_core_register Defines and Type Definitions
yihui 9:05f0b5a3a70a 240 \brief Type definitions and defines for Cortex-M processor based devices.
yihui 9:05f0b5a3a70a 241 */
yihui 9:05f0b5a3a70a 242
yihui 9:05f0b5a3a70a 243 /** \ingroup CMSIS_core_register
yihui 9:05f0b5a3a70a 244 \defgroup CMSIS_CORE Status and Control Registers
yihui 9:05f0b5a3a70a 245 \brief Core Register type definitions.
yihui 9:05f0b5a3a70a 246 @{
yihui 9:05f0b5a3a70a 247 */
yihui 9:05f0b5a3a70a 248
yihui 9:05f0b5a3a70a 249 /** \brief Union type to access the Application Program Status Register (APSR).
yihui 9:05f0b5a3a70a 250 */
yihui 9:05f0b5a3a70a 251 typedef union
yihui 9:05f0b5a3a70a 252 {
yihui 9:05f0b5a3a70a 253 struct
yihui 9:05f0b5a3a70a 254 {
yihui 9:05f0b5a3a70a 255 #if (__CORTEX_M != 0x04)
yihui 9:05f0b5a3a70a 256 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
yihui 9:05f0b5a3a70a 257 #else
yihui 9:05f0b5a3a70a 258 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
yihui 9:05f0b5a3a70a 259 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
yihui 9:05f0b5a3a70a 260 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
yihui 9:05f0b5a3a70a 261 #endif
yihui 9:05f0b5a3a70a 262 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
yihui 9:05f0b5a3a70a 263 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
yihui 9:05f0b5a3a70a 264 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
yihui 9:05f0b5a3a70a 265 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
yihui 9:05f0b5a3a70a 266 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
yihui 9:05f0b5a3a70a 267 } b; /*!< Structure used for bit access */
yihui 9:05f0b5a3a70a 268 uint32_t w; /*!< Type used for word access */
yihui 9:05f0b5a3a70a 269 } APSR_Type;
yihui 9:05f0b5a3a70a 270
yihui 9:05f0b5a3a70a 271
yihui 9:05f0b5a3a70a 272 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
yihui 9:05f0b5a3a70a 273 */
yihui 9:05f0b5a3a70a 274 typedef union
yihui 9:05f0b5a3a70a 275 {
yihui 9:05f0b5a3a70a 276 struct
yihui 9:05f0b5a3a70a 277 {
yihui 9:05f0b5a3a70a 278 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
yihui 9:05f0b5a3a70a 279 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
yihui 9:05f0b5a3a70a 280 } b; /*!< Structure used for bit access */
yihui 9:05f0b5a3a70a 281 uint32_t w; /*!< Type used for word access */
yihui 9:05f0b5a3a70a 282 } IPSR_Type;
yihui 9:05f0b5a3a70a 283
yihui 9:05f0b5a3a70a 284
yihui 9:05f0b5a3a70a 285 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
yihui 9:05f0b5a3a70a 286 */
yihui 9:05f0b5a3a70a 287 typedef union
yihui 9:05f0b5a3a70a 288 {
yihui 9:05f0b5a3a70a 289 struct
yihui 9:05f0b5a3a70a 290 {
yihui 9:05f0b5a3a70a 291 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
yihui 9:05f0b5a3a70a 292 #if (__CORTEX_M != 0x04)
yihui 9:05f0b5a3a70a 293 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
yihui 9:05f0b5a3a70a 294 #else
yihui 9:05f0b5a3a70a 295 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
yihui 9:05f0b5a3a70a 296 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
yihui 9:05f0b5a3a70a 297 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
yihui 9:05f0b5a3a70a 298 #endif
yihui 9:05f0b5a3a70a 299 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
yihui 9:05f0b5a3a70a 300 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
yihui 9:05f0b5a3a70a 301 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
yihui 9:05f0b5a3a70a 302 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
yihui 9:05f0b5a3a70a 303 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
yihui 9:05f0b5a3a70a 304 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
yihui 9:05f0b5a3a70a 305 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
yihui 9:05f0b5a3a70a 306 } b; /*!< Structure used for bit access */
yihui 9:05f0b5a3a70a 307 uint32_t w; /*!< Type used for word access */
yihui 9:05f0b5a3a70a 308 } xPSR_Type;
yihui 9:05f0b5a3a70a 309
yihui 9:05f0b5a3a70a 310
yihui 9:05f0b5a3a70a 311 /** \brief Union type to access the Control Registers (CONTROL).
yihui 9:05f0b5a3a70a 312 */
yihui 9:05f0b5a3a70a 313 typedef union
yihui 9:05f0b5a3a70a 314 {
yihui 9:05f0b5a3a70a 315 struct
yihui 9:05f0b5a3a70a 316 {
yihui 9:05f0b5a3a70a 317 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
yihui 9:05f0b5a3a70a 318 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
yihui 9:05f0b5a3a70a 319 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
yihui 9:05f0b5a3a70a 320 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
yihui 9:05f0b5a3a70a 321 } b; /*!< Structure used for bit access */
yihui 9:05f0b5a3a70a 322 uint32_t w; /*!< Type used for word access */
yihui 9:05f0b5a3a70a 323 } CONTROL_Type;
yihui 9:05f0b5a3a70a 324
yihui 9:05f0b5a3a70a 325 /*@} end of group CMSIS_CORE */
yihui 9:05f0b5a3a70a 326
yihui 9:05f0b5a3a70a 327
yihui 9:05f0b5a3a70a 328 /** \ingroup CMSIS_core_register
yihui 9:05f0b5a3a70a 329 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
yihui 9:05f0b5a3a70a 330 \brief Type definitions for the NVIC Registers
yihui 9:05f0b5a3a70a 331 @{
yihui 9:05f0b5a3a70a 332 */
yihui 9:05f0b5a3a70a 333
yihui 9:05f0b5a3a70a 334 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
yihui 9:05f0b5a3a70a 335 */
yihui 9:05f0b5a3a70a 336 typedef struct
yihui 9:05f0b5a3a70a 337 {
yihui 9:05f0b5a3a70a 338 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
yihui 9:05f0b5a3a70a 339 uint32_t RESERVED0[24];
yihui 9:05f0b5a3a70a 340 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
yihui 9:05f0b5a3a70a 341 uint32_t RSERVED1[24];
yihui 9:05f0b5a3a70a 342 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
yihui 9:05f0b5a3a70a 343 uint32_t RESERVED2[24];
yihui 9:05f0b5a3a70a 344 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
yihui 9:05f0b5a3a70a 345 uint32_t RESERVED3[24];
yihui 9:05f0b5a3a70a 346 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
yihui 9:05f0b5a3a70a 347 uint32_t RESERVED4[56];
yihui 9:05f0b5a3a70a 348 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
yihui 9:05f0b5a3a70a 349 uint32_t RESERVED5[644];
yihui 9:05f0b5a3a70a 350 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
yihui 9:05f0b5a3a70a 351 } NVIC_Type;
yihui 9:05f0b5a3a70a 352
yihui 9:05f0b5a3a70a 353 /* Software Triggered Interrupt Register Definitions */
yihui 9:05f0b5a3a70a 354 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
yihui 9:05f0b5a3a70a 355 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
yihui 9:05f0b5a3a70a 356
yihui 9:05f0b5a3a70a 357 /*@} end of group CMSIS_NVIC */
yihui 9:05f0b5a3a70a 358
yihui 9:05f0b5a3a70a 359
yihui 9:05f0b5a3a70a 360 /** \ingroup CMSIS_core_register
yihui 9:05f0b5a3a70a 361 \defgroup CMSIS_SCB System Control Block (SCB)
yihui 9:05f0b5a3a70a 362 \brief Type definitions for the System Control Block Registers
yihui 9:05f0b5a3a70a 363 @{
yihui 9:05f0b5a3a70a 364 */
yihui 9:05f0b5a3a70a 365
yihui 9:05f0b5a3a70a 366 /** \brief Structure type to access the System Control Block (SCB).
yihui 9:05f0b5a3a70a 367 */
yihui 9:05f0b5a3a70a 368 typedef struct
yihui 9:05f0b5a3a70a 369 {
yihui 9:05f0b5a3a70a 370 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
yihui 9:05f0b5a3a70a 371 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
yihui 9:05f0b5a3a70a 372 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
yihui 9:05f0b5a3a70a 373 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
yihui 9:05f0b5a3a70a 374 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
yihui 9:05f0b5a3a70a 375 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
yihui 9:05f0b5a3a70a 376 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
yihui 9:05f0b5a3a70a 377 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
yihui 9:05f0b5a3a70a 378 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
yihui 9:05f0b5a3a70a 379 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
yihui 9:05f0b5a3a70a 380 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
yihui 9:05f0b5a3a70a 381 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
yihui 9:05f0b5a3a70a 382 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
yihui 9:05f0b5a3a70a 383 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
yihui 9:05f0b5a3a70a 384 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
yihui 9:05f0b5a3a70a 385 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
yihui 9:05f0b5a3a70a 386 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
yihui 9:05f0b5a3a70a 387 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
yihui 9:05f0b5a3a70a 388 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
yihui 9:05f0b5a3a70a 389 uint32_t RESERVED0[5];
yihui 9:05f0b5a3a70a 390 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
yihui 9:05f0b5a3a70a 391 } SCB_Type;
yihui 9:05f0b5a3a70a 392
yihui 9:05f0b5a3a70a 393 /* SCB CPUID Register Definitions */
yihui 9:05f0b5a3a70a 394 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
yihui 9:05f0b5a3a70a 395 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
yihui 9:05f0b5a3a70a 396
yihui 9:05f0b5a3a70a 397 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
yihui 9:05f0b5a3a70a 398 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
yihui 9:05f0b5a3a70a 399
yihui 9:05f0b5a3a70a 400 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
yihui 9:05f0b5a3a70a 401 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
yihui 9:05f0b5a3a70a 402
yihui 9:05f0b5a3a70a 403 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
yihui 9:05f0b5a3a70a 404 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
yihui 9:05f0b5a3a70a 405
yihui 9:05f0b5a3a70a 406 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
yihui 9:05f0b5a3a70a 407 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
yihui 9:05f0b5a3a70a 408
yihui 9:05f0b5a3a70a 409 /* SCB Interrupt Control State Register Definitions */
yihui 9:05f0b5a3a70a 410 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
yihui 9:05f0b5a3a70a 411 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
yihui 9:05f0b5a3a70a 412
yihui 9:05f0b5a3a70a 413 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
yihui 9:05f0b5a3a70a 414 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
yihui 9:05f0b5a3a70a 415
yihui 9:05f0b5a3a70a 416 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
yihui 9:05f0b5a3a70a 417 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
yihui 9:05f0b5a3a70a 418
yihui 9:05f0b5a3a70a 419 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
yihui 9:05f0b5a3a70a 420 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
yihui 9:05f0b5a3a70a 421
yihui 9:05f0b5a3a70a 422 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
yihui 9:05f0b5a3a70a 423 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
yihui 9:05f0b5a3a70a 424
yihui 9:05f0b5a3a70a 425 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
yihui 9:05f0b5a3a70a 426 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
yihui 9:05f0b5a3a70a 427
yihui 9:05f0b5a3a70a 428 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
yihui 9:05f0b5a3a70a 429 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
yihui 9:05f0b5a3a70a 430
yihui 9:05f0b5a3a70a 431 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
yihui 9:05f0b5a3a70a 432 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
yihui 9:05f0b5a3a70a 433
yihui 9:05f0b5a3a70a 434 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
yihui 9:05f0b5a3a70a 435 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
yihui 9:05f0b5a3a70a 436
yihui 9:05f0b5a3a70a 437 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
yihui 9:05f0b5a3a70a 438 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
yihui 9:05f0b5a3a70a 439
yihui 9:05f0b5a3a70a 440 /* SCB Vector Table Offset Register Definitions */
yihui 9:05f0b5a3a70a 441 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
yihui 9:05f0b5a3a70a 442 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
yihui 9:05f0b5a3a70a 443
yihui 9:05f0b5a3a70a 444 /* SCB Application Interrupt and Reset Control Register Definitions */
yihui 9:05f0b5a3a70a 445 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
yihui 9:05f0b5a3a70a 446 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
yihui 9:05f0b5a3a70a 447
yihui 9:05f0b5a3a70a 448 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
yihui 9:05f0b5a3a70a 449 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
yihui 9:05f0b5a3a70a 450
yihui 9:05f0b5a3a70a 451 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
yihui 9:05f0b5a3a70a 452 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
yihui 9:05f0b5a3a70a 453
yihui 9:05f0b5a3a70a 454 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
yihui 9:05f0b5a3a70a 455 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
yihui 9:05f0b5a3a70a 456
yihui 9:05f0b5a3a70a 457 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
yihui 9:05f0b5a3a70a 458 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
yihui 9:05f0b5a3a70a 459
yihui 9:05f0b5a3a70a 460 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
yihui 9:05f0b5a3a70a 461 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
yihui 9:05f0b5a3a70a 462
yihui 9:05f0b5a3a70a 463 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
yihui 9:05f0b5a3a70a 464 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
yihui 9:05f0b5a3a70a 465
yihui 9:05f0b5a3a70a 466 /* SCB System Control Register Definitions */
yihui 9:05f0b5a3a70a 467 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
yihui 9:05f0b5a3a70a 468 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
yihui 9:05f0b5a3a70a 469
yihui 9:05f0b5a3a70a 470 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
yihui 9:05f0b5a3a70a 471 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
yihui 9:05f0b5a3a70a 472
yihui 9:05f0b5a3a70a 473 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
yihui 9:05f0b5a3a70a 474 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
yihui 9:05f0b5a3a70a 475
yihui 9:05f0b5a3a70a 476 /* SCB Configuration Control Register Definitions */
yihui 9:05f0b5a3a70a 477 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
yihui 9:05f0b5a3a70a 478 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
yihui 9:05f0b5a3a70a 479
yihui 9:05f0b5a3a70a 480 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
yihui 9:05f0b5a3a70a 481 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
yihui 9:05f0b5a3a70a 482
yihui 9:05f0b5a3a70a 483 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
yihui 9:05f0b5a3a70a 484 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
yihui 9:05f0b5a3a70a 485
yihui 9:05f0b5a3a70a 486 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
yihui 9:05f0b5a3a70a 487 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
yihui 9:05f0b5a3a70a 488
yihui 9:05f0b5a3a70a 489 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
yihui 9:05f0b5a3a70a 490 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
yihui 9:05f0b5a3a70a 491
yihui 9:05f0b5a3a70a 492 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
yihui 9:05f0b5a3a70a 493 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
yihui 9:05f0b5a3a70a 494
yihui 9:05f0b5a3a70a 495 /* SCB System Handler Control and State Register Definitions */
yihui 9:05f0b5a3a70a 496 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
yihui 9:05f0b5a3a70a 497 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
yihui 9:05f0b5a3a70a 498
yihui 9:05f0b5a3a70a 499 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
yihui 9:05f0b5a3a70a 500 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
yihui 9:05f0b5a3a70a 501
yihui 9:05f0b5a3a70a 502 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
yihui 9:05f0b5a3a70a 503 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
yihui 9:05f0b5a3a70a 504
yihui 9:05f0b5a3a70a 505 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
yihui 9:05f0b5a3a70a 506 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
yihui 9:05f0b5a3a70a 507
yihui 9:05f0b5a3a70a 508 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
yihui 9:05f0b5a3a70a 509 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
yihui 9:05f0b5a3a70a 510
yihui 9:05f0b5a3a70a 511 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
yihui 9:05f0b5a3a70a 512 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
yihui 9:05f0b5a3a70a 513
yihui 9:05f0b5a3a70a 514 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
yihui 9:05f0b5a3a70a 515 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
yihui 9:05f0b5a3a70a 516
yihui 9:05f0b5a3a70a 517 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
yihui 9:05f0b5a3a70a 518 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
yihui 9:05f0b5a3a70a 519
yihui 9:05f0b5a3a70a 520 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
yihui 9:05f0b5a3a70a 521 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
yihui 9:05f0b5a3a70a 522
yihui 9:05f0b5a3a70a 523 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
yihui 9:05f0b5a3a70a 524 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
yihui 9:05f0b5a3a70a 525
yihui 9:05f0b5a3a70a 526 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
yihui 9:05f0b5a3a70a 527 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
yihui 9:05f0b5a3a70a 528
yihui 9:05f0b5a3a70a 529 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
yihui 9:05f0b5a3a70a 530 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
yihui 9:05f0b5a3a70a 531
yihui 9:05f0b5a3a70a 532 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
yihui 9:05f0b5a3a70a 533 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
yihui 9:05f0b5a3a70a 534
yihui 9:05f0b5a3a70a 535 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
yihui 9:05f0b5a3a70a 536 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
yihui 9:05f0b5a3a70a 537
yihui 9:05f0b5a3a70a 538 /* SCB Configurable Fault Status Registers Definitions */
yihui 9:05f0b5a3a70a 539 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
yihui 9:05f0b5a3a70a 540 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
yihui 9:05f0b5a3a70a 541
yihui 9:05f0b5a3a70a 542 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
yihui 9:05f0b5a3a70a 543 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
yihui 9:05f0b5a3a70a 544
yihui 9:05f0b5a3a70a 545 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
yihui 9:05f0b5a3a70a 546 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
yihui 9:05f0b5a3a70a 547
yihui 9:05f0b5a3a70a 548 /* SCB Hard Fault Status Registers Definitions */
yihui 9:05f0b5a3a70a 549 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
yihui 9:05f0b5a3a70a 550 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
yihui 9:05f0b5a3a70a 551
yihui 9:05f0b5a3a70a 552 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
yihui 9:05f0b5a3a70a 553 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
yihui 9:05f0b5a3a70a 554
yihui 9:05f0b5a3a70a 555 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
yihui 9:05f0b5a3a70a 556 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
yihui 9:05f0b5a3a70a 557
yihui 9:05f0b5a3a70a 558 /* SCB Debug Fault Status Register Definitions */
yihui 9:05f0b5a3a70a 559 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
yihui 9:05f0b5a3a70a 560 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
yihui 9:05f0b5a3a70a 561
yihui 9:05f0b5a3a70a 562 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
yihui 9:05f0b5a3a70a 563 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
yihui 9:05f0b5a3a70a 564
yihui 9:05f0b5a3a70a 565 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
yihui 9:05f0b5a3a70a 566 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
yihui 9:05f0b5a3a70a 567
yihui 9:05f0b5a3a70a 568 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
yihui 9:05f0b5a3a70a 569 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
yihui 9:05f0b5a3a70a 570
yihui 9:05f0b5a3a70a 571 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
yihui 9:05f0b5a3a70a 572 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
yihui 9:05f0b5a3a70a 573
yihui 9:05f0b5a3a70a 574 /*@} end of group CMSIS_SCB */
yihui 9:05f0b5a3a70a 575
yihui 9:05f0b5a3a70a 576
yihui 9:05f0b5a3a70a 577 /** \ingroup CMSIS_core_register
yihui 9:05f0b5a3a70a 578 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
yihui 9:05f0b5a3a70a 579 \brief Type definitions for the System Control and ID Register not in the SCB
yihui 9:05f0b5a3a70a 580 @{
yihui 9:05f0b5a3a70a 581 */
yihui 9:05f0b5a3a70a 582
yihui 9:05f0b5a3a70a 583 /** \brief Structure type to access the System Control and ID Register not in the SCB.
yihui 9:05f0b5a3a70a 584 */
yihui 9:05f0b5a3a70a 585 typedef struct
yihui 9:05f0b5a3a70a 586 {
yihui 9:05f0b5a3a70a 587 uint32_t RESERVED0[1];
yihui 9:05f0b5a3a70a 588 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
yihui 9:05f0b5a3a70a 589 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
yihui 9:05f0b5a3a70a 590 } SCnSCB_Type;
yihui 9:05f0b5a3a70a 591
yihui 9:05f0b5a3a70a 592 /* Interrupt Controller Type Register Definitions */
yihui 9:05f0b5a3a70a 593 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
yihui 9:05f0b5a3a70a 594 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
yihui 9:05f0b5a3a70a 595
yihui 9:05f0b5a3a70a 596 /* Auxiliary Control Register Definitions */
yihui 9:05f0b5a3a70a 597 #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
yihui 9:05f0b5a3a70a 598 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
yihui 9:05f0b5a3a70a 599
yihui 9:05f0b5a3a70a 600 #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
yihui 9:05f0b5a3a70a 601 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
yihui 9:05f0b5a3a70a 602
yihui 9:05f0b5a3a70a 603 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
yihui 9:05f0b5a3a70a 604 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
yihui 9:05f0b5a3a70a 605
yihui 9:05f0b5a3a70a 606 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
yihui 9:05f0b5a3a70a 607 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
yihui 9:05f0b5a3a70a 608
yihui 9:05f0b5a3a70a 609 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
yihui 9:05f0b5a3a70a 610 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
yihui 9:05f0b5a3a70a 611
yihui 9:05f0b5a3a70a 612 /*@} end of group CMSIS_SCnotSCB */
yihui 9:05f0b5a3a70a 613
yihui 9:05f0b5a3a70a 614
yihui 9:05f0b5a3a70a 615 /** \ingroup CMSIS_core_register
yihui 9:05f0b5a3a70a 616 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
yihui 9:05f0b5a3a70a 617 \brief Type definitions for the System Timer Registers.
yihui 9:05f0b5a3a70a 618 @{
yihui 9:05f0b5a3a70a 619 */
yihui 9:05f0b5a3a70a 620
yihui 9:05f0b5a3a70a 621 /** \brief Structure type to access the System Timer (SysTick).
yihui 9:05f0b5a3a70a 622 */
yihui 9:05f0b5a3a70a 623 typedef struct
yihui 9:05f0b5a3a70a 624 {
yihui 9:05f0b5a3a70a 625 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
yihui 9:05f0b5a3a70a 626 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
yihui 9:05f0b5a3a70a 627 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
yihui 9:05f0b5a3a70a 628 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
yihui 9:05f0b5a3a70a 629 } SysTick_Type;
yihui 9:05f0b5a3a70a 630
yihui 9:05f0b5a3a70a 631 /* SysTick Control / Status Register Definitions */
yihui 9:05f0b5a3a70a 632 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
yihui 9:05f0b5a3a70a 633 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
yihui 9:05f0b5a3a70a 634
yihui 9:05f0b5a3a70a 635 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
yihui 9:05f0b5a3a70a 636 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
yihui 9:05f0b5a3a70a 637
yihui 9:05f0b5a3a70a 638 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
yihui 9:05f0b5a3a70a 639 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
yihui 9:05f0b5a3a70a 640
yihui 9:05f0b5a3a70a 641 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
yihui 9:05f0b5a3a70a 642 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
yihui 9:05f0b5a3a70a 643
yihui 9:05f0b5a3a70a 644 /* SysTick Reload Register Definitions */
yihui 9:05f0b5a3a70a 645 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
yihui 9:05f0b5a3a70a 646 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
yihui 9:05f0b5a3a70a 647
yihui 9:05f0b5a3a70a 648 /* SysTick Current Register Definitions */
yihui 9:05f0b5a3a70a 649 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
yihui 9:05f0b5a3a70a 650 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
yihui 9:05f0b5a3a70a 651
yihui 9:05f0b5a3a70a 652 /* SysTick Calibration Register Definitions */
yihui 9:05f0b5a3a70a 653 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
yihui 9:05f0b5a3a70a 654 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
yihui 9:05f0b5a3a70a 655
yihui 9:05f0b5a3a70a 656 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
yihui 9:05f0b5a3a70a 657 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
yihui 9:05f0b5a3a70a 658
yihui 9:05f0b5a3a70a 659 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
yihui 9:05f0b5a3a70a 660 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
yihui 9:05f0b5a3a70a 661
yihui 9:05f0b5a3a70a 662 /*@} end of group CMSIS_SysTick */
yihui 9:05f0b5a3a70a 663
yihui 9:05f0b5a3a70a 664
yihui 9:05f0b5a3a70a 665 /** \ingroup CMSIS_core_register
yihui 9:05f0b5a3a70a 666 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
yihui 9:05f0b5a3a70a 667 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
yihui 9:05f0b5a3a70a 668 @{
yihui 9:05f0b5a3a70a 669 */
yihui 9:05f0b5a3a70a 670
yihui 9:05f0b5a3a70a 671 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
yihui 9:05f0b5a3a70a 672 */
yihui 9:05f0b5a3a70a 673 typedef struct
yihui 9:05f0b5a3a70a 674 {
yihui 9:05f0b5a3a70a 675 __O union
yihui 9:05f0b5a3a70a 676 {
yihui 9:05f0b5a3a70a 677 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
yihui 9:05f0b5a3a70a 678 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
yihui 9:05f0b5a3a70a 679 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
yihui 9:05f0b5a3a70a 680 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
yihui 9:05f0b5a3a70a 681 uint32_t RESERVED0[864];
yihui 9:05f0b5a3a70a 682 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
yihui 9:05f0b5a3a70a 683 uint32_t RESERVED1[15];
yihui 9:05f0b5a3a70a 684 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
yihui 9:05f0b5a3a70a 685 uint32_t RESERVED2[15];
yihui 9:05f0b5a3a70a 686 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
yihui 9:05f0b5a3a70a 687 uint32_t RESERVED3[29];
yihui 9:05f0b5a3a70a 688 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
yihui 9:05f0b5a3a70a 689 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
yihui 9:05f0b5a3a70a 690 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
yihui 9:05f0b5a3a70a 691 uint32_t RESERVED4[43];
yihui 9:05f0b5a3a70a 692 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
yihui 9:05f0b5a3a70a 693 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
yihui 9:05f0b5a3a70a 694 uint32_t RESERVED5[6];
yihui 9:05f0b5a3a70a 695 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
yihui 9:05f0b5a3a70a 696 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
yihui 9:05f0b5a3a70a 697 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
yihui 9:05f0b5a3a70a 698 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
yihui 9:05f0b5a3a70a 699 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
yihui 9:05f0b5a3a70a 700 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
yihui 9:05f0b5a3a70a 701 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
yihui 9:05f0b5a3a70a 702 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
yihui 9:05f0b5a3a70a 703 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
yihui 9:05f0b5a3a70a 704 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
yihui 9:05f0b5a3a70a 705 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
yihui 9:05f0b5a3a70a 706 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
yihui 9:05f0b5a3a70a 707 } ITM_Type;
yihui 9:05f0b5a3a70a 708
yihui 9:05f0b5a3a70a 709 /* ITM Trace Privilege Register Definitions */
yihui 9:05f0b5a3a70a 710 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
yihui 9:05f0b5a3a70a 711 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
yihui 9:05f0b5a3a70a 712
yihui 9:05f0b5a3a70a 713 /* ITM Trace Control Register Definitions */
yihui 9:05f0b5a3a70a 714 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
yihui 9:05f0b5a3a70a 715 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
yihui 9:05f0b5a3a70a 716
yihui 9:05f0b5a3a70a 717 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
yihui 9:05f0b5a3a70a 718 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
yihui 9:05f0b5a3a70a 719
yihui 9:05f0b5a3a70a 720 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
yihui 9:05f0b5a3a70a 721 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
yihui 9:05f0b5a3a70a 722
yihui 9:05f0b5a3a70a 723 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
yihui 9:05f0b5a3a70a 724 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
yihui 9:05f0b5a3a70a 725
yihui 9:05f0b5a3a70a 726 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
yihui 9:05f0b5a3a70a 727 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
yihui 9:05f0b5a3a70a 728
yihui 9:05f0b5a3a70a 729 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
yihui 9:05f0b5a3a70a 730 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
yihui 9:05f0b5a3a70a 731
yihui 9:05f0b5a3a70a 732 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
yihui 9:05f0b5a3a70a 733 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
yihui 9:05f0b5a3a70a 734
yihui 9:05f0b5a3a70a 735 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
yihui 9:05f0b5a3a70a 736 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
yihui 9:05f0b5a3a70a 737
yihui 9:05f0b5a3a70a 738 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
yihui 9:05f0b5a3a70a 739 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
yihui 9:05f0b5a3a70a 740
yihui 9:05f0b5a3a70a 741 /* ITM Integration Write Register Definitions */
yihui 9:05f0b5a3a70a 742 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
yihui 9:05f0b5a3a70a 743 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
yihui 9:05f0b5a3a70a 744
yihui 9:05f0b5a3a70a 745 /* ITM Integration Read Register Definitions */
yihui 9:05f0b5a3a70a 746 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
yihui 9:05f0b5a3a70a 747 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
yihui 9:05f0b5a3a70a 748
yihui 9:05f0b5a3a70a 749 /* ITM Integration Mode Control Register Definitions */
yihui 9:05f0b5a3a70a 750 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
yihui 9:05f0b5a3a70a 751 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
yihui 9:05f0b5a3a70a 752
yihui 9:05f0b5a3a70a 753 /* ITM Lock Status Register Definitions */
yihui 9:05f0b5a3a70a 754 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
yihui 9:05f0b5a3a70a 755 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
yihui 9:05f0b5a3a70a 756
yihui 9:05f0b5a3a70a 757 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
yihui 9:05f0b5a3a70a 758 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
yihui 9:05f0b5a3a70a 759
yihui 9:05f0b5a3a70a 760 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
yihui 9:05f0b5a3a70a 761 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
yihui 9:05f0b5a3a70a 762
yihui 9:05f0b5a3a70a 763 /*@}*/ /* end of group CMSIS_ITM */
yihui 9:05f0b5a3a70a 764
yihui 9:05f0b5a3a70a 765
yihui 9:05f0b5a3a70a 766 /** \ingroup CMSIS_core_register
yihui 9:05f0b5a3a70a 767 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
yihui 9:05f0b5a3a70a 768 \brief Type definitions for the Data Watchpoint and Trace (DWT)
yihui 9:05f0b5a3a70a 769 @{
yihui 9:05f0b5a3a70a 770 */
yihui 9:05f0b5a3a70a 771
yihui 9:05f0b5a3a70a 772 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
yihui 9:05f0b5a3a70a 773 */
yihui 9:05f0b5a3a70a 774 typedef struct
yihui 9:05f0b5a3a70a 775 {
yihui 9:05f0b5a3a70a 776 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
yihui 9:05f0b5a3a70a 777 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
yihui 9:05f0b5a3a70a 778 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
yihui 9:05f0b5a3a70a 779 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
yihui 9:05f0b5a3a70a 780 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
yihui 9:05f0b5a3a70a 781 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
yihui 9:05f0b5a3a70a 782 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
yihui 9:05f0b5a3a70a 783 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
yihui 9:05f0b5a3a70a 784 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
yihui 9:05f0b5a3a70a 785 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
yihui 9:05f0b5a3a70a 786 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
yihui 9:05f0b5a3a70a 787 uint32_t RESERVED0[1];
yihui 9:05f0b5a3a70a 788 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
yihui 9:05f0b5a3a70a 789 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
yihui 9:05f0b5a3a70a 790 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
yihui 9:05f0b5a3a70a 791 uint32_t RESERVED1[1];
yihui 9:05f0b5a3a70a 792 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
yihui 9:05f0b5a3a70a 793 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
yihui 9:05f0b5a3a70a 794 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
yihui 9:05f0b5a3a70a 795 uint32_t RESERVED2[1];
yihui 9:05f0b5a3a70a 796 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
yihui 9:05f0b5a3a70a 797 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
yihui 9:05f0b5a3a70a 798 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
yihui 9:05f0b5a3a70a 799 } DWT_Type;
yihui 9:05f0b5a3a70a 800
yihui 9:05f0b5a3a70a 801 /* DWT Control Register Definitions */
yihui 9:05f0b5a3a70a 802 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
yihui 9:05f0b5a3a70a 803 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
yihui 9:05f0b5a3a70a 804
yihui 9:05f0b5a3a70a 805 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
yihui 9:05f0b5a3a70a 806 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
yihui 9:05f0b5a3a70a 807
yihui 9:05f0b5a3a70a 808 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
yihui 9:05f0b5a3a70a 809 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
yihui 9:05f0b5a3a70a 810
yihui 9:05f0b5a3a70a 811 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
yihui 9:05f0b5a3a70a 812 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
yihui 9:05f0b5a3a70a 813
yihui 9:05f0b5a3a70a 814 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
yihui 9:05f0b5a3a70a 815 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
yihui 9:05f0b5a3a70a 816
yihui 9:05f0b5a3a70a 817 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
yihui 9:05f0b5a3a70a 818 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
yihui 9:05f0b5a3a70a 819
yihui 9:05f0b5a3a70a 820 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
yihui 9:05f0b5a3a70a 821 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
yihui 9:05f0b5a3a70a 822
yihui 9:05f0b5a3a70a 823 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
yihui 9:05f0b5a3a70a 824 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
yihui 9:05f0b5a3a70a 825
yihui 9:05f0b5a3a70a 826 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
yihui 9:05f0b5a3a70a 827 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
yihui 9:05f0b5a3a70a 828
yihui 9:05f0b5a3a70a 829 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
yihui 9:05f0b5a3a70a 830 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
yihui 9:05f0b5a3a70a 831
yihui 9:05f0b5a3a70a 832 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
yihui 9:05f0b5a3a70a 833 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
yihui 9:05f0b5a3a70a 834
yihui 9:05f0b5a3a70a 835 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
yihui 9:05f0b5a3a70a 836 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
yihui 9:05f0b5a3a70a 837
yihui 9:05f0b5a3a70a 838 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
yihui 9:05f0b5a3a70a 839 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
yihui 9:05f0b5a3a70a 840
yihui 9:05f0b5a3a70a 841 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
yihui 9:05f0b5a3a70a 842 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
yihui 9:05f0b5a3a70a 843
yihui 9:05f0b5a3a70a 844 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
yihui 9:05f0b5a3a70a 845 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
yihui 9:05f0b5a3a70a 846
yihui 9:05f0b5a3a70a 847 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
yihui 9:05f0b5a3a70a 848 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
yihui 9:05f0b5a3a70a 849
yihui 9:05f0b5a3a70a 850 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
yihui 9:05f0b5a3a70a 851 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
yihui 9:05f0b5a3a70a 852
yihui 9:05f0b5a3a70a 853 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
yihui 9:05f0b5a3a70a 854 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
yihui 9:05f0b5a3a70a 855
yihui 9:05f0b5a3a70a 856 /* DWT CPI Count Register Definitions */
yihui 9:05f0b5a3a70a 857 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
yihui 9:05f0b5a3a70a 858 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
yihui 9:05f0b5a3a70a 859
yihui 9:05f0b5a3a70a 860 /* DWT Exception Overhead Count Register Definitions */
yihui 9:05f0b5a3a70a 861 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
yihui 9:05f0b5a3a70a 862 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
yihui 9:05f0b5a3a70a 863
yihui 9:05f0b5a3a70a 864 /* DWT Sleep Count Register Definitions */
yihui 9:05f0b5a3a70a 865 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
yihui 9:05f0b5a3a70a 866 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
yihui 9:05f0b5a3a70a 867
yihui 9:05f0b5a3a70a 868 /* DWT LSU Count Register Definitions */
yihui 9:05f0b5a3a70a 869 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
yihui 9:05f0b5a3a70a 870 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
yihui 9:05f0b5a3a70a 871
yihui 9:05f0b5a3a70a 872 /* DWT Folded-instruction Count Register Definitions */
yihui 9:05f0b5a3a70a 873 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
yihui 9:05f0b5a3a70a 874 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
yihui 9:05f0b5a3a70a 875
yihui 9:05f0b5a3a70a 876 /* DWT Comparator Mask Register Definitions */
yihui 9:05f0b5a3a70a 877 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
yihui 9:05f0b5a3a70a 878 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
yihui 9:05f0b5a3a70a 879
yihui 9:05f0b5a3a70a 880 /* DWT Comparator Function Register Definitions */
yihui 9:05f0b5a3a70a 881 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
yihui 9:05f0b5a3a70a 882 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
yihui 9:05f0b5a3a70a 883
yihui 9:05f0b5a3a70a 884 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
yihui 9:05f0b5a3a70a 885 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
yihui 9:05f0b5a3a70a 886
yihui 9:05f0b5a3a70a 887 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
yihui 9:05f0b5a3a70a 888 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
yihui 9:05f0b5a3a70a 889
yihui 9:05f0b5a3a70a 890 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
yihui 9:05f0b5a3a70a 891 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
yihui 9:05f0b5a3a70a 892
yihui 9:05f0b5a3a70a 893 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
yihui 9:05f0b5a3a70a 894 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
yihui 9:05f0b5a3a70a 895
yihui 9:05f0b5a3a70a 896 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
yihui 9:05f0b5a3a70a 897 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
yihui 9:05f0b5a3a70a 898
yihui 9:05f0b5a3a70a 899 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
yihui 9:05f0b5a3a70a 900 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
yihui 9:05f0b5a3a70a 901
yihui 9:05f0b5a3a70a 902 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
yihui 9:05f0b5a3a70a 903 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
yihui 9:05f0b5a3a70a 904
yihui 9:05f0b5a3a70a 905 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
yihui 9:05f0b5a3a70a 906 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
yihui 9:05f0b5a3a70a 907
yihui 9:05f0b5a3a70a 908 /*@}*/ /* end of group CMSIS_DWT */
yihui 9:05f0b5a3a70a 909
yihui 9:05f0b5a3a70a 910
yihui 9:05f0b5a3a70a 911 /** \ingroup CMSIS_core_register
yihui 9:05f0b5a3a70a 912 \defgroup CMSIS_TPI Trace Port Interface (TPI)
yihui 9:05f0b5a3a70a 913 \brief Type definitions for the Trace Port Interface (TPI)
yihui 9:05f0b5a3a70a 914 @{
yihui 9:05f0b5a3a70a 915 */
yihui 9:05f0b5a3a70a 916
yihui 9:05f0b5a3a70a 917 /** \brief Structure type to access the Trace Port Interface Register (TPI).
yihui 9:05f0b5a3a70a 918 */
yihui 9:05f0b5a3a70a 919 typedef struct
yihui 9:05f0b5a3a70a 920 {
yihui 9:05f0b5a3a70a 921 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
yihui 9:05f0b5a3a70a 922 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
yihui 9:05f0b5a3a70a 923 uint32_t RESERVED0[2];
yihui 9:05f0b5a3a70a 924 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
yihui 9:05f0b5a3a70a 925 uint32_t RESERVED1[55];
yihui 9:05f0b5a3a70a 926 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
yihui 9:05f0b5a3a70a 927 uint32_t RESERVED2[131];
yihui 9:05f0b5a3a70a 928 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
yihui 9:05f0b5a3a70a 929 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
yihui 9:05f0b5a3a70a 930 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
yihui 9:05f0b5a3a70a 931 uint32_t RESERVED3[759];
yihui 9:05f0b5a3a70a 932 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
yihui 9:05f0b5a3a70a 933 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
yihui 9:05f0b5a3a70a 934 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
yihui 9:05f0b5a3a70a 935 uint32_t RESERVED4[1];
yihui 9:05f0b5a3a70a 936 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
yihui 9:05f0b5a3a70a 937 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
yihui 9:05f0b5a3a70a 938 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
yihui 9:05f0b5a3a70a 939 uint32_t RESERVED5[39];
yihui 9:05f0b5a3a70a 940 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
yihui 9:05f0b5a3a70a 941 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
yihui 9:05f0b5a3a70a 942 uint32_t RESERVED7[8];
yihui 9:05f0b5a3a70a 943 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
yihui 9:05f0b5a3a70a 944 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
yihui 9:05f0b5a3a70a 945 } TPI_Type;
yihui 9:05f0b5a3a70a 946
yihui 9:05f0b5a3a70a 947 /* TPI Asynchronous Clock Prescaler Register Definitions */
yihui 9:05f0b5a3a70a 948 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
yihui 9:05f0b5a3a70a 949 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
yihui 9:05f0b5a3a70a 950
yihui 9:05f0b5a3a70a 951 /* TPI Selected Pin Protocol Register Definitions */
yihui 9:05f0b5a3a70a 952 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
yihui 9:05f0b5a3a70a 953 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
yihui 9:05f0b5a3a70a 954
yihui 9:05f0b5a3a70a 955 /* TPI Formatter and Flush Status Register Definitions */
yihui 9:05f0b5a3a70a 956 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
yihui 9:05f0b5a3a70a 957 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
yihui 9:05f0b5a3a70a 958
yihui 9:05f0b5a3a70a 959 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
yihui 9:05f0b5a3a70a 960 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
yihui 9:05f0b5a3a70a 961
yihui 9:05f0b5a3a70a 962 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
yihui 9:05f0b5a3a70a 963 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
yihui 9:05f0b5a3a70a 964
yihui 9:05f0b5a3a70a 965 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
yihui 9:05f0b5a3a70a 966 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
yihui 9:05f0b5a3a70a 967
yihui 9:05f0b5a3a70a 968 /* TPI Formatter and Flush Control Register Definitions */
yihui 9:05f0b5a3a70a 969 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
yihui 9:05f0b5a3a70a 970 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
yihui 9:05f0b5a3a70a 971
yihui 9:05f0b5a3a70a 972 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
yihui 9:05f0b5a3a70a 973 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
yihui 9:05f0b5a3a70a 974
yihui 9:05f0b5a3a70a 975 /* TPI TRIGGER Register Definitions */
yihui 9:05f0b5a3a70a 976 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
yihui 9:05f0b5a3a70a 977 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
yihui 9:05f0b5a3a70a 978
yihui 9:05f0b5a3a70a 979 /* TPI Integration ETM Data Register Definitions (FIFO0) */
yihui 9:05f0b5a3a70a 980 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
yihui 9:05f0b5a3a70a 981 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
yihui 9:05f0b5a3a70a 982
yihui 9:05f0b5a3a70a 983 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
yihui 9:05f0b5a3a70a 984 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
yihui 9:05f0b5a3a70a 985
yihui 9:05f0b5a3a70a 986 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
yihui 9:05f0b5a3a70a 987 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
yihui 9:05f0b5a3a70a 988
yihui 9:05f0b5a3a70a 989 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
yihui 9:05f0b5a3a70a 990 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
yihui 9:05f0b5a3a70a 991
yihui 9:05f0b5a3a70a 992 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
yihui 9:05f0b5a3a70a 993 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
yihui 9:05f0b5a3a70a 994
yihui 9:05f0b5a3a70a 995 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
yihui 9:05f0b5a3a70a 996 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
yihui 9:05f0b5a3a70a 997
yihui 9:05f0b5a3a70a 998 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
yihui 9:05f0b5a3a70a 999 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
yihui 9:05f0b5a3a70a 1000
yihui 9:05f0b5a3a70a 1001 /* TPI ITATBCTR2 Register Definitions */
yihui 9:05f0b5a3a70a 1002 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
yihui 9:05f0b5a3a70a 1003 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
yihui 9:05f0b5a3a70a 1004
yihui 9:05f0b5a3a70a 1005 /* TPI Integration ITM Data Register Definitions (FIFO1) */
yihui 9:05f0b5a3a70a 1006 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
yihui 9:05f0b5a3a70a 1007 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
yihui 9:05f0b5a3a70a 1008
yihui 9:05f0b5a3a70a 1009 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
yihui 9:05f0b5a3a70a 1010 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
yihui 9:05f0b5a3a70a 1011
yihui 9:05f0b5a3a70a 1012 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
yihui 9:05f0b5a3a70a 1013 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
yihui 9:05f0b5a3a70a 1014
yihui 9:05f0b5a3a70a 1015 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
yihui 9:05f0b5a3a70a 1016 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
yihui 9:05f0b5a3a70a 1017
yihui 9:05f0b5a3a70a 1018 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
yihui 9:05f0b5a3a70a 1019 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
yihui 9:05f0b5a3a70a 1020
yihui 9:05f0b5a3a70a 1021 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
yihui 9:05f0b5a3a70a 1022 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
yihui 9:05f0b5a3a70a 1023
yihui 9:05f0b5a3a70a 1024 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
yihui 9:05f0b5a3a70a 1025 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
yihui 9:05f0b5a3a70a 1026
yihui 9:05f0b5a3a70a 1027 /* TPI ITATBCTR0 Register Definitions */
yihui 9:05f0b5a3a70a 1028 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
yihui 9:05f0b5a3a70a 1029 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
yihui 9:05f0b5a3a70a 1030
yihui 9:05f0b5a3a70a 1031 /* TPI Integration Mode Control Register Definitions */
yihui 9:05f0b5a3a70a 1032 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
yihui 9:05f0b5a3a70a 1033 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
yihui 9:05f0b5a3a70a 1034
yihui 9:05f0b5a3a70a 1035 /* TPI DEVID Register Definitions */
yihui 9:05f0b5a3a70a 1036 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
yihui 9:05f0b5a3a70a 1037 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
yihui 9:05f0b5a3a70a 1038
yihui 9:05f0b5a3a70a 1039 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
yihui 9:05f0b5a3a70a 1040 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
yihui 9:05f0b5a3a70a 1041
yihui 9:05f0b5a3a70a 1042 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
yihui 9:05f0b5a3a70a 1043 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
yihui 9:05f0b5a3a70a 1044
yihui 9:05f0b5a3a70a 1045 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
yihui 9:05f0b5a3a70a 1046 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
yihui 9:05f0b5a3a70a 1047
yihui 9:05f0b5a3a70a 1048 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
yihui 9:05f0b5a3a70a 1049 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
yihui 9:05f0b5a3a70a 1050
yihui 9:05f0b5a3a70a 1051 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
yihui 9:05f0b5a3a70a 1052 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
yihui 9:05f0b5a3a70a 1053
yihui 9:05f0b5a3a70a 1054 /* TPI DEVTYPE Register Definitions */
yihui 9:05f0b5a3a70a 1055 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
yihui 9:05f0b5a3a70a 1056 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
yihui 9:05f0b5a3a70a 1057
yihui 9:05f0b5a3a70a 1058 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
yihui 9:05f0b5a3a70a 1059 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
yihui 9:05f0b5a3a70a 1060
yihui 9:05f0b5a3a70a 1061 /*@}*/ /* end of group CMSIS_TPI */
yihui 9:05f0b5a3a70a 1062
yihui 9:05f0b5a3a70a 1063
yihui 9:05f0b5a3a70a 1064 #if (__MPU_PRESENT == 1)
yihui 9:05f0b5a3a70a 1065 /** \ingroup CMSIS_core_register
yihui 9:05f0b5a3a70a 1066 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
yihui 9:05f0b5a3a70a 1067 \brief Type definitions for the Memory Protection Unit (MPU)
yihui 9:05f0b5a3a70a 1068 @{
yihui 9:05f0b5a3a70a 1069 */
yihui 9:05f0b5a3a70a 1070
yihui 9:05f0b5a3a70a 1071 /** \brief Structure type to access the Memory Protection Unit (MPU).
yihui 9:05f0b5a3a70a 1072 */
yihui 9:05f0b5a3a70a 1073 typedef struct
yihui 9:05f0b5a3a70a 1074 {
yihui 9:05f0b5a3a70a 1075 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
yihui 9:05f0b5a3a70a 1076 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
yihui 9:05f0b5a3a70a 1077 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
yihui 9:05f0b5a3a70a 1078 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
yihui 9:05f0b5a3a70a 1079 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
yihui 9:05f0b5a3a70a 1080 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
yihui 9:05f0b5a3a70a 1081 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
yihui 9:05f0b5a3a70a 1082 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
yihui 9:05f0b5a3a70a 1083 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
yihui 9:05f0b5a3a70a 1084 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
yihui 9:05f0b5a3a70a 1085 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
yihui 9:05f0b5a3a70a 1086 } MPU_Type;
yihui 9:05f0b5a3a70a 1087
yihui 9:05f0b5a3a70a 1088 /* MPU Type Register */
yihui 9:05f0b5a3a70a 1089 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
yihui 9:05f0b5a3a70a 1090 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
yihui 9:05f0b5a3a70a 1091
yihui 9:05f0b5a3a70a 1092 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
yihui 9:05f0b5a3a70a 1093 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
yihui 9:05f0b5a3a70a 1094
yihui 9:05f0b5a3a70a 1095 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
yihui 9:05f0b5a3a70a 1096 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
yihui 9:05f0b5a3a70a 1097
yihui 9:05f0b5a3a70a 1098 /* MPU Control Register */
yihui 9:05f0b5a3a70a 1099 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
yihui 9:05f0b5a3a70a 1100 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
yihui 9:05f0b5a3a70a 1101
yihui 9:05f0b5a3a70a 1102 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
yihui 9:05f0b5a3a70a 1103 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
yihui 9:05f0b5a3a70a 1104
yihui 9:05f0b5a3a70a 1105 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
yihui 9:05f0b5a3a70a 1106 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
yihui 9:05f0b5a3a70a 1107
yihui 9:05f0b5a3a70a 1108 /* MPU Region Number Register */
yihui 9:05f0b5a3a70a 1109 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
yihui 9:05f0b5a3a70a 1110 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
yihui 9:05f0b5a3a70a 1111
yihui 9:05f0b5a3a70a 1112 /* MPU Region Base Address Register */
yihui 9:05f0b5a3a70a 1113 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
yihui 9:05f0b5a3a70a 1114 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
yihui 9:05f0b5a3a70a 1115
yihui 9:05f0b5a3a70a 1116 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
yihui 9:05f0b5a3a70a 1117 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
yihui 9:05f0b5a3a70a 1118
yihui 9:05f0b5a3a70a 1119 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
yihui 9:05f0b5a3a70a 1120 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
yihui 9:05f0b5a3a70a 1121
yihui 9:05f0b5a3a70a 1122 /* MPU Region Attribute and Size Register */
yihui 9:05f0b5a3a70a 1123 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
yihui 9:05f0b5a3a70a 1124 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
yihui 9:05f0b5a3a70a 1125
yihui 9:05f0b5a3a70a 1126 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
yihui 9:05f0b5a3a70a 1127 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
yihui 9:05f0b5a3a70a 1128
yihui 9:05f0b5a3a70a 1129 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
yihui 9:05f0b5a3a70a 1130 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
yihui 9:05f0b5a3a70a 1131
yihui 9:05f0b5a3a70a 1132 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
yihui 9:05f0b5a3a70a 1133 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
yihui 9:05f0b5a3a70a 1134
yihui 9:05f0b5a3a70a 1135 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
yihui 9:05f0b5a3a70a 1136 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
yihui 9:05f0b5a3a70a 1137
yihui 9:05f0b5a3a70a 1138 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
yihui 9:05f0b5a3a70a 1139 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
yihui 9:05f0b5a3a70a 1140
yihui 9:05f0b5a3a70a 1141 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
yihui 9:05f0b5a3a70a 1142 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
yihui 9:05f0b5a3a70a 1143
yihui 9:05f0b5a3a70a 1144 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
yihui 9:05f0b5a3a70a 1145 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
yihui 9:05f0b5a3a70a 1146
yihui 9:05f0b5a3a70a 1147 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
yihui 9:05f0b5a3a70a 1148 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
yihui 9:05f0b5a3a70a 1149
yihui 9:05f0b5a3a70a 1150 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
yihui 9:05f0b5a3a70a 1151 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
yihui 9:05f0b5a3a70a 1152
yihui 9:05f0b5a3a70a 1153 /*@} end of group CMSIS_MPU */
yihui 9:05f0b5a3a70a 1154 #endif
yihui 9:05f0b5a3a70a 1155
yihui 9:05f0b5a3a70a 1156
yihui 9:05f0b5a3a70a 1157 #if (__FPU_PRESENT == 1)
yihui 9:05f0b5a3a70a 1158 /** \ingroup CMSIS_core_register
yihui 9:05f0b5a3a70a 1159 \defgroup CMSIS_FPU Floating Point Unit (FPU)
yihui 9:05f0b5a3a70a 1160 \brief Type definitions for the Floating Point Unit (FPU)
yihui 9:05f0b5a3a70a 1161 @{
yihui 9:05f0b5a3a70a 1162 */
yihui 9:05f0b5a3a70a 1163
yihui 9:05f0b5a3a70a 1164 /** \brief Structure type to access the Floating Point Unit (FPU).
yihui 9:05f0b5a3a70a 1165 */
yihui 9:05f0b5a3a70a 1166 typedef struct
yihui 9:05f0b5a3a70a 1167 {
yihui 9:05f0b5a3a70a 1168 uint32_t RESERVED0[1];
yihui 9:05f0b5a3a70a 1169 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
yihui 9:05f0b5a3a70a 1170 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
yihui 9:05f0b5a3a70a 1171 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
yihui 9:05f0b5a3a70a 1172 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
yihui 9:05f0b5a3a70a 1173 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
yihui 9:05f0b5a3a70a 1174 } FPU_Type;
yihui 9:05f0b5a3a70a 1175
yihui 9:05f0b5a3a70a 1176 /* Floating-Point Context Control Register */
yihui 9:05f0b5a3a70a 1177 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
yihui 9:05f0b5a3a70a 1178 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
yihui 9:05f0b5a3a70a 1179
yihui 9:05f0b5a3a70a 1180 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
yihui 9:05f0b5a3a70a 1181 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
yihui 9:05f0b5a3a70a 1182
yihui 9:05f0b5a3a70a 1183 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
yihui 9:05f0b5a3a70a 1184 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
yihui 9:05f0b5a3a70a 1185
yihui 9:05f0b5a3a70a 1186 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
yihui 9:05f0b5a3a70a 1187 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
yihui 9:05f0b5a3a70a 1188
yihui 9:05f0b5a3a70a 1189 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
yihui 9:05f0b5a3a70a 1190 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
yihui 9:05f0b5a3a70a 1191
yihui 9:05f0b5a3a70a 1192 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
yihui 9:05f0b5a3a70a 1193 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
yihui 9:05f0b5a3a70a 1194
yihui 9:05f0b5a3a70a 1195 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
yihui 9:05f0b5a3a70a 1196 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
yihui 9:05f0b5a3a70a 1197
yihui 9:05f0b5a3a70a 1198 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
yihui 9:05f0b5a3a70a 1199 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
yihui 9:05f0b5a3a70a 1200
yihui 9:05f0b5a3a70a 1201 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
yihui 9:05f0b5a3a70a 1202 #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
yihui 9:05f0b5a3a70a 1203
yihui 9:05f0b5a3a70a 1204 /* Floating-Point Context Address Register */
yihui 9:05f0b5a3a70a 1205 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
yihui 9:05f0b5a3a70a 1206 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
yihui 9:05f0b5a3a70a 1207
yihui 9:05f0b5a3a70a 1208 /* Floating-Point Default Status Control Register */
yihui 9:05f0b5a3a70a 1209 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
yihui 9:05f0b5a3a70a 1210 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
yihui 9:05f0b5a3a70a 1211
yihui 9:05f0b5a3a70a 1212 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
yihui 9:05f0b5a3a70a 1213 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
yihui 9:05f0b5a3a70a 1214
yihui 9:05f0b5a3a70a 1215 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
yihui 9:05f0b5a3a70a 1216 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
yihui 9:05f0b5a3a70a 1217
yihui 9:05f0b5a3a70a 1218 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
yihui 9:05f0b5a3a70a 1219 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
yihui 9:05f0b5a3a70a 1220
yihui 9:05f0b5a3a70a 1221 /* Media and FP Feature Register 0 */
yihui 9:05f0b5a3a70a 1222 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
yihui 9:05f0b5a3a70a 1223 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
yihui 9:05f0b5a3a70a 1224
yihui 9:05f0b5a3a70a 1225 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
yihui 9:05f0b5a3a70a 1226 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
yihui 9:05f0b5a3a70a 1227
yihui 9:05f0b5a3a70a 1228 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
yihui 9:05f0b5a3a70a 1229 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
yihui 9:05f0b5a3a70a 1230
yihui 9:05f0b5a3a70a 1231 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
yihui 9:05f0b5a3a70a 1232 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
yihui 9:05f0b5a3a70a 1233
yihui 9:05f0b5a3a70a 1234 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
yihui 9:05f0b5a3a70a 1235 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
yihui 9:05f0b5a3a70a 1236
yihui 9:05f0b5a3a70a 1237 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
yihui 9:05f0b5a3a70a 1238 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
yihui 9:05f0b5a3a70a 1239
yihui 9:05f0b5a3a70a 1240 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
yihui 9:05f0b5a3a70a 1241 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
yihui 9:05f0b5a3a70a 1242
yihui 9:05f0b5a3a70a 1243 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
yihui 9:05f0b5a3a70a 1244 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
yihui 9:05f0b5a3a70a 1245
yihui 9:05f0b5a3a70a 1246 /* Media and FP Feature Register 1 */
yihui 9:05f0b5a3a70a 1247 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
yihui 9:05f0b5a3a70a 1248 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
yihui 9:05f0b5a3a70a 1249
yihui 9:05f0b5a3a70a 1250 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
yihui 9:05f0b5a3a70a 1251 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
yihui 9:05f0b5a3a70a 1252
yihui 9:05f0b5a3a70a 1253 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
yihui 9:05f0b5a3a70a 1254 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
yihui 9:05f0b5a3a70a 1255
yihui 9:05f0b5a3a70a 1256 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
yihui 9:05f0b5a3a70a 1257 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
yihui 9:05f0b5a3a70a 1258
yihui 9:05f0b5a3a70a 1259 /*@} end of group CMSIS_FPU */
yihui 9:05f0b5a3a70a 1260 #endif
yihui 9:05f0b5a3a70a 1261
yihui 9:05f0b5a3a70a 1262
yihui 9:05f0b5a3a70a 1263 /** \ingroup CMSIS_core_register
yihui 9:05f0b5a3a70a 1264 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
yihui 9:05f0b5a3a70a 1265 \brief Type definitions for the Core Debug Registers
yihui 9:05f0b5a3a70a 1266 @{
yihui 9:05f0b5a3a70a 1267 */
yihui 9:05f0b5a3a70a 1268
yihui 9:05f0b5a3a70a 1269 /** \brief Structure type to access the Core Debug Register (CoreDebug).
yihui 9:05f0b5a3a70a 1270 */
yihui 9:05f0b5a3a70a 1271 typedef struct
yihui 9:05f0b5a3a70a 1272 {
yihui 9:05f0b5a3a70a 1273 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
yihui 9:05f0b5a3a70a 1274 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
yihui 9:05f0b5a3a70a 1275 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
yihui 9:05f0b5a3a70a 1276 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
yihui 9:05f0b5a3a70a 1277 } CoreDebug_Type;
yihui 9:05f0b5a3a70a 1278
yihui 9:05f0b5a3a70a 1279 /* Debug Halting Control and Status Register */
yihui 9:05f0b5a3a70a 1280 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
yihui 9:05f0b5a3a70a 1281 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
yihui 9:05f0b5a3a70a 1282
yihui 9:05f0b5a3a70a 1283 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
yihui 9:05f0b5a3a70a 1284 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
yihui 9:05f0b5a3a70a 1285
yihui 9:05f0b5a3a70a 1286 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
yihui 9:05f0b5a3a70a 1287 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
yihui 9:05f0b5a3a70a 1288
yihui 9:05f0b5a3a70a 1289 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
yihui 9:05f0b5a3a70a 1290 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
yihui 9:05f0b5a3a70a 1291
yihui 9:05f0b5a3a70a 1292 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
yihui 9:05f0b5a3a70a 1293 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
yihui 9:05f0b5a3a70a 1294
yihui 9:05f0b5a3a70a 1295 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
yihui 9:05f0b5a3a70a 1296 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
yihui 9:05f0b5a3a70a 1297
yihui 9:05f0b5a3a70a 1298 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
yihui 9:05f0b5a3a70a 1299 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
yihui 9:05f0b5a3a70a 1300
yihui 9:05f0b5a3a70a 1301 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
yihui 9:05f0b5a3a70a 1302 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
yihui 9:05f0b5a3a70a 1303
yihui 9:05f0b5a3a70a 1304 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
yihui 9:05f0b5a3a70a 1305 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
yihui 9:05f0b5a3a70a 1306
yihui 9:05f0b5a3a70a 1307 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
yihui 9:05f0b5a3a70a 1308 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
yihui 9:05f0b5a3a70a 1309
yihui 9:05f0b5a3a70a 1310 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
yihui 9:05f0b5a3a70a 1311 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
yihui 9:05f0b5a3a70a 1312
yihui 9:05f0b5a3a70a 1313 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
yihui 9:05f0b5a3a70a 1314 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
yihui 9:05f0b5a3a70a 1315
yihui 9:05f0b5a3a70a 1316 /* Debug Core Register Selector Register */
yihui 9:05f0b5a3a70a 1317 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
yihui 9:05f0b5a3a70a 1318 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
yihui 9:05f0b5a3a70a 1319
yihui 9:05f0b5a3a70a 1320 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
yihui 9:05f0b5a3a70a 1321 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
yihui 9:05f0b5a3a70a 1322
yihui 9:05f0b5a3a70a 1323 /* Debug Exception and Monitor Control Register */
yihui 9:05f0b5a3a70a 1324 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
yihui 9:05f0b5a3a70a 1325 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
yihui 9:05f0b5a3a70a 1326
yihui 9:05f0b5a3a70a 1327 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
yihui 9:05f0b5a3a70a 1328 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
yihui 9:05f0b5a3a70a 1329
yihui 9:05f0b5a3a70a 1330 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
yihui 9:05f0b5a3a70a 1331 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
yihui 9:05f0b5a3a70a 1332
yihui 9:05f0b5a3a70a 1333 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
yihui 9:05f0b5a3a70a 1334 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
yihui 9:05f0b5a3a70a 1335
yihui 9:05f0b5a3a70a 1336 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
yihui 9:05f0b5a3a70a 1337 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
yihui 9:05f0b5a3a70a 1338
yihui 9:05f0b5a3a70a 1339 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
yihui 9:05f0b5a3a70a 1340 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
yihui 9:05f0b5a3a70a 1341
yihui 9:05f0b5a3a70a 1342 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
yihui 9:05f0b5a3a70a 1343 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
yihui 9:05f0b5a3a70a 1344
yihui 9:05f0b5a3a70a 1345 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
yihui 9:05f0b5a3a70a 1346 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
yihui 9:05f0b5a3a70a 1347
yihui 9:05f0b5a3a70a 1348 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
yihui 9:05f0b5a3a70a 1349 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
yihui 9:05f0b5a3a70a 1350
yihui 9:05f0b5a3a70a 1351 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
yihui 9:05f0b5a3a70a 1352 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
yihui 9:05f0b5a3a70a 1353
yihui 9:05f0b5a3a70a 1354 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
yihui 9:05f0b5a3a70a 1355 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
yihui 9:05f0b5a3a70a 1356
yihui 9:05f0b5a3a70a 1357 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
yihui 9:05f0b5a3a70a 1358 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
yihui 9:05f0b5a3a70a 1359
yihui 9:05f0b5a3a70a 1360 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
yihui 9:05f0b5a3a70a 1361 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
yihui 9:05f0b5a3a70a 1362
yihui 9:05f0b5a3a70a 1363 /*@} end of group CMSIS_CoreDebug */
yihui 9:05f0b5a3a70a 1364
yihui 9:05f0b5a3a70a 1365
yihui 9:05f0b5a3a70a 1366 /** \ingroup CMSIS_core_register
yihui 9:05f0b5a3a70a 1367 \defgroup CMSIS_core_base Core Definitions
yihui 9:05f0b5a3a70a 1368 \brief Definitions for base addresses, unions, and structures.
yihui 9:05f0b5a3a70a 1369 @{
yihui 9:05f0b5a3a70a 1370 */
yihui 9:05f0b5a3a70a 1371
yihui 9:05f0b5a3a70a 1372 /* Memory mapping of Cortex-M4 Hardware */
yihui 9:05f0b5a3a70a 1373 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
yihui 9:05f0b5a3a70a 1374 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
yihui 9:05f0b5a3a70a 1375 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
yihui 9:05f0b5a3a70a 1376 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
yihui 9:05f0b5a3a70a 1377 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
yihui 9:05f0b5a3a70a 1378 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
yihui 9:05f0b5a3a70a 1379 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
yihui 9:05f0b5a3a70a 1380 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
yihui 9:05f0b5a3a70a 1381
yihui 9:05f0b5a3a70a 1382 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
yihui 9:05f0b5a3a70a 1383 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
yihui 9:05f0b5a3a70a 1384 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
yihui 9:05f0b5a3a70a 1385 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
yihui 9:05f0b5a3a70a 1386 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
yihui 9:05f0b5a3a70a 1387 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
yihui 9:05f0b5a3a70a 1388 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
yihui 9:05f0b5a3a70a 1389 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
yihui 9:05f0b5a3a70a 1390
yihui 9:05f0b5a3a70a 1391 #if (__MPU_PRESENT == 1)
yihui 9:05f0b5a3a70a 1392 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
yihui 9:05f0b5a3a70a 1393 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
yihui 9:05f0b5a3a70a 1394 #endif
yihui 9:05f0b5a3a70a 1395
yihui 9:05f0b5a3a70a 1396 #if (__FPU_PRESENT == 1)
yihui 9:05f0b5a3a70a 1397 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
yihui 9:05f0b5a3a70a 1398 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
yihui 9:05f0b5a3a70a 1399 #endif
yihui 9:05f0b5a3a70a 1400
yihui 9:05f0b5a3a70a 1401 /*@} */
yihui 9:05f0b5a3a70a 1402
yihui 9:05f0b5a3a70a 1403
yihui 9:05f0b5a3a70a 1404
yihui 9:05f0b5a3a70a 1405 /*******************************************************************************
yihui 9:05f0b5a3a70a 1406 * Hardware Abstraction Layer
yihui 9:05f0b5a3a70a 1407 Core Function Interface contains:
yihui 9:05f0b5a3a70a 1408 - Core NVIC Functions
yihui 9:05f0b5a3a70a 1409 - Core SysTick Functions
yihui 9:05f0b5a3a70a 1410 - Core Debug Functions
yihui 9:05f0b5a3a70a 1411 - Core Register Access Functions
yihui 9:05f0b5a3a70a 1412 ******************************************************************************/
yihui 9:05f0b5a3a70a 1413 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
yihui 9:05f0b5a3a70a 1414 */
yihui 9:05f0b5a3a70a 1415
yihui 9:05f0b5a3a70a 1416
yihui 9:05f0b5a3a70a 1417
yihui 9:05f0b5a3a70a 1418 /* ########################## NVIC functions #################################### */
yihui 9:05f0b5a3a70a 1419 /** \ingroup CMSIS_Core_FunctionInterface
yihui 9:05f0b5a3a70a 1420 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
yihui 9:05f0b5a3a70a 1421 \brief Functions that manage interrupts and exceptions via the NVIC.
yihui 9:05f0b5a3a70a 1422 @{
yihui 9:05f0b5a3a70a 1423 */
yihui 9:05f0b5a3a70a 1424
yihui 9:05f0b5a3a70a 1425 /** \brief Set Priority Grouping
yihui 9:05f0b5a3a70a 1426
yihui 9:05f0b5a3a70a 1427 The function sets the priority grouping field using the required unlock sequence.
yihui 9:05f0b5a3a70a 1428 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
yihui 9:05f0b5a3a70a 1429 Only values from 0..7 are used.
yihui 9:05f0b5a3a70a 1430 In case of a conflict between priority grouping and available
yihui 9:05f0b5a3a70a 1431 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
yihui 9:05f0b5a3a70a 1432
yihui 9:05f0b5a3a70a 1433 \param [in] PriorityGroup Priority grouping field.
yihui 9:05f0b5a3a70a 1434 */
yihui 9:05f0b5a3a70a 1435 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
yihui 9:05f0b5a3a70a 1436 {
yihui 9:05f0b5a3a70a 1437 uint32_t reg_value;
yihui 9:05f0b5a3a70a 1438 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
yihui 9:05f0b5a3a70a 1439
yihui 9:05f0b5a3a70a 1440 reg_value = SCB->AIRCR; /* read old register configuration */
yihui 9:05f0b5a3a70a 1441 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
yihui 9:05f0b5a3a70a 1442 reg_value = (reg_value |
yihui 9:05f0b5a3a70a 1443 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
yihui 9:05f0b5a3a70a 1444 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
yihui 9:05f0b5a3a70a 1445 SCB->AIRCR = reg_value;
yihui 9:05f0b5a3a70a 1446 }
yihui 9:05f0b5a3a70a 1447
yihui 9:05f0b5a3a70a 1448
yihui 9:05f0b5a3a70a 1449 /** \brief Get Priority Grouping
yihui 9:05f0b5a3a70a 1450
yihui 9:05f0b5a3a70a 1451 The function reads the priority grouping field from the NVIC Interrupt Controller.
yihui 9:05f0b5a3a70a 1452
yihui 9:05f0b5a3a70a 1453 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
yihui 9:05f0b5a3a70a 1454 */
yihui 9:05f0b5a3a70a 1455 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
yihui 9:05f0b5a3a70a 1456 {
yihui 9:05f0b5a3a70a 1457 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
yihui 9:05f0b5a3a70a 1458 }
yihui 9:05f0b5a3a70a 1459
yihui 9:05f0b5a3a70a 1460
yihui 9:05f0b5a3a70a 1461 /** \brief Enable External Interrupt
yihui 9:05f0b5a3a70a 1462
yihui 9:05f0b5a3a70a 1463 The function enables a device-specific interrupt in the NVIC interrupt controller.
yihui 9:05f0b5a3a70a 1464
yihui 9:05f0b5a3a70a 1465 \param [in] IRQn External interrupt number. Value cannot be negative.
yihui 9:05f0b5a3a70a 1466 */
yihui 9:05f0b5a3a70a 1467 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
yihui 9:05f0b5a3a70a 1468 {
yihui 9:05f0b5a3a70a 1469 /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
yihui 9:05f0b5a3a70a 1470 NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
yihui 9:05f0b5a3a70a 1471 }
yihui 9:05f0b5a3a70a 1472
yihui 9:05f0b5a3a70a 1473
yihui 9:05f0b5a3a70a 1474 /** \brief Disable External Interrupt
yihui 9:05f0b5a3a70a 1475
yihui 9:05f0b5a3a70a 1476 The function disables a device-specific interrupt in the NVIC interrupt controller.
yihui 9:05f0b5a3a70a 1477
yihui 9:05f0b5a3a70a 1478 \param [in] IRQn External interrupt number. Value cannot be negative.
yihui 9:05f0b5a3a70a 1479 */
yihui 9:05f0b5a3a70a 1480 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
yihui 9:05f0b5a3a70a 1481 {
yihui 9:05f0b5a3a70a 1482 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
yihui 9:05f0b5a3a70a 1483 }
yihui 9:05f0b5a3a70a 1484
yihui 9:05f0b5a3a70a 1485
yihui 9:05f0b5a3a70a 1486 /** \brief Get Pending Interrupt
yihui 9:05f0b5a3a70a 1487
yihui 9:05f0b5a3a70a 1488 The function reads the pending register in the NVIC and returns the pending bit
yihui 9:05f0b5a3a70a 1489 for the specified interrupt.
yihui 9:05f0b5a3a70a 1490
yihui 9:05f0b5a3a70a 1491 \param [in] IRQn Interrupt number.
yihui 9:05f0b5a3a70a 1492
yihui 9:05f0b5a3a70a 1493 \return 0 Interrupt status is not pending.
yihui 9:05f0b5a3a70a 1494 \return 1 Interrupt status is pending.
yihui 9:05f0b5a3a70a 1495 */
yihui 9:05f0b5a3a70a 1496 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
yihui 9:05f0b5a3a70a 1497 {
yihui 9:05f0b5a3a70a 1498 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
yihui 9:05f0b5a3a70a 1499 }
yihui 9:05f0b5a3a70a 1500
yihui 9:05f0b5a3a70a 1501
yihui 9:05f0b5a3a70a 1502 /** \brief Set Pending Interrupt
yihui 9:05f0b5a3a70a 1503
yihui 9:05f0b5a3a70a 1504 The function sets the pending bit of an external interrupt.
yihui 9:05f0b5a3a70a 1505
yihui 9:05f0b5a3a70a 1506 \param [in] IRQn Interrupt number. Value cannot be negative.
yihui 9:05f0b5a3a70a 1507 */
yihui 9:05f0b5a3a70a 1508 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
yihui 9:05f0b5a3a70a 1509 {
yihui 9:05f0b5a3a70a 1510 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
yihui 9:05f0b5a3a70a 1511 }
yihui 9:05f0b5a3a70a 1512
yihui 9:05f0b5a3a70a 1513
yihui 9:05f0b5a3a70a 1514 /** \brief Clear Pending Interrupt
yihui 9:05f0b5a3a70a 1515
yihui 9:05f0b5a3a70a 1516 The function clears the pending bit of an external interrupt.
yihui 9:05f0b5a3a70a 1517
yihui 9:05f0b5a3a70a 1518 \param [in] IRQn External interrupt number. Value cannot be negative.
yihui 9:05f0b5a3a70a 1519 */
yihui 9:05f0b5a3a70a 1520 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
yihui 9:05f0b5a3a70a 1521 {
yihui 9:05f0b5a3a70a 1522 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
yihui 9:05f0b5a3a70a 1523 }
yihui 9:05f0b5a3a70a 1524
yihui 9:05f0b5a3a70a 1525
yihui 9:05f0b5a3a70a 1526 /** \brief Get Active Interrupt
yihui 9:05f0b5a3a70a 1527
yihui 9:05f0b5a3a70a 1528 The function reads the active register in NVIC and returns the active bit.
yihui 9:05f0b5a3a70a 1529
yihui 9:05f0b5a3a70a 1530 \param [in] IRQn Interrupt number.
yihui 9:05f0b5a3a70a 1531
yihui 9:05f0b5a3a70a 1532 \return 0 Interrupt status is not active.
yihui 9:05f0b5a3a70a 1533 \return 1 Interrupt status is active.
yihui 9:05f0b5a3a70a 1534 */
yihui 9:05f0b5a3a70a 1535 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
yihui 9:05f0b5a3a70a 1536 {
yihui 9:05f0b5a3a70a 1537 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
yihui 9:05f0b5a3a70a 1538 }
yihui 9:05f0b5a3a70a 1539
yihui 9:05f0b5a3a70a 1540
yihui 9:05f0b5a3a70a 1541 /** \brief Set Interrupt Priority
yihui 9:05f0b5a3a70a 1542
yihui 9:05f0b5a3a70a 1543 The function sets the priority of an interrupt.
yihui 9:05f0b5a3a70a 1544
yihui 9:05f0b5a3a70a 1545 \note The priority cannot be set for every core interrupt.
yihui 9:05f0b5a3a70a 1546
yihui 9:05f0b5a3a70a 1547 \param [in] IRQn Interrupt number.
yihui 9:05f0b5a3a70a 1548 \param [in] priority Priority to set.
yihui 9:05f0b5a3a70a 1549 */
yihui 9:05f0b5a3a70a 1550 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
yihui 9:05f0b5a3a70a 1551 {
yihui 9:05f0b5a3a70a 1552 if(IRQn < 0) {
yihui 9:05f0b5a3a70a 1553 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
yihui 9:05f0b5a3a70a 1554 else {
yihui 9:05f0b5a3a70a 1555 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
yihui 9:05f0b5a3a70a 1556 }
yihui 9:05f0b5a3a70a 1557
yihui 9:05f0b5a3a70a 1558
yihui 9:05f0b5a3a70a 1559 /** \brief Get Interrupt Priority
yihui 9:05f0b5a3a70a 1560
yihui 9:05f0b5a3a70a 1561 The function reads the priority of an interrupt. The interrupt
yihui 9:05f0b5a3a70a 1562 number can be positive to specify an external (device specific)
yihui 9:05f0b5a3a70a 1563 interrupt, or negative to specify an internal (core) interrupt.
yihui 9:05f0b5a3a70a 1564
yihui 9:05f0b5a3a70a 1565
yihui 9:05f0b5a3a70a 1566 \param [in] IRQn Interrupt number.
yihui 9:05f0b5a3a70a 1567 \return Interrupt Priority. Value is aligned automatically to the implemented
yihui 9:05f0b5a3a70a 1568 priority bits of the microcontroller.
yihui 9:05f0b5a3a70a 1569 */
yihui 9:05f0b5a3a70a 1570 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
yihui 9:05f0b5a3a70a 1571 {
yihui 9:05f0b5a3a70a 1572
yihui 9:05f0b5a3a70a 1573 if(IRQn < 0) {
yihui 9:05f0b5a3a70a 1574 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
yihui 9:05f0b5a3a70a 1575 else {
yihui 9:05f0b5a3a70a 1576 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
yihui 9:05f0b5a3a70a 1577 }
yihui 9:05f0b5a3a70a 1578
yihui 9:05f0b5a3a70a 1579
yihui 9:05f0b5a3a70a 1580 /** \brief Encode Priority
yihui 9:05f0b5a3a70a 1581
yihui 9:05f0b5a3a70a 1582 The function encodes the priority for an interrupt with the given priority group,
yihui 9:05f0b5a3a70a 1583 preemptive priority value, and subpriority value.
yihui 9:05f0b5a3a70a 1584 In case of a conflict between priority grouping and available
yihui 9:05f0b5a3a70a 1585 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
yihui 9:05f0b5a3a70a 1586
yihui 9:05f0b5a3a70a 1587 \param [in] PriorityGroup Used priority group.
yihui 9:05f0b5a3a70a 1588 \param [in] PreemptPriority Preemptive priority value (starting from 0).
yihui 9:05f0b5a3a70a 1589 \param [in] SubPriority Subpriority value (starting from 0).
yihui 9:05f0b5a3a70a 1590 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
yihui 9:05f0b5a3a70a 1591 */
yihui 9:05f0b5a3a70a 1592 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
yihui 9:05f0b5a3a70a 1593 {
yihui 9:05f0b5a3a70a 1594 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
yihui 9:05f0b5a3a70a 1595 uint32_t PreemptPriorityBits;
yihui 9:05f0b5a3a70a 1596 uint32_t SubPriorityBits;
yihui 9:05f0b5a3a70a 1597
yihui 9:05f0b5a3a70a 1598 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
yihui 9:05f0b5a3a70a 1599 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
yihui 9:05f0b5a3a70a 1600
yihui 9:05f0b5a3a70a 1601 return (
yihui 9:05f0b5a3a70a 1602 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
yihui 9:05f0b5a3a70a 1603 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
yihui 9:05f0b5a3a70a 1604 );
yihui 9:05f0b5a3a70a 1605 }
yihui 9:05f0b5a3a70a 1606
yihui 9:05f0b5a3a70a 1607
yihui 9:05f0b5a3a70a 1608 /** \brief Decode Priority
yihui 9:05f0b5a3a70a 1609
yihui 9:05f0b5a3a70a 1610 The function decodes an interrupt priority value with a given priority group to
yihui 9:05f0b5a3a70a 1611 preemptive priority value and subpriority value.
yihui 9:05f0b5a3a70a 1612 In case of a conflict between priority grouping and available
yihui 9:05f0b5a3a70a 1613 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
yihui 9:05f0b5a3a70a 1614
yihui 9:05f0b5a3a70a 1615 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
yihui 9:05f0b5a3a70a 1616 \param [in] PriorityGroup Used priority group.
yihui 9:05f0b5a3a70a 1617 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
yihui 9:05f0b5a3a70a 1618 \param [out] pSubPriority Subpriority value (starting from 0).
yihui 9:05f0b5a3a70a 1619 */
yihui 9:05f0b5a3a70a 1620 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
yihui 9:05f0b5a3a70a 1621 {
yihui 9:05f0b5a3a70a 1622 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
yihui 9:05f0b5a3a70a 1623 uint32_t PreemptPriorityBits;
yihui 9:05f0b5a3a70a 1624 uint32_t SubPriorityBits;
yihui 9:05f0b5a3a70a 1625
yihui 9:05f0b5a3a70a 1626 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
yihui 9:05f0b5a3a70a 1627 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
yihui 9:05f0b5a3a70a 1628
yihui 9:05f0b5a3a70a 1629 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
yihui 9:05f0b5a3a70a 1630 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
yihui 9:05f0b5a3a70a 1631 }
yihui 9:05f0b5a3a70a 1632
yihui 9:05f0b5a3a70a 1633
yihui 9:05f0b5a3a70a 1634 /** \brief System Reset
yihui 9:05f0b5a3a70a 1635
yihui 9:05f0b5a3a70a 1636 The function initiates a system reset request to reset the MCU.
yihui 9:05f0b5a3a70a 1637 */
yihui 9:05f0b5a3a70a 1638 __STATIC_INLINE void NVIC_SystemReset(void)
yihui 9:05f0b5a3a70a 1639 {
yihui 9:05f0b5a3a70a 1640 __DSB(); /* Ensure all outstanding memory accesses included
yihui 9:05f0b5a3a70a 1641 buffered write are completed before reset */
yihui 9:05f0b5a3a70a 1642 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
yihui 9:05f0b5a3a70a 1643 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
yihui 9:05f0b5a3a70a 1644 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
yihui 9:05f0b5a3a70a 1645 __DSB(); /* Ensure completion of memory access */
yihui 9:05f0b5a3a70a 1646 while(1); /* wait until reset */
yihui 9:05f0b5a3a70a 1647 }
yihui 9:05f0b5a3a70a 1648
yihui 9:05f0b5a3a70a 1649 /*@} end of CMSIS_Core_NVICFunctions */
yihui 9:05f0b5a3a70a 1650
yihui 9:05f0b5a3a70a 1651
yihui 9:05f0b5a3a70a 1652
yihui 9:05f0b5a3a70a 1653 /* ################################## SysTick function ############################################ */
yihui 9:05f0b5a3a70a 1654 /** \ingroup CMSIS_Core_FunctionInterface
yihui 9:05f0b5a3a70a 1655 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
yihui 9:05f0b5a3a70a 1656 \brief Functions that configure the System.
yihui 9:05f0b5a3a70a 1657 @{
yihui 9:05f0b5a3a70a 1658 */
yihui 9:05f0b5a3a70a 1659
yihui 9:05f0b5a3a70a 1660 #if (__Vendor_SysTickConfig == 0)
yihui 9:05f0b5a3a70a 1661
yihui 9:05f0b5a3a70a 1662 /** \brief System Tick Configuration
yihui 9:05f0b5a3a70a 1663
yihui 9:05f0b5a3a70a 1664 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
yihui 9:05f0b5a3a70a 1665 Counter is in free running mode to generate periodic interrupts.
yihui 9:05f0b5a3a70a 1666
yihui 9:05f0b5a3a70a 1667 \param [in] ticks Number of ticks between two interrupts.
yihui 9:05f0b5a3a70a 1668
yihui 9:05f0b5a3a70a 1669 \return 0 Function succeeded.
yihui 9:05f0b5a3a70a 1670 \return 1 Function failed.
yihui 9:05f0b5a3a70a 1671
yihui 9:05f0b5a3a70a 1672 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
yihui 9:05f0b5a3a70a 1673 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
yihui 9:05f0b5a3a70a 1674 must contain a vendor-specific implementation of this function.
yihui 9:05f0b5a3a70a 1675
yihui 9:05f0b5a3a70a 1676 */
yihui 9:05f0b5a3a70a 1677 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
yihui 9:05f0b5a3a70a 1678 {
yihui 9:05f0b5a3a70a 1679 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
yihui 9:05f0b5a3a70a 1680
yihui 9:05f0b5a3a70a 1681 SysTick->LOAD = ticks - 1; /* set reload register */
yihui 9:05f0b5a3a70a 1682 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
yihui 9:05f0b5a3a70a 1683 SysTick->VAL = 0; /* Load the SysTick Counter Value */
yihui 9:05f0b5a3a70a 1684 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
yihui 9:05f0b5a3a70a 1685 SysTick_CTRL_TICKINT_Msk |
yihui 9:05f0b5a3a70a 1686 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
yihui 9:05f0b5a3a70a 1687 return (0); /* Function successful */
yihui 9:05f0b5a3a70a 1688 }
yihui 9:05f0b5a3a70a 1689
yihui 9:05f0b5a3a70a 1690 #endif
yihui 9:05f0b5a3a70a 1691
yihui 9:05f0b5a3a70a 1692 /*@} end of CMSIS_Core_SysTickFunctions */
yihui 9:05f0b5a3a70a 1693
yihui 9:05f0b5a3a70a 1694
yihui 9:05f0b5a3a70a 1695
yihui 9:05f0b5a3a70a 1696 /* ##################################### Debug In/Output function ########################################### */
yihui 9:05f0b5a3a70a 1697 /** \ingroup CMSIS_Core_FunctionInterface
yihui 9:05f0b5a3a70a 1698 \defgroup CMSIS_core_DebugFunctions ITM Functions
yihui 9:05f0b5a3a70a 1699 \brief Functions that access the ITM debug interface.
yihui 9:05f0b5a3a70a 1700 @{
yihui 9:05f0b5a3a70a 1701 */
yihui 9:05f0b5a3a70a 1702
yihui 9:05f0b5a3a70a 1703 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
yihui 9:05f0b5a3a70a 1704 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
yihui 9:05f0b5a3a70a 1705
yihui 9:05f0b5a3a70a 1706
yihui 9:05f0b5a3a70a 1707 /** \brief ITM Send Character
yihui 9:05f0b5a3a70a 1708
yihui 9:05f0b5a3a70a 1709 The function transmits a character via the ITM channel 0, and
yihui 9:05f0b5a3a70a 1710 \li Just returns when no debugger is connected that has booked the output.
yihui 9:05f0b5a3a70a 1711 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
yihui 9:05f0b5a3a70a 1712
yihui 9:05f0b5a3a70a 1713 \param [in] ch Character to transmit.
yihui 9:05f0b5a3a70a 1714
yihui 9:05f0b5a3a70a 1715 \returns Character to transmit.
yihui 9:05f0b5a3a70a 1716 */
yihui 9:05f0b5a3a70a 1717 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
yihui 9:05f0b5a3a70a 1718 {
yihui 9:05f0b5a3a70a 1719 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
yihui 9:05f0b5a3a70a 1720 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
yihui 9:05f0b5a3a70a 1721 {
yihui 9:05f0b5a3a70a 1722 while (ITM->PORT[0].u32 == 0);
yihui 9:05f0b5a3a70a 1723 ITM->PORT[0].u8 = (uint8_t) ch;
yihui 9:05f0b5a3a70a 1724 }
yihui 9:05f0b5a3a70a 1725 return (ch);
yihui 9:05f0b5a3a70a 1726 }
yihui 9:05f0b5a3a70a 1727
yihui 9:05f0b5a3a70a 1728
yihui 9:05f0b5a3a70a 1729 /** \brief ITM Receive Character
yihui 9:05f0b5a3a70a 1730
yihui 9:05f0b5a3a70a 1731 The function inputs a character via the external variable \ref ITM_RxBuffer.
yihui 9:05f0b5a3a70a 1732
yihui 9:05f0b5a3a70a 1733 \return Received character.
yihui 9:05f0b5a3a70a 1734 \return -1 No character pending.
yihui 9:05f0b5a3a70a 1735 */
yihui 9:05f0b5a3a70a 1736 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
yihui 9:05f0b5a3a70a 1737 int32_t ch = -1; /* no character available */
yihui 9:05f0b5a3a70a 1738
yihui 9:05f0b5a3a70a 1739 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
yihui 9:05f0b5a3a70a 1740 ch = ITM_RxBuffer;
yihui 9:05f0b5a3a70a 1741 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
yihui 9:05f0b5a3a70a 1742 }
yihui 9:05f0b5a3a70a 1743
yihui 9:05f0b5a3a70a 1744 return (ch);
yihui 9:05f0b5a3a70a 1745 }
yihui 9:05f0b5a3a70a 1746
yihui 9:05f0b5a3a70a 1747
yihui 9:05f0b5a3a70a 1748 /** \brief ITM Check Character
yihui 9:05f0b5a3a70a 1749
yihui 9:05f0b5a3a70a 1750 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
yihui 9:05f0b5a3a70a 1751
yihui 9:05f0b5a3a70a 1752 \return 0 No character available.
yihui 9:05f0b5a3a70a 1753 \return 1 Character available.
yihui 9:05f0b5a3a70a 1754 */
yihui 9:05f0b5a3a70a 1755 __STATIC_INLINE int32_t ITM_CheckChar (void) {
yihui 9:05f0b5a3a70a 1756
yihui 9:05f0b5a3a70a 1757 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
yihui 9:05f0b5a3a70a 1758 return (0); /* no character available */
yihui 9:05f0b5a3a70a 1759 } else {
yihui 9:05f0b5a3a70a 1760 return (1); /* character available */
yihui 9:05f0b5a3a70a 1761 }
yihui 9:05f0b5a3a70a 1762 }
yihui 9:05f0b5a3a70a 1763
yihui 9:05f0b5a3a70a 1764 /*@} end of CMSIS_core_DebugFunctions */
yihui 9:05f0b5a3a70a 1765
yihui 9:05f0b5a3a70a 1766 #endif /* __CORE_CM4_H_DEPENDANT */
yihui 9:05f0b5a3a70a 1767
yihui 9:05f0b5a3a70a 1768 #endif /* __CMSIS_GENERIC */
yihui 9:05f0b5a3a70a 1769
yihui 9:05f0b5a3a70a 1770 #ifdef __cplusplus
yihui 9:05f0b5a3a70a 1771 }
yihui 9:05f0b5a3a70a 1772 #endif