Yihui Xiong / BLE_NODE_TEST

Test code for Grove Node BLE

Dependencies:   BLE_API nRF51822

Fork of BLE_LoopbackUART by Bluetooth Low Energy

mbed-src/targets/cmsis/core_cm0plus.h@10:22480ac31879, 2014-11-27 (annotated)

Committer:
yihui
Date:
Thu Nov 27 09:30:36 2014 +0000
Revision:
10:22480ac31879
Parent:
9:05f0b5a3a70a 
change to new revision hardware

Who changed what in which revision?

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yihui 9:05f0b5a3a70a 1 /**************************************************************************//**
yihui 9:05f0b5a3a70a 2 * @file core_cm0plus.h
yihui 9:05f0b5a3a70a 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
yihui 9:05f0b5a3a70a 4 * @version V3.20
yihui 9:05f0b5a3a70a 5 * @date 25. February 2013
yihui 9:05f0b5a3a70a 6 *
yihui 9:05f0b5a3a70a 7 * @note
yihui 9:05f0b5a3a70a 8 *
yihui 9:05f0b5a3a70a 9 ******************************************************************************/
yihui 9:05f0b5a3a70a 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
yihui 9:05f0b5a3a70a 11
yihui 9:05f0b5a3a70a 12 All rights reserved.
yihui 9:05f0b5a3a70a 13 Redistribution and use in source and binary forms, with or without
yihui 9:05f0b5a3a70a 14 modification, are permitted provided that the following conditions are met:
yihui 9:05f0b5a3a70a 15 - Redistributions of source code must retain the above copyright
yihui 9:05f0b5a3a70a 16 notice, this list of conditions and the following disclaimer.
yihui 9:05f0b5a3a70a 17 - Redistributions in binary form must reproduce the above copyright
yihui 9:05f0b5a3a70a 18 notice, this list of conditions and the following disclaimer in the
yihui 9:05f0b5a3a70a 19 documentation and/or other materials provided with the distribution.
yihui 9:05f0b5a3a70a 20 - Neither the name of ARM nor the names of its contributors may be used
yihui 9:05f0b5a3a70a 21 to endorse or promote products derived from this software without
yihui 9:05f0b5a3a70a 22 specific prior written permission.
yihui 9:05f0b5a3a70a 23 *
yihui 9:05f0b5a3a70a 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
yihui 9:05f0b5a3a70a 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
yihui 9:05f0b5a3a70a 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
yihui 9:05f0b5a3a70a 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
yihui 9:05f0b5a3a70a 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
yihui 9:05f0b5a3a70a 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
yihui 9:05f0b5a3a70a 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
yihui 9:05f0b5a3a70a 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
yihui 9:05f0b5a3a70a 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
yihui 9:05f0b5a3a70a 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
yihui 9:05f0b5a3a70a 34 POSSIBILITY OF SUCH DAMAGE.
yihui 9:05f0b5a3a70a 35 ---------------------------------------------------------------------------*/
yihui 9:05f0b5a3a70a 36
yihui 9:05f0b5a3a70a 37
yihui 9:05f0b5a3a70a 38 #if defined ( __ICCARM__ )
yihui 9:05f0b5a3a70a 39 #pragma system_include /* treat file as system include file for MISRA check */
yihui 9:05f0b5a3a70a 40 #endif
yihui 9:05f0b5a3a70a 41
yihui 9:05f0b5a3a70a 42 #ifdef __cplusplus
yihui 9:05f0b5a3a70a 43 extern "C" {
yihui 9:05f0b5a3a70a 44 #endif
yihui 9:05f0b5a3a70a 45
yihui 9:05f0b5a3a70a 46 #ifndef __CORE_CM0PLUS_H_GENERIC
yihui 9:05f0b5a3a70a 47 #define __CORE_CM0PLUS_H_GENERIC
yihui 9:05f0b5a3a70a 48
yihui 9:05f0b5a3a70a 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
yihui 9:05f0b5a3a70a 50 CMSIS violates the following MISRA-C:2004 rules:
yihui 9:05f0b5a3a70a 51
yihui 9:05f0b5a3a70a 52 \li Required Rule 8.5, object/function definition in header file.<br>
yihui 9:05f0b5a3a70a 53 Function definitions in header files are used to allow 'inlining'.
yihui 9:05f0b5a3a70a 54
yihui 9:05f0b5a3a70a 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
yihui 9:05f0b5a3a70a 56 Unions are used for effective representation of core registers.
yihui 9:05f0b5a3a70a 57
yihui 9:05f0b5a3a70a 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
yihui 9:05f0b5a3a70a 59 Function-like macros are used to allow more efficient code.
yihui 9:05f0b5a3a70a 60 */
yihui 9:05f0b5a3a70a 61
yihui 9:05f0b5a3a70a 62
yihui 9:05f0b5a3a70a 63 /*******************************************************************************
yihui 9:05f0b5a3a70a 64 * CMSIS definitions
yihui 9:05f0b5a3a70a 65 ******************************************************************************/
yihui 9:05f0b5a3a70a 66 /** \ingroup Cortex-M0+
yihui 9:05f0b5a3a70a 67 @{
yihui 9:05f0b5a3a70a 68 */
yihui 9:05f0b5a3a70a 69
yihui 9:05f0b5a3a70a 70 /* CMSIS CM0P definitions */
yihui 9:05f0b5a3a70a 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
yihui 9:05f0b5a3a70a 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
yihui 9:05f0b5a3a70a 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
yihui 9:05f0b5a3a70a 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
yihui 9:05f0b5a3a70a 75
yihui 9:05f0b5a3a70a 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
yihui 9:05f0b5a3a70a 77
yihui 9:05f0b5a3a70a 78
yihui 9:05f0b5a3a70a 79 #if defined ( __CC_ARM )
yihui 9:05f0b5a3a70a 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
yihui 9:05f0b5a3a70a 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
yihui 9:05f0b5a3a70a 82 #define __STATIC_INLINE static __inline
yihui 9:05f0b5a3a70a 83
yihui 9:05f0b5a3a70a 84 #elif defined ( __ICCARM__ )
yihui 9:05f0b5a3a70a 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
yihui 9:05f0b5a3a70a 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
yihui 9:05f0b5a3a70a 87 #define __STATIC_INLINE static inline
yihui 9:05f0b5a3a70a 88
yihui 9:05f0b5a3a70a 89 #elif defined ( __GNUC__ )
yihui 9:05f0b5a3a70a 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
yihui 9:05f0b5a3a70a 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
yihui 9:05f0b5a3a70a 92 #define __STATIC_INLINE static inline
yihui 9:05f0b5a3a70a 93
yihui 9:05f0b5a3a70a 94 #elif defined ( __TASKING__ )
yihui 9:05f0b5a3a70a 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
yihui 9:05f0b5a3a70a 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
yihui 9:05f0b5a3a70a 97 #define __STATIC_INLINE static inline
yihui 9:05f0b5a3a70a 98
yihui 9:05f0b5a3a70a 99 #endif
yihui 9:05f0b5a3a70a 100
yihui 9:05f0b5a3a70a 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
yihui 9:05f0b5a3a70a 102 */
yihui 9:05f0b5a3a70a 103 #define __FPU_USED 0
yihui 9:05f0b5a3a70a 104
yihui 9:05f0b5a3a70a 105 #if defined ( __CC_ARM )
yihui 9:05f0b5a3a70a 106 #if defined __TARGET_FPU_VFP
yihui 9:05f0b5a3a70a 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
yihui 9:05f0b5a3a70a 108 #endif
yihui 9:05f0b5a3a70a 109
yihui 9:05f0b5a3a70a 110 #elif defined ( __ICCARM__ )
yihui 9:05f0b5a3a70a 111 #if defined __ARMVFP__
yihui 9:05f0b5a3a70a 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
yihui 9:05f0b5a3a70a 113 #endif
yihui 9:05f0b5a3a70a 114
yihui 9:05f0b5a3a70a 115 #elif defined ( __GNUC__ )
yihui 9:05f0b5a3a70a 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
yihui 9:05f0b5a3a70a 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
yihui 9:05f0b5a3a70a 118 #endif
yihui 9:05f0b5a3a70a 119
yihui 9:05f0b5a3a70a 120 #elif defined ( __TASKING__ )
yihui 9:05f0b5a3a70a 121 #if defined __FPU_VFP__
yihui 9:05f0b5a3a70a 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
yihui 9:05f0b5a3a70a 123 #endif
yihui 9:05f0b5a3a70a 124 #endif
yihui 9:05f0b5a3a70a 125
yihui 9:05f0b5a3a70a 126 #include <stdint.h> /* standard types definitions */
yihui 9:05f0b5a3a70a 127 #include <core_cmInstr.h> /* Core Instruction Access */
yihui 9:05f0b5a3a70a 128 #include <core_cmFunc.h> /* Core Function Access */
yihui 9:05f0b5a3a70a 129
yihui 9:05f0b5a3a70a 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
yihui 9:05f0b5a3a70a 131
yihui 9:05f0b5a3a70a 132 #ifndef __CMSIS_GENERIC
yihui 9:05f0b5a3a70a 133
yihui 9:05f0b5a3a70a 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
yihui 9:05f0b5a3a70a 135 #define __CORE_CM0PLUS_H_DEPENDANT
yihui 9:05f0b5a3a70a 136
yihui 9:05f0b5a3a70a 137 /* check device defines and use defaults */
yihui 9:05f0b5a3a70a 138 #if defined __CHECK_DEVICE_DEFINES
yihui 9:05f0b5a3a70a 139 #ifndef __CM0PLUS_REV
yihui 9:05f0b5a3a70a 140 #define __CM0PLUS_REV 0x0000
yihui 9:05f0b5a3a70a 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
yihui 9:05f0b5a3a70a 142 #endif
yihui 9:05f0b5a3a70a 143
yihui 9:05f0b5a3a70a 144 #ifndef __MPU_PRESENT
yihui 9:05f0b5a3a70a 145 #define __MPU_PRESENT 0
yihui 9:05f0b5a3a70a 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
yihui 9:05f0b5a3a70a 147 #endif
yihui 9:05f0b5a3a70a 148
yihui 9:05f0b5a3a70a 149 #ifndef __VTOR_PRESENT
yihui 9:05f0b5a3a70a 150 #define __VTOR_PRESENT 0
yihui 9:05f0b5a3a70a 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
yihui 9:05f0b5a3a70a 152 #endif
yihui 9:05f0b5a3a70a 153
yihui 9:05f0b5a3a70a 154 #ifndef __NVIC_PRIO_BITS
yihui 9:05f0b5a3a70a 155 #define __NVIC_PRIO_BITS 2
yihui 9:05f0b5a3a70a 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
yihui 9:05f0b5a3a70a 157 #endif
yihui 9:05f0b5a3a70a 158
yihui 9:05f0b5a3a70a 159 #ifndef __Vendor_SysTickConfig
yihui 9:05f0b5a3a70a 160 #define __Vendor_SysTickConfig 0
yihui 9:05f0b5a3a70a 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
yihui 9:05f0b5a3a70a 162 #endif
yihui 9:05f0b5a3a70a 163 #endif
yihui 9:05f0b5a3a70a 164
yihui 9:05f0b5a3a70a 165 /* IO definitions (access restrictions to peripheral registers) */
yihui 9:05f0b5a3a70a 166 /**
yihui 9:05f0b5a3a70a 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
yihui 9:05f0b5a3a70a 168
yihui 9:05f0b5a3a70a 169 <strong>IO Type Qualifiers</strong> are used
yihui 9:05f0b5a3a70a 170 \li to specify the access to peripheral variables.
yihui 9:05f0b5a3a70a 171 \li for automatic generation of peripheral register debug information.
yihui 9:05f0b5a3a70a 172 */
yihui 9:05f0b5a3a70a 173 #ifdef __cplusplus
yihui 9:05f0b5a3a70a 174 #define __I volatile /*!< Defines 'read only' permissions */
yihui 9:05f0b5a3a70a 175 #else
yihui 9:05f0b5a3a70a 176 #define __I volatile const /*!< Defines 'read only' permissions */
yihui 9:05f0b5a3a70a 177 #endif
yihui 9:05f0b5a3a70a 178 #define __O volatile /*!< Defines 'write only' permissions */
yihui 9:05f0b5a3a70a 179 #define __IO volatile /*!< Defines 'read / write' permissions */
yihui 9:05f0b5a3a70a 180
yihui 9:05f0b5a3a70a 181 /*@} end of group Cortex-M0+ */
yihui 9:05f0b5a3a70a 182
yihui 9:05f0b5a3a70a 183
yihui 9:05f0b5a3a70a 184
yihui 9:05f0b5a3a70a 185 /*******************************************************************************
yihui 9:05f0b5a3a70a 186 * Register Abstraction
yihui 9:05f0b5a3a70a 187 Core Register contain:
yihui 9:05f0b5a3a70a 188 - Core Register
yihui 9:05f0b5a3a70a 189 - Core NVIC Register
yihui 9:05f0b5a3a70a 190 - Core SCB Register
yihui 9:05f0b5a3a70a 191 - Core SysTick Register
yihui 9:05f0b5a3a70a 192 - Core MPU Register
yihui 9:05f0b5a3a70a 193 ******************************************************************************/
yihui 9:05f0b5a3a70a 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
yihui 9:05f0b5a3a70a 195 \brief Type definitions and defines for Cortex-M processor based devices.
yihui 9:05f0b5a3a70a 196 */
yihui 9:05f0b5a3a70a 197
yihui 9:05f0b5a3a70a 198 /** \ingroup CMSIS_core_register
yihui 9:05f0b5a3a70a 199 \defgroup CMSIS_CORE Status and Control Registers
yihui 9:05f0b5a3a70a 200 \brief Core Register type definitions.
yihui 9:05f0b5a3a70a 201 @{
yihui 9:05f0b5a3a70a 202 */
yihui 9:05f0b5a3a70a 203
yihui 9:05f0b5a3a70a 204 /** \brief Union type to access the Application Program Status Register (APSR).
yihui 9:05f0b5a3a70a 205 */
yihui 9:05f0b5a3a70a 206 typedef union
yihui 9:05f0b5a3a70a 207 {
yihui 9:05f0b5a3a70a 208 struct
yihui 9:05f0b5a3a70a 209 {
yihui 9:05f0b5a3a70a 210 #if (__CORTEX_M != 0x04)
yihui 9:05f0b5a3a70a 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
yihui 9:05f0b5a3a70a 212 #else
yihui 9:05f0b5a3a70a 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
yihui 9:05f0b5a3a70a 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
yihui 9:05f0b5a3a70a 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
yihui 9:05f0b5a3a70a 216 #endif
yihui 9:05f0b5a3a70a 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
yihui 9:05f0b5a3a70a 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
yihui 9:05f0b5a3a70a 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
yihui 9:05f0b5a3a70a 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
yihui 9:05f0b5a3a70a 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
yihui 9:05f0b5a3a70a 222 } b; /*!< Structure used for bit access */
yihui 9:05f0b5a3a70a 223 uint32_t w; /*!< Type used for word access */
yihui 9:05f0b5a3a70a 224 } APSR_Type;
yihui 9:05f0b5a3a70a 225
yihui 9:05f0b5a3a70a 226
yihui 9:05f0b5a3a70a 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
yihui 9:05f0b5a3a70a 228 */
yihui 9:05f0b5a3a70a 229 typedef union
yihui 9:05f0b5a3a70a 230 {
yihui 9:05f0b5a3a70a 231 struct
yihui 9:05f0b5a3a70a 232 {
yihui 9:05f0b5a3a70a 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
yihui 9:05f0b5a3a70a 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
yihui 9:05f0b5a3a70a 235 } b; /*!< Structure used for bit access */
yihui 9:05f0b5a3a70a 236 uint32_t w; /*!< Type used for word access */
yihui 9:05f0b5a3a70a 237 } IPSR_Type;
yihui 9:05f0b5a3a70a 238
yihui 9:05f0b5a3a70a 239
yihui 9:05f0b5a3a70a 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
yihui 9:05f0b5a3a70a 241 */
yihui 9:05f0b5a3a70a 242 typedef union
yihui 9:05f0b5a3a70a 243 {
yihui 9:05f0b5a3a70a 244 struct
yihui 9:05f0b5a3a70a 245 {
yihui 9:05f0b5a3a70a 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
yihui 9:05f0b5a3a70a 247 #if (__CORTEX_M != 0x04)
yihui 9:05f0b5a3a70a 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
yihui 9:05f0b5a3a70a 249 #else
yihui 9:05f0b5a3a70a 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
yihui 9:05f0b5a3a70a 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
yihui 9:05f0b5a3a70a 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
yihui 9:05f0b5a3a70a 253 #endif
yihui 9:05f0b5a3a70a 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
yihui 9:05f0b5a3a70a 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
yihui 9:05f0b5a3a70a 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
yihui 9:05f0b5a3a70a 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
yihui 9:05f0b5a3a70a 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
yihui 9:05f0b5a3a70a 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
yihui 9:05f0b5a3a70a 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
yihui 9:05f0b5a3a70a 261 } b; /*!< Structure used for bit access */
yihui 9:05f0b5a3a70a 262 uint32_t w; /*!< Type used for word access */
yihui 9:05f0b5a3a70a 263 } xPSR_Type;
yihui 9:05f0b5a3a70a 264
yihui 9:05f0b5a3a70a 265
yihui 9:05f0b5a3a70a 266 /** \brief Union type to access the Control Registers (CONTROL).
yihui 9:05f0b5a3a70a 267 */
yihui 9:05f0b5a3a70a 268 typedef union
yihui 9:05f0b5a3a70a 269 {
yihui 9:05f0b5a3a70a 270 struct
yihui 9:05f0b5a3a70a 271 {
yihui 9:05f0b5a3a70a 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
yihui 9:05f0b5a3a70a 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
yihui 9:05f0b5a3a70a 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
yihui 9:05f0b5a3a70a 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
yihui 9:05f0b5a3a70a 276 } b; /*!< Structure used for bit access */
yihui 9:05f0b5a3a70a 277 uint32_t w; /*!< Type used for word access */
yihui 9:05f0b5a3a70a 278 } CONTROL_Type;
yihui 9:05f0b5a3a70a 279
yihui 9:05f0b5a3a70a 280 /*@} end of group CMSIS_CORE */
yihui 9:05f0b5a3a70a 281
yihui 9:05f0b5a3a70a 282
yihui 9:05f0b5a3a70a 283 /** \ingroup CMSIS_core_register
yihui 9:05f0b5a3a70a 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
yihui 9:05f0b5a3a70a 285 \brief Type definitions for the NVIC Registers
yihui 9:05f0b5a3a70a 286 @{
yihui 9:05f0b5a3a70a 287 */
yihui 9:05f0b5a3a70a 288
yihui 9:05f0b5a3a70a 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
yihui 9:05f0b5a3a70a 290 */
yihui 9:05f0b5a3a70a 291 typedef struct
yihui 9:05f0b5a3a70a 292 {
yihui 9:05f0b5a3a70a 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
yihui 9:05f0b5a3a70a 294 uint32_t RESERVED0[31];
yihui 9:05f0b5a3a70a 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
yihui 9:05f0b5a3a70a 296 uint32_t RSERVED1[31];
yihui 9:05f0b5a3a70a 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
yihui 9:05f0b5a3a70a 298 uint32_t RESERVED2[31];
yihui 9:05f0b5a3a70a 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
yihui 9:05f0b5a3a70a 300 uint32_t RESERVED3[31];
yihui 9:05f0b5a3a70a 301 uint32_t RESERVED4[64];
yihui 9:05f0b5a3a70a 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
yihui 9:05f0b5a3a70a 303 } NVIC_Type;
yihui 9:05f0b5a3a70a 304
yihui 9:05f0b5a3a70a 305 /*@} end of group CMSIS_NVIC */
yihui 9:05f0b5a3a70a 306
yihui 9:05f0b5a3a70a 307
yihui 9:05f0b5a3a70a 308 /** \ingroup CMSIS_core_register
yihui 9:05f0b5a3a70a 309 \defgroup CMSIS_SCB System Control Block (SCB)
yihui 9:05f0b5a3a70a 310 \brief Type definitions for the System Control Block Registers
yihui 9:05f0b5a3a70a 311 @{
yihui 9:05f0b5a3a70a 312 */
yihui 9:05f0b5a3a70a 313
yihui 9:05f0b5a3a70a 314 /** \brief Structure type to access the System Control Block (SCB).
yihui 9:05f0b5a3a70a 315 */
yihui 9:05f0b5a3a70a 316 typedef struct
yihui 9:05f0b5a3a70a 317 {
yihui 9:05f0b5a3a70a 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
yihui 9:05f0b5a3a70a 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
yihui 9:05f0b5a3a70a 320 #if (__VTOR_PRESENT == 1)
yihui 9:05f0b5a3a70a 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
yihui 9:05f0b5a3a70a 322 #else
yihui 9:05f0b5a3a70a 323 uint32_t RESERVED0;
yihui 9:05f0b5a3a70a 324 #endif
yihui 9:05f0b5a3a70a 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
yihui 9:05f0b5a3a70a 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
yihui 9:05f0b5a3a70a 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
yihui 9:05f0b5a3a70a 328 uint32_t RESERVED1;
yihui 9:05f0b5a3a70a 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
yihui 9:05f0b5a3a70a 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
yihui 9:05f0b5a3a70a 331 } SCB_Type;
yihui 9:05f0b5a3a70a 332
yihui 9:05f0b5a3a70a 333 /* SCB CPUID Register Definitions */
yihui 9:05f0b5a3a70a 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
yihui 9:05f0b5a3a70a 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
yihui 9:05f0b5a3a70a 336
yihui 9:05f0b5a3a70a 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
yihui 9:05f0b5a3a70a 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
yihui 9:05f0b5a3a70a 339
yihui 9:05f0b5a3a70a 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
yihui 9:05f0b5a3a70a 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
yihui 9:05f0b5a3a70a 342
yihui 9:05f0b5a3a70a 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
yihui 9:05f0b5a3a70a 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
yihui 9:05f0b5a3a70a 345
yihui 9:05f0b5a3a70a 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
yihui 9:05f0b5a3a70a 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
yihui 9:05f0b5a3a70a 348
yihui 9:05f0b5a3a70a 349 /* SCB Interrupt Control State Register Definitions */
yihui 9:05f0b5a3a70a 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
yihui 9:05f0b5a3a70a 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
yihui 9:05f0b5a3a70a 352
yihui 9:05f0b5a3a70a 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
yihui 9:05f0b5a3a70a 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
yihui 9:05f0b5a3a70a 355
yihui 9:05f0b5a3a70a 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
yihui 9:05f0b5a3a70a 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
yihui 9:05f0b5a3a70a 358
yihui 9:05f0b5a3a70a 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
yihui 9:05f0b5a3a70a 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
yihui 9:05f0b5a3a70a 361
yihui 9:05f0b5a3a70a 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
yihui 9:05f0b5a3a70a 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
yihui 9:05f0b5a3a70a 364
yihui 9:05f0b5a3a70a 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
yihui 9:05f0b5a3a70a 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
yihui 9:05f0b5a3a70a 367
yihui 9:05f0b5a3a70a 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
yihui 9:05f0b5a3a70a 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
yihui 9:05f0b5a3a70a 370
yihui 9:05f0b5a3a70a 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
yihui 9:05f0b5a3a70a 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
yihui 9:05f0b5a3a70a 373
yihui 9:05f0b5a3a70a 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
yihui 9:05f0b5a3a70a 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
yihui 9:05f0b5a3a70a 376
yihui 9:05f0b5a3a70a 377 #if (__VTOR_PRESENT == 1)
yihui 9:05f0b5a3a70a 378 /* SCB Interrupt Control State Register Definitions */
yihui 9:05f0b5a3a70a 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
yihui 9:05f0b5a3a70a 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
yihui 9:05f0b5a3a70a 381 #endif
yihui 9:05f0b5a3a70a 382
yihui 9:05f0b5a3a70a 383 /* SCB Application Interrupt and Reset Control Register Definitions */
yihui 9:05f0b5a3a70a 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
yihui 9:05f0b5a3a70a 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
yihui 9:05f0b5a3a70a 386
yihui 9:05f0b5a3a70a 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
yihui 9:05f0b5a3a70a 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
yihui 9:05f0b5a3a70a 389
yihui 9:05f0b5a3a70a 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
yihui 9:05f0b5a3a70a 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
yihui 9:05f0b5a3a70a 392
yihui 9:05f0b5a3a70a 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
yihui 9:05f0b5a3a70a 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
yihui 9:05f0b5a3a70a 395
yihui 9:05f0b5a3a70a 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
yihui 9:05f0b5a3a70a 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
yihui 9:05f0b5a3a70a 398
yihui 9:05f0b5a3a70a 399 /* SCB System Control Register Definitions */
yihui 9:05f0b5a3a70a 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
yihui 9:05f0b5a3a70a 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
yihui 9:05f0b5a3a70a 402
yihui 9:05f0b5a3a70a 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
yihui 9:05f0b5a3a70a 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
yihui 9:05f0b5a3a70a 405
yihui 9:05f0b5a3a70a 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
yihui 9:05f0b5a3a70a 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
yihui 9:05f0b5a3a70a 408
yihui 9:05f0b5a3a70a 409 /* SCB Configuration Control Register Definitions */
yihui 9:05f0b5a3a70a 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
yihui 9:05f0b5a3a70a 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
yihui 9:05f0b5a3a70a 412
yihui 9:05f0b5a3a70a 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
yihui 9:05f0b5a3a70a 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
yihui 9:05f0b5a3a70a 415
yihui 9:05f0b5a3a70a 416 /* SCB System Handler Control and State Register Definitions */
yihui 9:05f0b5a3a70a 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
yihui 9:05f0b5a3a70a 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
yihui 9:05f0b5a3a70a 419
yihui 9:05f0b5a3a70a 420 /*@} end of group CMSIS_SCB */
yihui 9:05f0b5a3a70a 421
yihui 9:05f0b5a3a70a 422
yihui 9:05f0b5a3a70a 423 /** \ingroup CMSIS_core_register
yihui 9:05f0b5a3a70a 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
yihui 9:05f0b5a3a70a 425 \brief Type definitions for the System Timer Registers.
yihui 9:05f0b5a3a70a 426 @{
yihui 9:05f0b5a3a70a 427 */
yihui 9:05f0b5a3a70a 428
yihui 9:05f0b5a3a70a 429 /** \brief Structure type to access the System Timer (SysTick).
yihui 9:05f0b5a3a70a 430 */
yihui 9:05f0b5a3a70a 431 typedef struct
yihui 9:05f0b5a3a70a 432 {
yihui 9:05f0b5a3a70a 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
yihui 9:05f0b5a3a70a 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
yihui 9:05f0b5a3a70a 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
yihui 9:05f0b5a3a70a 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
yihui 9:05f0b5a3a70a 437 } SysTick_Type;
yihui 9:05f0b5a3a70a 438
yihui 9:05f0b5a3a70a 439 /* SysTick Control / Status Register Definitions */
yihui 9:05f0b5a3a70a 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
yihui 9:05f0b5a3a70a 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
yihui 9:05f0b5a3a70a 442
yihui 9:05f0b5a3a70a 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
yihui 9:05f0b5a3a70a 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
yihui 9:05f0b5a3a70a 445
yihui 9:05f0b5a3a70a 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
yihui 9:05f0b5a3a70a 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
yihui 9:05f0b5a3a70a 448
yihui 9:05f0b5a3a70a 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
yihui 9:05f0b5a3a70a 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
yihui 9:05f0b5a3a70a 451
yihui 9:05f0b5a3a70a 452 /* SysTick Reload Register Definitions */
yihui 9:05f0b5a3a70a 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
yihui 9:05f0b5a3a70a 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
yihui 9:05f0b5a3a70a 455
yihui 9:05f0b5a3a70a 456 /* SysTick Current Register Definitions */
yihui 9:05f0b5a3a70a 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
yihui 9:05f0b5a3a70a 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
yihui 9:05f0b5a3a70a 459
yihui 9:05f0b5a3a70a 460 /* SysTick Calibration Register Definitions */
yihui 9:05f0b5a3a70a 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
yihui 9:05f0b5a3a70a 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
yihui 9:05f0b5a3a70a 463
yihui 9:05f0b5a3a70a 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
yihui 9:05f0b5a3a70a 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
yihui 9:05f0b5a3a70a 466
yihui 9:05f0b5a3a70a 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
yihui 9:05f0b5a3a70a 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
yihui 9:05f0b5a3a70a 469
yihui 9:05f0b5a3a70a 470 /*@} end of group CMSIS_SysTick */
yihui 9:05f0b5a3a70a 471
yihui 9:05f0b5a3a70a 472 #if (__MPU_PRESENT == 1)
yihui 9:05f0b5a3a70a 473 /** \ingroup CMSIS_core_register
yihui 9:05f0b5a3a70a 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
yihui 9:05f0b5a3a70a 475 \brief Type definitions for the Memory Protection Unit (MPU)
yihui 9:05f0b5a3a70a 476 @{
yihui 9:05f0b5a3a70a 477 */
yihui 9:05f0b5a3a70a 478
yihui 9:05f0b5a3a70a 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
yihui 9:05f0b5a3a70a 480 */
yihui 9:05f0b5a3a70a 481 typedef struct
yihui 9:05f0b5a3a70a 482 {
yihui 9:05f0b5a3a70a 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
yihui 9:05f0b5a3a70a 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
yihui 9:05f0b5a3a70a 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
yihui 9:05f0b5a3a70a 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
yihui 9:05f0b5a3a70a 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
yihui 9:05f0b5a3a70a 488 } MPU_Type;
yihui 9:05f0b5a3a70a 489
yihui 9:05f0b5a3a70a 490 /* MPU Type Register */
yihui 9:05f0b5a3a70a 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
yihui 9:05f0b5a3a70a 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
yihui 9:05f0b5a3a70a 493
yihui 9:05f0b5a3a70a 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
yihui 9:05f0b5a3a70a 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
yihui 9:05f0b5a3a70a 496
yihui 9:05f0b5a3a70a 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
yihui 9:05f0b5a3a70a 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
yihui 9:05f0b5a3a70a 499
yihui 9:05f0b5a3a70a 500 /* MPU Control Register */
yihui 9:05f0b5a3a70a 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
yihui 9:05f0b5a3a70a 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
yihui 9:05f0b5a3a70a 503
yihui 9:05f0b5a3a70a 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
yihui 9:05f0b5a3a70a 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
yihui 9:05f0b5a3a70a 506
yihui 9:05f0b5a3a70a 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
yihui 9:05f0b5a3a70a 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
yihui 9:05f0b5a3a70a 509
yihui 9:05f0b5a3a70a 510 /* MPU Region Number Register */
yihui 9:05f0b5a3a70a 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
yihui 9:05f0b5a3a70a 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
yihui 9:05f0b5a3a70a 513
yihui 9:05f0b5a3a70a 514 /* MPU Region Base Address Register */
yihui 9:05f0b5a3a70a 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
yihui 9:05f0b5a3a70a 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
yihui 9:05f0b5a3a70a 517
yihui 9:05f0b5a3a70a 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
yihui 9:05f0b5a3a70a 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
yihui 9:05f0b5a3a70a 520
yihui 9:05f0b5a3a70a 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
yihui 9:05f0b5a3a70a 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
yihui 9:05f0b5a3a70a 523
yihui 9:05f0b5a3a70a 524 /* MPU Region Attribute and Size Register */
yihui 9:05f0b5a3a70a 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
yihui 9:05f0b5a3a70a 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
yihui 9:05f0b5a3a70a 527
yihui 9:05f0b5a3a70a 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
yihui 9:05f0b5a3a70a 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
yihui 9:05f0b5a3a70a 530
yihui 9:05f0b5a3a70a 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
yihui 9:05f0b5a3a70a 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
yihui 9:05f0b5a3a70a 533
yihui 9:05f0b5a3a70a 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
yihui 9:05f0b5a3a70a 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
yihui 9:05f0b5a3a70a 536
yihui 9:05f0b5a3a70a 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
yihui 9:05f0b5a3a70a 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
yihui 9:05f0b5a3a70a 539
yihui 9:05f0b5a3a70a 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
yihui 9:05f0b5a3a70a 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
yihui 9:05f0b5a3a70a 542
yihui 9:05f0b5a3a70a 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
yihui 9:05f0b5a3a70a 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
yihui 9:05f0b5a3a70a 545
yihui 9:05f0b5a3a70a 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
yihui 9:05f0b5a3a70a 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
yihui 9:05f0b5a3a70a 548
yihui 9:05f0b5a3a70a 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
yihui 9:05f0b5a3a70a 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
yihui 9:05f0b5a3a70a 551
yihui 9:05f0b5a3a70a 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
yihui 9:05f0b5a3a70a 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
yihui 9:05f0b5a3a70a 554
yihui 9:05f0b5a3a70a 555 /*@} end of group CMSIS_MPU */
yihui 9:05f0b5a3a70a 556 #endif
yihui 9:05f0b5a3a70a 557
yihui 9:05f0b5a3a70a 558
yihui 9:05f0b5a3a70a 559 /** \ingroup CMSIS_core_register
yihui 9:05f0b5a3a70a 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
yihui 9:05f0b5a3a70a 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
yihui 9:05f0b5a3a70a 562 are only accessible over DAP and not via processor. Therefore
yihui 9:05f0b5a3a70a 563 they are not covered by the Cortex-M0 header file.
yihui 9:05f0b5a3a70a 564 @{
yihui 9:05f0b5a3a70a 565 */
yihui 9:05f0b5a3a70a 566 /*@} end of group CMSIS_CoreDebug */
yihui 9:05f0b5a3a70a 567
yihui 9:05f0b5a3a70a 568
yihui 9:05f0b5a3a70a 569 /** \ingroup CMSIS_core_register
yihui 9:05f0b5a3a70a 570 \defgroup CMSIS_core_base Core Definitions
yihui 9:05f0b5a3a70a 571 \brief Definitions for base addresses, unions, and structures.
yihui 9:05f0b5a3a70a 572 @{
yihui 9:05f0b5a3a70a 573 */
yihui 9:05f0b5a3a70a 574
yihui 9:05f0b5a3a70a 575 /* Memory mapping of Cortex-M0+ Hardware */
yihui 9:05f0b5a3a70a 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
yihui 9:05f0b5a3a70a 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
yihui 9:05f0b5a3a70a 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
yihui 9:05f0b5a3a70a 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
yihui 9:05f0b5a3a70a 580
yihui 9:05f0b5a3a70a 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
yihui 9:05f0b5a3a70a 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
yihui 9:05f0b5a3a70a 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
yihui 9:05f0b5a3a70a 584
yihui 9:05f0b5a3a70a 585 #if (__MPU_PRESENT == 1)
yihui 9:05f0b5a3a70a 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
yihui 9:05f0b5a3a70a 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
yihui 9:05f0b5a3a70a 588 #endif
yihui 9:05f0b5a3a70a 589
yihui 9:05f0b5a3a70a 590 /*@} */
yihui 9:05f0b5a3a70a 591
yihui 9:05f0b5a3a70a 592
yihui 9:05f0b5a3a70a 593
yihui 9:05f0b5a3a70a 594 /*******************************************************************************
yihui 9:05f0b5a3a70a 595 * Hardware Abstraction Layer
yihui 9:05f0b5a3a70a 596 Core Function Interface contains:
yihui 9:05f0b5a3a70a 597 - Core NVIC Functions
yihui 9:05f0b5a3a70a 598 - Core SysTick Functions
yihui 9:05f0b5a3a70a 599 - Core Register Access Functions
yihui 9:05f0b5a3a70a 600 ******************************************************************************/
yihui 9:05f0b5a3a70a 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
yihui 9:05f0b5a3a70a 602 */
yihui 9:05f0b5a3a70a 603
yihui 9:05f0b5a3a70a 604
yihui 9:05f0b5a3a70a 605
yihui 9:05f0b5a3a70a 606 /* ########################## NVIC functions #################################### */
yihui 9:05f0b5a3a70a 607 /** \ingroup CMSIS_Core_FunctionInterface
yihui 9:05f0b5a3a70a 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
yihui 9:05f0b5a3a70a 609 \brief Functions that manage interrupts and exceptions via the NVIC.
yihui 9:05f0b5a3a70a 610 @{
yihui 9:05f0b5a3a70a 611 */
yihui 9:05f0b5a3a70a 612
yihui 9:05f0b5a3a70a 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
yihui 9:05f0b5a3a70a 614 /* The following MACROS handle generation of the register offset and byte masks */
yihui 9:05f0b5a3a70a 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
yihui 9:05f0b5a3a70a 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
yihui 9:05f0b5a3a70a 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
yihui 9:05f0b5a3a70a 618
yihui 9:05f0b5a3a70a 619
yihui 9:05f0b5a3a70a 620 /** \brief Enable External Interrupt
yihui 9:05f0b5a3a70a 621
yihui 9:05f0b5a3a70a 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
yihui 9:05f0b5a3a70a 623
yihui 9:05f0b5a3a70a 624 \param [in] IRQn External interrupt number. Value cannot be negative.
yihui 9:05f0b5a3a70a 625 */
yihui 9:05f0b5a3a70a 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
yihui 9:05f0b5a3a70a 627 {
yihui 9:05f0b5a3a70a 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
yihui 9:05f0b5a3a70a 629 }
yihui 9:05f0b5a3a70a 630
yihui 9:05f0b5a3a70a 631
yihui 9:05f0b5a3a70a 632 /** \brief Disable External Interrupt
yihui 9:05f0b5a3a70a 633
yihui 9:05f0b5a3a70a 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
yihui 9:05f0b5a3a70a 635
yihui 9:05f0b5a3a70a 636 \param [in] IRQn External interrupt number. Value cannot be negative.
yihui 9:05f0b5a3a70a 637 */
yihui 9:05f0b5a3a70a 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
yihui 9:05f0b5a3a70a 639 {
yihui 9:05f0b5a3a70a 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
yihui 9:05f0b5a3a70a 641 }
yihui 9:05f0b5a3a70a 642
yihui 9:05f0b5a3a70a 643
yihui 9:05f0b5a3a70a 644 /** \brief Get Pending Interrupt
yihui 9:05f0b5a3a70a 645
yihui 9:05f0b5a3a70a 646 The function reads the pending register in the NVIC and returns the pending bit
yihui 9:05f0b5a3a70a 647 for the specified interrupt.
yihui 9:05f0b5a3a70a 648
yihui 9:05f0b5a3a70a 649 \param [in] IRQn Interrupt number.
yihui 9:05f0b5a3a70a 650
yihui 9:05f0b5a3a70a 651 \return 0 Interrupt status is not pending.
yihui 9:05f0b5a3a70a 652 \return 1 Interrupt status is pending.
yihui 9:05f0b5a3a70a 653 */
yihui 9:05f0b5a3a70a 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
yihui 9:05f0b5a3a70a 655 {
yihui 9:05f0b5a3a70a 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
yihui 9:05f0b5a3a70a 657 }
yihui 9:05f0b5a3a70a 658
yihui 9:05f0b5a3a70a 659
yihui 9:05f0b5a3a70a 660 /** \brief Set Pending Interrupt
yihui 9:05f0b5a3a70a 661
yihui 9:05f0b5a3a70a 662 The function sets the pending bit of an external interrupt.
yihui 9:05f0b5a3a70a 663
yihui 9:05f0b5a3a70a 664 \param [in] IRQn Interrupt number. Value cannot be negative.
yihui 9:05f0b5a3a70a 665 */
yihui 9:05f0b5a3a70a 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
yihui 9:05f0b5a3a70a 667 {
yihui 9:05f0b5a3a70a 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
yihui 9:05f0b5a3a70a 669 }
yihui 9:05f0b5a3a70a 670
yihui 9:05f0b5a3a70a 671
yihui 9:05f0b5a3a70a 672 /** \brief Clear Pending Interrupt
yihui 9:05f0b5a3a70a 673
yihui 9:05f0b5a3a70a 674 The function clears the pending bit of an external interrupt.
yihui 9:05f0b5a3a70a 675
yihui 9:05f0b5a3a70a 676 \param [in] IRQn External interrupt number. Value cannot be negative.
yihui 9:05f0b5a3a70a 677 */
yihui 9:05f0b5a3a70a 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
yihui 9:05f0b5a3a70a 679 {
yihui 9:05f0b5a3a70a 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
yihui 9:05f0b5a3a70a 681 }
yihui 9:05f0b5a3a70a 682
yihui 9:05f0b5a3a70a 683
yihui 9:05f0b5a3a70a 684 /** \brief Set Interrupt Priority
yihui 9:05f0b5a3a70a 685
yihui 9:05f0b5a3a70a 686 The function sets the priority of an interrupt.
yihui 9:05f0b5a3a70a 687
yihui 9:05f0b5a3a70a 688 \note The priority cannot be set for every core interrupt.
yihui 9:05f0b5a3a70a 689
yihui 9:05f0b5a3a70a 690 \param [in] IRQn Interrupt number.
yihui 9:05f0b5a3a70a 691 \param [in] priority Priority to set.
yihui 9:05f0b5a3a70a 692 */
yihui 9:05f0b5a3a70a 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
yihui 9:05f0b5a3a70a 694 {
yihui 9:05f0b5a3a70a 695 if(IRQn < 0) {
yihui 9:05f0b5a3a70a 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
yihui 9:05f0b5a3a70a 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
yihui 9:05f0b5a3a70a 698 else {
yihui 9:05f0b5a3a70a 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
yihui 9:05f0b5a3a70a 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
yihui 9:05f0b5a3a70a 701 }
yihui 9:05f0b5a3a70a 702
yihui 9:05f0b5a3a70a 703
yihui 9:05f0b5a3a70a 704 /** \brief Get Interrupt Priority
yihui 9:05f0b5a3a70a 705
yihui 9:05f0b5a3a70a 706 The function reads the priority of an interrupt. The interrupt
yihui 9:05f0b5a3a70a 707 number can be positive to specify an external (device specific)
yihui 9:05f0b5a3a70a 708 interrupt, or negative to specify an internal (core) interrupt.
yihui 9:05f0b5a3a70a 709
yihui 9:05f0b5a3a70a 710
yihui 9:05f0b5a3a70a 711 \param [in] IRQn Interrupt number.
yihui 9:05f0b5a3a70a 712 \return Interrupt Priority. Value is aligned automatically to the implemented
yihui 9:05f0b5a3a70a 713 priority bits of the microcontroller.
yihui 9:05f0b5a3a70a 714 */
yihui 9:05f0b5a3a70a 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
yihui 9:05f0b5a3a70a 716 {
yihui 9:05f0b5a3a70a 717
yihui 9:05f0b5a3a70a 718 if(IRQn < 0) {
yihui 9:05f0b5a3a70a 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
yihui 9:05f0b5a3a70a 720 else {
yihui 9:05f0b5a3a70a 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
yihui 9:05f0b5a3a70a 722 }
yihui 9:05f0b5a3a70a 723
yihui 9:05f0b5a3a70a 724
yihui 9:05f0b5a3a70a 725 /** \brief System Reset
yihui 9:05f0b5a3a70a 726
yihui 9:05f0b5a3a70a 727 The function initiates a system reset request to reset the MCU.
yihui 9:05f0b5a3a70a 728 */
yihui 9:05f0b5a3a70a 729 __STATIC_INLINE void NVIC_SystemReset(void)
yihui 9:05f0b5a3a70a 730 {
yihui 9:05f0b5a3a70a 731 __DSB(); /* Ensure all outstanding memory accesses included
yihui 9:05f0b5a3a70a 732 buffered write are completed before reset */
yihui 9:05f0b5a3a70a 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
yihui 9:05f0b5a3a70a 734 SCB_AIRCR_SYSRESETREQ_Msk);
yihui 9:05f0b5a3a70a 735 __DSB(); /* Ensure completion of memory access */
yihui 9:05f0b5a3a70a 736 while(1); /* wait until reset */
yihui 9:05f0b5a3a70a 737 }
yihui 9:05f0b5a3a70a 738
yihui 9:05f0b5a3a70a 739 /*@} end of CMSIS_Core_NVICFunctions */
yihui 9:05f0b5a3a70a 740
yihui 9:05f0b5a3a70a 741
yihui 9:05f0b5a3a70a 742
yihui 9:05f0b5a3a70a 743 /* ################################## SysTick function ############################################ */
yihui 9:05f0b5a3a70a 744 /** \ingroup CMSIS_Core_FunctionInterface
yihui 9:05f0b5a3a70a 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
yihui 9:05f0b5a3a70a 746 \brief Functions that configure the System.
yihui 9:05f0b5a3a70a 747 @{
yihui 9:05f0b5a3a70a 748 */
yihui 9:05f0b5a3a70a 749
yihui 9:05f0b5a3a70a 750 #if (__Vendor_SysTickConfig == 0)
yihui 9:05f0b5a3a70a 751
yihui 9:05f0b5a3a70a 752 /** \brief System Tick Configuration
yihui 9:05f0b5a3a70a 753
yihui 9:05f0b5a3a70a 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
yihui 9:05f0b5a3a70a 755 Counter is in free running mode to generate periodic interrupts.
yihui 9:05f0b5a3a70a 756
yihui 9:05f0b5a3a70a 757 \param [in] ticks Number of ticks between two interrupts.
yihui 9:05f0b5a3a70a 758
yihui 9:05f0b5a3a70a 759 \return 0 Function succeeded.
yihui 9:05f0b5a3a70a 760 \return 1 Function failed.
yihui 9:05f0b5a3a70a 761
yihui 9:05f0b5a3a70a 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
yihui 9:05f0b5a3a70a 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
yihui 9:05f0b5a3a70a 764 must contain a vendor-specific implementation of this function.
yihui 9:05f0b5a3a70a 765
yihui 9:05f0b5a3a70a 766 */
yihui 9:05f0b5a3a70a 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
yihui 9:05f0b5a3a70a 768 {
yihui 9:05f0b5a3a70a 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
yihui 9:05f0b5a3a70a 770
yihui 9:05f0b5a3a70a 771 SysTick->LOAD = ticks - 1; /* set reload register */
yihui 9:05f0b5a3a70a 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
yihui 9:05f0b5a3a70a 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
yihui 9:05f0b5a3a70a 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
yihui 9:05f0b5a3a70a 775 SysTick_CTRL_TICKINT_Msk |
yihui 9:05f0b5a3a70a 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
yihui 9:05f0b5a3a70a 777 return (0); /* Function successful */
yihui 9:05f0b5a3a70a 778 }
yihui 9:05f0b5a3a70a 779
yihui 9:05f0b5a3a70a 780 #endif
yihui 9:05f0b5a3a70a 781
yihui 9:05f0b5a3a70a 782 /*@} end of CMSIS_Core_SysTickFunctions */
yihui 9:05f0b5a3a70a 783
yihui 9:05f0b5a3a70a 784
yihui 9:05f0b5a3a70a 785
yihui 9:05f0b5a3a70a 786
yihui 9:05f0b5a3a70a 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
yihui 9:05f0b5a3a70a 788
yihui 9:05f0b5a3a70a 789 #endif /* __CMSIS_GENERIC */
yihui 9:05f0b5a3a70a 790
yihui 9:05f0b5a3a70a 791 #ifdef __cplusplus
yihui 9:05f0b5a3a70a 792 }
yihui 9:05f0b5a3a70a 793 #endif