BLE_NODE_TEST - Test code for Grove Node BLE

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Test code for Grove Node BLE

Fork of BLE_LoopbackUART by Bluetooth Low Energy

mbed-src/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51_bitfields.h@10:22480ac31879, 2014-11-27 (annotated)

Committer:: yihui
Date:: Thu Nov 27 09:30:36 2014 +0000
Revision:: 10:22480ac31879
Parent:: 9:05f0b5a3a70a

change to new revision hardware

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User	Revision	Line number	New contents of line
yihui	9:05f0b5a3a70a	1	/* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
yihui	9:05f0b5a3a70a	2	*
yihui	9:05f0b5a3a70a	3	* The information contained herein is property of Nordic Semiconductor ASA.
yihui	9:05f0b5a3a70a	4	* Terms and conditions of usage are described in detail in NORDIC
yihui	9:05f0b5a3a70a	5	* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
yihui	9:05f0b5a3a70a	6	*
yihui	9:05f0b5a3a70a	7	* Licensees are granted free, non-transferable use of the information. NO
yihui	9:05f0b5a3a70a	8	* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
yihui	9:05f0b5a3a70a	9	* the file.
yihui	9:05f0b5a3a70a	10	*
yihui	9:05f0b5a3a70a	11	*/
yihui	9:05f0b5a3a70a	12
yihui	9:05f0b5a3a70a	13
yihui	9:05f0b5a3a70a	14	#ifndef __NRF51_BITS_H
yihui	9:05f0b5a3a70a	15	#define __NRF51_BITS_H
yihui	9:05f0b5a3a70a	16
yihui	9:05f0b5a3a70a	17	/lint ++flb "Enter library region /
yihui	9:05f0b5a3a70a	18
yihui	9:05f0b5a3a70a	19	//#include <core_cm0.h>
yihui	9:05f0b5a3a70a	20
yihui	9:05f0b5a3a70a	21	/* Peripheral: AAR */
yihui	9:05f0b5a3a70a	22	/* Description: Accelerated Address Resolver. */
yihui	9:05f0b5a3a70a	23
yihui	9:05f0b5a3a70a	24	/* Register: AAR_INTENSET */
yihui	9:05f0b5a3a70a	25	/* Description: Interrupt enable set register. */
yihui	9:05f0b5a3a70a	26
yihui	9:05f0b5a3a70a	27	/* Bit 2 : Enable interrupt on NOTRESOLVED event. */
yihui	9:05f0b5a3a70a	28	#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
yihui	9:05f0b5a3a70a	29	#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
yihui	9:05f0b5a3a70a	30	#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	31	#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	32	#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	33
yihui	9:05f0b5a3a70a	34	/* Bit 1 : Enable interrupt on RESOLVED event. */
yihui	9:05f0b5a3a70a	35	#define AAR_INTENSET_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
yihui	9:05f0b5a3a70a	36	#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
yihui	9:05f0b5a3a70a	37	#define AAR_INTENSET_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	38	#define AAR_INTENSET_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	39	#define AAR_INTENSET_RESOLVED_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	40
yihui	9:05f0b5a3a70a	41	/* Bit 0 : Enable interrupt on END event. */
yihui	9:05f0b5a3a70a	42	#define AAR_INTENSET_END_Pos (0UL) /!< Position of END field. /
yihui	9:05f0b5a3a70a	43	#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /!< Bit mask of END field. /
yihui	9:05f0b5a3a70a	44	#define AAR_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	45	#define AAR_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	46	#define AAR_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	47
yihui	9:05f0b5a3a70a	48	/* Register: AAR_INTENCLR */
yihui	9:05f0b5a3a70a	49	/* Description: Interrupt enable clear register. */
yihui	9:05f0b5a3a70a	50
yihui	9:05f0b5a3a70a	51	/* Bit 2 : Disable interrupt on NOTRESOLVED event. */
yihui	9:05f0b5a3a70a	52	#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
yihui	9:05f0b5a3a70a	53	#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
yihui	9:05f0b5a3a70a	54	#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	55	#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	56	#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	57
yihui	9:05f0b5a3a70a	58	/* Bit 1 : Disable interrupt on RESOLVED event. */
yihui	9:05f0b5a3a70a	59	#define AAR_INTENCLR_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
yihui	9:05f0b5a3a70a	60	#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
yihui	9:05f0b5a3a70a	61	#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	62	#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	63	#define AAR_INTENCLR_RESOLVED_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	64
yihui	9:05f0b5a3a70a	65	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
yihui	9:05f0b5a3a70a	66	#define AAR_INTENCLR_END_Pos (0UL) /!< Position of END field. /
yihui	9:05f0b5a3a70a	67	#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /!< Bit mask of END field. /
yihui	9:05f0b5a3a70a	68	#define AAR_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	69	#define AAR_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	70	#define AAR_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	71
yihui	9:05f0b5a3a70a	72	/* Register: AAR_STATUS */
yihui	9:05f0b5a3a70a	73	/* Description: Resolution status. */
yihui	9:05f0b5a3a70a	74
yihui	9:05f0b5a3a70a	75	/* Bits 3..0 : The IRK used last time an address was resolved. */
yihui	9:05f0b5a3a70a	76	#define AAR_STATUS_STATUS_Pos (0UL) /!< Position of STATUS field. /
yihui	9:05f0b5a3a70a	77	#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /!< Bit mask of STATUS field. /
yihui	9:05f0b5a3a70a	78
yihui	9:05f0b5a3a70a	79	/* Register: AAR_ENABLE */
yihui	9:05f0b5a3a70a	80	/* Description: Enable AAR. */
yihui	9:05f0b5a3a70a	81
yihui	9:05f0b5a3a70a	82	/* Bits 1..0 : Enable AAR. */
yihui	9:05f0b5a3a70a	83	#define AAR_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
yihui	9:05f0b5a3a70a	84	#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
yihui	9:05f0b5a3a70a	85	#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled AAR. /
yihui	9:05f0b5a3a70a	86	#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /!< Enable AAR. /
yihui	9:05f0b5a3a70a	87
yihui	9:05f0b5a3a70a	88	/* Register: AAR_NIRK */
yihui	9:05f0b5a3a70a	89	/* Description: Number of Identity root Keys in the IRK data structure. */
yihui	9:05f0b5a3a70a	90
yihui	9:05f0b5a3a70a	91	/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
yihui	9:05f0b5a3a70a	92	#define AAR_NIRK_NIRK_Pos (0UL) /!< Position of NIRK field. /
yihui	9:05f0b5a3a70a	93	#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /!< Bit mask of NIRK field. /
yihui	9:05f0b5a3a70a	94
yihui	9:05f0b5a3a70a	95	/* Register: AAR_POWER */
yihui	9:05f0b5a3a70a	96	/* Description: Peripheral power control. */
yihui	9:05f0b5a3a70a	97
yihui	9:05f0b5a3a70a	98	/* Bit 0 : Peripheral power control. */
yihui	9:05f0b5a3a70a	99	#define AAR_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
yihui	9:05f0b5a3a70a	100	#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /!< Bit mask of POWER field. /
yihui	9:05f0b5a3a70a	101	#define AAR_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
yihui	9:05f0b5a3a70a	102	#define AAR_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
yihui	9:05f0b5a3a70a	103
yihui	9:05f0b5a3a70a	104
yihui	9:05f0b5a3a70a	105	/* Peripheral: ADC */
yihui	9:05f0b5a3a70a	106	/* Description: Analog to digital converter. */
yihui	9:05f0b5a3a70a	107
yihui	9:05f0b5a3a70a	108	/* Register: ADC_INTENSET */
yihui	9:05f0b5a3a70a	109	/* Description: Interrupt enable set register. */
yihui	9:05f0b5a3a70a	110
yihui	9:05f0b5a3a70a	111	/* Bit 0 : Enable interrupt on END event. */
yihui	9:05f0b5a3a70a	112	#define ADC_INTENSET_END_Pos (0UL) /!< Position of END field. /
yihui	9:05f0b5a3a70a	113	#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /!< Bit mask of END field. /
yihui	9:05f0b5a3a70a	114	#define ADC_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	115	#define ADC_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	116	#define ADC_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	117
yihui	9:05f0b5a3a70a	118	/* Register: ADC_INTENCLR */
yihui	9:05f0b5a3a70a	119	/* Description: Interrupt enable clear register. */
yihui	9:05f0b5a3a70a	120
yihui	9:05f0b5a3a70a	121	/* Bit 0 : Disable interrupt on END event. */
yihui	9:05f0b5a3a70a	122	#define ADC_INTENCLR_END_Pos (0UL) /!< Position of END field. /
yihui	9:05f0b5a3a70a	123	#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /!< Bit mask of END field. /
yihui	9:05f0b5a3a70a	124	#define ADC_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	125	#define ADC_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	126	#define ADC_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	127
yihui	9:05f0b5a3a70a	128	/* Register: ADC_BUSY */
yihui	9:05f0b5a3a70a	129	/* Description: ADC busy register. */
yihui	9:05f0b5a3a70a	130
yihui	9:05f0b5a3a70a	131	/* Bit 0 : ADC busy register. */
yihui	9:05f0b5a3a70a	132	#define ADC_BUSY_BUSY_Pos (0UL) /!< Position of BUSY field. /
yihui	9:05f0b5a3a70a	133	#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /!< Bit mask of BUSY field. /
yihui	9:05f0b5a3a70a	134	#define ADC_BUSY_BUSY_Ready (0UL) /!< No ongoing ADC conversion is taking place. ADC is ready. /
yihui	9:05f0b5a3a70a	135	#define ADC_BUSY_BUSY_Busy (1UL) /!< An ADC conversion is taking place. ADC is busy. /
yihui	9:05f0b5a3a70a	136
yihui	9:05f0b5a3a70a	137	/* Register: ADC_ENABLE */
yihui	9:05f0b5a3a70a	138	/* Description: ADC enable. */
yihui	9:05f0b5a3a70a	139
yihui	9:05f0b5a3a70a	140	/* Bits 1..0 : ADC enable. */
yihui	9:05f0b5a3a70a	141	#define ADC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
yihui	9:05f0b5a3a70a	142	#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
yihui	9:05f0b5a3a70a	143	#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /!< ADC is disabled. /
yihui	9:05f0b5a3a70a	144	#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. /
yihui	9:05f0b5a3a70a	145
yihui	9:05f0b5a3a70a	146	/* Register: ADC_CONFIG */
yihui	9:05f0b5a3a70a	147	/* Description: ADC configuration register. */
yihui	9:05f0b5a3a70a	148
yihui	9:05f0b5a3a70a	149	/* Bits 17..16 : ADC external reference pin selection. */
yihui	9:05f0b5a3a70a	150	#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /!< Position of EXTREFSEL field. /
yihui	9:05f0b5a3a70a	151	#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
yihui	9:05f0b5a3a70a	152	#define ADC_CONFIG_EXTREFSEL_None (0UL) /!< Analog external reference inputs disabled. /
yihui	9:05f0b5a3a70a	153	#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /!< Use analog reference 0 as reference. /
yihui	9:05f0b5a3a70a	154	#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /!< Use analog reference 1 as reference. /
yihui	9:05f0b5a3a70a	155
yihui	9:05f0b5a3a70a	156	/* Bits 15..8 : ADC analog pin selection. */
yihui	9:05f0b5a3a70a	157	#define ADC_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
yihui	9:05f0b5a3a70a	158	#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
yihui	9:05f0b5a3a70a	159	#define ADC_CONFIG_PSEL_Disabled (0UL) /!< Analog input pins disabled. /
yihui	9:05f0b5a3a70a	160	#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /!< Use analog input 0 as analog input. /
yihui	9:05f0b5a3a70a	161	#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /!< Use analog input 1 as analog input. /
yihui	9:05f0b5a3a70a	162	#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /!< Use analog input 2 as analog input. /
yihui	9:05f0b5a3a70a	163	#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /!< Use analog input 3 as analog input. /
yihui	9:05f0b5a3a70a	164	#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /!< Use analog input 4 as analog input. /
yihui	9:05f0b5a3a70a	165	#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /!< Use analog input 5 as analog input. /
yihui	9:05f0b5a3a70a	166	#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /!< Use analog input 6 as analog input. /
yihui	9:05f0b5a3a70a	167	#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /!< Use analog input 7 as analog input. /
yihui	9:05f0b5a3a70a	168
yihui	9:05f0b5a3a70a	169	/* Bits 6..5 : ADC reference selection. */
yihui	9:05f0b5a3a70a	170	#define ADC_CONFIG_REFSEL_Pos (5UL) /!< Position of REFSEL field. /
yihui	9:05f0b5a3a70a	171	#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /!< Bit mask of REFSEL field. /
yihui	9:05f0b5a3a70a	172	#define ADC_CONFIG_REFSEL_VBG (0x00UL) /!< Use internal 1.2V bandgap voltage as reference for conversion. /
yihui	9:05f0b5a3a70a	173	#define ADC_CONFIG_REFSEL_External (0x01UL) /!< Use external source configured by EXTREFSEL as reference for conversion. /
yihui	9:05f0b5a3a70a	174	#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. /
yihui	9:05f0b5a3a70a	175	#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. /
yihui	9:05f0b5a3a70a	176
yihui	9:05f0b5a3a70a	177	/* Bits 4..2 : ADC input selection. */
yihui	9:05f0b5a3a70a	178	#define ADC_CONFIG_INPSEL_Pos (2UL) /!< Position of INPSEL field. /
yihui	9:05f0b5a3a70a	179	#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /!< Bit mask of INPSEL field. /
yihui	9:05f0b5a3a70a	180	#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /!< Analog input specified by PSEL with no prescaling used as input for the conversion. /
yihui	9:05f0b5a3a70a	181	#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. /
yihui	9:05f0b5a3a70a	182	#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. /
yihui	9:05f0b5a3a70a	183	#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /!< Supply voltage with 2/3 prescaling used as input for the conversion. /
yihui	9:05f0b5a3a70a	184	#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /!< Supply voltage with 1/3 prescaling used as input for the conversion. /
yihui	9:05f0b5a3a70a	185
yihui	9:05f0b5a3a70a	186	/* Bits 1..0 : ADC resolution. */
yihui	9:05f0b5a3a70a	187	#define ADC_CONFIG_RES_Pos (0UL) /!< Position of RES field. /
yihui	9:05f0b5a3a70a	188	#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /!< Bit mask of RES field. /
yihui	9:05f0b5a3a70a	189	#define ADC_CONFIG_RES_8bit (0x00UL) /!< 8bit ADC resolution. /
yihui	9:05f0b5a3a70a	190	#define ADC_CONFIG_RES_9bit (0x01UL) /!< 9bit ADC resolution. /
yihui	9:05f0b5a3a70a	191	#define ADC_CONFIG_RES_10bit (0x02UL) /!< 10bit ADC resolution. /
yihui	9:05f0b5a3a70a	192
yihui	9:05f0b5a3a70a	193	/* Register: ADC_RESULT */
yihui	9:05f0b5a3a70a	194	/* Description: Result of ADC conversion. */
yihui	9:05f0b5a3a70a	195
yihui	9:05f0b5a3a70a	196	/* Bits 9..0 : Result of ADC conversion. */
yihui	9:05f0b5a3a70a	197	#define ADC_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
yihui	9:05f0b5a3a70a	198	#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
yihui	9:05f0b5a3a70a	199
yihui	9:05f0b5a3a70a	200	/* Register: ADC_POWER */
yihui	9:05f0b5a3a70a	201	/* Description: Peripheral power control. */
yihui	9:05f0b5a3a70a	202
yihui	9:05f0b5a3a70a	203	/* Bit 0 : Peripheral power control. */
yihui	9:05f0b5a3a70a	204	#define ADC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
yihui	9:05f0b5a3a70a	205	#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
yihui	9:05f0b5a3a70a	206	#define ADC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
yihui	9:05f0b5a3a70a	207	#define ADC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
yihui	9:05f0b5a3a70a	208
yihui	9:05f0b5a3a70a	209
yihui	9:05f0b5a3a70a	210	/* Peripheral: AMLI */
yihui	9:05f0b5a3a70a	211	/* Description: AHB Multi-Layer Interface. */
yihui	9:05f0b5a3a70a	212
yihui	9:05f0b5a3a70a	213	/* Register: AMLI_RAMPRI_CPU0 */
yihui	9:05f0b5a3a70a	214	/* Description: Configurable priority configuration register for CPU0. */
yihui	9:05f0b5a3a70a	215
yihui	9:05f0b5a3a70a	216	/* Bits 15..12 : Configuration field for RAM block 3. */
yihui	9:05f0b5a3a70a	217	#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /!< Position of RAM3 field. /
yihui	9:05f0b5a3a70a	218	#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /!< Bit mask of RAM3 field. /
yihui	9:05f0b5a3a70a	219
yihui	9:05f0b5a3a70a	220	/* Bits 11..8 : Configuration field for RAM block 2. */
yihui	9:05f0b5a3a70a	221	#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /!< Position of RAM2 field. /
yihui	9:05f0b5a3a70a	222	#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /!< Bit mask of RAM2 field. /
yihui	9:05f0b5a3a70a	223
yihui	9:05f0b5a3a70a	224	/* Bits 7..4 : Configuration field for RAM block 1. */
yihui	9:05f0b5a3a70a	225	#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /!< Position of RAM1 field. /
yihui	9:05f0b5a3a70a	226	#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /!< Bit mask of RAM1 field. /
yihui	9:05f0b5a3a70a	227
yihui	9:05f0b5a3a70a	228	/* Bits 3..0 : Configuration field for RAM block 0. */
yihui	9:05f0b5a3a70a	229	#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /!< Position of RAM0 field. /
yihui	9:05f0b5a3a70a	230	#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /!< Bit mask of RAM0 field. /
yihui	9:05f0b5a3a70a	231
yihui	9:05f0b5a3a70a	232	/* Register: AMLI_RAMPRI_SPIS1 */
yihui	9:05f0b5a3a70a	233	/* Description: Configurable priority configuration register for SPIS1. */
yihui	9:05f0b5a3a70a	234
yihui	9:05f0b5a3a70a	235	/* Bits 15..12 : Configuration field for RAM block 3. */
yihui	9:05f0b5a3a70a	236	#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /!< Position of RAM3 field. /
yihui	9:05f0b5a3a70a	237	#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /!< Bit mask of RAM3 field. /
yihui	9:05f0b5a3a70a	238
yihui	9:05f0b5a3a70a	239	/* Bits 11..8 : Configuration field for RAM block 2. */
yihui	9:05f0b5a3a70a	240	#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /!< Position of RAM2 field. /
yihui	9:05f0b5a3a70a	241	#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /!< Bit mask of RAM2 field. /
yihui	9:05f0b5a3a70a	242
yihui	9:05f0b5a3a70a	243	/* Bits 7..4 : Configuration field for RAM block 1. */
yihui	9:05f0b5a3a70a	244	#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /!< Position of RAM1 field. /
yihui	9:05f0b5a3a70a	245	#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /!< Bit mask of RAM1 field. /
yihui	9:05f0b5a3a70a	246
yihui	9:05f0b5a3a70a	247	/* Bits 3..0 : Configuration field for RAM block 0. */
yihui	9:05f0b5a3a70a	248	#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /!< Position of RAM0 field. /
yihui	9:05f0b5a3a70a	249	#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /!< Bit mask of RAM0 field. /
yihui	9:05f0b5a3a70a	250
yihui	9:05f0b5a3a70a	251	/* Register: AMLI_RAMPRI_RADIO */
yihui	9:05f0b5a3a70a	252	/* Description: Configurable priority configuration register for RADIO. */
yihui	9:05f0b5a3a70a	253
yihui	9:05f0b5a3a70a	254	/* Bits 15..12 : Configuration field for RAM block 3. */
yihui	9:05f0b5a3a70a	255	#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /!< Position of RAM3 field. /
yihui	9:05f0b5a3a70a	256	#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /!< Bit mask of RAM3 field. /
yihui	9:05f0b5a3a70a	257
yihui	9:05f0b5a3a70a	258	/* Bits 11..8 : Configuration field for RAM block 2. */
yihui	9:05f0b5a3a70a	259	#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /!< Position of RAM2 field. /
yihui	9:05f0b5a3a70a	260	#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /!< Bit mask of RAM2 field. /
yihui	9:05f0b5a3a70a	261
yihui	9:05f0b5a3a70a	262	/* Bits 7..4 : Configuration field for RAM block 1. */
yihui	9:05f0b5a3a70a	263	#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /!< Position of RAM1 field. /
yihui	9:05f0b5a3a70a	264	#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /!< Bit mask of RAM1 field. /
yihui	9:05f0b5a3a70a	265
yihui	9:05f0b5a3a70a	266	/* Bits 3..0 : Configuration field for RAM block 0. */
yihui	9:05f0b5a3a70a	267	#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /!< Position of RAM0 field. /
yihui	9:05f0b5a3a70a	268	#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /!< Bit mask of RAM0 field. /
yihui	9:05f0b5a3a70a	269
yihui	9:05f0b5a3a70a	270	/* Register: AMLI_RAMPRI_ECB */
yihui	9:05f0b5a3a70a	271	/* Description: Configurable priority configuration register for ECB. */
yihui	9:05f0b5a3a70a	272
yihui	9:05f0b5a3a70a	273	/* Bits 15..12 : Configuration field for RAM block 3. */
yihui	9:05f0b5a3a70a	274	#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /!< Position of RAM3 field. /
yihui	9:05f0b5a3a70a	275	#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /!< Bit mask of RAM3 field. /
yihui	9:05f0b5a3a70a	276
yihui	9:05f0b5a3a70a	277	/* Bits 11..8 : Configuration field for RAM block 2. */
yihui	9:05f0b5a3a70a	278	#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /!< Position of RAM2 field. /
yihui	9:05f0b5a3a70a	279	#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /!< Bit mask of RAM2 field. /
yihui	9:05f0b5a3a70a	280
yihui	9:05f0b5a3a70a	281	/* Bits 7..4 : Configuration field for RAM block 1. */
yihui	9:05f0b5a3a70a	282	#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /!< Position of RAM1 field. /
yihui	9:05f0b5a3a70a	283	#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /!< Bit mask of RAM1 field. /
yihui	9:05f0b5a3a70a	284
yihui	9:05f0b5a3a70a	285	/* Bits 3..0 : Configuration field for RAM block 0. */
yihui	9:05f0b5a3a70a	286	#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /!< Position of RAM0 field. /
yihui	9:05f0b5a3a70a	287	#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /!< Bit mask of RAM0 field. /
yihui	9:05f0b5a3a70a	288
yihui	9:05f0b5a3a70a	289	/* Register: AMLI_RAMPRI_CCM */
yihui	9:05f0b5a3a70a	290	/* Description: Configurable priority configuration register for CCM. */
yihui	9:05f0b5a3a70a	291
yihui	9:05f0b5a3a70a	292	/* Bits 15..12 : Configuration field for RAM block 3. */
yihui	9:05f0b5a3a70a	293	#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /!< Position of RAM3 field. /
yihui	9:05f0b5a3a70a	294	#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /!< Bit mask of RAM3 field. /
yihui	9:05f0b5a3a70a	295
yihui	9:05f0b5a3a70a	296	/* Bits 11..8 : Configuration field for RAM block 2. */
yihui	9:05f0b5a3a70a	297	#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /!< Position of RAM2 field. /
yihui	9:05f0b5a3a70a	298	#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /!< Bit mask of RAM2 field. /
yihui	9:05f0b5a3a70a	299
yihui	9:05f0b5a3a70a	300	/* Bits 7..4 : Configuration field for RAM block 1. */
yihui	9:05f0b5a3a70a	301	#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /!< Position of RAM1 field. /
yihui	9:05f0b5a3a70a	302	#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /!< Bit mask of RAM1 field. /
yihui	9:05f0b5a3a70a	303
yihui	9:05f0b5a3a70a	304	/* Bits 3..0 : Configuration field for RAM block 0. */
yihui	9:05f0b5a3a70a	305	#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /!< Position of RAM0 field. /
yihui	9:05f0b5a3a70a	306	#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /!< Bit mask of RAM0 field. /
yihui	9:05f0b5a3a70a	307
yihui	9:05f0b5a3a70a	308	/* Register: AMLI_RAMPRI_AAR */
yihui	9:05f0b5a3a70a	309	/* Description: Configurable priority configuration register for AAR. */
yihui	9:05f0b5a3a70a	310
yihui	9:05f0b5a3a70a	311	/* Bits 15..12 : Configuration field for RAM block 3. */
yihui	9:05f0b5a3a70a	312	#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /!< Position of RAM3 field. /
yihui	9:05f0b5a3a70a	313	#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /!< Bit mask of RAM3 field. /
yihui	9:05f0b5a3a70a	314
yihui	9:05f0b5a3a70a	315	/* Bits 11..8 : Configuration field for RAM block 2. */
yihui	9:05f0b5a3a70a	316	#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /!< Position of RAM2 field. /
yihui	9:05f0b5a3a70a	317	#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /!< Bit mask of RAM2 field. /
yihui	9:05f0b5a3a70a	318
yihui	9:05f0b5a3a70a	319	/* Bits 7..4 : Configuration field for RAM block 1. */
yihui	9:05f0b5a3a70a	320	#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /!< Position of RAM1 field. /
yihui	9:05f0b5a3a70a	321	#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /!< Bit mask of RAM1 field. /
yihui	9:05f0b5a3a70a	322
yihui	9:05f0b5a3a70a	323	/* Bits 3..0 : Configuration field for RAM block 0. */
yihui	9:05f0b5a3a70a	324	#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /!< Position of RAM0 field. /
yihui	9:05f0b5a3a70a	325	#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /!< Bit mask of RAM0 field. /
yihui	9:05f0b5a3a70a	326
yihui	9:05f0b5a3a70a	327	/* Peripheral: CCM */
yihui	9:05f0b5a3a70a	328	/* Description: AES CCM Mode Encryption. */
yihui	9:05f0b5a3a70a	329
yihui	9:05f0b5a3a70a	330	/* Register: CCM_SHORTS */
yihui	9:05f0b5a3a70a	331	/* Description: Shortcut for the CCM. */
yihui	9:05f0b5a3a70a	332
yihui	9:05f0b5a3a70a	333	/* Bit 0 : Short-cut between ENDKSGEN event and CRYPT task. */
yihui	9:05f0b5a3a70a	334	#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /!< Position of ENDKSGEN_CRYPT field. /
yihui	9:05f0b5a3a70a	335	#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /!< Bit mask of ENDKSGEN_CRYPT field. /
yihui	9:05f0b5a3a70a	336	#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	337	#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	338
yihui	9:05f0b5a3a70a	339	/* Register: CCM_INTENSET */
yihui	9:05f0b5a3a70a	340	/* Description: Interrupt enable set register. */
yihui	9:05f0b5a3a70a	341
yihui	9:05f0b5a3a70a	342	/* Bit 2 : Enable interrupt on ERROR event. */
yihui	9:05f0b5a3a70a	343	#define CCM_INTENSET_ERROR_Pos (2UL) /!< Position of ERROR field. /
yihui	9:05f0b5a3a70a	344	#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
yihui	9:05f0b5a3a70a	345	#define CCM_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	346	#define CCM_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	347	#define CCM_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	348
yihui	9:05f0b5a3a70a	349	/* Bit 1 : Enable interrupt on ENDCRYPT event. */
yihui	9:05f0b5a3a70a	350	#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
yihui	9:05f0b5a3a70a	351	#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
yihui	9:05f0b5a3a70a	352	#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	353	#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	354	#define CCM_INTENSET_ENDCRYPT_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	355
yihui	9:05f0b5a3a70a	356	/* Bit 0 : Enable interrupt on ENDKSGEN event. */
yihui	9:05f0b5a3a70a	357	#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
yihui	9:05f0b5a3a70a	358	#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
yihui	9:05f0b5a3a70a	359	#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	360	#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	361	#define CCM_INTENSET_ENDKSGEN_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	362
yihui	9:05f0b5a3a70a	363	/* Register: CCM_INTENCLR */
yihui	9:05f0b5a3a70a	364	/* Description: Interrupt enable clear register. */
yihui	9:05f0b5a3a70a	365
yihui	9:05f0b5a3a70a	366	/* Bit 2 : Disable interrupt on ERROR event. */
yihui	9:05f0b5a3a70a	367	#define CCM_INTENCLR_ERROR_Pos (2UL) /!< Position of ERROR field. /
yihui	9:05f0b5a3a70a	368	#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
yihui	9:05f0b5a3a70a	369	#define CCM_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	370	#define CCM_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	371	#define CCM_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	372
yihui	9:05f0b5a3a70a	373	/* Bit 1 : Disable interrupt on ENDCRYPT event. */
yihui	9:05f0b5a3a70a	374	#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
yihui	9:05f0b5a3a70a	375	#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
yihui	9:05f0b5a3a70a	376	#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	377	#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	378	#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	379
yihui	9:05f0b5a3a70a	380	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
yihui	9:05f0b5a3a70a	381	#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
yihui	9:05f0b5a3a70a	382	#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
yihui	9:05f0b5a3a70a	383	#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	384	#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	385	#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	386
yihui	9:05f0b5a3a70a	387	/* Register: CCM_MICSTATUS */
yihui	9:05f0b5a3a70a	388	/* Description: CCM RX MIC check result. */
yihui	9:05f0b5a3a70a	389
yihui	9:05f0b5a3a70a	390	/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
yihui	9:05f0b5a3a70a	391	#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /!< Position of MICSTATUS field. /
yihui	9:05f0b5a3a70a	392	#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /!< Bit mask of MICSTATUS field. /
yihui	9:05f0b5a3a70a	393	#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /!< MIC check failed. /
yihui	9:05f0b5a3a70a	394	#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /!< MIC check passed. /
yihui	9:05f0b5a3a70a	395
yihui	9:05f0b5a3a70a	396	/* Register: CCM_ENABLE */
yihui	9:05f0b5a3a70a	397	/* Description: CCM enable. */
yihui	9:05f0b5a3a70a	398
yihui	9:05f0b5a3a70a	399	/* Bits 1..0 : CCM enable. */
yihui	9:05f0b5a3a70a	400	#define CCM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
yihui	9:05f0b5a3a70a	401	#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
yihui	9:05f0b5a3a70a	402	#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /!< CCM is disabled. /
yihui	9:05f0b5a3a70a	403	#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /!< CCM is enabled. /
yihui	9:05f0b5a3a70a	404
yihui	9:05f0b5a3a70a	405	/* Register: CCM_MODE */
yihui	9:05f0b5a3a70a	406	/* Description: Operation mode. */
yihui	9:05f0b5a3a70a	407
yihui	9:05f0b5a3a70a	408	/* Bit 0 : CCM mode operation. */
yihui	9:05f0b5a3a70a	409	#define CCM_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
yihui	9:05f0b5a3a70a	410	#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /!< Bit mask of MODE field. /
yihui	9:05f0b5a3a70a	411	#define CCM_MODE_MODE_Encryption (0UL) /!< CCM mode TX /
yihui	9:05f0b5a3a70a	412	#define CCM_MODE_MODE_Decryption (1UL) /!< CCM mode TX /
yihui	9:05f0b5a3a70a	413
yihui	9:05f0b5a3a70a	414	/* Register: CCM_POWER */
yihui	9:05f0b5a3a70a	415	/* Description: Peripheral power control. */
yihui	9:05f0b5a3a70a	416
yihui	9:05f0b5a3a70a	417	/* Bit 0 : Peripheral power control. */
yihui	9:05f0b5a3a70a	418	#define CCM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
yihui	9:05f0b5a3a70a	419	#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
yihui	9:05f0b5a3a70a	420	#define CCM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
yihui	9:05f0b5a3a70a	421	#define CCM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
yihui	9:05f0b5a3a70a	422
yihui	9:05f0b5a3a70a	423
yihui	9:05f0b5a3a70a	424	/* Peripheral: CLOCK */
yihui	9:05f0b5a3a70a	425	/* Description: Clock control. */
yihui	9:05f0b5a3a70a	426
yihui	9:05f0b5a3a70a	427	/* Register: CLOCK_INTENSET */
yihui	9:05f0b5a3a70a	428	/* Description: Interrupt enable set register. */
yihui	9:05f0b5a3a70a	429
yihui	9:05f0b5a3a70a	430	/* Bit 4 : Enable interrupt on CTTO event. */
yihui	9:05f0b5a3a70a	431	#define CLOCK_INTENSET_CTTO_Pos (4UL) /!< Position of CTTO field. /
yihui	9:05f0b5a3a70a	432	#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /!< Bit mask of CTTO field. /
yihui	9:05f0b5a3a70a	433	#define CLOCK_INTENSET_CTTO_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	434	#define CLOCK_INTENSET_CTTO_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	435	#define CLOCK_INTENSET_CTTO_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	436
yihui	9:05f0b5a3a70a	437	/* Bit 3 : Enable interrupt on DONE event. */
yihui	9:05f0b5a3a70a	438	#define CLOCK_INTENSET_DONE_Pos (3UL) /!< Position of DONE field. /
yihui	9:05f0b5a3a70a	439	#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /!< Bit mask of DONE field. /
yihui	9:05f0b5a3a70a	440	#define CLOCK_INTENSET_DONE_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	441	#define CLOCK_INTENSET_DONE_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	442	#define CLOCK_INTENSET_DONE_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	443
yihui	9:05f0b5a3a70a	444	/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
yihui	9:05f0b5a3a70a	445	#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
yihui	9:05f0b5a3a70a	446	#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
yihui	9:05f0b5a3a70a	447	#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	448	#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	449	#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	450
yihui	9:05f0b5a3a70a	451	/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
yihui	9:05f0b5a3a70a	452	#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
yihui	9:05f0b5a3a70a	453	#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
yihui	9:05f0b5a3a70a	454	#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	455	#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	456	#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	457
yihui	9:05f0b5a3a70a	458	/* Register: CLOCK_INTENCLR */
yihui	9:05f0b5a3a70a	459	/* Description: Interrupt enable clear register. */
yihui	9:05f0b5a3a70a	460
yihui	9:05f0b5a3a70a	461	/* Bit 4 : Disable interrupt on CTTO event. */
yihui	9:05f0b5a3a70a	462	#define CLOCK_INTENCLR_CTTO_Pos (4UL) /!< Position of CTTO field. /
yihui	9:05f0b5a3a70a	463	#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /!< Bit mask of CTTO field. /
yihui	9:05f0b5a3a70a	464	#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	465	#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	466	#define CLOCK_INTENCLR_CTTO_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	467
yihui	9:05f0b5a3a70a	468	/* Bit 3 : Disable interrupt on DONE event. */
yihui	9:05f0b5a3a70a	469	#define CLOCK_INTENCLR_DONE_Pos (3UL) /!< Position of DONE field. /
yihui	9:05f0b5a3a70a	470	#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /!< Bit mask of DONE field. /
yihui	9:05f0b5a3a70a	471	#define CLOCK_INTENCLR_DONE_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	472	#define CLOCK_INTENCLR_DONE_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	473	#define CLOCK_INTENCLR_DONE_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	474
yihui	9:05f0b5a3a70a	475	/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
yihui	9:05f0b5a3a70a	476	#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
yihui	9:05f0b5a3a70a	477	#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
yihui	9:05f0b5a3a70a	478	#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	479	#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	480	#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	481
yihui	9:05f0b5a3a70a	482	/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
yihui	9:05f0b5a3a70a	483	#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
yihui	9:05f0b5a3a70a	484	#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
yihui	9:05f0b5a3a70a	485	#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	486	#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	487	#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	488
yihui	9:05f0b5a3a70a	489	/* Register: CLOCK_HFCLKSTAT */
yihui	9:05f0b5a3a70a	490	/* Description: High frequency clock status. */
yihui	9:05f0b5a3a70a	491
yihui	9:05f0b5a3a70a	492	/* Bit 16 : State for the HFCLK. */
yihui	9:05f0b5a3a70a	493	#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
yihui	9:05f0b5a3a70a	494	#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
yihui	9:05f0b5a3a70a	495	#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /!< HFCLK clock not running. /
yihui	9:05f0b5a3a70a	496	#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /!< HFCLK clock running. /
yihui	9:05f0b5a3a70a	497
yihui	9:05f0b5a3a70a	498	/* Bit 0 : Active clock source for the HF clock. */
yihui	9:05f0b5a3a70a	499	#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
yihui	9:05f0b5a3a70a	500	#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
yihui	9:05f0b5a3a70a	501	#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /!< Internal 16MHz RC oscillator running and generating the HFCLK clock. /
yihui	9:05f0b5a3a70a	502	#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. /
yihui	9:05f0b5a3a70a	503
yihui	9:05f0b5a3a70a	504	/* Register: CLOCK_LFCLKSTAT */
yihui	9:05f0b5a3a70a	505	/* Description: Low frequency clock status. */
yihui	9:05f0b5a3a70a	506
yihui	9:05f0b5a3a70a	507	/* Bit 16 : State for the LF clock. */
yihui	9:05f0b5a3a70a	508	#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
yihui	9:05f0b5a3a70a	509	#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
yihui	9:05f0b5a3a70a	510	#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /!< LFCLK clock not running. /
yihui	9:05f0b5a3a70a	511	#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /!< LFCLK clock running. /
yihui	9:05f0b5a3a70a	512
yihui	9:05f0b5a3a70a	513	/* Bits 1..0 : Active clock source for the LF clock. */
yihui	9:05f0b5a3a70a	514	#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
yihui	9:05f0b5a3a70a	515	#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
yihui	9:05f0b5a3a70a	516	#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. /
yihui	9:05f0b5a3a70a	517	#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /!< External 32KiHz crystal oscillator running and generating the LFCLK clock. /
yihui	9:05f0b5a3a70a	518	#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. /
yihui	9:05f0b5a3a70a	519
yihui	9:05f0b5a3a70a	520	/* Register: CLOCK_LFCLKSRC */
yihui	9:05f0b5a3a70a	521	/* Description: Clock source for the LFCLK clock. */
yihui	9:05f0b5a3a70a	522
yihui	9:05f0b5a3a70a	523	/* Bits 1..0 : Clock source. */
yihui	9:05f0b5a3a70a	524	#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /!< Position of SRC field. /
yihui	9:05f0b5a3a70a	525	#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /!< Bit mask of SRC field. /
yihui	9:05f0b5a3a70a	526	#define CLOCK_LFCLKSRC_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
yihui	9:05f0b5a3a70a	527	#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
yihui	9:05f0b5a3a70a	528	#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
yihui	9:05f0b5a3a70a	529
yihui	9:05f0b5a3a70a	530	/* Register: CLOCK_CTIV */
yihui	9:05f0b5a3a70a	531	/* Description: Calibration timer interval. */
yihui	9:05f0b5a3a70a	532
yihui	9:05f0b5a3a70a	533	/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
yihui	9:05f0b5a3a70a	534	#define CLOCK_CTIV_CTIV_Pos (0UL) /!< Position of CTIV field. /
yihui	9:05f0b5a3a70a	535	#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /!< Bit mask of CTIV field. /
yihui	9:05f0b5a3a70a	536
yihui	9:05f0b5a3a70a	537	/* Register: CLOCK_XTALFREQ */
yihui	9:05f0b5a3a70a	538	/* Description: Crystal frequency. */
yihui	9:05f0b5a3a70a	539
yihui	9:05f0b5a3a70a	540	/* Bits 7..0 : External Xtal frequency selection. */
yihui	9:05f0b5a3a70a	541	#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
yihui	9:05f0b5a3a70a	542	#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
yihui	9:05f0b5a3a70a	543	#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz xtal is used. /
yihui	9:05f0b5a3a70a	544	#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz xtal is used. /
yihui	9:05f0b5a3a70a	545
yihui	9:05f0b5a3a70a	546
yihui	9:05f0b5a3a70a	547	/* Peripheral: COMP */
yihui	9:05f0b5a3a70a	548	/* Description: Comparator. */
yihui	9:05f0b5a3a70a	549
yihui	9:05f0b5a3a70a	550	/* Register: COMP_SHORTS */
yihui	9:05f0b5a3a70a	551	/* Description: Shortcut for the COMP. */
yihui	9:05f0b5a3a70a	552
yihui	9:05f0b5a3a70a	553	/* Bit 4 : Short-cut between CROSS event and STOP task. */
yihui	9:05f0b5a3a70a	554	#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /!< Position of CROSS_STOP field. /
yihui	9:05f0b5a3a70a	555	#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /!< Bit mask of CROSS_STOP field. /
yihui	9:05f0b5a3a70a	556	#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	557	#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	558
yihui	9:05f0b5a3a70a	559	/* Bit 3 : Short-cut between UP event and STOP task. */
yihui	9:05f0b5a3a70a	560	#define COMP_SHORTS_UP_STOP_Pos (3UL) /!< Position of UP_STOP field. /
yihui	9:05f0b5a3a70a	561	#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /!< Bit mask of UP_STOP field. /
yihui	9:05f0b5a3a70a	562	#define COMP_SHORTS_UP_STOP_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	563	#define COMP_SHORTS_UP_STOP_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	564
yihui	9:05f0b5a3a70a	565	/* Bit 2 : Short-cut between DOWN event and STOP task. */
yihui	9:05f0b5a3a70a	566	#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /!< Position of DOWN_STOP field. /
yihui	9:05f0b5a3a70a	567	#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /!< Bit mask of DOWN_STOP field. /
yihui	9:05f0b5a3a70a	568	#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	569	#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	570
yihui	9:05f0b5a3a70a	571	/* Bit 1 : Short-cut between RADY event and STOP task. */
yihui	9:05f0b5a3a70a	572	#define COMP_SHORTS_READY_STOP_Pos (1UL) /!< Position of READY_STOP field. /
yihui	9:05f0b5a3a70a	573	#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /!< Bit mask of READY_STOP field. /
yihui	9:05f0b5a3a70a	574	#define COMP_SHORTS_READY_STOP_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	575	#define COMP_SHORTS_READY_STOP_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	576
yihui	9:05f0b5a3a70a	577	/* Bit 0 : Short-cut between READY event and SAMPLE task. */
yihui	9:05f0b5a3a70a	578	#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /!< Position of READY_SAMPLE field. /
yihui	9:05f0b5a3a70a	579	#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /!< Bit mask of READY_SAMPLE field. /
yihui	9:05f0b5a3a70a	580	#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	581	#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	582
yihui	9:05f0b5a3a70a	583	/* Register: COMP_INTENSET */
yihui	9:05f0b5a3a70a	584	/* Description: Interrupt enable set register. */
yihui	9:05f0b5a3a70a	585
yihui	9:05f0b5a3a70a	586	/* Bit 3 : Enable interrupt on CROSS event. */
yihui	9:05f0b5a3a70a	587	#define COMP_INTENSET_CROSS_Pos (3UL) /!< Position of CROSS field. /
yihui	9:05f0b5a3a70a	588	#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /!< Bit mask of CROSS field. /
yihui	9:05f0b5a3a70a	589	#define COMP_INTENSET_CROSS_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	590	#define COMP_INTENSET_CROSS_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	591	#define COMP_INTENSET_CROSS_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	592
yihui	9:05f0b5a3a70a	593	/* Bit 2 : Enable interrupt on UP event. */
yihui	9:05f0b5a3a70a	594	#define COMP_INTENSET_UP_Pos (2UL) /!< Position of UP field. /
yihui	9:05f0b5a3a70a	595	#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /!< Bit mask of UP field. /
yihui	9:05f0b5a3a70a	596	#define COMP_INTENSET_UP_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	597	#define COMP_INTENSET_UP_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	598	#define COMP_INTENSET_UP_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	599
yihui	9:05f0b5a3a70a	600	/* Bit 1 : Enable interrupt on DOWN event. */
yihui	9:05f0b5a3a70a	601	#define COMP_INTENSET_DOWN_Pos (1UL) /!< Position of DOWN field. /
yihui	9:05f0b5a3a70a	602	#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /!< Bit mask of DOWN field. /
yihui	9:05f0b5a3a70a	603	#define COMP_INTENSET_DOWN_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	604	#define COMP_INTENSET_DOWN_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	605	#define COMP_INTENSET_DOWN_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	606
yihui	9:05f0b5a3a70a	607	/* Bit 0 : Enable interrupt on READY event. */
yihui	9:05f0b5a3a70a	608	#define COMP_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
yihui	9:05f0b5a3a70a	609	#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /!< Bit mask of READY field. /
yihui	9:05f0b5a3a70a	610	#define COMP_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	611	#define COMP_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	612	#define COMP_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	613
yihui	9:05f0b5a3a70a	614	/* Register: COMP_INTENCLR */
yihui	9:05f0b5a3a70a	615	/* Description: Interrupt enable clear register. */
yihui	9:05f0b5a3a70a	616
yihui	9:05f0b5a3a70a	617	/* Bit 3 : Disable interrupt on CROSS event. */
yihui	9:05f0b5a3a70a	618	#define COMP_INTENCLR_CROSS_Pos (3UL) /!< Position of CROSS field. /
yihui	9:05f0b5a3a70a	619	#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /!< Bit mask of CROSS field. /
yihui	9:05f0b5a3a70a	620	#define COMP_INTENCLR_CROSS_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	621	#define COMP_INTENCLR_CROSS_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	622	#define COMP_INTENCLR_CROSS_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	623
yihui	9:05f0b5a3a70a	624	/* Bit 2 : Disable interrupt on UP event. */
yihui	9:05f0b5a3a70a	625	#define COMP_INTENCLR_UP_Pos (2UL) /!< Position of UP field. /
yihui	9:05f0b5a3a70a	626	#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /!< Bit mask of UP field. /
yihui	9:05f0b5a3a70a	627	#define COMP_INTENCLR_UP_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	628	#define COMP_INTENCLR_UP_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	629	#define COMP_INTENCLR_UP_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	630
yihui	9:05f0b5a3a70a	631	/* Bit 1 : Disable interrupt on DOWN event. */
yihui	9:05f0b5a3a70a	632	#define COMP_INTENCLR_DOWN_Pos (1UL) /!< Position of DOWN field. /
yihui	9:05f0b5a3a70a	633	#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /!< Bit mask of DOWN field. /
yihui	9:05f0b5a3a70a	634	#define COMP_INTENCLR_DOWN_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	635	#define COMP_INTENCLR_DOWN_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	636	#define COMP_INTENCLR_DOWN_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	637
yihui	9:05f0b5a3a70a	638	/* Bit 0 : Disable interrupt on READY event. */
yihui	9:05f0b5a3a70a	639	#define COMP_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
yihui	9:05f0b5a3a70a	640	#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
yihui	9:05f0b5a3a70a	641	#define COMP_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	642	#define COMP_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	643	#define COMP_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	644
yihui	9:05f0b5a3a70a	645	/* Register: COMP_RESULT */
yihui	9:05f0b5a3a70a	646	/* Description: Compare result. */
yihui	9:05f0b5a3a70a	647
yihui	9:05f0b5a3a70a	648	/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
yihui	9:05f0b5a3a70a	649	#define COMP_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
yihui	9:05f0b5a3a70a	650	#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
yihui	9:05f0b5a3a70a	651	#define COMP_RESULT_RESULT_Bellow (0UL) /!< Input voltage is bellow the reference threshold. /
yihui	9:05f0b5a3a70a	652	#define COMP_RESULT_RESULT_Above (1UL) /!< Input voltage is above the reference threshold. /
yihui	9:05f0b5a3a70a	653
yihui	9:05f0b5a3a70a	654	/* Register: COMP_ENABLE */
yihui	9:05f0b5a3a70a	655	/* Description: Enable the COMP. */
yihui	9:05f0b5a3a70a	656
yihui	9:05f0b5a3a70a	657	/* Bits 1..0 : Enable or disable COMP. */
yihui	9:05f0b5a3a70a	658	#define COMP_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
yihui	9:05f0b5a3a70a	659	#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
yihui	9:05f0b5a3a70a	660	#define COMP_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled COMP. /
yihui	9:05f0b5a3a70a	661	#define COMP_ENABLE_ENABLE_Enabled (0x02UL) /!< Enable COMP. /
yihui	9:05f0b5a3a70a	662
yihui	9:05f0b5a3a70a	663	/* Register: COMP_PSEL */
yihui	9:05f0b5a3a70a	664	/* Description: Input pin select. */
yihui	9:05f0b5a3a70a	665
yihui	9:05f0b5a3a70a	666	/* Bits 2..0 : Analog input pin select. */
yihui	9:05f0b5a3a70a	667	#define COMP_PSEL_PSEL_Pos (0UL) /!< Position of PSEL field. /
yihui	9:05f0b5a3a70a	668	#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /!< Bit mask of PSEL field. /
yihui	9:05f0b5a3a70a	669	#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /!< Use analog input 0 as analog input. /
yihui	9:05f0b5a3a70a	670	#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /!< Use analog input 1 as analog input. /
yihui	9:05f0b5a3a70a	671	#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /!< Use analog input 2 as analog input. /
yihui	9:05f0b5a3a70a	672	#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /!< Use analog input 3 as analog input. /
yihui	9:05f0b5a3a70a	673	#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /!< Use analog input 4 as analog input. /
yihui	9:05f0b5a3a70a	674	#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /!< Use analog input 5 as analog input. /
yihui	9:05f0b5a3a70a	675	#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /!< Use analog input 6 as analog input. /
yihui	9:05f0b5a3a70a	676	#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /!< Use analog input 7 as analog input. /
yihui	9:05f0b5a3a70a	677
yihui	9:05f0b5a3a70a	678	/* Register: COMP_REFSEL */
yihui	9:05f0b5a3a70a	679	/* Description: Reference select. */
yihui	9:05f0b5a3a70a	680
yihui	9:05f0b5a3a70a	681	/* Bits 2..0 : Reference select. */
yihui	9:05f0b5a3a70a	682	#define COMP_REFSEL_REFSEL_Pos (0UL) /!< Position of REFSEL field. /
yihui	9:05f0b5a3a70a	683	#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /!< Bit mask of REFSEL field. /
yihui	9:05f0b5a3a70a	684	#define COMP_REFSEL_REFSEL_Int1V5 (0UL) /!< Use internal 1V5 as reference. /
yihui	9:05f0b5a3a70a	685	#define COMP_REFSEL_REFSEL_Int2V0 (1UL) /!< Use internal 2V0 as reference. /
yihui	9:05f0b5a3a70a	686	#define COMP_REFSEL_REFSEL_Int2V5 (2UL) /!< Use internal 2V5 as reference. /
yihui	9:05f0b5a3a70a	687	#define COMP_REFSEL_REFSEL_Supply (4UL) /!< Use supply as reference. /
yihui	9:05f0b5a3a70a	688	#define COMP_REFSEL_REFSEL_ARef (5UL) /!< Use external analog reference as reference. /
yihui	9:05f0b5a3a70a	689
yihui	9:05f0b5a3a70a	690	/* Register: COMP_EXTREFSEL */
yihui	9:05f0b5a3a70a	691	/* Description: External reference select. */
yihui	9:05f0b5a3a70a	692
yihui	9:05f0b5a3a70a	693	/* Bit 0 : External analog reference pin selection. */
yihui	9:05f0b5a3a70a	694	#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /!< Position of EXTREFSEL field. /
yihui	9:05f0b5a3a70a	695	#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
yihui	9:05f0b5a3a70a	696	#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /!< Use analog reference 0 as reference. /
yihui	9:05f0b5a3a70a	697	#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /!< Use analog reference 1 as reference. /
yihui	9:05f0b5a3a70a	698
yihui	9:05f0b5a3a70a	699	/* Register: COMP_TH */
yihui	9:05f0b5a3a70a	700	/* Description: Threshold configuration for hysteresis unit. */
yihui	9:05f0b5a3a70a	701
yihui	9:05f0b5a3a70a	702	/* Bits 13..8 : VDOWN configuration. */
yihui	9:05f0b5a3a70a	703	#define COMP_TH_THDOWN_Pos (8UL) /!< Position of THDOWN field. /
yihui	9:05f0b5a3a70a	704	#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /!< Bit mask of THDOWN field. /
yihui	9:05f0b5a3a70a	705
yihui	9:05f0b5a3a70a	706	/* Bits 5..0 : VUP configuration. */
yihui	9:05f0b5a3a70a	707	#define COMP_TH_THUP_Pos (0UL) /!< Position of THUP field. /
yihui	9:05f0b5a3a70a	708	#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /!< Bit mask of THUP field. /
yihui	9:05f0b5a3a70a	709
yihui	9:05f0b5a3a70a	710	/* Register: COMP_MODE */
yihui	9:05f0b5a3a70a	711	/* Description: Mode configuration. */
yihui	9:05f0b5a3a70a	712
yihui	9:05f0b5a3a70a	713	/* Bit 8 : Main operation mode. */
yihui	9:05f0b5a3a70a	714	#define COMP_MODE_MAIN_Pos (8UL) /!< Position of MAIN field. /
yihui	9:05f0b5a3a70a	715	#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /!< Bit mask of MAIN field. /
yihui	9:05f0b5a3a70a	716	#define COMP_MODE_MAIN_Single (0UL) /!< Single ended mode. /
yihui	9:05f0b5a3a70a	717	#define COMP_MODE_MAIN_Diff (1UL) /!< Differential mode. /
yihui	9:05f0b5a3a70a	718
yihui	9:05f0b5a3a70a	719	/* Bits 1..0 : Speed and power mode. */
yihui	9:05f0b5a3a70a	720	#define COMP_MODE_SP_Pos (0UL) /!< Position of SP field. /
yihui	9:05f0b5a3a70a	721	#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /!< Bit mask of SP field. /
yihui	9:05f0b5a3a70a	722	#define COMP_MODE_SP_Low (0UL) /!< Low power mode. /
yihui	9:05f0b5a3a70a	723	#define COMP_MODE_SP_Normal (1UL) /!< Normal mode. /
yihui	9:05f0b5a3a70a	724	#define COMP_MODE_SP_High (2UL) /!< High speed mode. /
yihui	9:05f0b5a3a70a	725
yihui	9:05f0b5a3a70a	726	/* Register: COMP_POWER */
yihui	9:05f0b5a3a70a	727	/* Description: Peripheral power control. */
yihui	9:05f0b5a3a70a	728
yihui	9:05f0b5a3a70a	729	/* Bit 0 : Peripheral power control. */
yihui	9:05f0b5a3a70a	730	#define COMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
yihui	9:05f0b5a3a70a	731	#define COMP_POWER_POWER_Msk (0x1UL << COMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
yihui	9:05f0b5a3a70a	732	#define COMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
yihui	9:05f0b5a3a70a	733	#define COMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
yihui	9:05f0b5a3a70a	734
yihui	9:05f0b5a3a70a	735
yihui	9:05f0b5a3a70a	736	/* Peripheral: ECB */
yihui	9:05f0b5a3a70a	737	/* Description: AES ECB Mode Encryption. */
yihui	9:05f0b5a3a70a	738
yihui	9:05f0b5a3a70a	739	/* Register: ECB_INTENSET */
yihui	9:05f0b5a3a70a	740	/* Description: Interrupt enable set register. */
yihui	9:05f0b5a3a70a	741
yihui	9:05f0b5a3a70a	742	/* Bit 1 : Enable interrupt on ERRORECB event. */
yihui	9:05f0b5a3a70a	743	#define ECB_INTENSET_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
yihui	9:05f0b5a3a70a	744	#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
yihui	9:05f0b5a3a70a	745	#define ECB_INTENSET_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	746	#define ECB_INTENSET_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	747	#define ECB_INTENSET_ERRORECB_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	748
yihui	9:05f0b5a3a70a	749	/* Bit 0 : Enable interrupt on ENDECB event. */
yihui	9:05f0b5a3a70a	750	#define ECB_INTENSET_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
yihui	9:05f0b5a3a70a	751	#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /!< Bit mask of ENDECB field. /
yihui	9:05f0b5a3a70a	752	#define ECB_INTENSET_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	753	#define ECB_INTENSET_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	754	#define ECB_INTENSET_ENDECB_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	755
yihui	9:05f0b5a3a70a	756	/* Register: ECB_INTENCLR */
yihui	9:05f0b5a3a70a	757	/* Description: Interrupt enable clear register. */
yihui	9:05f0b5a3a70a	758
yihui	9:05f0b5a3a70a	759	/* Bit 1 : Disable interrupt on ERRORECB event. */
yihui	9:05f0b5a3a70a	760	#define ECB_INTENCLR_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
yihui	9:05f0b5a3a70a	761	#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
yihui	9:05f0b5a3a70a	762	#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	763	#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	764	#define ECB_INTENCLR_ERRORECB_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	765
yihui	9:05f0b5a3a70a	766	/* Bit 0 : Disable interrupt on ENDECB event. */
yihui	9:05f0b5a3a70a	767	#define ECB_INTENCLR_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
yihui	9:05f0b5a3a70a	768	#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /!< Bit mask of ENDECB field. /
yihui	9:05f0b5a3a70a	769	#define ECB_INTENCLR_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	770	#define ECB_INTENCLR_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	771	#define ECB_INTENCLR_ENDECB_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	772
yihui	9:05f0b5a3a70a	773	/* Register: ECB_POWER */
yihui	9:05f0b5a3a70a	774	/* Description: Peripheral power control. */
yihui	9:05f0b5a3a70a	775
yihui	9:05f0b5a3a70a	776	/* Bit 0 : Peripheral power control. */
yihui	9:05f0b5a3a70a	777	#define ECB_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
yihui	9:05f0b5a3a70a	778	#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /!< Bit mask of POWER field. /
yihui	9:05f0b5a3a70a	779	#define ECB_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
yihui	9:05f0b5a3a70a	780	#define ECB_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
yihui	9:05f0b5a3a70a	781
yihui	9:05f0b5a3a70a	782
yihui	9:05f0b5a3a70a	783	/* Peripheral: FICR */
yihui	9:05f0b5a3a70a	784	/* Description: Factory Information Configuration. */
yihui	9:05f0b5a3a70a	785
yihui	9:05f0b5a3a70a	786	/* Register: FICR_PPFC */
yihui	9:05f0b5a3a70a	787	/* Description: Pre-programmed factory code present. */
yihui	9:05f0b5a3a70a	788
yihui	9:05f0b5a3a70a	789	/* Bits 7..0 : Pre-programmed factory code present. */
yihui	9:05f0b5a3a70a	790	#define FICR_PPFC_PPFC_Pos (0UL) /!< Position of PPFC field. /
yihui	9:05f0b5a3a70a	791	#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /!< Bit mask of PPFC field. /
yihui	9:05f0b5a3a70a	792	#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /!< Not present. /
yihui	9:05f0b5a3a70a	793	#define FICR_PPFC_PPFC_Present (0x00UL) /!< Present. /
yihui	9:05f0b5a3a70a	794
yihui	9:05f0b5a3a70a	795	/* Register: FICR_CONFIGID */
yihui	9:05f0b5a3a70a	796	/* Description: Configuration identifier. */
yihui	9:05f0b5a3a70a	797
yihui	9:05f0b5a3a70a	798	/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
yihui	9:05f0b5a3a70a	799	#define FICR_CONFIGID_FWID_Pos (16UL) /!< Position of FWID field. /
yihui	9:05f0b5a3a70a	800	#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /!< Bit mask of FWID field. /
yihui	9:05f0b5a3a70a	801
yihui	9:05f0b5a3a70a	802	/* Bits 15..0 : Hardware Identification Number. */
yihui	9:05f0b5a3a70a	803	#define FICR_CONFIGID_HWID_Pos (0UL) /!< Position of HWID field. /
yihui	9:05f0b5a3a70a	804	#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /!< Bit mask of HWID field. /
yihui	9:05f0b5a3a70a	805
yihui	9:05f0b5a3a70a	806	/* Register: FICR_DEVICEADDRTYPE */
yihui	9:05f0b5a3a70a	807	/* Description: Device address type. */
yihui	9:05f0b5a3a70a	808
yihui	9:05f0b5a3a70a	809	/* Bit 0 : Device address type. */
yihui	9:05f0b5a3a70a	810	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /!< Position of DEVICEADDRTYPE field. /
yihui	9:05f0b5a3a70a	811	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /!< Bit mask of DEVICEADDRTYPE field. /
yihui	9:05f0b5a3a70a	812	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /!< Public address. /
yihui	9:05f0b5a3a70a	813	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /!< Random address. /
yihui	9:05f0b5a3a70a	814
yihui	9:05f0b5a3a70a	815	/* Register: FICR_OVERRIDEEN */
yihui	9:05f0b5a3a70a	816	/* Description: Radio calibration override enable. */
yihui	9:05f0b5a3a70a	817
yihui	9:05f0b5a3a70a	818	/* Bit 3 : Override default values for BLE_1Mbit mode. */
yihui	9:05f0b5a3a70a	819	#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /!< Position of BLE_1MBIT field. /
yihui	9:05f0b5a3a70a	820	#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /!< Bit mask of BLE_1MBIT field. /
yihui	9:05f0b5a3a70a	821	#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /!< Override the default values for BLE_1Mbit mode. /
yihui	9:05f0b5a3a70a	822	#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /!< Do not override the default values for BLE_1Mbit mode. /
yihui	9:05f0b5a3a70a	823
yihui	9:05f0b5a3a70a	824
yihui	9:05f0b5a3a70a	825	/* Peripheral: GPIO */
yihui	9:05f0b5a3a70a	826	/* Description: General purpose input and output. */
yihui	9:05f0b5a3a70a	827
yihui	9:05f0b5a3a70a	828	/* Register: GPIO_OUT */
yihui	9:05f0b5a3a70a	829	/* Description: Write GPIO port. */
yihui	9:05f0b5a3a70a	830
yihui	9:05f0b5a3a70a	831	/* Bit 31 : Pin 31. */
yihui	9:05f0b5a3a70a	832	#define GPIO_OUT_PIN31_Pos (31UL) /!< Position of PIN31 field. /
yihui	9:05f0b5a3a70a	833	#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /!< Bit mask of PIN31 field. /
yihui	9:05f0b5a3a70a	834	#define GPIO_OUT_PIN31_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	835	#define GPIO_OUT_PIN31_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	836
yihui	9:05f0b5a3a70a	837	/* Bit 30 : Pin 30. */
yihui	9:05f0b5a3a70a	838	#define GPIO_OUT_PIN30_Pos (30UL) /!< Position of PIN30 field. /
yihui	9:05f0b5a3a70a	839	#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /!< Bit mask of PIN30 field. /
yihui	9:05f0b5a3a70a	840	#define GPIO_OUT_PIN30_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	841	#define GPIO_OUT_PIN30_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	842
yihui	9:05f0b5a3a70a	843	/* Bit 29 : Pin 29. */
yihui	9:05f0b5a3a70a	844	#define GPIO_OUT_PIN29_Pos (29UL) /!< Position of PIN29 field. /
yihui	9:05f0b5a3a70a	845	#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /!< Bit mask of PIN29 field. /
yihui	9:05f0b5a3a70a	846	#define GPIO_OUT_PIN29_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	847	#define GPIO_OUT_PIN29_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	848
yihui	9:05f0b5a3a70a	849	/* Bit 28 : Pin 28. */
yihui	9:05f0b5a3a70a	850	#define GPIO_OUT_PIN28_Pos (28UL) /!< Position of PIN28 field. /
yihui	9:05f0b5a3a70a	851	#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /!< Bit mask of PIN28 field. /
yihui	9:05f0b5a3a70a	852	#define GPIO_OUT_PIN28_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	853	#define GPIO_OUT_PIN28_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	854
yihui	9:05f0b5a3a70a	855	/* Bit 27 : Pin 27. */
yihui	9:05f0b5a3a70a	856	#define GPIO_OUT_PIN27_Pos (27UL) /!< Position of PIN27 field. /
yihui	9:05f0b5a3a70a	857	#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /!< Bit mask of PIN27 field. /
yihui	9:05f0b5a3a70a	858	#define GPIO_OUT_PIN27_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	859	#define GPIO_OUT_PIN27_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	860
yihui	9:05f0b5a3a70a	861	/* Bit 26 : Pin 26. */
yihui	9:05f0b5a3a70a	862	#define GPIO_OUT_PIN26_Pos (26UL) /!< Position of PIN26 field. /
yihui	9:05f0b5a3a70a	863	#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /!< Bit mask of PIN26 field. /
yihui	9:05f0b5a3a70a	864	#define GPIO_OUT_PIN26_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	865	#define GPIO_OUT_PIN26_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	866
yihui	9:05f0b5a3a70a	867	/* Bit 25 : Pin 25. */
yihui	9:05f0b5a3a70a	868	#define GPIO_OUT_PIN25_Pos (25UL) /!< Position of PIN25 field. /
yihui	9:05f0b5a3a70a	869	#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /!< Bit mask of PIN25 field. /
yihui	9:05f0b5a3a70a	870	#define GPIO_OUT_PIN25_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	871	#define GPIO_OUT_PIN25_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	872
yihui	9:05f0b5a3a70a	873	/* Bit 24 : Pin 24. */
yihui	9:05f0b5a3a70a	874	#define GPIO_OUT_PIN24_Pos (24UL) /!< Position of PIN24 field. /
yihui	9:05f0b5a3a70a	875	#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /!< Bit mask of PIN24 field. /
yihui	9:05f0b5a3a70a	876	#define GPIO_OUT_PIN24_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	877	#define GPIO_OUT_PIN24_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	878
yihui	9:05f0b5a3a70a	879	/* Bit 23 : Pin 23. */
yihui	9:05f0b5a3a70a	880	#define GPIO_OUT_PIN23_Pos (23UL) /!< Position of PIN23 field. /
yihui	9:05f0b5a3a70a	881	#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /!< Bit mask of PIN23 field. /
yihui	9:05f0b5a3a70a	882	#define GPIO_OUT_PIN23_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	883	#define GPIO_OUT_PIN23_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	884
yihui	9:05f0b5a3a70a	885	/* Bit 22 : Pin 22. */
yihui	9:05f0b5a3a70a	886	#define GPIO_OUT_PIN22_Pos (22UL) /!< Position of PIN22 field. /
yihui	9:05f0b5a3a70a	887	#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /!< Bit mask of PIN22 field. /
yihui	9:05f0b5a3a70a	888	#define GPIO_OUT_PIN22_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	889	#define GPIO_OUT_PIN22_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	890
yihui	9:05f0b5a3a70a	891	/* Bit 21 : Pin 21. */
yihui	9:05f0b5a3a70a	892	#define GPIO_OUT_PIN21_Pos (21UL) /!< Position of PIN21 field. /
yihui	9:05f0b5a3a70a	893	#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /!< Bit mask of PIN21 field. /
yihui	9:05f0b5a3a70a	894	#define GPIO_OUT_PIN21_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	895	#define GPIO_OUT_PIN21_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	896
yihui	9:05f0b5a3a70a	897	/* Bit 20 : Pin 20. */
yihui	9:05f0b5a3a70a	898	#define GPIO_OUT_PIN20_Pos (20UL) /!< Position of PIN20 field. /
yihui	9:05f0b5a3a70a	899	#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /!< Bit mask of PIN20 field. /
yihui	9:05f0b5a3a70a	900	#define GPIO_OUT_PIN20_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	901	#define GPIO_OUT_PIN20_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	902
yihui	9:05f0b5a3a70a	903	/* Bit 19 : Pin 19. */
yihui	9:05f0b5a3a70a	904	#define GPIO_OUT_PIN19_Pos (19UL) /!< Position of PIN19 field. /
yihui	9:05f0b5a3a70a	905	#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /!< Bit mask of PIN19 field. /
yihui	9:05f0b5a3a70a	906	#define GPIO_OUT_PIN19_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	907	#define GPIO_OUT_PIN19_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	908
yihui	9:05f0b5a3a70a	909	/* Bit 18 : Pin 18. */
yihui	9:05f0b5a3a70a	910	#define GPIO_OUT_PIN18_Pos (18UL) /!< Position of PIN18 field. /
yihui	9:05f0b5a3a70a	911	#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /!< Bit mask of PIN18 field. /
yihui	9:05f0b5a3a70a	912	#define GPIO_OUT_PIN18_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	913	#define GPIO_OUT_PIN18_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	914
yihui	9:05f0b5a3a70a	915	/* Bit 17 : Pin 17. */
yihui	9:05f0b5a3a70a	916	#define GPIO_OUT_PIN17_Pos (17UL) /!< Position of PIN17 field. /
yihui	9:05f0b5a3a70a	917	#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /!< Bit mask of PIN17 field. /
yihui	9:05f0b5a3a70a	918	#define GPIO_OUT_PIN17_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	919	#define GPIO_OUT_PIN17_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	920
yihui	9:05f0b5a3a70a	921	/* Bit 16 : Pin 16. */
yihui	9:05f0b5a3a70a	922	#define GPIO_OUT_PIN16_Pos (16UL) /!< Position of PIN16 field. /
yihui	9:05f0b5a3a70a	923	#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /!< Bit mask of PIN16 field. /
yihui	9:05f0b5a3a70a	924	#define GPIO_OUT_PIN16_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	925	#define GPIO_OUT_PIN16_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	926
yihui	9:05f0b5a3a70a	927	/* Bit 15 : Pin 15. */
yihui	9:05f0b5a3a70a	928	#define GPIO_OUT_PIN15_Pos (15UL) /!< Position of PIN15 field. /
yihui	9:05f0b5a3a70a	929	#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /!< Bit mask of PIN15 field. /
yihui	9:05f0b5a3a70a	930	#define GPIO_OUT_PIN15_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	931	#define GPIO_OUT_PIN15_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	932
yihui	9:05f0b5a3a70a	933	/* Bit 14 : Pin 14. */
yihui	9:05f0b5a3a70a	934	#define GPIO_OUT_PIN14_Pos (14UL) /!< Position of PIN14 field. /
yihui	9:05f0b5a3a70a	935	#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /!< Bit mask of PIN14 field. /
yihui	9:05f0b5a3a70a	936	#define GPIO_OUT_PIN14_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	937	#define GPIO_OUT_PIN14_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	938
yihui	9:05f0b5a3a70a	939	/* Bit 13 : Pin 13. */
yihui	9:05f0b5a3a70a	940	#define GPIO_OUT_PIN13_Pos (13UL) /!< Position of PIN13 field. /
yihui	9:05f0b5a3a70a	941	#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /!< Bit mask of PIN13 field. /
yihui	9:05f0b5a3a70a	942	#define GPIO_OUT_PIN13_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	943	#define GPIO_OUT_PIN13_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	944
yihui	9:05f0b5a3a70a	945	/* Bit 12 : Pin 12. */
yihui	9:05f0b5a3a70a	946	#define GPIO_OUT_PIN12_Pos (12UL) /!< Position of PIN12 field. /
yihui	9:05f0b5a3a70a	947	#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /!< Bit mask of PIN12 field. /
yihui	9:05f0b5a3a70a	948	#define GPIO_OUT_PIN12_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	949	#define GPIO_OUT_PIN12_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	950
yihui	9:05f0b5a3a70a	951	/* Bit 11 : Pin 11. */
yihui	9:05f0b5a3a70a	952	#define GPIO_OUT_PIN11_Pos (11UL) /!< Position of PIN11 field. /
yihui	9:05f0b5a3a70a	953	#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /!< Bit mask of PIN11 field. /
yihui	9:05f0b5a3a70a	954	#define GPIO_OUT_PIN11_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	955	#define GPIO_OUT_PIN11_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	956
yihui	9:05f0b5a3a70a	957	/* Bit 10 : Pin 10. */
yihui	9:05f0b5a3a70a	958	#define GPIO_OUT_PIN10_Pos (10UL) /!< Position of PIN10 field. /
yihui	9:05f0b5a3a70a	959	#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /!< Bit mask of PIN10 field. /
yihui	9:05f0b5a3a70a	960	#define GPIO_OUT_PIN10_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	961	#define GPIO_OUT_PIN10_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	962
yihui	9:05f0b5a3a70a	963	/* Bit 9 : Pin 9. */
yihui	9:05f0b5a3a70a	964	#define GPIO_OUT_PIN9_Pos (9UL) /!< Position of PIN9 field. /
yihui	9:05f0b5a3a70a	965	#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /!< Bit mask of PIN9 field. /
yihui	9:05f0b5a3a70a	966	#define GPIO_OUT_PIN9_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	967	#define GPIO_OUT_PIN9_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	968
yihui	9:05f0b5a3a70a	969	/* Bit 8 : Pin 8. */
yihui	9:05f0b5a3a70a	970	#define GPIO_OUT_PIN8_Pos (8UL) /!< Position of PIN8 field. /
yihui	9:05f0b5a3a70a	971	#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /!< Bit mask of PIN8 field. /
yihui	9:05f0b5a3a70a	972	#define GPIO_OUT_PIN8_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	973	#define GPIO_OUT_PIN8_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	974
yihui	9:05f0b5a3a70a	975	/* Bit 7 : Pin 7. */
yihui	9:05f0b5a3a70a	976	#define GPIO_OUT_PIN7_Pos (7UL) /!< Position of PIN7 field. /
yihui	9:05f0b5a3a70a	977	#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /!< Bit mask of PIN7 field. /
yihui	9:05f0b5a3a70a	978	#define GPIO_OUT_PIN7_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	979	#define GPIO_OUT_PIN7_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	980
yihui	9:05f0b5a3a70a	981	/* Bit 6 : Pin 6. */
yihui	9:05f0b5a3a70a	982	#define GPIO_OUT_PIN6_Pos (6UL) /!< Position of PIN6 field. /
yihui	9:05f0b5a3a70a	983	#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /!< Bit mask of PIN6 field. /
yihui	9:05f0b5a3a70a	984	#define GPIO_OUT_PIN6_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	985	#define GPIO_OUT_PIN6_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	986
yihui	9:05f0b5a3a70a	987	/* Bit 5 : Pin 5. */
yihui	9:05f0b5a3a70a	988	#define GPIO_OUT_PIN5_Pos (5UL) /!< Position of PIN5 field. /
yihui	9:05f0b5a3a70a	989	#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /!< Bit mask of PIN5 field. /
yihui	9:05f0b5a3a70a	990	#define GPIO_OUT_PIN5_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	991	#define GPIO_OUT_PIN5_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	992
yihui	9:05f0b5a3a70a	993	/* Bit 4 : Pin 4. */
yihui	9:05f0b5a3a70a	994	#define GPIO_OUT_PIN4_Pos (4UL) /!< Position of PIN4 field. /
yihui	9:05f0b5a3a70a	995	#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /!< Bit mask of PIN4 field. /
yihui	9:05f0b5a3a70a	996	#define GPIO_OUT_PIN4_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	997	#define GPIO_OUT_PIN4_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	998
yihui	9:05f0b5a3a70a	999	/* Bit 3 : Pin 3. */
yihui	9:05f0b5a3a70a	1000	#define GPIO_OUT_PIN3_Pos (3UL) /!< Position of PIN3 field. /
yihui	9:05f0b5a3a70a	1001	#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /!< Bit mask of PIN3 field. /
yihui	9:05f0b5a3a70a	1002	#define GPIO_OUT_PIN3_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1003	#define GPIO_OUT_PIN3_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1004
yihui	9:05f0b5a3a70a	1005	/* Bit 2 : Pin 2. */
yihui	9:05f0b5a3a70a	1006	#define GPIO_OUT_PIN2_Pos (2UL) /!< Position of PIN2 field. /
yihui	9:05f0b5a3a70a	1007	#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /!< Bit mask of PIN2 field. /
yihui	9:05f0b5a3a70a	1008	#define GPIO_OUT_PIN2_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1009	#define GPIO_OUT_PIN2_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1010
yihui	9:05f0b5a3a70a	1011	/* Bit 1 : Pin 1. */
yihui	9:05f0b5a3a70a	1012	#define GPIO_OUT_PIN1_Pos (1UL) /!< Position of PIN1 field. /
yihui	9:05f0b5a3a70a	1013	#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /!< Bit mask of PIN1 field. /
yihui	9:05f0b5a3a70a	1014	#define GPIO_OUT_PIN1_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1015	#define GPIO_OUT_PIN1_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1016
yihui	9:05f0b5a3a70a	1017	/* Bit 0 : Pin 0. */
yihui	9:05f0b5a3a70a	1018	#define GPIO_OUT_PIN0_Pos (0UL) /!< Position of PIN0 field. /
yihui	9:05f0b5a3a70a	1019	#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /!< Bit mask of PIN0 field. /
yihui	9:05f0b5a3a70a	1020	#define GPIO_OUT_PIN0_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1021	#define GPIO_OUT_PIN0_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1022
yihui	9:05f0b5a3a70a	1023	/* Register: GPIO_OUTSET */
yihui	9:05f0b5a3a70a	1024	/* Description: Set individual bits in GPIO port. */
yihui	9:05f0b5a3a70a	1025
yihui	9:05f0b5a3a70a	1026	/* Bit 31 : Pin 31. */
yihui	9:05f0b5a3a70a	1027	#define GPIO_OUTSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
yihui	9:05f0b5a3a70a	1028	#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
yihui	9:05f0b5a3a70a	1029	#define GPIO_OUTSET_PIN31_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1030	#define GPIO_OUTSET_PIN31_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1031	#define GPIO_OUTSET_PIN31_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1032
yihui	9:05f0b5a3a70a	1033	/* Bit 30 : Pin 30. */
yihui	9:05f0b5a3a70a	1034	#define GPIO_OUTSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
yihui	9:05f0b5a3a70a	1035	#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
yihui	9:05f0b5a3a70a	1036	#define GPIO_OUTSET_PIN30_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1037	#define GPIO_OUTSET_PIN30_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1038	#define GPIO_OUTSET_PIN30_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1039
yihui	9:05f0b5a3a70a	1040	/* Bit 29 : Pin 29. */
yihui	9:05f0b5a3a70a	1041	#define GPIO_OUTSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
yihui	9:05f0b5a3a70a	1042	#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
yihui	9:05f0b5a3a70a	1043	#define GPIO_OUTSET_PIN29_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1044	#define GPIO_OUTSET_PIN29_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1045	#define GPIO_OUTSET_PIN29_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1046
yihui	9:05f0b5a3a70a	1047	/* Bit 28 : Pin 28. */
yihui	9:05f0b5a3a70a	1048	#define GPIO_OUTSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
yihui	9:05f0b5a3a70a	1049	#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
yihui	9:05f0b5a3a70a	1050	#define GPIO_OUTSET_PIN28_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1051	#define GPIO_OUTSET_PIN28_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1052	#define GPIO_OUTSET_PIN28_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1053
yihui	9:05f0b5a3a70a	1054	/* Bit 27 : Pin 27. */
yihui	9:05f0b5a3a70a	1055	#define GPIO_OUTSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
yihui	9:05f0b5a3a70a	1056	#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
yihui	9:05f0b5a3a70a	1057	#define GPIO_OUTSET_PIN27_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1058	#define GPIO_OUTSET_PIN27_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1059	#define GPIO_OUTSET_PIN27_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1060
yihui	9:05f0b5a3a70a	1061	/* Bit 26 : Pin 26. */
yihui	9:05f0b5a3a70a	1062	#define GPIO_OUTSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
yihui	9:05f0b5a3a70a	1063	#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
yihui	9:05f0b5a3a70a	1064	#define GPIO_OUTSET_PIN26_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1065	#define GPIO_OUTSET_PIN26_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1066	#define GPIO_OUTSET_PIN26_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1067
yihui	9:05f0b5a3a70a	1068	/* Bit 25 : Pin 25. */
yihui	9:05f0b5a3a70a	1069	#define GPIO_OUTSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
yihui	9:05f0b5a3a70a	1070	#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
yihui	9:05f0b5a3a70a	1071	#define GPIO_OUTSET_PIN25_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1072	#define GPIO_OUTSET_PIN25_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1073	#define GPIO_OUTSET_PIN25_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1074
yihui	9:05f0b5a3a70a	1075	/* Bit 24 : Pin 24. */
yihui	9:05f0b5a3a70a	1076	#define GPIO_OUTSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
yihui	9:05f0b5a3a70a	1077	#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
yihui	9:05f0b5a3a70a	1078	#define GPIO_OUTSET_PIN24_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1079	#define GPIO_OUTSET_PIN24_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1080	#define GPIO_OUTSET_PIN24_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1081
yihui	9:05f0b5a3a70a	1082	/* Bit 23 : Pin 23. */
yihui	9:05f0b5a3a70a	1083	#define GPIO_OUTSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
yihui	9:05f0b5a3a70a	1084	#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
yihui	9:05f0b5a3a70a	1085	#define GPIO_OUTSET_PIN23_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1086	#define GPIO_OUTSET_PIN23_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1087	#define GPIO_OUTSET_PIN23_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1088
yihui	9:05f0b5a3a70a	1089	/* Bit 22 : Pin 22. */
yihui	9:05f0b5a3a70a	1090	#define GPIO_OUTSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
yihui	9:05f0b5a3a70a	1091	#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
yihui	9:05f0b5a3a70a	1092	#define GPIO_OUTSET_PIN22_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1093	#define GPIO_OUTSET_PIN22_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1094	#define GPIO_OUTSET_PIN22_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1095
yihui	9:05f0b5a3a70a	1096	/* Bit 21 : Pin 21. */
yihui	9:05f0b5a3a70a	1097	#define GPIO_OUTSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
yihui	9:05f0b5a3a70a	1098	#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
yihui	9:05f0b5a3a70a	1099	#define GPIO_OUTSET_PIN21_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1100	#define GPIO_OUTSET_PIN21_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1101	#define GPIO_OUTSET_PIN21_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1102
yihui	9:05f0b5a3a70a	1103	/* Bit 20 : Pin 20. */
yihui	9:05f0b5a3a70a	1104	#define GPIO_OUTSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
yihui	9:05f0b5a3a70a	1105	#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
yihui	9:05f0b5a3a70a	1106	#define GPIO_OUTSET_PIN20_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1107	#define GPIO_OUTSET_PIN20_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1108	#define GPIO_OUTSET_PIN20_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1109
yihui	9:05f0b5a3a70a	1110	/* Bit 19 : Pin 19. */
yihui	9:05f0b5a3a70a	1111	#define GPIO_OUTSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
yihui	9:05f0b5a3a70a	1112	#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
yihui	9:05f0b5a3a70a	1113	#define GPIO_OUTSET_PIN19_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1114	#define GPIO_OUTSET_PIN19_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1115	#define GPIO_OUTSET_PIN19_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1116
yihui	9:05f0b5a3a70a	1117	/* Bit 18 : Pin 18. */
yihui	9:05f0b5a3a70a	1118	#define GPIO_OUTSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
yihui	9:05f0b5a3a70a	1119	#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
yihui	9:05f0b5a3a70a	1120	#define GPIO_OUTSET_PIN18_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1121	#define GPIO_OUTSET_PIN18_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1122	#define GPIO_OUTSET_PIN18_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1123
yihui	9:05f0b5a3a70a	1124	/* Bit 17 : Pin 17. */
yihui	9:05f0b5a3a70a	1125	#define GPIO_OUTSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
yihui	9:05f0b5a3a70a	1126	#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
yihui	9:05f0b5a3a70a	1127	#define GPIO_OUTSET_PIN17_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1128	#define GPIO_OUTSET_PIN17_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1129	#define GPIO_OUTSET_PIN17_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1130
yihui	9:05f0b5a3a70a	1131	/* Bit 16 : Pin 16. */
yihui	9:05f0b5a3a70a	1132	#define GPIO_OUTSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
yihui	9:05f0b5a3a70a	1133	#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
yihui	9:05f0b5a3a70a	1134	#define GPIO_OUTSET_PIN16_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1135	#define GPIO_OUTSET_PIN16_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1136	#define GPIO_OUTSET_PIN16_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1137
yihui	9:05f0b5a3a70a	1138	/* Bit 15 : Pin 15. */
yihui	9:05f0b5a3a70a	1139	#define GPIO_OUTSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
yihui	9:05f0b5a3a70a	1140	#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
yihui	9:05f0b5a3a70a	1141	#define GPIO_OUTSET_PIN15_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1142	#define GPIO_OUTSET_PIN15_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1143	#define GPIO_OUTSET_PIN15_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1144
yihui	9:05f0b5a3a70a	1145	/* Bit 14 : Pin 14. */
yihui	9:05f0b5a3a70a	1146	#define GPIO_OUTSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
yihui	9:05f0b5a3a70a	1147	#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
yihui	9:05f0b5a3a70a	1148	#define GPIO_OUTSET_PIN14_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1149	#define GPIO_OUTSET_PIN14_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1150	#define GPIO_OUTSET_PIN14_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1151
yihui	9:05f0b5a3a70a	1152	/* Bit 13 : Pin 13. */
yihui	9:05f0b5a3a70a	1153	#define GPIO_OUTSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
yihui	9:05f0b5a3a70a	1154	#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
yihui	9:05f0b5a3a70a	1155	#define GPIO_OUTSET_PIN13_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1156	#define GPIO_OUTSET_PIN13_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1157	#define GPIO_OUTSET_PIN13_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1158
yihui	9:05f0b5a3a70a	1159	/* Bit 12 : Pin 12. */
yihui	9:05f0b5a3a70a	1160	#define GPIO_OUTSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
yihui	9:05f0b5a3a70a	1161	#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
yihui	9:05f0b5a3a70a	1162	#define GPIO_OUTSET_PIN12_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1163	#define GPIO_OUTSET_PIN12_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1164	#define GPIO_OUTSET_PIN12_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1165
yihui	9:05f0b5a3a70a	1166	/* Bit 11 : Pin 11. */
yihui	9:05f0b5a3a70a	1167	#define GPIO_OUTSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
yihui	9:05f0b5a3a70a	1168	#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
yihui	9:05f0b5a3a70a	1169	#define GPIO_OUTSET_PIN11_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1170	#define GPIO_OUTSET_PIN11_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1171	#define GPIO_OUTSET_PIN11_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1172
yihui	9:05f0b5a3a70a	1173	/* Bit 10 : Pin 10. */
yihui	9:05f0b5a3a70a	1174	#define GPIO_OUTSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
yihui	9:05f0b5a3a70a	1175	#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
yihui	9:05f0b5a3a70a	1176	#define GPIO_OUTSET_PIN10_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1177	#define GPIO_OUTSET_PIN10_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1178	#define GPIO_OUTSET_PIN10_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1179
yihui	9:05f0b5a3a70a	1180	/* Bit 9 : Pin 9. */
yihui	9:05f0b5a3a70a	1181	#define GPIO_OUTSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
yihui	9:05f0b5a3a70a	1182	#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
yihui	9:05f0b5a3a70a	1183	#define GPIO_OUTSET_PIN9_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1184	#define GPIO_OUTSET_PIN9_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1185	#define GPIO_OUTSET_PIN9_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1186
yihui	9:05f0b5a3a70a	1187	/* Bit 8 : Pin 8. */
yihui	9:05f0b5a3a70a	1188	#define GPIO_OUTSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
yihui	9:05f0b5a3a70a	1189	#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
yihui	9:05f0b5a3a70a	1190	#define GPIO_OUTSET_PIN8_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1191	#define GPIO_OUTSET_PIN8_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1192	#define GPIO_OUTSET_PIN8_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1193
yihui	9:05f0b5a3a70a	1194	/* Bit 7 : Pin 7. */
yihui	9:05f0b5a3a70a	1195	#define GPIO_OUTSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
yihui	9:05f0b5a3a70a	1196	#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
yihui	9:05f0b5a3a70a	1197	#define GPIO_OUTSET_PIN7_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1198	#define GPIO_OUTSET_PIN7_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1199	#define GPIO_OUTSET_PIN7_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1200
yihui	9:05f0b5a3a70a	1201	/* Bit 6 : Pin 6. */
yihui	9:05f0b5a3a70a	1202	#define GPIO_OUTSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
yihui	9:05f0b5a3a70a	1203	#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
yihui	9:05f0b5a3a70a	1204	#define GPIO_OUTSET_PIN6_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1205	#define GPIO_OUTSET_PIN6_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1206	#define GPIO_OUTSET_PIN6_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1207
yihui	9:05f0b5a3a70a	1208	/* Bit 5 : Pin 5. */
yihui	9:05f0b5a3a70a	1209	#define GPIO_OUTSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
yihui	9:05f0b5a3a70a	1210	#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
yihui	9:05f0b5a3a70a	1211	#define GPIO_OUTSET_PIN5_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1212	#define GPIO_OUTSET_PIN5_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1213	#define GPIO_OUTSET_PIN5_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1214
yihui	9:05f0b5a3a70a	1215	/* Bit 4 : Pin 4. */
yihui	9:05f0b5a3a70a	1216	#define GPIO_OUTSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
yihui	9:05f0b5a3a70a	1217	#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
yihui	9:05f0b5a3a70a	1218	#define GPIO_OUTSET_PIN4_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1219	#define GPIO_OUTSET_PIN4_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1220	#define GPIO_OUTSET_PIN4_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1221
yihui	9:05f0b5a3a70a	1222	/* Bit 3 : Pin 3. */
yihui	9:05f0b5a3a70a	1223	#define GPIO_OUTSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
yihui	9:05f0b5a3a70a	1224	#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
yihui	9:05f0b5a3a70a	1225	#define GPIO_OUTSET_PIN3_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1226	#define GPIO_OUTSET_PIN3_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1227	#define GPIO_OUTSET_PIN3_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1228
yihui	9:05f0b5a3a70a	1229	/* Bit 2 : Pin 2. */
yihui	9:05f0b5a3a70a	1230	#define GPIO_OUTSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
yihui	9:05f0b5a3a70a	1231	#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
yihui	9:05f0b5a3a70a	1232	#define GPIO_OUTSET_PIN2_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1233	#define GPIO_OUTSET_PIN2_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1234	#define GPIO_OUTSET_PIN2_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1235
yihui	9:05f0b5a3a70a	1236	/* Bit 1 : Pin 1. */
yihui	9:05f0b5a3a70a	1237	#define GPIO_OUTSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
yihui	9:05f0b5a3a70a	1238	#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
yihui	9:05f0b5a3a70a	1239	#define GPIO_OUTSET_PIN1_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1240	#define GPIO_OUTSET_PIN1_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1241	#define GPIO_OUTSET_PIN1_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1242
yihui	9:05f0b5a3a70a	1243	/* Bit 0 : Pin 0. */
yihui	9:05f0b5a3a70a	1244	#define GPIO_OUTSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
yihui	9:05f0b5a3a70a	1245	#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
yihui	9:05f0b5a3a70a	1246	#define GPIO_OUTSET_PIN0_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1247	#define GPIO_OUTSET_PIN0_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1248	#define GPIO_OUTSET_PIN0_Set (1UL) /!< Set pin driver high. /
yihui	9:05f0b5a3a70a	1249
yihui	9:05f0b5a3a70a	1250	/* Register: GPIO_OUTCLR */
yihui	9:05f0b5a3a70a	1251	/* Description: Clear individual bits in GPIO port. */
yihui	9:05f0b5a3a70a	1252
yihui	9:05f0b5a3a70a	1253	/* Bit 31 : Pin 31. */
yihui	9:05f0b5a3a70a	1254	#define GPIO_OUTCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
yihui	9:05f0b5a3a70a	1255	#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
yihui	9:05f0b5a3a70a	1256	#define GPIO_OUTCLR_PIN31_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1257	#define GPIO_OUTCLR_PIN31_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1258	#define GPIO_OUTCLR_PIN31_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1259
yihui	9:05f0b5a3a70a	1260	/* Bit 30 : Pin 30. */
yihui	9:05f0b5a3a70a	1261	#define GPIO_OUTCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
yihui	9:05f0b5a3a70a	1262	#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
yihui	9:05f0b5a3a70a	1263	#define GPIO_OUTCLR_PIN30_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1264	#define GPIO_OUTCLR_PIN30_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1265	#define GPIO_OUTCLR_PIN30_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1266
yihui	9:05f0b5a3a70a	1267	/* Bit 29 : Pin 29. */
yihui	9:05f0b5a3a70a	1268	#define GPIO_OUTCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
yihui	9:05f0b5a3a70a	1269	#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
yihui	9:05f0b5a3a70a	1270	#define GPIO_OUTCLR_PIN29_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1271	#define GPIO_OUTCLR_PIN29_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1272	#define GPIO_OUTCLR_PIN29_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1273
yihui	9:05f0b5a3a70a	1274	/* Bit 28 : Pin 28. */
yihui	9:05f0b5a3a70a	1275	#define GPIO_OUTCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
yihui	9:05f0b5a3a70a	1276	#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
yihui	9:05f0b5a3a70a	1277	#define GPIO_OUTCLR_PIN28_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1278	#define GPIO_OUTCLR_PIN28_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1279	#define GPIO_OUTCLR_PIN28_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1280
yihui	9:05f0b5a3a70a	1281	/* Bit 27 : Pin 27. */
yihui	9:05f0b5a3a70a	1282	#define GPIO_OUTCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
yihui	9:05f0b5a3a70a	1283	#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
yihui	9:05f0b5a3a70a	1284	#define GPIO_OUTCLR_PIN27_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1285	#define GPIO_OUTCLR_PIN27_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1286	#define GPIO_OUTCLR_PIN27_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1287
yihui	9:05f0b5a3a70a	1288	/* Bit 26 : Pin 26. */
yihui	9:05f0b5a3a70a	1289	#define GPIO_OUTCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
yihui	9:05f0b5a3a70a	1290	#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
yihui	9:05f0b5a3a70a	1291	#define GPIO_OUTCLR_PIN26_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1292	#define GPIO_OUTCLR_PIN26_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1293	#define GPIO_OUTCLR_PIN26_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1294
yihui	9:05f0b5a3a70a	1295	/* Bit 25 : Pin 25. */
yihui	9:05f0b5a3a70a	1296	#define GPIO_OUTCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
yihui	9:05f0b5a3a70a	1297	#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
yihui	9:05f0b5a3a70a	1298	#define GPIO_OUTCLR_PIN25_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1299	#define GPIO_OUTCLR_PIN25_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1300	#define GPIO_OUTCLR_PIN25_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1301
yihui	9:05f0b5a3a70a	1302	/* Bit 24 : Pin 24. */
yihui	9:05f0b5a3a70a	1303	#define GPIO_OUTCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
yihui	9:05f0b5a3a70a	1304	#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
yihui	9:05f0b5a3a70a	1305	#define GPIO_OUTCLR_PIN24_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1306	#define GPIO_OUTCLR_PIN24_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1307	#define GPIO_OUTCLR_PIN24_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1308
yihui	9:05f0b5a3a70a	1309	/* Bit 23 : Pin 23. */
yihui	9:05f0b5a3a70a	1310	#define GPIO_OUTCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
yihui	9:05f0b5a3a70a	1311	#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
yihui	9:05f0b5a3a70a	1312	#define GPIO_OUTCLR_PIN23_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1313	#define GPIO_OUTCLR_PIN23_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1314	#define GPIO_OUTCLR_PIN23_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1315
yihui	9:05f0b5a3a70a	1316	/* Bit 22 : Pin 22. */
yihui	9:05f0b5a3a70a	1317	#define GPIO_OUTCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
yihui	9:05f0b5a3a70a	1318	#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
yihui	9:05f0b5a3a70a	1319	#define GPIO_OUTCLR_PIN22_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1320	#define GPIO_OUTCLR_PIN22_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1321	#define GPIO_OUTCLR_PIN22_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1322
yihui	9:05f0b5a3a70a	1323	/* Bit 21 : Pin 21. */
yihui	9:05f0b5a3a70a	1324	#define GPIO_OUTCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
yihui	9:05f0b5a3a70a	1325	#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
yihui	9:05f0b5a3a70a	1326	#define GPIO_OUTCLR_PIN21_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1327	#define GPIO_OUTCLR_PIN21_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1328	#define GPIO_OUTCLR_PIN21_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1329
yihui	9:05f0b5a3a70a	1330	/* Bit 20 : Pin 20. */
yihui	9:05f0b5a3a70a	1331	#define GPIO_OUTCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
yihui	9:05f0b5a3a70a	1332	#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
yihui	9:05f0b5a3a70a	1333	#define GPIO_OUTCLR_PIN20_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1334	#define GPIO_OUTCLR_PIN20_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1335	#define GPIO_OUTCLR_PIN20_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1336
yihui	9:05f0b5a3a70a	1337	/* Bit 19 : Pin 19. */
yihui	9:05f0b5a3a70a	1338	#define GPIO_OUTCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
yihui	9:05f0b5a3a70a	1339	#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
yihui	9:05f0b5a3a70a	1340	#define GPIO_OUTCLR_PIN19_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1341	#define GPIO_OUTCLR_PIN19_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1342	#define GPIO_OUTCLR_PIN19_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1343
yihui	9:05f0b5a3a70a	1344	/* Bit 18 : Pin 18. */
yihui	9:05f0b5a3a70a	1345	#define GPIO_OUTCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
yihui	9:05f0b5a3a70a	1346	#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
yihui	9:05f0b5a3a70a	1347	#define GPIO_OUTCLR_PIN18_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1348	#define GPIO_OUTCLR_PIN18_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1349	#define GPIO_OUTCLR_PIN18_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1350
yihui	9:05f0b5a3a70a	1351	/* Bit 17 : Pin 17. */
yihui	9:05f0b5a3a70a	1352	#define GPIO_OUTCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
yihui	9:05f0b5a3a70a	1353	#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
yihui	9:05f0b5a3a70a	1354	#define GPIO_OUTCLR_PIN17_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1355	#define GPIO_OUTCLR_PIN17_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1356	#define GPIO_OUTCLR_PIN17_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1357
yihui	9:05f0b5a3a70a	1358	/* Bit 16 : Pin 16. */
yihui	9:05f0b5a3a70a	1359	#define GPIO_OUTCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
yihui	9:05f0b5a3a70a	1360	#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
yihui	9:05f0b5a3a70a	1361	#define GPIO_OUTCLR_PIN16_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1362	#define GPIO_OUTCLR_PIN16_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1363	#define GPIO_OUTCLR_PIN16_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1364
yihui	9:05f0b5a3a70a	1365	/* Bit 15 : Pin 15. */
yihui	9:05f0b5a3a70a	1366	#define GPIO_OUTCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
yihui	9:05f0b5a3a70a	1367	#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
yihui	9:05f0b5a3a70a	1368	#define GPIO_OUTCLR_PIN15_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1369	#define GPIO_OUTCLR_PIN15_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1370	#define GPIO_OUTCLR_PIN15_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1371
yihui	9:05f0b5a3a70a	1372	/* Bit 14 : Pin 14. */
yihui	9:05f0b5a3a70a	1373	#define GPIO_OUTCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
yihui	9:05f0b5a3a70a	1374	#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
yihui	9:05f0b5a3a70a	1375	#define GPIO_OUTCLR_PIN14_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1376	#define GPIO_OUTCLR_PIN14_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1377	#define GPIO_OUTCLR_PIN14_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1378
yihui	9:05f0b5a3a70a	1379	/* Bit 13 : Pin 13. */
yihui	9:05f0b5a3a70a	1380	#define GPIO_OUTCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
yihui	9:05f0b5a3a70a	1381	#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
yihui	9:05f0b5a3a70a	1382	#define GPIO_OUTCLR_PIN13_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1383	#define GPIO_OUTCLR_PIN13_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1384	#define GPIO_OUTCLR_PIN13_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1385
yihui	9:05f0b5a3a70a	1386	/* Bit 12 : Pin 12. */
yihui	9:05f0b5a3a70a	1387	#define GPIO_OUTCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
yihui	9:05f0b5a3a70a	1388	#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
yihui	9:05f0b5a3a70a	1389	#define GPIO_OUTCLR_PIN12_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1390	#define GPIO_OUTCLR_PIN12_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1391	#define GPIO_OUTCLR_PIN12_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1392
yihui	9:05f0b5a3a70a	1393	/* Bit 11 : Pin 11. */
yihui	9:05f0b5a3a70a	1394	#define GPIO_OUTCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
yihui	9:05f0b5a3a70a	1395	#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
yihui	9:05f0b5a3a70a	1396	#define GPIO_OUTCLR_PIN11_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1397	#define GPIO_OUTCLR_PIN11_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1398	#define GPIO_OUTCLR_PIN11_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1399
yihui	9:05f0b5a3a70a	1400	/* Bit 10 : Pin 10. */
yihui	9:05f0b5a3a70a	1401	#define GPIO_OUTCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
yihui	9:05f0b5a3a70a	1402	#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
yihui	9:05f0b5a3a70a	1403	#define GPIO_OUTCLR_PIN10_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1404	#define GPIO_OUTCLR_PIN10_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1405	#define GPIO_OUTCLR_PIN10_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1406
yihui	9:05f0b5a3a70a	1407	/* Bit 9 : Pin 9. */
yihui	9:05f0b5a3a70a	1408	#define GPIO_OUTCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
yihui	9:05f0b5a3a70a	1409	#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
yihui	9:05f0b5a3a70a	1410	#define GPIO_OUTCLR_PIN9_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1411	#define GPIO_OUTCLR_PIN9_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1412	#define GPIO_OUTCLR_PIN9_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1413
yihui	9:05f0b5a3a70a	1414	/* Bit 8 : Pin 8. */
yihui	9:05f0b5a3a70a	1415	#define GPIO_OUTCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
yihui	9:05f0b5a3a70a	1416	#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
yihui	9:05f0b5a3a70a	1417	#define GPIO_OUTCLR_PIN8_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1418	#define GPIO_OUTCLR_PIN8_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1419	#define GPIO_OUTCLR_PIN8_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1420
yihui	9:05f0b5a3a70a	1421	/* Bit 7 : Pin 7. */
yihui	9:05f0b5a3a70a	1422	#define GPIO_OUTCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
yihui	9:05f0b5a3a70a	1423	#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
yihui	9:05f0b5a3a70a	1424	#define GPIO_OUTCLR_PIN7_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1425	#define GPIO_OUTCLR_PIN7_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1426	#define GPIO_OUTCLR_PIN7_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1427
yihui	9:05f0b5a3a70a	1428	/* Bit 6 : Pin 6. */
yihui	9:05f0b5a3a70a	1429	#define GPIO_OUTCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
yihui	9:05f0b5a3a70a	1430	#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
yihui	9:05f0b5a3a70a	1431	#define GPIO_OUTCLR_PIN6_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1432	#define GPIO_OUTCLR_PIN6_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1433	#define GPIO_OUTCLR_PIN6_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1434
yihui	9:05f0b5a3a70a	1435	/* Bit 5 : Pin 5. */
yihui	9:05f0b5a3a70a	1436	#define GPIO_OUTCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
yihui	9:05f0b5a3a70a	1437	#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
yihui	9:05f0b5a3a70a	1438	#define GPIO_OUTCLR_PIN5_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1439	#define GPIO_OUTCLR_PIN5_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1440	#define GPIO_OUTCLR_PIN5_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1441
yihui	9:05f0b5a3a70a	1442	/* Bit 4 : Pin 4. */
yihui	9:05f0b5a3a70a	1443	#define GPIO_OUTCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
yihui	9:05f0b5a3a70a	1444	#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
yihui	9:05f0b5a3a70a	1445	#define GPIO_OUTCLR_PIN4_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1446	#define GPIO_OUTCLR_PIN4_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1447	#define GPIO_OUTCLR_PIN4_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1448
yihui	9:05f0b5a3a70a	1449	/* Bit 3 : Pin 3. */
yihui	9:05f0b5a3a70a	1450	#define GPIO_OUTCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
yihui	9:05f0b5a3a70a	1451	#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
yihui	9:05f0b5a3a70a	1452	#define GPIO_OUTCLR_PIN3_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1453	#define GPIO_OUTCLR_PIN3_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1454	#define GPIO_OUTCLR_PIN3_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1455
yihui	9:05f0b5a3a70a	1456	/* Bit 2 : Pin 2. */
yihui	9:05f0b5a3a70a	1457	#define GPIO_OUTCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
yihui	9:05f0b5a3a70a	1458	#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
yihui	9:05f0b5a3a70a	1459	#define GPIO_OUTCLR_PIN2_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1460	#define GPIO_OUTCLR_PIN2_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1461	#define GPIO_OUTCLR_PIN2_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1462
yihui	9:05f0b5a3a70a	1463	/* Bit 1 : Pin 1. */
yihui	9:05f0b5a3a70a	1464	#define GPIO_OUTCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
yihui	9:05f0b5a3a70a	1465	#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
yihui	9:05f0b5a3a70a	1466	#define GPIO_OUTCLR_PIN1_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1467	#define GPIO_OUTCLR_PIN1_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1468	#define GPIO_OUTCLR_PIN1_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1469
yihui	9:05f0b5a3a70a	1470	/* Bit 0 : Pin 0. */
yihui	9:05f0b5a3a70a	1471	#define GPIO_OUTCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
yihui	9:05f0b5a3a70a	1472	#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
yihui	9:05f0b5a3a70a	1473	#define GPIO_OUTCLR_PIN0_Low (0UL) /!< Pin driver is low. /
yihui	9:05f0b5a3a70a	1474	#define GPIO_OUTCLR_PIN0_High (1UL) /!< Pin driver is high. /
yihui	9:05f0b5a3a70a	1475	#define GPIO_OUTCLR_PIN0_Clear (1UL) /!< Set pin driver low. /
yihui	9:05f0b5a3a70a	1476
yihui	9:05f0b5a3a70a	1477	/* Register: GPIO_IN */
yihui	9:05f0b5a3a70a	1478	/* Description: Read GPIO port. */
yihui	9:05f0b5a3a70a	1479
yihui	9:05f0b5a3a70a	1480	/* Bit 31 : Pin 31. */
yihui	9:05f0b5a3a70a	1481	#define GPIO_IN_PIN31_Pos (31UL) /!< Position of PIN31 field. /
yihui	9:05f0b5a3a70a	1482	#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /!< Bit mask of PIN31 field. /
yihui	9:05f0b5a3a70a	1483	#define GPIO_IN_PIN31_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1484	#define GPIO_IN_PIN31_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1485
yihui	9:05f0b5a3a70a	1486	/* Bit 30 : Pin 30. */
yihui	9:05f0b5a3a70a	1487	#define GPIO_IN_PIN30_Pos (30UL) /!< Position of PIN30 field. /
yihui	9:05f0b5a3a70a	1488	#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /!< Bit mask of PIN30 field. /
yihui	9:05f0b5a3a70a	1489	#define GPIO_IN_PIN30_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1490	#define GPIO_IN_PIN30_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1491
yihui	9:05f0b5a3a70a	1492	/* Bit 29 : Pin 29. */
yihui	9:05f0b5a3a70a	1493	#define GPIO_IN_PIN29_Pos (29UL) /!< Position of PIN29 field. /
yihui	9:05f0b5a3a70a	1494	#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /!< Bit mask of PIN29 field. /
yihui	9:05f0b5a3a70a	1495	#define GPIO_IN_PIN29_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1496	#define GPIO_IN_PIN29_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1497
yihui	9:05f0b5a3a70a	1498	/* Bit 28 : Pin 28. */
yihui	9:05f0b5a3a70a	1499	#define GPIO_IN_PIN28_Pos (28UL) /!< Position of PIN28 field. /
yihui	9:05f0b5a3a70a	1500	#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /!< Bit mask of PIN28 field. /
yihui	9:05f0b5a3a70a	1501	#define GPIO_IN_PIN28_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1502	#define GPIO_IN_PIN28_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1503
yihui	9:05f0b5a3a70a	1504	/* Bit 27 : Pin 27. */
yihui	9:05f0b5a3a70a	1505	#define GPIO_IN_PIN27_Pos (27UL) /!< Position of PIN27 field. /
yihui	9:05f0b5a3a70a	1506	#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /!< Bit mask of PIN27 field. /
yihui	9:05f0b5a3a70a	1507	#define GPIO_IN_PIN27_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1508	#define GPIO_IN_PIN27_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1509
yihui	9:05f0b5a3a70a	1510	/* Bit 26 : Pin 26. */
yihui	9:05f0b5a3a70a	1511	#define GPIO_IN_PIN26_Pos (26UL) /!< Position of PIN26 field. /
yihui	9:05f0b5a3a70a	1512	#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /!< Bit mask of PIN26 field. /
yihui	9:05f0b5a3a70a	1513	#define GPIO_IN_PIN26_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1514	#define GPIO_IN_PIN26_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1515
yihui	9:05f0b5a3a70a	1516	/* Bit 25 : Pin 25. */
yihui	9:05f0b5a3a70a	1517	#define GPIO_IN_PIN25_Pos (25UL) /!< Position of PIN25 field. /
yihui	9:05f0b5a3a70a	1518	#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /!< Bit mask of PIN25 field. /
yihui	9:05f0b5a3a70a	1519	#define GPIO_IN_PIN25_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1520	#define GPIO_IN_PIN25_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1521
yihui	9:05f0b5a3a70a	1522	/* Bit 24 : Pin 24. */
yihui	9:05f0b5a3a70a	1523	#define GPIO_IN_PIN24_Pos (24UL) /!< Position of PIN24 field. /
yihui	9:05f0b5a3a70a	1524	#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /!< Bit mask of PIN24 field. /
yihui	9:05f0b5a3a70a	1525	#define GPIO_IN_PIN24_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1526	#define GPIO_IN_PIN24_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1527
yihui	9:05f0b5a3a70a	1528	/* Bit 23 : Pin 23. */
yihui	9:05f0b5a3a70a	1529	#define GPIO_IN_PIN23_Pos (23UL) /!< Position of PIN23 field. /
yihui	9:05f0b5a3a70a	1530	#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /!< Bit mask of PIN23 field. /
yihui	9:05f0b5a3a70a	1531	#define GPIO_IN_PIN23_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1532	#define GPIO_IN_PIN23_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1533
yihui	9:05f0b5a3a70a	1534	/* Bit 22 : Pin 22. */
yihui	9:05f0b5a3a70a	1535	#define GPIO_IN_PIN22_Pos (22UL) /!< Position of PIN22 field. /
yihui	9:05f0b5a3a70a	1536	#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /!< Bit mask of PIN22 field. /
yihui	9:05f0b5a3a70a	1537	#define GPIO_IN_PIN22_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1538	#define GPIO_IN_PIN22_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1539
yihui	9:05f0b5a3a70a	1540	/* Bit 21 : Pin 21. */
yihui	9:05f0b5a3a70a	1541	#define GPIO_IN_PIN21_Pos (21UL) /!< Position of PIN21 field. /
yihui	9:05f0b5a3a70a	1542	#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /!< Bit mask of PIN21 field. /
yihui	9:05f0b5a3a70a	1543	#define GPIO_IN_PIN21_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1544	#define GPIO_IN_PIN21_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1545
yihui	9:05f0b5a3a70a	1546	/* Bit 20 : Pin 20. */
yihui	9:05f0b5a3a70a	1547	#define GPIO_IN_PIN20_Pos (20UL) /!< Position of PIN20 field. /
yihui	9:05f0b5a3a70a	1548	#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /!< Bit mask of PIN20 field. /
yihui	9:05f0b5a3a70a	1549	#define GPIO_IN_PIN20_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1550	#define GPIO_IN_PIN20_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1551
yihui	9:05f0b5a3a70a	1552	/* Bit 19 : Pin 19. */
yihui	9:05f0b5a3a70a	1553	#define GPIO_IN_PIN19_Pos (19UL) /!< Position of PIN19 field. /
yihui	9:05f0b5a3a70a	1554	#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /!< Bit mask of PIN19 field. /
yihui	9:05f0b5a3a70a	1555	#define GPIO_IN_PIN19_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1556	#define GPIO_IN_PIN19_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1557
yihui	9:05f0b5a3a70a	1558	/* Bit 18 : Pin 18. */
yihui	9:05f0b5a3a70a	1559	#define GPIO_IN_PIN18_Pos (18UL) /!< Position of PIN18 field. /
yihui	9:05f0b5a3a70a	1560	#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /!< Bit mask of PIN18 field. /
yihui	9:05f0b5a3a70a	1561	#define GPIO_IN_PIN18_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1562	#define GPIO_IN_PIN18_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1563
yihui	9:05f0b5a3a70a	1564	/* Bit 17 : Pin 17. */
yihui	9:05f0b5a3a70a	1565	#define GPIO_IN_PIN17_Pos (17UL) /!< Position of PIN17 field. /
yihui	9:05f0b5a3a70a	1566	#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /!< Bit mask of PIN17 field. /
yihui	9:05f0b5a3a70a	1567	#define GPIO_IN_PIN17_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1568	#define GPIO_IN_PIN17_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1569
yihui	9:05f0b5a3a70a	1570	/* Bit 16 : Pin 16. */
yihui	9:05f0b5a3a70a	1571	#define GPIO_IN_PIN16_Pos (16UL) /!< Position of PIN16 field. /
yihui	9:05f0b5a3a70a	1572	#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /!< Bit mask of PIN16 field. /
yihui	9:05f0b5a3a70a	1573	#define GPIO_IN_PIN16_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1574	#define GPIO_IN_PIN16_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1575
yihui	9:05f0b5a3a70a	1576	/* Bit 15 : Pin 15. */
yihui	9:05f0b5a3a70a	1577	#define GPIO_IN_PIN15_Pos (15UL) /!< Position of PIN15 field. /
yihui	9:05f0b5a3a70a	1578	#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /!< Bit mask of PIN15 field. /
yihui	9:05f0b5a3a70a	1579	#define GPIO_IN_PIN15_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1580	#define GPIO_IN_PIN15_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1581
yihui	9:05f0b5a3a70a	1582	/* Bit 14 : Pin 14. */
yihui	9:05f0b5a3a70a	1583	#define GPIO_IN_PIN14_Pos (14UL) /!< Position of PIN14 field. /
yihui	9:05f0b5a3a70a	1584	#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /!< Bit mask of PIN14 field. /
yihui	9:05f0b5a3a70a	1585	#define GPIO_IN_PIN14_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1586	#define GPIO_IN_PIN14_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1587
yihui	9:05f0b5a3a70a	1588	/* Bit 13 : Pin 13. */
yihui	9:05f0b5a3a70a	1589	#define GPIO_IN_PIN13_Pos (13UL) /!< Position of PIN13 field. /
yihui	9:05f0b5a3a70a	1590	#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /!< Bit mask of PIN13 field. /
yihui	9:05f0b5a3a70a	1591	#define GPIO_IN_PIN13_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1592	#define GPIO_IN_PIN13_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1593
yihui	9:05f0b5a3a70a	1594	/* Bit 12 : Pin 12. */
yihui	9:05f0b5a3a70a	1595	#define GPIO_IN_PIN12_Pos (12UL) /!< Position of PIN12 field. /
yihui	9:05f0b5a3a70a	1596	#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /!< Bit mask of PIN12 field. /
yihui	9:05f0b5a3a70a	1597	#define GPIO_IN_PIN12_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1598	#define GPIO_IN_PIN12_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1599
yihui	9:05f0b5a3a70a	1600	/* Bit 11 : Pin 11. */
yihui	9:05f0b5a3a70a	1601	#define GPIO_IN_PIN11_Pos (11UL) /!< Position of PIN11 field. /
yihui	9:05f0b5a3a70a	1602	#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /!< Bit mask of PIN11 field. /
yihui	9:05f0b5a3a70a	1603	#define GPIO_IN_PIN11_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1604	#define GPIO_IN_PIN11_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1605
yihui	9:05f0b5a3a70a	1606	/* Bit 10 : Pin 10. */
yihui	9:05f0b5a3a70a	1607	#define GPIO_IN_PIN10_Pos (10UL) /!< Position of PIN10 field. /
yihui	9:05f0b5a3a70a	1608	#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /!< Bit mask of PIN10 field. /
yihui	9:05f0b5a3a70a	1609	#define GPIO_IN_PIN10_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1610	#define GPIO_IN_PIN10_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1611
yihui	9:05f0b5a3a70a	1612	/* Bit 9 : Pin 9. */
yihui	9:05f0b5a3a70a	1613	#define GPIO_IN_PIN9_Pos (9UL) /!< Position of PIN9 field. /
yihui	9:05f0b5a3a70a	1614	#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /!< Bit mask of PIN9 field. /
yihui	9:05f0b5a3a70a	1615	#define GPIO_IN_PIN9_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1616	#define GPIO_IN_PIN9_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1617
yihui	9:05f0b5a3a70a	1618	/* Bit 8 : Pin 8. */
yihui	9:05f0b5a3a70a	1619	#define GPIO_IN_PIN8_Pos (8UL) /!< Position of PIN8 field. /
yihui	9:05f0b5a3a70a	1620	#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /!< Bit mask of PIN8 field. /
yihui	9:05f0b5a3a70a	1621	#define GPIO_IN_PIN8_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1622	#define GPIO_IN_PIN8_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1623
yihui	9:05f0b5a3a70a	1624	/* Bit 7 : Pin 7. */
yihui	9:05f0b5a3a70a	1625	#define GPIO_IN_PIN7_Pos (7UL) /!< Position of PIN7 field. /
yihui	9:05f0b5a3a70a	1626	#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /!< Bit mask of PIN7 field. /
yihui	9:05f0b5a3a70a	1627	#define GPIO_IN_PIN7_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1628	#define GPIO_IN_PIN7_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1629
yihui	9:05f0b5a3a70a	1630	/* Bit 6 : Pin 6. */
yihui	9:05f0b5a3a70a	1631	#define GPIO_IN_PIN6_Pos (6UL) /!< Position of PIN6 field. /
yihui	9:05f0b5a3a70a	1632	#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /!< Bit mask of PIN6 field. /
yihui	9:05f0b5a3a70a	1633	#define GPIO_IN_PIN6_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1634	#define GPIO_IN_PIN6_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1635
yihui	9:05f0b5a3a70a	1636	/* Bit 5 : Pin 5. */
yihui	9:05f0b5a3a70a	1637	#define GPIO_IN_PIN5_Pos (5UL) /!< Position of PIN5 field. /
yihui	9:05f0b5a3a70a	1638	#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /!< Bit mask of PIN5 field. /
yihui	9:05f0b5a3a70a	1639	#define GPIO_IN_PIN5_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1640	#define GPIO_IN_PIN5_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1641
yihui	9:05f0b5a3a70a	1642	/* Bit 4 : Pin 4. */
yihui	9:05f0b5a3a70a	1643	#define GPIO_IN_PIN4_Pos (4UL) /!< Position of PIN4 field. /
yihui	9:05f0b5a3a70a	1644	#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /!< Bit mask of PIN4 field. /
yihui	9:05f0b5a3a70a	1645	#define GPIO_IN_PIN4_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1646	#define GPIO_IN_PIN4_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1647
yihui	9:05f0b5a3a70a	1648	/* Bit 3 : Pin 3. */
yihui	9:05f0b5a3a70a	1649	#define GPIO_IN_PIN3_Pos (3UL) /!< Position of PIN3 field. /
yihui	9:05f0b5a3a70a	1650	#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /!< Bit mask of PIN3 field. /
yihui	9:05f0b5a3a70a	1651	#define GPIO_IN_PIN3_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1652	#define GPIO_IN_PIN3_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1653
yihui	9:05f0b5a3a70a	1654	/* Bit 2 : Pin 2. */
yihui	9:05f0b5a3a70a	1655	#define GPIO_IN_PIN2_Pos (2UL) /!< Position of PIN2 field. /
yihui	9:05f0b5a3a70a	1656	#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /!< Bit mask of PIN2 field. /
yihui	9:05f0b5a3a70a	1657	#define GPIO_IN_PIN2_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1658	#define GPIO_IN_PIN2_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1659
yihui	9:05f0b5a3a70a	1660	/* Bit 1 : Pin 1. */
yihui	9:05f0b5a3a70a	1661	#define GPIO_IN_PIN1_Pos (1UL) /!< Position of PIN1 field. /
yihui	9:05f0b5a3a70a	1662	#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /!< Bit mask of PIN1 field. /
yihui	9:05f0b5a3a70a	1663	#define GPIO_IN_PIN1_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1664	#define GPIO_IN_PIN1_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1665
yihui	9:05f0b5a3a70a	1666	/* Bit 0 : Pin 0. */
yihui	9:05f0b5a3a70a	1667	#define GPIO_IN_PIN0_Pos (0UL) /!< Position of PIN0 field. /
yihui	9:05f0b5a3a70a	1668	#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /!< Bit mask of PIN0 field. /
yihui	9:05f0b5a3a70a	1669	#define GPIO_IN_PIN0_Low (0UL) /!< Pin input is low. /
yihui	9:05f0b5a3a70a	1670	#define GPIO_IN_PIN0_High (1UL) /!< Pin input is high. /
yihui	9:05f0b5a3a70a	1671
yihui	9:05f0b5a3a70a	1672	/* Register: GPIO_DIR */
yihui	9:05f0b5a3a70a	1673	/* Description: Direction of GPIO pins. */
yihui	9:05f0b5a3a70a	1674
yihui	9:05f0b5a3a70a	1675	/* Bit 31 : Pin 31. */
yihui	9:05f0b5a3a70a	1676	#define GPIO_DIR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
yihui	9:05f0b5a3a70a	1677	#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /!< Bit mask of PIN31 field. /
yihui	9:05f0b5a3a70a	1678	#define GPIO_DIR_PIN31_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1679	#define GPIO_DIR_PIN31_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1680
yihui	9:05f0b5a3a70a	1681	/* Bit 30 : Pin 30. */
yihui	9:05f0b5a3a70a	1682	#define GPIO_DIR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
yihui	9:05f0b5a3a70a	1683	#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /!< Bit mask of PIN30 field. /
yihui	9:05f0b5a3a70a	1684	#define GPIO_DIR_PIN30_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1685	#define GPIO_DIR_PIN30_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1686
yihui	9:05f0b5a3a70a	1687	/* Bit 29 : Pin 29. */
yihui	9:05f0b5a3a70a	1688	#define GPIO_DIR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
yihui	9:05f0b5a3a70a	1689	#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /!< Bit mask of PIN29 field. /
yihui	9:05f0b5a3a70a	1690	#define GPIO_DIR_PIN29_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1691	#define GPIO_DIR_PIN29_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1692
yihui	9:05f0b5a3a70a	1693	/* Bit 28 : Pin 28. */
yihui	9:05f0b5a3a70a	1694	#define GPIO_DIR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
yihui	9:05f0b5a3a70a	1695	#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /!< Bit mask of PIN28 field. /
yihui	9:05f0b5a3a70a	1696	#define GPIO_DIR_PIN28_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1697	#define GPIO_DIR_PIN28_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1698
yihui	9:05f0b5a3a70a	1699	/* Bit 27 : Pin 27. */
yihui	9:05f0b5a3a70a	1700	#define GPIO_DIR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
yihui	9:05f0b5a3a70a	1701	#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /!< Bit mask of PIN27 field. /
yihui	9:05f0b5a3a70a	1702	#define GPIO_DIR_PIN27_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1703	#define GPIO_DIR_PIN27_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1704
yihui	9:05f0b5a3a70a	1705	/* Bit 26 : Pin 26. */
yihui	9:05f0b5a3a70a	1706	#define GPIO_DIR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
yihui	9:05f0b5a3a70a	1707	#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /!< Bit mask of PIN26 field. /
yihui	9:05f0b5a3a70a	1708	#define GPIO_DIR_PIN26_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1709	#define GPIO_DIR_PIN26_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1710
yihui	9:05f0b5a3a70a	1711	/* Bit 25 : Pin 25. */
yihui	9:05f0b5a3a70a	1712	#define GPIO_DIR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
yihui	9:05f0b5a3a70a	1713	#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /!< Bit mask of PIN25 field. /
yihui	9:05f0b5a3a70a	1714	#define GPIO_DIR_PIN25_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1715	#define GPIO_DIR_PIN25_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1716
yihui	9:05f0b5a3a70a	1717	/* Bit 24 : Pin 24. */
yihui	9:05f0b5a3a70a	1718	#define GPIO_DIR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
yihui	9:05f0b5a3a70a	1719	#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /!< Bit mask of PIN24 field. /
yihui	9:05f0b5a3a70a	1720	#define GPIO_DIR_PIN24_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1721	#define GPIO_DIR_PIN24_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1722
yihui	9:05f0b5a3a70a	1723	/* Bit 23 : Pin 23. */
yihui	9:05f0b5a3a70a	1724	#define GPIO_DIR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
yihui	9:05f0b5a3a70a	1725	#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /!< Bit mask of PIN23 field. /
yihui	9:05f0b5a3a70a	1726	#define GPIO_DIR_PIN23_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1727	#define GPIO_DIR_PIN23_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1728
yihui	9:05f0b5a3a70a	1729	/* Bit 22 : Pin 22. */
yihui	9:05f0b5a3a70a	1730	#define GPIO_DIR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
yihui	9:05f0b5a3a70a	1731	#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /!< Bit mask of PIN22 field. /
yihui	9:05f0b5a3a70a	1732	#define GPIO_DIR_PIN22_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1733	#define GPIO_DIR_PIN22_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1734
yihui	9:05f0b5a3a70a	1735	/* Bit 21 : Pin 21. */
yihui	9:05f0b5a3a70a	1736	#define GPIO_DIR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
yihui	9:05f0b5a3a70a	1737	#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /!< Bit mask of PIN21 field. /
yihui	9:05f0b5a3a70a	1738	#define GPIO_DIR_PIN21_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1739	#define GPIO_DIR_PIN21_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1740
yihui	9:05f0b5a3a70a	1741	/* Bit 20 : Pin 20. */
yihui	9:05f0b5a3a70a	1742	#define GPIO_DIR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
yihui	9:05f0b5a3a70a	1743	#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /!< Bit mask of PIN20 field. /
yihui	9:05f0b5a3a70a	1744	#define GPIO_DIR_PIN20_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1745	#define GPIO_DIR_PIN20_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1746
yihui	9:05f0b5a3a70a	1747	/* Bit 19 : Pin 19. */
yihui	9:05f0b5a3a70a	1748	#define GPIO_DIR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
yihui	9:05f0b5a3a70a	1749	#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /!< Bit mask of PIN19 field. /
yihui	9:05f0b5a3a70a	1750	#define GPIO_DIR_PIN19_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1751	#define GPIO_DIR_PIN19_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1752
yihui	9:05f0b5a3a70a	1753	/* Bit 18 : Pin 18. */
yihui	9:05f0b5a3a70a	1754	#define GPIO_DIR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
yihui	9:05f0b5a3a70a	1755	#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /!< Bit mask of PIN18 field. /
yihui	9:05f0b5a3a70a	1756	#define GPIO_DIR_PIN18_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1757	#define GPIO_DIR_PIN18_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1758
yihui	9:05f0b5a3a70a	1759	/* Bit 17 : Pin 17. */
yihui	9:05f0b5a3a70a	1760	#define GPIO_DIR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
yihui	9:05f0b5a3a70a	1761	#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /!< Bit mask of PIN17 field. /
yihui	9:05f0b5a3a70a	1762	#define GPIO_DIR_PIN17_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1763	#define GPIO_DIR_PIN17_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1764
yihui	9:05f0b5a3a70a	1765	/* Bit 16 : Pin 16. */
yihui	9:05f0b5a3a70a	1766	#define GPIO_DIR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
yihui	9:05f0b5a3a70a	1767	#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /!< Bit mask of PIN16 field. /
yihui	9:05f0b5a3a70a	1768	#define GPIO_DIR_PIN16_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1769	#define GPIO_DIR_PIN16_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1770
yihui	9:05f0b5a3a70a	1771	/* Bit 15 : Pin 15. */
yihui	9:05f0b5a3a70a	1772	#define GPIO_DIR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
yihui	9:05f0b5a3a70a	1773	#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /!< Bit mask of PIN15 field. /
yihui	9:05f0b5a3a70a	1774	#define GPIO_DIR_PIN15_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1775	#define GPIO_DIR_PIN15_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1776
yihui	9:05f0b5a3a70a	1777	/* Bit 14 : Pin 14. */
yihui	9:05f0b5a3a70a	1778	#define GPIO_DIR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
yihui	9:05f0b5a3a70a	1779	#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /!< Bit mask of PIN14 field. /
yihui	9:05f0b5a3a70a	1780	#define GPIO_DIR_PIN14_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1781	#define GPIO_DIR_PIN14_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1782
yihui	9:05f0b5a3a70a	1783	/* Bit 13 : Pin 13. */
yihui	9:05f0b5a3a70a	1784	#define GPIO_DIR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
yihui	9:05f0b5a3a70a	1785	#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /!< Bit mask of PIN13 field. /
yihui	9:05f0b5a3a70a	1786	#define GPIO_DIR_PIN13_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1787	#define GPIO_DIR_PIN13_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1788
yihui	9:05f0b5a3a70a	1789	/* Bit 12 : Pin 12. */
yihui	9:05f0b5a3a70a	1790	#define GPIO_DIR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
yihui	9:05f0b5a3a70a	1791	#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /!< Bit mask of PIN12 field. /
yihui	9:05f0b5a3a70a	1792	#define GPIO_DIR_PIN12_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1793	#define GPIO_DIR_PIN12_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1794
yihui	9:05f0b5a3a70a	1795	/* Bit 11 : Pin 11. */
yihui	9:05f0b5a3a70a	1796	#define GPIO_DIR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
yihui	9:05f0b5a3a70a	1797	#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /!< Bit mask of PIN11 field. /
yihui	9:05f0b5a3a70a	1798	#define GPIO_DIR_PIN11_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1799	#define GPIO_DIR_PIN11_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1800
yihui	9:05f0b5a3a70a	1801	/* Bit 10 : Pin 10. */
yihui	9:05f0b5a3a70a	1802	#define GPIO_DIR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
yihui	9:05f0b5a3a70a	1803	#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /!< Bit mask of PIN10 field. /
yihui	9:05f0b5a3a70a	1804	#define GPIO_DIR_PIN10_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1805	#define GPIO_DIR_PIN10_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1806
yihui	9:05f0b5a3a70a	1807	/* Bit 9 : Pin 9. */
yihui	9:05f0b5a3a70a	1808	#define GPIO_DIR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
yihui	9:05f0b5a3a70a	1809	#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /!< Bit mask of PIN9 field. /
yihui	9:05f0b5a3a70a	1810	#define GPIO_DIR_PIN9_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1811	#define GPIO_DIR_PIN9_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1812
yihui	9:05f0b5a3a70a	1813	/* Bit 8 : Pin 8. */
yihui	9:05f0b5a3a70a	1814	#define GPIO_DIR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
yihui	9:05f0b5a3a70a	1815	#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /!< Bit mask of PIN8 field. /
yihui	9:05f0b5a3a70a	1816	#define GPIO_DIR_PIN8_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1817	#define GPIO_DIR_PIN8_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1818
yihui	9:05f0b5a3a70a	1819	/* Bit 7 : Pin 7. */
yihui	9:05f0b5a3a70a	1820	#define GPIO_DIR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
yihui	9:05f0b5a3a70a	1821	#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /!< Bit mask of PIN7 field. /
yihui	9:05f0b5a3a70a	1822	#define GPIO_DIR_PIN7_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1823	#define GPIO_DIR_PIN7_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1824
yihui	9:05f0b5a3a70a	1825	/* Bit 6 : Pin 6. */
yihui	9:05f0b5a3a70a	1826	#define GPIO_DIR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
yihui	9:05f0b5a3a70a	1827	#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /!< Bit mask of PIN6 field. /
yihui	9:05f0b5a3a70a	1828	#define GPIO_DIR_PIN6_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1829	#define GPIO_DIR_PIN6_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1830
yihui	9:05f0b5a3a70a	1831	/* Bit 5 : Pin 5. */
yihui	9:05f0b5a3a70a	1832	#define GPIO_DIR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
yihui	9:05f0b5a3a70a	1833	#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /!< Bit mask of PIN5 field. /
yihui	9:05f0b5a3a70a	1834	#define GPIO_DIR_PIN5_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1835	#define GPIO_DIR_PIN5_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1836
yihui	9:05f0b5a3a70a	1837	/* Bit 4 : Pin 4. */
yihui	9:05f0b5a3a70a	1838	#define GPIO_DIR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
yihui	9:05f0b5a3a70a	1839	#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /!< Bit mask of PIN4 field. /
yihui	9:05f0b5a3a70a	1840	#define GPIO_DIR_PIN4_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1841	#define GPIO_DIR_PIN4_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1842
yihui	9:05f0b5a3a70a	1843	/* Bit 3 : Pin 3. */
yihui	9:05f0b5a3a70a	1844	#define GPIO_DIR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
yihui	9:05f0b5a3a70a	1845	#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /!< Bit mask of PIN3 field. /
yihui	9:05f0b5a3a70a	1846	#define GPIO_DIR_PIN3_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1847	#define GPIO_DIR_PIN3_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1848
yihui	9:05f0b5a3a70a	1849	/* Bit 2 : Pin 2. */
yihui	9:05f0b5a3a70a	1850	#define GPIO_DIR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
yihui	9:05f0b5a3a70a	1851	#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /!< Bit mask of PIN2 field. /
yihui	9:05f0b5a3a70a	1852	#define GPIO_DIR_PIN2_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1853	#define GPIO_DIR_PIN2_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1854
yihui	9:05f0b5a3a70a	1855	/* Bit 1 : Pin 1. */
yihui	9:05f0b5a3a70a	1856	#define GPIO_DIR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
yihui	9:05f0b5a3a70a	1857	#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /!< Bit mask of PIN1 field. /
yihui	9:05f0b5a3a70a	1858	#define GPIO_DIR_PIN1_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1859	#define GPIO_DIR_PIN1_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1860
yihui	9:05f0b5a3a70a	1861	/* Bit 0 : Pin 0. */
yihui	9:05f0b5a3a70a	1862	#define GPIO_DIR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
yihui	9:05f0b5a3a70a	1863	#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /!< Bit mask of PIN0 field. /
yihui	9:05f0b5a3a70a	1864	#define GPIO_DIR_PIN0_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1865	#define GPIO_DIR_PIN0_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1866
yihui	9:05f0b5a3a70a	1867	/* Register: GPIO_DIRSET */
yihui	9:05f0b5a3a70a	1868	/* Description: DIR set register. */
yihui	9:05f0b5a3a70a	1869
yihui	9:05f0b5a3a70a	1870	/* Bit 31 : Set as output pin 31. */
yihui	9:05f0b5a3a70a	1871	#define GPIO_DIRSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
yihui	9:05f0b5a3a70a	1872	#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
yihui	9:05f0b5a3a70a	1873	#define GPIO_DIRSET_PIN31_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1874	#define GPIO_DIRSET_PIN31_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1875	#define GPIO_DIRSET_PIN31_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	1876
yihui	9:05f0b5a3a70a	1877	/* Bit 30 : Set as output pin 30. */
yihui	9:05f0b5a3a70a	1878	#define GPIO_DIRSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
yihui	9:05f0b5a3a70a	1879	#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
yihui	9:05f0b5a3a70a	1880	#define GPIO_DIRSET_PIN30_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1881	#define GPIO_DIRSET_PIN30_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1882	#define GPIO_DIRSET_PIN30_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	1883
yihui	9:05f0b5a3a70a	1884	/* Bit 29 : Set as output pin 29. */
yihui	9:05f0b5a3a70a	1885	#define GPIO_DIRSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
yihui	9:05f0b5a3a70a	1886	#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
yihui	9:05f0b5a3a70a	1887	#define GPIO_DIRSET_PIN29_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1888	#define GPIO_DIRSET_PIN29_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1889	#define GPIO_DIRSET_PIN29_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	1890
yihui	9:05f0b5a3a70a	1891	/* Bit 28 : Set as output pin 28. */
yihui	9:05f0b5a3a70a	1892	#define GPIO_DIRSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
yihui	9:05f0b5a3a70a	1893	#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
yihui	9:05f0b5a3a70a	1894	#define GPIO_DIRSET_PIN28_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1895	#define GPIO_DIRSET_PIN28_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1896	#define GPIO_DIRSET_PIN28_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	1897
yihui	9:05f0b5a3a70a	1898	/* Bit 27 : Set as output pin 27. */
yihui	9:05f0b5a3a70a	1899	#define GPIO_DIRSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
yihui	9:05f0b5a3a70a	1900	#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
yihui	9:05f0b5a3a70a	1901	#define GPIO_DIRSET_PIN27_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1902	#define GPIO_DIRSET_PIN27_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1903	#define GPIO_DIRSET_PIN27_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	1904
yihui	9:05f0b5a3a70a	1905	/* Bit 26 : Set as output pin 26. */
yihui	9:05f0b5a3a70a	1906	#define GPIO_DIRSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
yihui	9:05f0b5a3a70a	1907	#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
yihui	9:05f0b5a3a70a	1908	#define GPIO_DIRSET_PIN26_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1909	#define GPIO_DIRSET_PIN26_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1910	#define GPIO_DIRSET_PIN26_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	1911
yihui	9:05f0b5a3a70a	1912	/* Bit 25 : Set as output pin 25. */
yihui	9:05f0b5a3a70a	1913	#define GPIO_DIRSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
yihui	9:05f0b5a3a70a	1914	#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
yihui	9:05f0b5a3a70a	1915	#define GPIO_DIRSET_PIN25_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1916	#define GPIO_DIRSET_PIN25_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1917	#define GPIO_DIRSET_PIN25_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	1918
yihui	9:05f0b5a3a70a	1919	/* Bit 24 : Set as output pin 24. */
yihui	9:05f0b5a3a70a	1920	#define GPIO_DIRSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
yihui	9:05f0b5a3a70a	1921	#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
yihui	9:05f0b5a3a70a	1922	#define GPIO_DIRSET_PIN24_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1923	#define GPIO_DIRSET_PIN24_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1924	#define GPIO_DIRSET_PIN24_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	1925
yihui	9:05f0b5a3a70a	1926	/* Bit 23 : Set as output pin 23. */
yihui	9:05f0b5a3a70a	1927	#define GPIO_DIRSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
yihui	9:05f0b5a3a70a	1928	#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
yihui	9:05f0b5a3a70a	1929	#define GPIO_DIRSET_PIN23_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1930	#define GPIO_DIRSET_PIN23_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1931	#define GPIO_DIRSET_PIN23_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	1932
yihui	9:05f0b5a3a70a	1933	/* Bit 22 : Set as output pin 22. */
yihui	9:05f0b5a3a70a	1934	#define GPIO_DIRSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
yihui	9:05f0b5a3a70a	1935	#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
yihui	9:05f0b5a3a70a	1936	#define GPIO_DIRSET_PIN22_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1937	#define GPIO_DIRSET_PIN22_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1938	#define GPIO_DIRSET_PIN22_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	1939
yihui	9:05f0b5a3a70a	1940	/* Bit 21 : Set as output pin 21. */
yihui	9:05f0b5a3a70a	1941	#define GPIO_DIRSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
yihui	9:05f0b5a3a70a	1942	#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
yihui	9:05f0b5a3a70a	1943	#define GPIO_DIRSET_PIN21_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1944	#define GPIO_DIRSET_PIN21_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1945	#define GPIO_DIRSET_PIN21_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	1946
yihui	9:05f0b5a3a70a	1947	/* Bit 20 : Set as output pin 20. */
yihui	9:05f0b5a3a70a	1948	#define GPIO_DIRSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
yihui	9:05f0b5a3a70a	1949	#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
yihui	9:05f0b5a3a70a	1950	#define GPIO_DIRSET_PIN20_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1951	#define GPIO_DIRSET_PIN20_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1952	#define GPIO_DIRSET_PIN20_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	1953
yihui	9:05f0b5a3a70a	1954	/* Bit 19 : Set as output pin 19. */
yihui	9:05f0b5a3a70a	1955	#define GPIO_DIRSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
yihui	9:05f0b5a3a70a	1956	#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
yihui	9:05f0b5a3a70a	1957	#define GPIO_DIRSET_PIN19_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1958	#define GPIO_DIRSET_PIN19_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1959	#define GPIO_DIRSET_PIN19_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	1960
yihui	9:05f0b5a3a70a	1961	/* Bit 18 : Set as output pin 18. */
yihui	9:05f0b5a3a70a	1962	#define GPIO_DIRSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
yihui	9:05f0b5a3a70a	1963	#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
yihui	9:05f0b5a3a70a	1964	#define GPIO_DIRSET_PIN18_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1965	#define GPIO_DIRSET_PIN18_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1966	#define GPIO_DIRSET_PIN18_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	1967
yihui	9:05f0b5a3a70a	1968	/* Bit 17 : Set as output pin 17. */
yihui	9:05f0b5a3a70a	1969	#define GPIO_DIRSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
yihui	9:05f0b5a3a70a	1970	#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
yihui	9:05f0b5a3a70a	1971	#define GPIO_DIRSET_PIN17_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1972	#define GPIO_DIRSET_PIN17_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1973	#define GPIO_DIRSET_PIN17_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	1974
yihui	9:05f0b5a3a70a	1975	/* Bit 16 : Set as output pin 16. */
yihui	9:05f0b5a3a70a	1976	#define GPIO_DIRSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
yihui	9:05f0b5a3a70a	1977	#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
yihui	9:05f0b5a3a70a	1978	#define GPIO_DIRSET_PIN16_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1979	#define GPIO_DIRSET_PIN16_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1980	#define GPIO_DIRSET_PIN16_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	1981
yihui	9:05f0b5a3a70a	1982	/* Bit 15 : Set as output pin 15. */
yihui	9:05f0b5a3a70a	1983	#define GPIO_DIRSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
yihui	9:05f0b5a3a70a	1984	#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
yihui	9:05f0b5a3a70a	1985	#define GPIO_DIRSET_PIN15_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1986	#define GPIO_DIRSET_PIN15_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1987	#define GPIO_DIRSET_PIN15_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	1988
yihui	9:05f0b5a3a70a	1989	/* Bit 14 : Set as output pin 14. */
yihui	9:05f0b5a3a70a	1990	#define GPIO_DIRSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
yihui	9:05f0b5a3a70a	1991	#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
yihui	9:05f0b5a3a70a	1992	#define GPIO_DIRSET_PIN14_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	1993	#define GPIO_DIRSET_PIN14_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	1994	#define GPIO_DIRSET_PIN14_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	1995
yihui	9:05f0b5a3a70a	1996	/* Bit 13 : Set as output pin 13. */
yihui	9:05f0b5a3a70a	1997	#define GPIO_DIRSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
yihui	9:05f0b5a3a70a	1998	#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
yihui	9:05f0b5a3a70a	1999	#define GPIO_DIRSET_PIN13_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2000	#define GPIO_DIRSET_PIN13_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2001	#define GPIO_DIRSET_PIN13_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	2002
yihui	9:05f0b5a3a70a	2003	/* Bit 12 : Set as output pin 12. */
yihui	9:05f0b5a3a70a	2004	#define GPIO_DIRSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
yihui	9:05f0b5a3a70a	2005	#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
yihui	9:05f0b5a3a70a	2006	#define GPIO_DIRSET_PIN12_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2007	#define GPIO_DIRSET_PIN12_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2008	#define GPIO_DIRSET_PIN12_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	2009
yihui	9:05f0b5a3a70a	2010	/* Bit 11 : Set as output pin 11. */
yihui	9:05f0b5a3a70a	2011	#define GPIO_DIRSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
yihui	9:05f0b5a3a70a	2012	#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
yihui	9:05f0b5a3a70a	2013	#define GPIO_DIRSET_PIN11_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2014	#define GPIO_DIRSET_PIN11_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2015	#define GPIO_DIRSET_PIN11_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	2016
yihui	9:05f0b5a3a70a	2017	/* Bit 10 : Set as output pin 10. */
yihui	9:05f0b5a3a70a	2018	#define GPIO_DIRSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
yihui	9:05f0b5a3a70a	2019	#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
yihui	9:05f0b5a3a70a	2020	#define GPIO_DIRSET_PIN10_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2021	#define GPIO_DIRSET_PIN10_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2022	#define GPIO_DIRSET_PIN10_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	2023
yihui	9:05f0b5a3a70a	2024	/* Bit 9 : Set as output pin 9. */
yihui	9:05f0b5a3a70a	2025	#define GPIO_DIRSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
yihui	9:05f0b5a3a70a	2026	#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
yihui	9:05f0b5a3a70a	2027	#define GPIO_DIRSET_PIN9_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2028	#define GPIO_DIRSET_PIN9_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2029	#define GPIO_DIRSET_PIN9_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	2030
yihui	9:05f0b5a3a70a	2031	/* Bit 8 : Set as output pin 8. */
yihui	9:05f0b5a3a70a	2032	#define GPIO_DIRSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
yihui	9:05f0b5a3a70a	2033	#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
yihui	9:05f0b5a3a70a	2034	#define GPIO_DIRSET_PIN8_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2035	#define GPIO_DIRSET_PIN8_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2036	#define GPIO_DIRSET_PIN8_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	2037
yihui	9:05f0b5a3a70a	2038	/* Bit 7 : Set as output pin 7. */
yihui	9:05f0b5a3a70a	2039	#define GPIO_DIRSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
yihui	9:05f0b5a3a70a	2040	#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
yihui	9:05f0b5a3a70a	2041	#define GPIO_DIRSET_PIN7_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2042	#define GPIO_DIRSET_PIN7_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2043	#define GPIO_DIRSET_PIN7_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	2044
yihui	9:05f0b5a3a70a	2045	/* Bit 6 : Set as output pin 6. */
yihui	9:05f0b5a3a70a	2046	#define GPIO_DIRSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
yihui	9:05f0b5a3a70a	2047	#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
yihui	9:05f0b5a3a70a	2048	#define GPIO_DIRSET_PIN6_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2049	#define GPIO_DIRSET_PIN6_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2050	#define GPIO_DIRSET_PIN6_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	2051
yihui	9:05f0b5a3a70a	2052	/* Bit 5 : Set as output pin 5. */
yihui	9:05f0b5a3a70a	2053	#define GPIO_DIRSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
yihui	9:05f0b5a3a70a	2054	#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
yihui	9:05f0b5a3a70a	2055	#define GPIO_DIRSET_PIN5_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2056	#define GPIO_DIRSET_PIN5_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2057	#define GPIO_DIRSET_PIN5_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	2058
yihui	9:05f0b5a3a70a	2059	/* Bit 4 : Set as output pin 4. */
yihui	9:05f0b5a3a70a	2060	#define GPIO_DIRSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
yihui	9:05f0b5a3a70a	2061	#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
yihui	9:05f0b5a3a70a	2062	#define GPIO_DIRSET_PIN4_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2063	#define GPIO_DIRSET_PIN4_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2064	#define GPIO_DIRSET_PIN4_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	2065
yihui	9:05f0b5a3a70a	2066	/* Bit 3 : Set as output pin 3. */
yihui	9:05f0b5a3a70a	2067	#define GPIO_DIRSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
yihui	9:05f0b5a3a70a	2068	#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
yihui	9:05f0b5a3a70a	2069	#define GPIO_DIRSET_PIN3_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2070	#define GPIO_DIRSET_PIN3_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2071	#define GPIO_DIRSET_PIN3_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	2072
yihui	9:05f0b5a3a70a	2073	/* Bit 2 : Set as output pin 2. */
yihui	9:05f0b5a3a70a	2074	#define GPIO_DIRSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
yihui	9:05f0b5a3a70a	2075	#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
yihui	9:05f0b5a3a70a	2076	#define GPIO_DIRSET_PIN2_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2077	#define GPIO_DIRSET_PIN2_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2078	#define GPIO_DIRSET_PIN2_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	2079
yihui	9:05f0b5a3a70a	2080	/* Bit 1 : Set as output pin 1. */
yihui	9:05f0b5a3a70a	2081	#define GPIO_DIRSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
yihui	9:05f0b5a3a70a	2082	#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
yihui	9:05f0b5a3a70a	2083	#define GPIO_DIRSET_PIN1_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2084	#define GPIO_DIRSET_PIN1_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2085	#define GPIO_DIRSET_PIN1_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	2086
yihui	9:05f0b5a3a70a	2087	/* Bit 0 : Set as output pin 0. */
yihui	9:05f0b5a3a70a	2088	#define GPIO_DIRSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
yihui	9:05f0b5a3a70a	2089	#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
yihui	9:05f0b5a3a70a	2090	#define GPIO_DIRSET_PIN0_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2091	#define GPIO_DIRSET_PIN0_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2092	#define GPIO_DIRSET_PIN0_Set (1UL) /!< Set pin as output. /
yihui	9:05f0b5a3a70a	2093
yihui	9:05f0b5a3a70a	2094	/* Register: GPIO_DIRCLR */
yihui	9:05f0b5a3a70a	2095	/* Description: DIR clear register. */
yihui	9:05f0b5a3a70a	2096
yihui	9:05f0b5a3a70a	2097	/* Bit 31 : Set as input pin 31. */
yihui	9:05f0b5a3a70a	2098	#define GPIO_DIRCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
yihui	9:05f0b5a3a70a	2099	#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
yihui	9:05f0b5a3a70a	2100	#define GPIO_DIRCLR_PIN31_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2101	#define GPIO_DIRCLR_PIN31_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2102	#define GPIO_DIRCLR_PIN31_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2103
yihui	9:05f0b5a3a70a	2104	/* Bit 30 : Set as input pin 30. */
yihui	9:05f0b5a3a70a	2105	#define GPIO_DIRCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
yihui	9:05f0b5a3a70a	2106	#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
yihui	9:05f0b5a3a70a	2107	#define GPIO_DIRCLR_PIN30_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2108	#define GPIO_DIRCLR_PIN30_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2109	#define GPIO_DIRCLR_PIN30_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2110
yihui	9:05f0b5a3a70a	2111	/* Bit 29 : Set as input pin 29. */
yihui	9:05f0b5a3a70a	2112	#define GPIO_DIRCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
yihui	9:05f0b5a3a70a	2113	#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
yihui	9:05f0b5a3a70a	2114	#define GPIO_DIRCLR_PIN29_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2115	#define GPIO_DIRCLR_PIN29_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2116	#define GPIO_DIRCLR_PIN29_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2117
yihui	9:05f0b5a3a70a	2118	/* Bit 28 : Set as input pin 28. */
yihui	9:05f0b5a3a70a	2119	#define GPIO_DIRCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
yihui	9:05f0b5a3a70a	2120	#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
yihui	9:05f0b5a3a70a	2121	#define GPIO_DIRCLR_PIN28_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2122	#define GPIO_DIRCLR_PIN28_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2123	#define GPIO_DIRCLR_PIN28_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2124
yihui	9:05f0b5a3a70a	2125	/* Bit 27 : Set as input pin 27. */
yihui	9:05f0b5a3a70a	2126	#define GPIO_DIRCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
yihui	9:05f0b5a3a70a	2127	#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
yihui	9:05f0b5a3a70a	2128	#define GPIO_DIRCLR_PIN27_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2129	#define GPIO_DIRCLR_PIN27_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2130	#define GPIO_DIRCLR_PIN27_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2131
yihui	9:05f0b5a3a70a	2132	/* Bit 26 : Set as input pin 26. */
yihui	9:05f0b5a3a70a	2133	#define GPIO_DIRCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
yihui	9:05f0b5a3a70a	2134	#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
yihui	9:05f0b5a3a70a	2135	#define GPIO_DIRCLR_PIN26_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2136	#define GPIO_DIRCLR_PIN26_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2137	#define GPIO_DIRCLR_PIN26_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2138
yihui	9:05f0b5a3a70a	2139	/* Bit 25 : Set as input pin 25. */
yihui	9:05f0b5a3a70a	2140	#define GPIO_DIRCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
yihui	9:05f0b5a3a70a	2141	#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
yihui	9:05f0b5a3a70a	2142	#define GPIO_DIRCLR_PIN25_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2143	#define GPIO_DIRCLR_PIN25_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2144	#define GPIO_DIRCLR_PIN25_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2145
yihui	9:05f0b5a3a70a	2146	/* Bit 24 : Set as input pin 24. */
yihui	9:05f0b5a3a70a	2147	#define GPIO_DIRCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
yihui	9:05f0b5a3a70a	2148	#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
yihui	9:05f0b5a3a70a	2149	#define GPIO_DIRCLR_PIN24_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2150	#define GPIO_DIRCLR_PIN24_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2151	#define GPIO_DIRCLR_PIN24_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2152
yihui	9:05f0b5a3a70a	2153	/* Bit 23 : Set as input pin 23. */
yihui	9:05f0b5a3a70a	2154	#define GPIO_DIRCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
yihui	9:05f0b5a3a70a	2155	#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
yihui	9:05f0b5a3a70a	2156	#define GPIO_DIRCLR_PIN23_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2157	#define GPIO_DIRCLR_PIN23_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2158	#define GPIO_DIRCLR_PIN23_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2159
yihui	9:05f0b5a3a70a	2160	/* Bit 22 : Set as input pin 22. */
yihui	9:05f0b5a3a70a	2161	#define GPIO_DIRCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
yihui	9:05f0b5a3a70a	2162	#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
yihui	9:05f0b5a3a70a	2163	#define GPIO_DIRCLR_PIN22_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2164	#define GPIO_DIRCLR_PIN22_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2165	#define GPIO_DIRCLR_PIN22_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2166
yihui	9:05f0b5a3a70a	2167	/* Bit 21 : Set as input pin 21. */
yihui	9:05f0b5a3a70a	2168	#define GPIO_DIRCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
yihui	9:05f0b5a3a70a	2169	#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
yihui	9:05f0b5a3a70a	2170	#define GPIO_DIRCLR_PIN21_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2171	#define GPIO_DIRCLR_PIN21_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2172	#define GPIO_DIRCLR_PIN21_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2173
yihui	9:05f0b5a3a70a	2174	/* Bit 20 : Set as input pin 20. */
yihui	9:05f0b5a3a70a	2175	#define GPIO_DIRCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
yihui	9:05f0b5a3a70a	2176	#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
yihui	9:05f0b5a3a70a	2177	#define GPIO_DIRCLR_PIN20_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2178	#define GPIO_DIRCLR_PIN20_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2179	#define GPIO_DIRCLR_PIN20_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2180
yihui	9:05f0b5a3a70a	2181	/* Bit 19 : Set as input pin 19. */
yihui	9:05f0b5a3a70a	2182	#define GPIO_DIRCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
yihui	9:05f0b5a3a70a	2183	#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
yihui	9:05f0b5a3a70a	2184	#define GPIO_DIRCLR_PIN19_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2185	#define GPIO_DIRCLR_PIN19_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2186	#define GPIO_DIRCLR_PIN19_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2187
yihui	9:05f0b5a3a70a	2188	/* Bit 18 : Set as input pin 18. */
yihui	9:05f0b5a3a70a	2189	#define GPIO_DIRCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
yihui	9:05f0b5a3a70a	2190	#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
yihui	9:05f0b5a3a70a	2191	#define GPIO_DIRCLR_PIN18_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2192	#define GPIO_DIRCLR_PIN18_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2193	#define GPIO_DIRCLR_PIN18_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2194
yihui	9:05f0b5a3a70a	2195	/* Bit 17 : Set as input pin 17. */
yihui	9:05f0b5a3a70a	2196	#define GPIO_DIRCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
yihui	9:05f0b5a3a70a	2197	#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
yihui	9:05f0b5a3a70a	2198	#define GPIO_DIRCLR_PIN17_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2199	#define GPIO_DIRCLR_PIN17_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2200	#define GPIO_DIRCLR_PIN17_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2201
yihui	9:05f0b5a3a70a	2202	/* Bit 16 : Set as input pin 16. */
yihui	9:05f0b5a3a70a	2203	#define GPIO_DIRCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
yihui	9:05f0b5a3a70a	2204	#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
yihui	9:05f0b5a3a70a	2205	#define GPIO_DIRCLR_PIN16_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2206	#define GPIO_DIRCLR_PIN16_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2207	#define GPIO_DIRCLR_PIN16_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2208
yihui	9:05f0b5a3a70a	2209	/* Bit 15 : Set as input pin 15. */
yihui	9:05f0b5a3a70a	2210	#define GPIO_DIRCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
yihui	9:05f0b5a3a70a	2211	#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
yihui	9:05f0b5a3a70a	2212	#define GPIO_DIRCLR_PIN15_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2213	#define GPIO_DIRCLR_PIN15_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2214	#define GPIO_DIRCLR_PIN15_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2215
yihui	9:05f0b5a3a70a	2216	/* Bit 14 : Set as input pin 14. */
yihui	9:05f0b5a3a70a	2217	#define GPIO_DIRCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
yihui	9:05f0b5a3a70a	2218	#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
yihui	9:05f0b5a3a70a	2219	#define GPIO_DIRCLR_PIN14_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2220	#define GPIO_DIRCLR_PIN14_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2221	#define GPIO_DIRCLR_PIN14_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2222
yihui	9:05f0b5a3a70a	2223	/* Bit 13 : Set as input pin 13. */
yihui	9:05f0b5a3a70a	2224	#define GPIO_DIRCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
yihui	9:05f0b5a3a70a	2225	#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
yihui	9:05f0b5a3a70a	2226	#define GPIO_DIRCLR_PIN13_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2227	#define GPIO_DIRCLR_PIN13_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2228	#define GPIO_DIRCLR_PIN13_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2229
yihui	9:05f0b5a3a70a	2230	/* Bit 12 : Set as input pin 12. */
yihui	9:05f0b5a3a70a	2231	#define GPIO_DIRCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
yihui	9:05f0b5a3a70a	2232	#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
yihui	9:05f0b5a3a70a	2233	#define GPIO_DIRCLR_PIN12_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2234	#define GPIO_DIRCLR_PIN12_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2235	#define GPIO_DIRCLR_PIN12_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2236
yihui	9:05f0b5a3a70a	2237	/* Bit 11 : Set as input pin 11. */
yihui	9:05f0b5a3a70a	2238	#define GPIO_DIRCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
yihui	9:05f0b5a3a70a	2239	#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
yihui	9:05f0b5a3a70a	2240	#define GPIO_DIRCLR_PIN11_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2241	#define GPIO_DIRCLR_PIN11_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2242	#define GPIO_DIRCLR_PIN11_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2243
yihui	9:05f0b5a3a70a	2244	/* Bit 10 : Set as input pin 10. */
yihui	9:05f0b5a3a70a	2245	#define GPIO_DIRCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
yihui	9:05f0b5a3a70a	2246	#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
yihui	9:05f0b5a3a70a	2247	#define GPIO_DIRCLR_PIN10_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2248	#define GPIO_DIRCLR_PIN10_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2249	#define GPIO_DIRCLR_PIN10_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2250
yihui	9:05f0b5a3a70a	2251	/* Bit 9 : Set as input pin 9. */
yihui	9:05f0b5a3a70a	2252	#define GPIO_DIRCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
yihui	9:05f0b5a3a70a	2253	#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
yihui	9:05f0b5a3a70a	2254	#define GPIO_DIRCLR_PIN9_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2255	#define GPIO_DIRCLR_PIN9_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2256	#define GPIO_DIRCLR_PIN9_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2257
yihui	9:05f0b5a3a70a	2258	/* Bit 8 : Set as input pin 8. */
yihui	9:05f0b5a3a70a	2259	#define GPIO_DIRCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
yihui	9:05f0b5a3a70a	2260	#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
yihui	9:05f0b5a3a70a	2261	#define GPIO_DIRCLR_PIN8_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2262	#define GPIO_DIRCLR_PIN8_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2263	#define GPIO_DIRCLR_PIN8_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2264
yihui	9:05f0b5a3a70a	2265	/* Bit 7 : Set as input pin 7. */
yihui	9:05f0b5a3a70a	2266	#define GPIO_DIRCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
yihui	9:05f0b5a3a70a	2267	#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
yihui	9:05f0b5a3a70a	2268	#define GPIO_DIRCLR_PIN7_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2269	#define GPIO_DIRCLR_PIN7_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2270	#define GPIO_DIRCLR_PIN7_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2271
yihui	9:05f0b5a3a70a	2272	/* Bit 6 : Set as input pin 6. */
yihui	9:05f0b5a3a70a	2273	#define GPIO_DIRCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
yihui	9:05f0b5a3a70a	2274	#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
yihui	9:05f0b5a3a70a	2275	#define GPIO_DIRCLR_PIN6_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2276	#define GPIO_DIRCLR_PIN6_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2277	#define GPIO_DIRCLR_PIN6_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2278
yihui	9:05f0b5a3a70a	2279	/* Bit 5 : Set as input pin 5. */
yihui	9:05f0b5a3a70a	2280	#define GPIO_DIRCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
yihui	9:05f0b5a3a70a	2281	#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
yihui	9:05f0b5a3a70a	2282	#define GPIO_DIRCLR_PIN5_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2283	#define GPIO_DIRCLR_PIN5_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2284	#define GPIO_DIRCLR_PIN5_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2285
yihui	9:05f0b5a3a70a	2286	/* Bit 4 : Set as input pin 4. */
yihui	9:05f0b5a3a70a	2287	#define GPIO_DIRCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
yihui	9:05f0b5a3a70a	2288	#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
yihui	9:05f0b5a3a70a	2289	#define GPIO_DIRCLR_PIN4_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2290	#define GPIO_DIRCLR_PIN4_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2291	#define GPIO_DIRCLR_PIN4_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2292
yihui	9:05f0b5a3a70a	2293	/* Bit 3 : Set as input pin 3. */
yihui	9:05f0b5a3a70a	2294	#define GPIO_DIRCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
yihui	9:05f0b5a3a70a	2295	#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
yihui	9:05f0b5a3a70a	2296	#define GPIO_DIRCLR_PIN3_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2297	#define GPIO_DIRCLR_PIN3_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2298	#define GPIO_DIRCLR_PIN3_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2299
yihui	9:05f0b5a3a70a	2300	/* Bit 2 : Set as input pin 2. */
yihui	9:05f0b5a3a70a	2301	#define GPIO_DIRCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
yihui	9:05f0b5a3a70a	2302	#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
yihui	9:05f0b5a3a70a	2303	#define GPIO_DIRCLR_PIN2_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2304	#define GPIO_DIRCLR_PIN2_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2305	#define GPIO_DIRCLR_PIN2_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2306
yihui	9:05f0b5a3a70a	2307	/* Bit 1 : Set as input pin 1. */
yihui	9:05f0b5a3a70a	2308	#define GPIO_DIRCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
yihui	9:05f0b5a3a70a	2309	#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
yihui	9:05f0b5a3a70a	2310	#define GPIO_DIRCLR_PIN1_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2311	#define GPIO_DIRCLR_PIN1_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2312	#define GPIO_DIRCLR_PIN1_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2313
yihui	9:05f0b5a3a70a	2314	/* Bit 0 : Set as input pin 0. */
yihui	9:05f0b5a3a70a	2315	#define GPIO_DIRCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
yihui	9:05f0b5a3a70a	2316	#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
yihui	9:05f0b5a3a70a	2317	#define GPIO_DIRCLR_PIN0_Input (0UL) /!< Pin set as input. /
yihui	9:05f0b5a3a70a	2318	#define GPIO_DIRCLR_PIN0_Output (1UL) /!< Pin set as output. /
yihui	9:05f0b5a3a70a	2319	#define GPIO_DIRCLR_PIN0_Clear (1UL) /!< Set pin as input. /
yihui	9:05f0b5a3a70a	2320
yihui	9:05f0b5a3a70a	2321	/* Register: GPIO_PIN_CNF */
yihui	9:05f0b5a3a70a	2322	/* Description: Configuration of GPIO pins. */
yihui	9:05f0b5a3a70a	2323
yihui	9:05f0b5a3a70a	2324	/* Bits 17..16 : Pin sensing mechanism. */
yihui	9:05f0b5a3a70a	2325	#define GPIO_PIN_CNF_SENSE_Pos (16UL) /!< Position of SENSE field. /
yihui	9:05f0b5a3a70a	2326	#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /!< Bit mask of SENSE field. /
yihui	9:05f0b5a3a70a	2327	#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /!< Disabled. /
yihui	9:05f0b5a3a70a	2328	#define GPIO_PIN_CNF_SENSE_High (0x02UL) /!< Wakeup on high level. /
yihui	9:05f0b5a3a70a	2329	#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /!< Wakeup on low level. /
yihui	9:05f0b5a3a70a	2330
yihui	9:05f0b5a3a70a	2331	/* Bits 10..8 : Drive configuration. */
yihui	9:05f0b5a3a70a	2332	#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /!< Position of DRIVE field. /
yihui	9:05f0b5a3a70a	2333	#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /!< Bit mask of DRIVE field. /
yihui	9:05f0b5a3a70a	2334	#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /!< Standard '0', Standard '1'. /
yihui	9:05f0b5a3a70a	2335	#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /!< High '0', Standard '1'. /
yihui	9:05f0b5a3a70a	2336	#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /!< Standard '0', High '1'. /
yihui	9:05f0b5a3a70a	2337	#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /!< High '0', High '1'. /
yihui	9:05f0b5a3a70a	2338	#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /!< Disconnected '0', Standard '1'. /
yihui	9:05f0b5a3a70a	2339	#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /!< Disconnected '0', High '1'. /
yihui	9:05f0b5a3a70a	2340	#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /!< Standard '0', Disconnected '1'. /
yihui	9:05f0b5a3a70a	2341	#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /!< High '0', Disconnected '1'. /
yihui	9:05f0b5a3a70a	2342
yihui	9:05f0b5a3a70a	2343	/* Bits 3..2 : Pull-up or -down configuration. */
yihui	9:05f0b5a3a70a	2344	#define GPIO_PIN_CNF_PULL_Pos (2UL) /!< Position of PULL field. /
yihui	9:05f0b5a3a70a	2345	#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /!< Bit mask of PULL field. /
yihui	9:05f0b5a3a70a	2346	#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /!< No pull. /
yihui	9:05f0b5a3a70a	2347	#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /!< Pulldown on pin. /
yihui	9:05f0b5a3a70a	2348	#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /!< Pullup on pin. /
yihui	9:05f0b5a3a70a	2349
yihui	9:05f0b5a3a70a	2350	/* Bit 1 : Connect or disconnect input path. */
yihui	9:05f0b5a3a70a	2351	#define GPIO_PIN_CNF_INPUT_Pos (1UL) /!< Position of INPUT field. /
yihui	9:05f0b5a3a70a	2352	#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /!< Bit mask of INPUT field. /
yihui	9:05f0b5a3a70a	2353	#define GPIO_PIN_CNF_INPUT_Connect (0UL) /!< Connect input pin. /
yihui	9:05f0b5a3a70a	2354	#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /!< Disconnect input pin. /
yihui	9:05f0b5a3a70a	2355
yihui	9:05f0b5a3a70a	2356	/* Bit 0 : Pin direction. */
yihui	9:05f0b5a3a70a	2357	#define GPIO_PIN_CNF_DIR_Pos (0UL) /!< Position of DIR field. /
yihui	9:05f0b5a3a70a	2358	#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /!< Bit mask of DIR field. /
yihui	9:05f0b5a3a70a	2359	#define GPIO_PIN_CNF_DIR_Input (0UL) /!< Configure pin as an input pin. /
yihui	9:05f0b5a3a70a	2360	#define GPIO_PIN_CNF_DIR_Output (1UL) /!< Configure pin as an output pin. /
yihui	9:05f0b5a3a70a	2361
yihui	9:05f0b5a3a70a	2362
yihui	9:05f0b5a3a70a	2363	/* Peripheral: GPIOTE */
yihui	9:05f0b5a3a70a	2364	/* Description: GPIO tasks and events. */
yihui	9:05f0b5a3a70a	2365
yihui	9:05f0b5a3a70a	2366	/* Register: GPIOTE_INTENSET */
yihui	9:05f0b5a3a70a	2367	/* Description: Interrupt enable set register. */
yihui	9:05f0b5a3a70a	2368
yihui	9:05f0b5a3a70a	2369	/* Bit 31 : Enable interrupt on PORT event. */
yihui	9:05f0b5a3a70a	2370	#define GPIOTE_INTENSET_PORT_Pos (31UL) /!< Position of PORT field. /
yihui	9:05f0b5a3a70a	2371	#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /!< Bit mask of PORT field. /
yihui	9:05f0b5a3a70a	2372	#define GPIOTE_INTENSET_PORT_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	2373	#define GPIOTE_INTENSET_PORT_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	2374	#define GPIOTE_INTENSET_PORT_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	2375
yihui	9:05f0b5a3a70a	2376	/* Bit 3 : Enable interrupt on IN[3] event. */
yihui	9:05f0b5a3a70a	2377	#define GPIOTE_INTENSET_IN3_Pos (3UL) /!< Position of IN3 field. /
yihui	9:05f0b5a3a70a	2378	#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /!< Bit mask of IN3 field. /
yihui	9:05f0b5a3a70a	2379	#define GPIOTE_INTENSET_IN3_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	2380	#define GPIOTE_INTENSET_IN3_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	2381	#define GPIOTE_INTENSET_IN3_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	2382
yihui	9:05f0b5a3a70a	2383	/* Bit 2 : Enable interrupt on IN[2] event. */
yihui	9:05f0b5a3a70a	2384	#define GPIOTE_INTENSET_IN2_Pos (2UL) /!< Position of IN2 field. /
yihui	9:05f0b5a3a70a	2385	#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /!< Bit mask of IN2 field. /
yihui	9:05f0b5a3a70a	2386	#define GPIOTE_INTENSET_IN2_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	2387	#define GPIOTE_INTENSET_IN2_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	2388	#define GPIOTE_INTENSET_IN2_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	2389
yihui	9:05f0b5a3a70a	2390	/* Bit 1 : Enable interrupt on IN[1] event. */
yihui	9:05f0b5a3a70a	2391	#define GPIOTE_INTENSET_IN1_Pos (1UL) /!< Position of IN1 field. /
yihui	9:05f0b5a3a70a	2392	#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /!< Bit mask of IN1 field. /
yihui	9:05f0b5a3a70a	2393	#define GPIOTE_INTENSET_IN1_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	2394	#define GPIOTE_INTENSET_IN1_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	2395	#define GPIOTE_INTENSET_IN1_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	2396
yihui	9:05f0b5a3a70a	2397	/* Bit 0 : Enable interrupt on IN[0] event. */
yihui	9:05f0b5a3a70a	2398	#define GPIOTE_INTENSET_IN0_Pos (0UL) /!< Position of IN0 field. /
yihui	9:05f0b5a3a70a	2399	#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /!< Bit mask of IN0 field. /
yihui	9:05f0b5a3a70a	2400	#define GPIOTE_INTENSET_IN0_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	2401	#define GPIOTE_INTENSET_IN0_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	2402	#define GPIOTE_INTENSET_IN0_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	2403
yihui	9:05f0b5a3a70a	2404	/* Register: GPIOTE_INTENCLR */
yihui	9:05f0b5a3a70a	2405	/* Description: Interrupt enable clear register. */
yihui	9:05f0b5a3a70a	2406
yihui	9:05f0b5a3a70a	2407	/* Bit 31 : Disable interrupt on PORT event. */
yihui	9:05f0b5a3a70a	2408	#define GPIOTE_INTENCLR_PORT_Pos (31UL) /!< Position of PORT field. /
yihui	9:05f0b5a3a70a	2409	#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /!< Bit mask of PORT field. /
yihui	9:05f0b5a3a70a	2410	#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	2411	#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	2412	#define GPIOTE_INTENCLR_PORT_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	2413
yihui	9:05f0b5a3a70a	2414	/* Bit 3 : Disable interrupt on IN[3] event. */
yihui	9:05f0b5a3a70a	2415	#define GPIOTE_INTENCLR_IN3_Pos (3UL) /!< Position of IN3 field. /
yihui	9:05f0b5a3a70a	2416	#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /!< Bit mask of IN3 field. /
yihui	9:05f0b5a3a70a	2417	#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	2418	#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	2419	#define GPIOTE_INTENCLR_IN3_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	2420
yihui	9:05f0b5a3a70a	2421	/* Bit 2 : Disable interrupt on IN[2] event. */
yihui	9:05f0b5a3a70a	2422	#define GPIOTE_INTENCLR_IN2_Pos (2UL) /!< Position of IN2 field. /
yihui	9:05f0b5a3a70a	2423	#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /!< Bit mask of IN2 field. /
yihui	9:05f0b5a3a70a	2424	#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	2425	#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	2426	#define GPIOTE_INTENCLR_IN2_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	2427
yihui	9:05f0b5a3a70a	2428	/* Bit 1 : Disable interrupt on IN[1] event. */
yihui	9:05f0b5a3a70a	2429	#define GPIOTE_INTENCLR_IN1_Pos (1UL) /!< Position of IN1 field. /
yihui	9:05f0b5a3a70a	2430	#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /!< Bit mask of IN1 field. /
yihui	9:05f0b5a3a70a	2431	#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	2432	#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	2433	#define GPIOTE_INTENCLR_IN1_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	2434
yihui	9:05f0b5a3a70a	2435	/* Bit 0 : Disable interrupt on IN[0] event. */
yihui	9:05f0b5a3a70a	2436	#define GPIOTE_INTENCLR_IN0_Pos (0UL) /!< Position of IN0 field. /
yihui	9:05f0b5a3a70a	2437	#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /!< Bit mask of IN0 field. /
yihui	9:05f0b5a3a70a	2438	#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	2439	#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	2440	#define GPIOTE_INTENCLR_IN0_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	2441
yihui	9:05f0b5a3a70a	2442	/* Register: GPIOTE_CONFIG */
yihui	9:05f0b5a3a70a	2443	/* Description: Channel configuration registers. */
yihui	9:05f0b5a3a70a	2444
yihui	9:05f0b5a3a70a	2445	/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
yihui	9:05f0b5a3a70a	2446	#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /!< Position of OUTINIT field. /
yihui	9:05f0b5a3a70a	2447	#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /!< Bit mask of OUTINIT field. /
yihui	9:05f0b5a3a70a	2448	#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /!< Initial low output when in task mode. /
yihui	9:05f0b5a3a70a	2449	#define GPIOTE_CONFIG_OUTINIT_High (1UL) /!< Initial high output when in task mode. /
yihui	9:05f0b5a3a70a	2450
yihui	9:05f0b5a3a70a	2451	/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
yihui	9:05f0b5a3a70a	2452	#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /!< Position of POLARITY field. /
yihui	9:05f0b5a3a70a	2453	#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /!< Bit mask of POLARITY field. /
yihui	9:05f0b5a3a70a	2454	#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /!< Low to high. /
yihui	9:05f0b5a3a70a	2455	#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /!< High to low. /
yihui	9:05f0b5a3a70a	2456	#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /!< Toggle. /
yihui	9:05f0b5a3a70a	2457
yihui	9:05f0b5a3a70a	2458	/* Bits 12..8 : Pin select. */
yihui	9:05f0b5a3a70a	2459	#define GPIOTE_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
yihui	9:05f0b5a3a70a	2460	#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
yihui	9:05f0b5a3a70a	2461
yihui	9:05f0b5a3a70a	2462	/* Bits 1..0 : Mode */
yihui	9:05f0b5a3a70a	2463	#define GPIOTE_CONFIG_MODE_Pos (0UL) /!< Position of MODE field. /
yihui	9:05f0b5a3a70a	2464	#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /!< Bit mask of MODE field. /
yihui	9:05f0b5a3a70a	2465	#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /!< Disabled. /
yihui	9:05f0b5a3a70a	2466	#define GPIOTE_CONFIG_MODE_Event (0x01UL) /!< Channel configure in event mode. /
yihui	9:05f0b5a3a70a	2467	#define GPIOTE_CONFIG_MODE_Task (0x03UL) /!< Channel configure in task mode. /
yihui	9:05f0b5a3a70a	2468
yihui	9:05f0b5a3a70a	2469	/* Register: GPIOTE_POWER */
yihui	9:05f0b5a3a70a	2470	/* Description: Peripheral power control. */
yihui	9:05f0b5a3a70a	2471
yihui	9:05f0b5a3a70a	2472	/* Bit 0 : Peripheral power control. */
yihui	9:05f0b5a3a70a	2473	#define GPIOTE_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
yihui	9:05f0b5a3a70a	2474	#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /!< Bit mask of POWER field. /
yihui	9:05f0b5a3a70a	2475	#define GPIOTE_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
yihui	9:05f0b5a3a70a	2476	#define GPIOTE_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
yihui	9:05f0b5a3a70a	2477
yihui	9:05f0b5a3a70a	2478
yihui	9:05f0b5a3a70a	2479	/* Peripheral: LPCOMP */
yihui	9:05f0b5a3a70a	2480	/* Description: Wakeup Comparator. */
yihui	9:05f0b5a3a70a	2481
yihui	9:05f0b5a3a70a	2482	/* Register: LPCOMP_SHORTS */
yihui	9:05f0b5a3a70a	2483	/* Description: Shortcut for the LPCOMP. */
yihui	9:05f0b5a3a70a	2484
yihui	9:05f0b5a3a70a	2485	/* Bit 4 : Short-cut between CROSS event and STOP task. */
yihui	9:05f0b5a3a70a	2486	#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /!< Position of CROSS_STOP field. /
yihui	9:05f0b5a3a70a	2487	#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /!< Bit mask of CROSS_STOP field. /
yihui	9:05f0b5a3a70a	2488	#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	2489	#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	2490
yihui	9:05f0b5a3a70a	2491	/* Bit 3 : Short-cut between UP event and STOP task. */
yihui	9:05f0b5a3a70a	2492	#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /!< Position of UP_STOP field. /
yihui	9:05f0b5a3a70a	2493	#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /!< Bit mask of UP_STOP field. /
yihui	9:05f0b5a3a70a	2494	#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	2495	#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	2496
yihui	9:05f0b5a3a70a	2497	/* Bit 2 : Short-cut between DOWN event and STOP task. */
yihui	9:05f0b5a3a70a	2498	#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /!< Position of DOWN_STOP field. /
yihui	9:05f0b5a3a70a	2499	#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /!< Bit mask of DOWN_STOP field. /
yihui	9:05f0b5a3a70a	2500	#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	2501	#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	2502
yihui	9:05f0b5a3a70a	2503	/* Bit 1 : Short-cut between RADY event and STOP task. */
yihui	9:05f0b5a3a70a	2504	#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /!< Position of READY_STOP field. /
yihui	9:05f0b5a3a70a	2505	#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /!< Bit mask of READY_STOP field. /
yihui	9:05f0b5a3a70a	2506	#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	2507	#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	2508
yihui	9:05f0b5a3a70a	2509	/* Bit 0 : Short-cut between READY event and SAMPLE task. */
yihui	9:05f0b5a3a70a	2510	#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /!< Position of READY_SAMPLE field. /
yihui	9:05f0b5a3a70a	2511	#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /!< Bit mask of READY_SAMPLE field. /
yihui	9:05f0b5a3a70a	2512	#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	2513	#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	2514
yihui	9:05f0b5a3a70a	2515	/* Register: LPCOMP_INTENSET */
yihui	9:05f0b5a3a70a	2516	/* Description: Interrupt enable set register. */
yihui	9:05f0b5a3a70a	2517
yihui	9:05f0b5a3a70a	2518	/* Bit 3 : Enable interrupt on CROSS event. */
yihui	9:05f0b5a3a70a	2519	#define LPCOMP_INTENSET_CROSS_Pos (3UL) /!< Position of CROSS field. /
yihui	9:05f0b5a3a70a	2520	#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /!< Bit mask of CROSS field. /
yihui	9:05f0b5a3a70a	2521	#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	2522	#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	2523	#define LPCOMP_INTENSET_CROSS_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	2524
yihui	9:05f0b5a3a70a	2525	/* Bit 2 : Enable interrupt on UP event. */
yihui	9:05f0b5a3a70a	2526	#define LPCOMP_INTENSET_UP_Pos (2UL) /!< Position of UP field. /
yihui	9:05f0b5a3a70a	2527	#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /!< Bit mask of UP field. /
yihui	9:05f0b5a3a70a	2528	#define LPCOMP_INTENSET_UP_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	2529	#define LPCOMP_INTENSET_UP_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	2530	#define LPCOMP_INTENSET_UP_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	2531
yihui	9:05f0b5a3a70a	2532	/* Bit 1 : Enable interrupt on DOWN event. */
yihui	9:05f0b5a3a70a	2533	#define LPCOMP_INTENSET_DOWN_Pos (1UL) /!< Position of DOWN field. /
yihui	9:05f0b5a3a70a	2534	#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /!< Bit mask of DOWN field. /
yihui	9:05f0b5a3a70a	2535	#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	2536	#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	2537	#define LPCOMP_INTENSET_DOWN_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	2538
yihui	9:05f0b5a3a70a	2539	/* Bit 0 : Enable interrupt on READY event. */
yihui	9:05f0b5a3a70a	2540	#define LPCOMP_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
yihui	9:05f0b5a3a70a	2541	#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /!< Bit mask of READY field. /
yihui	9:05f0b5a3a70a	2542	#define LPCOMP_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	2543	#define LPCOMP_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	2544	#define LPCOMP_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	2545
yihui	9:05f0b5a3a70a	2546	/* Register: LPCOMP_INTENCLR */
yihui	9:05f0b5a3a70a	2547	/* Description: Interrupt enable clear register. */
yihui	9:05f0b5a3a70a	2548
yihui	9:05f0b5a3a70a	2549	/* Bit 3 : Disable interrupt on CROSS event. */
yihui	9:05f0b5a3a70a	2550	#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /!< Position of CROSS field. /
yihui	9:05f0b5a3a70a	2551	#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /!< Bit mask of CROSS field. /
yihui	9:05f0b5a3a70a	2552	#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	2553	#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	2554	#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	2555
yihui	9:05f0b5a3a70a	2556	/* Bit 2 : Disable interrupt on UP event. */
yihui	9:05f0b5a3a70a	2557	#define LPCOMP_INTENCLR_UP_Pos (2UL) /!< Position of UP field. /
yihui	9:05f0b5a3a70a	2558	#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /!< Bit mask of UP field. /
yihui	9:05f0b5a3a70a	2559	#define LPCOMP_INTENCLR_UP_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	2560	#define LPCOMP_INTENCLR_UP_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	2561	#define LPCOMP_INTENCLR_UP_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	2562
yihui	9:05f0b5a3a70a	2563	/* Bit 1 : Disable interrupt on DOWN event. */
yihui	9:05f0b5a3a70a	2564	#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /!< Position of DOWN field. /
yihui	9:05f0b5a3a70a	2565	#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /!< Bit mask of DOWN field. /
yihui	9:05f0b5a3a70a	2566	#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	2567	#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	2568	#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	2569
yihui	9:05f0b5a3a70a	2570	/* Bit 0 : Disable interrupt on READY event. */
yihui	9:05f0b5a3a70a	2571	#define LPCOMP_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
yihui	9:05f0b5a3a70a	2572	#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
yihui	9:05f0b5a3a70a	2573	#define LPCOMP_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	2574	#define LPCOMP_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	2575	#define LPCOMP_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	2576
yihui	9:05f0b5a3a70a	2577	/* Register: LPCOMP_RESULT */
yihui	9:05f0b5a3a70a	2578	/* Description: Result of last compare. */
yihui	9:05f0b5a3a70a	2579
yihui	9:05f0b5a3a70a	2580	/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
yihui	9:05f0b5a3a70a	2581	#define LPCOMP_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
yihui	9:05f0b5a3a70a	2582	#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
yihui	9:05f0b5a3a70a	2583	#define LPCOMP_RESULT_RESULT_Bellow (0UL) /!< Input voltage is bellow the reference threshold. /
yihui	9:05f0b5a3a70a	2584	#define LPCOMP_RESULT_RESULT_Above (1UL) /!< Input voltage is above the reference threshold. /
yihui	9:05f0b5a3a70a	2585
yihui	9:05f0b5a3a70a	2586	/* Register: LPCOMP_ENABLE */
yihui	9:05f0b5a3a70a	2587	/* Description: Enable the LPCOMP. */
yihui	9:05f0b5a3a70a	2588
yihui	9:05f0b5a3a70a	2589	/* Bits 1..0 : Enable or disable LPCOMP. */
yihui	9:05f0b5a3a70a	2590	#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
yihui	9:05f0b5a3a70a	2591	#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
yihui	9:05f0b5a3a70a	2592	#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled LPCOMP. /
yihui	9:05f0b5a3a70a	2593	#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable LPCOMP. /
yihui	9:05f0b5a3a70a	2594
yihui	9:05f0b5a3a70a	2595	/* Register: LPCOMP_PSEL */
yihui	9:05f0b5a3a70a	2596	/* Description: Input pin select. */
yihui	9:05f0b5a3a70a	2597
yihui	9:05f0b5a3a70a	2598	/* Bits 2..0 : Analog input pin select. */
yihui	9:05f0b5a3a70a	2599	#define LPCOMP_PSEL_PSEL_Pos (0UL) /!< Position of PSEL field. /
yihui	9:05f0b5a3a70a	2600	#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /!< Bit mask of PSEL field. /
yihui	9:05f0b5a3a70a	2601	#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /!< Use analog input 0 as analog input. /
yihui	9:05f0b5a3a70a	2602	#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /!< Use analog input 1 as analog input. /
yihui	9:05f0b5a3a70a	2603	#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /!< Use analog input 2 as analog input. /
yihui	9:05f0b5a3a70a	2604	#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /!< Use analog input 3 as analog input. /
yihui	9:05f0b5a3a70a	2605	#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /!< Use analog input 4 as analog input. /
yihui	9:05f0b5a3a70a	2606	#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /!< Use analog input 5 as analog input. /
yihui	9:05f0b5a3a70a	2607	#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /!< Use analog input 6 as analog input. /
yihui	9:05f0b5a3a70a	2608	#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /!< Use analog input 7 as analog input. /
yihui	9:05f0b5a3a70a	2609
yihui	9:05f0b5a3a70a	2610	/* Register: LPCOMP_REFSEL */
yihui	9:05f0b5a3a70a	2611	/* Description: Reference select. */
yihui	9:05f0b5a3a70a	2612
yihui	9:05f0b5a3a70a	2613	/* Bits 2..0 : Reference select. */
yihui	9:05f0b5a3a70a	2614	#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /!< Position of REFSEL field. /
yihui	9:05f0b5a3a70a	2615	#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /!< Bit mask of REFSEL field. /
yihui	9:05f0b5a3a70a	2616	#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /!< Use analog supply with a 1/8 prescaler as reference. /
yihui	9:05f0b5a3a70a	2617	#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /!< Use analog supply with a 2/8 prescaler as reference. /
yihui	9:05f0b5a3a70a	2618	#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /!< Use analog supply with a 3/8 prescaler as reference. /
yihui	9:05f0b5a3a70a	2619	#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /!< Use analog supply with a 4/8 prescaler as reference. /
yihui	9:05f0b5a3a70a	2620	#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /!< Use analog supply with a 5/8 prescaler as reference. /
yihui	9:05f0b5a3a70a	2621	#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /!< Use analog supply with a 6/8 prescaler as reference. /
yihui	9:05f0b5a3a70a	2622	#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /!< Use analog supply with a 7/8 prescaler as reference. /
yihui	9:05f0b5a3a70a	2623	#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /!< Use external analog reference as reference. /
yihui	9:05f0b5a3a70a	2624
yihui	9:05f0b5a3a70a	2625	/* Register: LPCOMP_EXTREFSEL */
yihui	9:05f0b5a3a70a	2626	/* Description: External reference select. */
yihui	9:05f0b5a3a70a	2627
yihui	9:05f0b5a3a70a	2628	/* Bit 0 : External analog reference pin selection. */
yihui	9:05f0b5a3a70a	2629	#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /!< Position of EXTREFSEL field. /
yihui	9:05f0b5a3a70a	2630	#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
yihui	9:05f0b5a3a70a	2631	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /!< Use analog reference 0 as reference. /
yihui	9:05f0b5a3a70a	2632	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /!< Use analog reference 1 as reference. /
yihui	9:05f0b5a3a70a	2633
yihui	9:05f0b5a3a70a	2634	/* Register: LPCOMP_ANADETECT */
yihui	9:05f0b5a3a70a	2635	/* Description: Analog detect configuration. */
yihui	9:05f0b5a3a70a	2636
yihui	9:05f0b5a3a70a	2637	/* Bits 1..0 : Analog detect configuration. */
yihui	9:05f0b5a3a70a	2638	#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /!< Position of ANADETECT field. /
yihui	9:05f0b5a3a70a	2639	#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /!< Bit mask of ANADETECT field. /
yihui	9:05f0b5a3a70a	2640	#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /!< Generate ANADETEC on crossing, both upwards and downwards crossing. /
yihui	9:05f0b5a3a70a	2641	#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /!< Generate ANADETEC on upwards crossing only. /
yihui	9:05f0b5a3a70a	2642	#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /!< Generate ANADETEC on downwards crossing only. /
yihui	9:05f0b5a3a70a	2643
yihui	9:05f0b5a3a70a	2644	/* Register: LPCOMP_POWER */
yihui	9:05f0b5a3a70a	2645	/* Description: Peripheral power control. */
yihui	9:05f0b5a3a70a	2646
yihui	9:05f0b5a3a70a	2647	/* Bit 0 : Peripheral power control. */
yihui	9:05f0b5a3a70a	2648	#define LPCOMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
yihui	9:05f0b5a3a70a	2649	#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
yihui	9:05f0b5a3a70a	2650	#define LPCOMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
yihui	9:05f0b5a3a70a	2651	#define LPCOMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
yihui	9:05f0b5a3a70a	2652
yihui	9:05f0b5a3a70a	2653
yihui	9:05f0b5a3a70a	2654	/* Peripheral: MPU */
yihui	9:05f0b5a3a70a	2655	/* Description: Memory Protection Unit. */
yihui	9:05f0b5a3a70a	2656
yihui	9:05f0b5a3a70a	2657	/* Register: MPU_PERR0 */
yihui	9:05f0b5a3a70a	2658	/* Description: Configuration of peripherals in mpu regions. */
yihui	9:05f0b5a3a70a	2659
yihui	9:05f0b5a3a70a	2660	/* Bit 31 : PPI region configuration. */
yihui	9:05f0b5a3a70a	2661	#define MPU_PERR0_PPI_Pos (31UL) /!< Position of PPI field. /
yihui	9:05f0b5a3a70a	2662	#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /!< Bit mask of PPI field. /
yihui	9:05f0b5a3a70a	2663	#define MPU_PERR0_PPI_InRegion1 (0UL) /!< Peripheral configured in region 1. /
yihui	9:05f0b5a3a70a	2664	#define MPU_PERR0_PPI_InRegion0 (1UL) /!< Peripheral configured in region 0. /
yihui	9:05f0b5a3a70a	2665
yihui	9:05f0b5a3a70a	2666	/* Bit 30 : NVMC region configuration. */
yihui	9:05f0b5a3a70a	2667	#define MPU_PERR0_NVMC_Pos (30UL) /!< Position of NVMC field. /
yihui	9:05f0b5a3a70a	2668	#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /!< Bit mask of NVMC field. /
yihui	9:05f0b5a3a70a	2669	#define MPU_PERR0_NVMC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
yihui	9:05f0b5a3a70a	2670	#define MPU_PERR0_NVMC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
yihui	9:05f0b5a3a70a	2671
yihui	9:05f0b5a3a70a	2672	/* Bit 19 : LPCOMP_COMP region configuration. */
yihui	9:05f0b5a3a70a	2673	#define MPU_PERR0_LPCOMP_COMP_Pos (19UL) /!< Position of LPCOMP_COMP field. /
yihui	9:05f0b5a3a70a	2674	#define MPU_PERR0_LPCOMP_COMP_Msk (0x1UL << MPU_PERR0_LPCOMP_COMP_Pos) /!< Bit mask of LPCOMP_COMP field. /
yihui	9:05f0b5a3a70a	2675	#define MPU_PERR0_LPCOMP_COMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
yihui	9:05f0b5a3a70a	2676	#define MPU_PERR0_LPCOMP_COMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
yihui	9:05f0b5a3a70a	2677
yihui	9:05f0b5a3a70a	2678	/* Bit 18 : QDEC region configuration. */
yihui	9:05f0b5a3a70a	2679	#define MPU_PERR0_QDEC_Pos (18UL) /!< Position of QDEC field. /
yihui	9:05f0b5a3a70a	2680	#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /!< Bit mask of QDEC field. /
yihui	9:05f0b5a3a70a	2681	#define MPU_PERR0_QDEC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
yihui	9:05f0b5a3a70a	2682	#define MPU_PERR0_QDEC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
yihui	9:05f0b5a3a70a	2683
yihui	9:05f0b5a3a70a	2684	/* Bit 17 : RTC1 region configuration. */
yihui	9:05f0b5a3a70a	2685	#define MPU_PERR0_RTC1_Pos (17UL) /!< Position of RTC1 field. /
yihui	9:05f0b5a3a70a	2686	#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /!< Bit mask of RTC1 field. /
yihui	9:05f0b5a3a70a	2687	#define MPU_PERR0_RTC1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
yihui	9:05f0b5a3a70a	2688	#define MPU_PERR0_RTC1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
yihui	9:05f0b5a3a70a	2689
yihui	9:05f0b5a3a70a	2690	/* Bit 16 : WDT region configuration. */
yihui	9:05f0b5a3a70a	2691	#define MPU_PERR0_WDT_Pos (16UL) /!< Position of WDT field. /
yihui	9:05f0b5a3a70a	2692	#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /!< Bit mask of WDT field. /
yihui	9:05f0b5a3a70a	2693	#define MPU_PERR0_WDT_InRegion1 (0UL) /!< Peripheral configured in region 1. /
yihui	9:05f0b5a3a70a	2694	#define MPU_PERR0_WDT_InRegion0 (1UL) /!< Peripheral configured in region 0. /
yihui	9:05f0b5a3a70a	2695
yihui	9:05f0b5a3a70a	2696	/* Bit 15 : CCM and AAR region configuration. */
yihui	9:05f0b5a3a70a	2697	#define MPU_PERR0_CCM_AAR_Pos (15UL) /!< Position of CCM_AAR field. /
yihui	9:05f0b5a3a70a	2698	#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /!< Bit mask of CCM_AAR field. /
yihui	9:05f0b5a3a70a	2699	#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /!< Peripheral configured in region 1. /
yihui	9:05f0b5a3a70a	2700	#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /!< Peripheral configured in region 0. /
yihui	9:05f0b5a3a70a	2701
yihui	9:05f0b5a3a70a	2702	/* Bit 14 : ECB region configuration. */
yihui	9:05f0b5a3a70a	2703	#define MPU_PERR0_ECB_Pos (14UL) /!< Position of ECB field. /
yihui	9:05f0b5a3a70a	2704	#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /!< Bit mask of ECB field. /
yihui	9:05f0b5a3a70a	2705	#define MPU_PERR0_ECB_InRegion1 (0UL) /!< Peripheral configured in region 1. /
yihui	9:05f0b5a3a70a	2706	#define MPU_PERR0_ECB_InRegion0 (1UL) /!< Peripheral configured in region 0. /
yihui	9:05f0b5a3a70a	2707
yihui	9:05f0b5a3a70a	2708	/* Bit 13 : RNG region configuration. */
yihui	9:05f0b5a3a70a	2709	#define MPU_PERR0_RNG_Pos (13UL) /!< Position of RNG field. /
yihui	9:05f0b5a3a70a	2710	#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /!< Bit mask of RNG field. /
yihui	9:05f0b5a3a70a	2711	#define MPU_PERR0_RNG_InRegion1 (0UL) /!< Peripheral configured in region 1. /
yihui	9:05f0b5a3a70a	2712	#define MPU_PERR0_RNG_InRegion0 (1UL) /!< Peripheral configured in region 0. /
yihui	9:05f0b5a3a70a	2713
yihui	9:05f0b5a3a70a	2714	/* Bit 12 : TEMP region configuration. */
yihui	9:05f0b5a3a70a	2715	#define MPU_PERR0_TEMP_Pos (12UL) /!< Position of TEMP field. /
yihui	9:05f0b5a3a70a	2716	#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /!< Bit mask of TEMP field. /
yihui	9:05f0b5a3a70a	2717	#define MPU_PERR0_TEMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
yihui	9:05f0b5a3a70a	2718	#define MPU_PERR0_TEMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
yihui	9:05f0b5a3a70a	2719
yihui	9:05f0b5a3a70a	2720	/* Bit 11 : RTC0 region configuration. */
yihui	9:05f0b5a3a70a	2721	#define MPU_PERR0_RTC0_Pos (11UL) /!< Position of RTC0 field. /
yihui	9:05f0b5a3a70a	2722	#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /!< Bit mask of RTC0 field. /
yihui	9:05f0b5a3a70a	2723	#define MPU_PERR0_RTC0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
yihui	9:05f0b5a3a70a	2724	#define MPU_PERR0_RTC0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
yihui	9:05f0b5a3a70a	2725
yihui	9:05f0b5a3a70a	2726	/* Bit 10 : TIMER2 region configuration. */
yihui	9:05f0b5a3a70a	2727	#define MPU_PERR0_TIMER2_Pos (10UL) /!< Position of TIMER2 field. /
yihui	9:05f0b5a3a70a	2728	#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /!< Bit mask of TIMER2 field. /
yihui	9:05f0b5a3a70a	2729	#define MPU_PERR0_TIMER2_InRegion1 (0UL) /!< Peripheral configured in region 1. /
yihui	9:05f0b5a3a70a	2730	#define MPU_PERR0_TIMER2_InRegion0 (1UL) /!< Peripheral configured in region 0. /
yihui	9:05f0b5a3a70a	2731
yihui	9:05f0b5a3a70a	2732	/* Bit 9 : TIMER1 region configuration. */
yihui	9:05f0b5a3a70a	2733	#define MPU_PERR0_TIMER1_Pos (9UL) /!< Position of TIMER1 field. /
yihui	9:05f0b5a3a70a	2734	#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /!< Bit mask of TIMER1 field. /
yihui	9:05f0b5a3a70a	2735	#define MPU_PERR0_TIMER1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
yihui	9:05f0b5a3a70a	2736	#define MPU_PERR0_TIMER1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
yihui	9:05f0b5a3a70a	2737
yihui	9:05f0b5a3a70a	2738	/* Bit 8 : TIMER0 region configuration. */
yihui	9:05f0b5a3a70a	2739	#define MPU_PERR0_TIMER0_Pos (8UL) /!< Position of TIMER0 field. /
yihui	9:05f0b5a3a70a	2740	#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /!< Bit mask of TIMER0 field. /
yihui	9:05f0b5a3a70a	2741	#define MPU_PERR0_TIMER0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
yihui	9:05f0b5a3a70a	2742	#define MPU_PERR0_TIMER0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
yihui	9:05f0b5a3a70a	2743
yihui	9:05f0b5a3a70a	2744	/* Bit 7 : ADC region configuration. */
yihui	9:05f0b5a3a70a	2745	#define MPU_PERR0_ADC_Pos (7UL) /!< Position of ADC field. /
yihui	9:05f0b5a3a70a	2746	#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /!< Bit mask of ADC field. /
yihui	9:05f0b5a3a70a	2747	#define MPU_PERR0_ADC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
yihui	9:05f0b5a3a70a	2748	#define MPU_PERR0_ADC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
yihui	9:05f0b5a3a70a	2749
yihui	9:05f0b5a3a70a	2750	/* Bit 6 : GPIOTE region configuration. */
yihui	9:05f0b5a3a70a	2751	#define MPU_PERR0_GPIOTE_Pos (6UL) /!< Position of GPIOTE field. /
yihui	9:05f0b5a3a70a	2752	#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /!< Bit mask of GPIOTE field. /
yihui	9:05f0b5a3a70a	2753	#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /!< Peripheral configured in region 1. /
yihui	9:05f0b5a3a70a	2754	#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /!< Peripheral configured in region 0. /
yihui	9:05f0b5a3a70a	2755
yihui	9:05f0b5a3a70a	2756	/* Bit 4 : SPI1 and TWI1 region configuration. */
yihui	9:05f0b5a3a70a	2757	#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /!< Position of SPI1_TWI1 field. /
yihui	9:05f0b5a3a70a	2758	#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /!< Bit mask of SPI1_TWI1 field. /
yihui	9:05f0b5a3a70a	2759	#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
yihui	9:05f0b5a3a70a	2760	#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
yihui	9:05f0b5a3a70a	2761
yihui	9:05f0b5a3a70a	2762	/* Bit 3 : SPI0 and TWI0 region configuration. */
yihui	9:05f0b5a3a70a	2763	#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /!< Position of SPI0_TWI0 field. /
yihui	9:05f0b5a3a70a	2764	#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /!< Bit mask of SPI0_TWI0 field. /
yihui	9:05f0b5a3a70a	2765	#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
yihui	9:05f0b5a3a70a	2766	#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
yihui	9:05f0b5a3a70a	2767
yihui	9:05f0b5a3a70a	2768	/* Bit 2 : UART0 region configuration. */
yihui	9:05f0b5a3a70a	2769	#define MPU_PERR0_UART0_Pos (2UL) /!< Position of UART0 field. /
yihui	9:05f0b5a3a70a	2770	#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /!< Bit mask of UART0 field. /
yihui	9:05f0b5a3a70a	2771	#define MPU_PERR0_UART0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
yihui	9:05f0b5a3a70a	2772	#define MPU_PERR0_UART0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
yihui	9:05f0b5a3a70a	2773
yihui	9:05f0b5a3a70a	2774	/* Bit 1 : RADIO region configuration. */
yihui	9:05f0b5a3a70a	2775	#define MPU_PERR0_RADIO_Pos (1UL) /!< Position of RADIO field. /
yihui	9:05f0b5a3a70a	2776	#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /!< Bit mask of RADIO field. /
yihui	9:05f0b5a3a70a	2777	#define MPU_PERR0_RADIO_InRegion1 (0UL) /!< Peripheral configured in region 1. /
yihui	9:05f0b5a3a70a	2778	#define MPU_PERR0_RADIO_InRegion0 (1UL) /!< Peripheral configured in region 0. /
yihui	9:05f0b5a3a70a	2779
yihui	9:05f0b5a3a70a	2780	/* Bit 0 : POWER_CLOCK region configuration. */
yihui	9:05f0b5a3a70a	2781	#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /!< Position of POWER_CLOCK field. /
yihui	9:05f0b5a3a70a	2782	#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /!< Bit mask of POWER_CLOCK field. /
yihui	9:05f0b5a3a70a	2783	#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /!< Peripheral configured in region 1. /
yihui	9:05f0b5a3a70a	2784	#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /!< Peripheral configured in region 0. /
yihui	9:05f0b5a3a70a	2785
yihui	9:05f0b5a3a70a	2786	/* Register: MPU_PROTENSET0 */
yihui	9:05f0b5a3a70a	2787	/* Description: Protection bit enable set register for low addresses. */
yihui	9:05f0b5a3a70a	2788
yihui	9:05f0b5a3a70a	2789	/* Bit 31 : Protection enable for region 31. */
yihui	9:05f0b5a3a70a	2790	#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /!< Position of PROTREG31 field. /
yihui	9:05f0b5a3a70a	2791	#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /!< Bit mask of PROTREG31 field. /
yihui	9:05f0b5a3a70a	2792	#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2793	#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2794	#define MPU_PROTENSET0_PROTREG31_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2795
yihui	9:05f0b5a3a70a	2796	/* Bit 30 : Protection enable for region 30. */
yihui	9:05f0b5a3a70a	2797	#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /!< Position of PROTREG30 field. /
yihui	9:05f0b5a3a70a	2798	#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /!< Bit mask of PROTREG30 field. /
yihui	9:05f0b5a3a70a	2799	#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2800	#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2801	#define MPU_PROTENSET0_PROTREG30_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2802
yihui	9:05f0b5a3a70a	2803	/* Bit 29 : Protection enable for region 29. */
yihui	9:05f0b5a3a70a	2804	#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /!< Position of PROTREG29 field. /
yihui	9:05f0b5a3a70a	2805	#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /!< Bit mask of PROTREG29 field. /
yihui	9:05f0b5a3a70a	2806	#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2807	#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2808	#define MPU_PROTENSET0_PROTREG29_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2809
yihui	9:05f0b5a3a70a	2810	/* Bit 28 : Protection enable for region 28. */
yihui	9:05f0b5a3a70a	2811	#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /!< Position of PROTREG28 field. /
yihui	9:05f0b5a3a70a	2812	#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /!< Bit mask of PROTREG28 field. /
yihui	9:05f0b5a3a70a	2813	#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2814	#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2815	#define MPU_PROTENSET0_PROTREG28_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2816
yihui	9:05f0b5a3a70a	2817	/* Bit 27 : Protection enable for region 27. */
yihui	9:05f0b5a3a70a	2818	#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /!< Position of PROTREG27 field. /
yihui	9:05f0b5a3a70a	2819	#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /!< Bit mask of PROTREG27 field. /
yihui	9:05f0b5a3a70a	2820	#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2821	#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2822	#define MPU_PROTENSET0_PROTREG27_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2823
yihui	9:05f0b5a3a70a	2824	/* Bit 26 : Protection enable for region 26. */
yihui	9:05f0b5a3a70a	2825	#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /!< Position of PROTREG26 field. /
yihui	9:05f0b5a3a70a	2826	#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /!< Bit mask of PROTREG26 field. /
yihui	9:05f0b5a3a70a	2827	#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2828	#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2829	#define MPU_PROTENSET0_PROTREG26_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2830
yihui	9:05f0b5a3a70a	2831	/* Bit 25 : Protection enable for region 25. */
yihui	9:05f0b5a3a70a	2832	#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /!< Position of PROTREG25 field. /
yihui	9:05f0b5a3a70a	2833	#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /!< Bit mask of PROTREG25 field. /
yihui	9:05f0b5a3a70a	2834	#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2835	#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2836	#define MPU_PROTENSET0_PROTREG25_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2837
yihui	9:05f0b5a3a70a	2838	/* Bit 24 : Protection enable for region 24. */
yihui	9:05f0b5a3a70a	2839	#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /!< Position of PROTREG24 field. /
yihui	9:05f0b5a3a70a	2840	#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /!< Bit mask of PROTREG24 field. /
yihui	9:05f0b5a3a70a	2841	#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2842	#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2843	#define MPU_PROTENSET0_PROTREG24_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2844
yihui	9:05f0b5a3a70a	2845	/* Bit 23 : Protection enable for region 23. */
yihui	9:05f0b5a3a70a	2846	#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /!< Position of PROTREG23 field. /
yihui	9:05f0b5a3a70a	2847	#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /!< Bit mask of PROTREG23 field. /
yihui	9:05f0b5a3a70a	2848	#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2849	#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2850	#define MPU_PROTENSET0_PROTREG23_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2851
yihui	9:05f0b5a3a70a	2852	/* Bit 22 : Protection enable for region 22. */
yihui	9:05f0b5a3a70a	2853	#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /!< Position of PROTREG22 field. /
yihui	9:05f0b5a3a70a	2854	#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /!< Bit mask of PROTREG22 field. /
yihui	9:05f0b5a3a70a	2855	#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2856	#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2857	#define MPU_PROTENSET0_PROTREG22_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2858
yihui	9:05f0b5a3a70a	2859	/* Bit 21 : Protection enable for region 21. */
yihui	9:05f0b5a3a70a	2860	#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /!< Position of PROTREG21 field. /
yihui	9:05f0b5a3a70a	2861	#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /!< Bit mask of PROTREG21 field. /
yihui	9:05f0b5a3a70a	2862	#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2863	#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2864	#define MPU_PROTENSET0_PROTREG21_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2865
yihui	9:05f0b5a3a70a	2866	/* Bit 20 : Protection enable for region 20. */
yihui	9:05f0b5a3a70a	2867	#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /!< Position of PROTREG20 field. /
yihui	9:05f0b5a3a70a	2868	#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /!< Bit mask of PROTREG20 field. /
yihui	9:05f0b5a3a70a	2869	#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2870	#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2871	#define MPU_PROTENSET0_PROTREG20_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2872
yihui	9:05f0b5a3a70a	2873	/* Bit 19 : Protection enable for region 19. */
yihui	9:05f0b5a3a70a	2874	#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /!< Position of PROTREG19 field. /
yihui	9:05f0b5a3a70a	2875	#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /!< Bit mask of PROTREG19 field. /
yihui	9:05f0b5a3a70a	2876	#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2877	#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2878	#define MPU_PROTENSET0_PROTREG19_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2879
yihui	9:05f0b5a3a70a	2880	/* Bit 18 : Protection enable for region 18. */
yihui	9:05f0b5a3a70a	2881	#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /!< Position of PROTREG18 field. /
yihui	9:05f0b5a3a70a	2882	#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /!< Bit mask of PROTREG18 field. /
yihui	9:05f0b5a3a70a	2883	#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2884	#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2885	#define MPU_PROTENSET0_PROTREG18_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2886
yihui	9:05f0b5a3a70a	2887	/* Bit 17 : Protection enable for region 17. */
yihui	9:05f0b5a3a70a	2888	#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /!< Position of PROTREG17 field. /
yihui	9:05f0b5a3a70a	2889	#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /!< Bit mask of PROTREG17 field. /
yihui	9:05f0b5a3a70a	2890	#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2891	#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2892	#define MPU_PROTENSET0_PROTREG17_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2893
yihui	9:05f0b5a3a70a	2894	/* Bit 16 : Protection enable for region 16. */
yihui	9:05f0b5a3a70a	2895	#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /!< Position of PROTREG16 field. /
yihui	9:05f0b5a3a70a	2896	#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /!< Bit mask of PROTREG16 field. /
yihui	9:05f0b5a3a70a	2897	#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2898	#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2899	#define MPU_PROTENSET0_PROTREG16_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2900
yihui	9:05f0b5a3a70a	2901	/* Bit 15 : Protection enable for region 15. */
yihui	9:05f0b5a3a70a	2902	#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /!< Position of PROTREG15 field. /
yihui	9:05f0b5a3a70a	2903	#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /!< Bit mask of PROTREG15 field. /
yihui	9:05f0b5a3a70a	2904	#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2905	#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2906	#define MPU_PROTENSET0_PROTREG15_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2907
yihui	9:05f0b5a3a70a	2908	/* Bit 14 : Protection enable for region 14. */
yihui	9:05f0b5a3a70a	2909	#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /!< Position of PROTREG14 field. /
yihui	9:05f0b5a3a70a	2910	#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /!< Bit mask of PROTREG14 field. /
yihui	9:05f0b5a3a70a	2911	#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2912	#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2913	#define MPU_PROTENSET0_PROTREG14_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2914
yihui	9:05f0b5a3a70a	2915	/* Bit 13 : Protection enable for region 13. */
yihui	9:05f0b5a3a70a	2916	#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /!< Position of PROTREG13 field. /
yihui	9:05f0b5a3a70a	2917	#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /!< Bit mask of PROTREG13 field. /
yihui	9:05f0b5a3a70a	2918	#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2919	#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2920	#define MPU_PROTENSET0_PROTREG13_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2921
yihui	9:05f0b5a3a70a	2922	/* Bit 12 : Protection enable for region 12. */
yihui	9:05f0b5a3a70a	2923	#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /!< Position of PROTREG12 field. /
yihui	9:05f0b5a3a70a	2924	#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /!< Bit mask of PROTREG12 field. /
yihui	9:05f0b5a3a70a	2925	#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2926	#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2927	#define MPU_PROTENSET0_PROTREG12_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2928
yihui	9:05f0b5a3a70a	2929	/* Bit 11 : Protection enable for region 11. */
yihui	9:05f0b5a3a70a	2930	#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /!< Position of PROTREG11 field. /
yihui	9:05f0b5a3a70a	2931	#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /!< Bit mask of PROTREG11 field. /
yihui	9:05f0b5a3a70a	2932	#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2933	#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2934	#define MPU_PROTENSET0_PROTREG11_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2935
yihui	9:05f0b5a3a70a	2936	/* Bit 10 : Protection enable for region 10. */
yihui	9:05f0b5a3a70a	2937	#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /!< Position of PROTREG10 field. /
yihui	9:05f0b5a3a70a	2938	#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /!< Bit mask of PROTREG10 field. /
yihui	9:05f0b5a3a70a	2939	#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2940	#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2941	#define MPU_PROTENSET0_PROTREG10_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2942
yihui	9:05f0b5a3a70a	2943	/* Bit 9 : Protection enable for region 9. */
yihui	9:05f0b5a3a70a	2944	#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /!< Position of PROTREG9 field. /
yihui	9:05f0b5a3a70a	2945	#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /!< Bit mask of PROTREG9 field. /
yihui	9:05f0b5a3a70a	2946	#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2947	#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2948	#define MPU_PROTENSET0_PROTREG9_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2949
yihui	9:05f0b5a3a70a	2950	/* Bit 8 : Protection enable for region 8. */
yihui	9:05f0b5a3a70a	2951	#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /!< Position of PROTREG8 field. /
yihui	9:05f0b5a3a70a	2952	#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /!< Bit mask of PROTREG8 field. /
yihui	9:05f0b5a3a70a	2953	#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2954	#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2955	#define MPU_PROTENSET0_PROTREG8_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2956
yihui	9:05f0b5a3a70a	2957	/* Bit 7 : Protection enable for region 7. */
yihui	9:05f0b5a3a70a	2958	#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /!< Position of PROTREG7 field. /
yihui	9:05f0b5a3a70a	2959	#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /!< Bit mask of PROTREG7 field. /
yihui	9:05f0b5a3a70a	2960	#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2961	#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2962	#define MPU_PROTENSET0_PROTREG7_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2963
yihui	9:05f0b5a3a70a	2964	/* Bit 6 : Protection enable for region 6. */
yihui	9:05f0b5a3a70a	2965	#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /!< Position of PROTREG6 field. /
yihui	9:05f0b5a3a70a	2966	#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /!< Bit mask of PROTREG6 field. /
yihui	9:05f0b5a3a70a	2967	#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2968	#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2969	#define MPU_PROTENSET0_PROTREG6_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2970
yihui	9:05f0b5a3a70a	2971	/* Bit 5 : Protection enable for region 5. */
yihui	9:05f0b5a3a70a	2972	#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /!< Position of PROTREG5 field. /
yihui	9:05f0b5a3a70a	2973	#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /!< Bit mask of PROTREG5 field. /
yihui	9:05f0b5a3a70a	2974	#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2975	#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2976	#define MPU_PROTENSET0_PROTREG5_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2977
yihui	9:05f0b5a3a70a	2978	/* Bit 4 : Protection enable for region 4. */
yihui	9:05f0b5a3a70a	2979	#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /!< Position of PROTREG4 field. /
yihui	9:05f0b5a3a70a	2980	#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /!< Bit mask of PROTREG4 field. /
yihui	9:05f0b5a3a70a	2981	#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2982	#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2983	#define MPU_PROTENSET0_PROTREG4_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2984
yihui	9:05f0b5a3a70a	2985	/* Bit 3 : Protection enable for region 3. */
yihui	9:05f0b5a3a70a	2986	#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /!< Position of PROTREG3 field. /
yihui	9:05f0b5a3a70a	2987	#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /!< Bit mask of PROTREG3 field. /
yihui	9:05f0b5a3a70a	2988	#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2989	#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2990	#define MPU_PROTENSET0_PROTREG3_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2991
yihui	9:05f0b5a3a70a	2992	/* Bit 2 : Protection enable for region 2. */
yihui	9:05f0b5a3a70a	2993	#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /!< Position of PROTREG2 field. /
yihui	9:05f0b5a3a70a	2994	#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /!< Bit mask of PROTREG2 field. /
yihui	9:05f0b5a3a70a	2995	#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	2996	#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	2997	#define MPU_PROTENSET0_PROTREG2_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	2998
yihui	9:05f0b5a3a70a	2999	/* Bit 1 : Protection enable for region 1. */
yihui	9:05f0b5a3a70a	3000	#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /!< Position of PROTREG1 field. /
yihui	9:05f0b5a3a70a	3001	#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /!< Bit mask of PROTREG1 field. /
yihui	9:05f0b5a3a70a	3002	#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3003	#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3004	#define MPU_PROTENSET0_PROTREG1_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3005
yihui	9:05f0b5a3a70a	3006	/* Bit 0 : Protection enable for region 0. */
yihui	9:05f0b5a3a70a	3007	#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /!< Position of PROTREG0 field. /
yihui	9:05f0b5a3a70a	3008	#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /!< Bit mask of PROTREG0 field. /
yihui	9:05f0b5a3a70a	3009	#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3010	#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3011	#define MPU_PROTENSET0_PROTREG0_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3012
yihui	9:05f0b5a3a70a	3013	/* Register: MPU_PROTENSET1 */
yihui	9:05f0b5a3a70a	3014	/* Description: Protection bit enable set register for high addresses. */
yihui	9:05f0b5a3a70a	3015
yihui	9:05f0b5a3a70a	3016	/* Bit 31 : Protection enable for region 63. */
yihui	9:05f0b5a3a70a	3017	#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /!< Position of PROTREG63 field. /
yihui	9:05f0b5a3a70a	3018	#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /!< Bit mask of PROTREG63 field. /
yihui	9:05f0b5a3a70a	3019	#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3020	#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3021	#define MPU_PROTENSET1_PROTREG63_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3022
yihui	9:05f0b5a3a70a	3023	/* Bit 30 : Protection enable for region 62. */
yihui	9:05f0b5a3a70a	3024	#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /!< Position of PROTREG62 field. /
yihui	9:05f0b5a3a70a	3025	#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /!< Bit mask of PROTREG62 field. /
yihui	9:05f0b5a3a70a	3026	#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3027	#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3028	#define MPU_PROTENSET1_PROTREG62_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3029
yihui	9:05f0b5a3a70a	3030	/* Bit 29 : Protection enable for region 61. */
yihui	9:05f0b5a3a70a	3031	#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /!< Position of PROTREG61 field. /
yihui	9:05f0b5a3a70a	3032	#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /!< Bit mask of PROTREG61 field. /
yihui	9:05f0b5a3a70a	3033	#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3034	#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3035	#define MPU_PROTENSET1_PROTREG61_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3036
yihui	9:05f0b5a3a70a	3037	/* Bit 28 : Protection enable for region 60. */
yihui	9:05f0b5a3a70a	3038	#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /!< Position of PROTREG60 field. /
yihui	9:05f0b5a3a70a	3039	#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /!< Bit mask of PROTREG60 field. /
yihui	9:05f0b5a3a70a	3040	#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3041	#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3042	#define MPU_PROTENSET1_PROTREG60_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3043
yihui	9:05f0b5a3a70a	3044	/* Bit 27 : Protection enable for region 59. */
yihui	9:05f0b5a3a70a	3045	#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /!< Position of PROTREG59 field. /
yihui	9:05f0b5a3a70a	3046	#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /!< Bit mask of PROTREG59 field. /
yihui	9:05f0b5a3a70a	3047	#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3048	#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3049	#define MPU_PROTENSET1_PROTREG59_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3050
yihui	9:05f0b5a3a70a	3051	/* Bit 26 : Protection enable for region 58. */
yihui	9:05f0b5a3a70a	3052	#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /!< Position of PROTREG58 field. /
yihui	9:05f0b5a3a70a	3053	#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /!< Bit mask of PROTREG58 field. /
yihui	9:05f0b5a3a70a	3054	#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3055	#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3056	#define MPU_PROTENSET1_PROTREG58_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3057
yihui	9:05f0b5a3a70a	3058	/* Bit 25 : Protection enable for region 57. */
yihui	9:05f0b5a3a70a	3059	#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /!< Position of PROTREG57 field. /
yihui	9:05f0b5a3a70a	3060	#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /!< Bit mask of PROTREG57 field. /
yihui	9:05f0b5a3a70a	3061	#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3062	#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3063	#define MPU_PROTENSET1_PROTREG57_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3064
yihui	9:05f0b5a3a70a	3065	/* Bit 24 : Protection enable for region 56. */
yihui	9:05f0b5a3a70a	3066	#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /!< Position of PROTREG56 field. /
yihui	9:05f0b5a3a70a	3067	#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /!< Bit mask of PROTREG56 field. /
yihui	9:05f0b5a3a70a	3068	#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3069	#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3070	#define MPU_PROTENSET1_PROTREG56_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3071
yihui	9:05f0b5a3a70a	3072	/* Bit 23 : Protection enable for region 55. */
yihui	9:05f0b5a3a70a	3073	#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /!< Position of PROTREG55 field. /
yihui	9:05f0b5a3a70a	3074	#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /!< Bit mask of PROTREG55 field. /
yihui	9:05f0b5a3a70a	3075	#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3076	#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3077	#define MPU_PROTENSET1_PROTREG55_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3078
yihui	9:05f0b5a3a70a	3079	/* Bit 22 : Protection enable for region 54. */
yihui	9:05f0b5a3a70a	3080	#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /!< Position of PROTREG54 field. /
yihui	9:05f0b5a3a70a	3081	#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /!< Bit mask of PROTREG54 field. /
yihui	9:05f0b5a3a70a	3082	#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3083	#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3084	#define MPU_PROTENSET1_PROTREG54_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3085
yihui	9:05f0b5a3a70a	3086	/* Bit 21 : Protection enable for region 53. */
yihui	9:05f0b5a3a70a	3087	#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /!< Position of PROTREG53 field. /
yihui	9:05f0b5a3a70a	3088	#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /!< Bit mask of PROTREG53 field. /
yihui	9:05f0b5a3a70a	3089	#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3090	#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3091	#define MPU_PROTENSET1_PROTREG53_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3092
yihui	9:05f0b5a3a70a	3093	/* Bit 20 : Protection enable for region 52. */
yihui	9:05f0b5a3a70a	3094	#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /!< Position of PROTREG52 field. /
yihui	9:05f0b5a3a70a	3095	#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /!< Bit mask of PROTREG52 field. /
yihui	9:05f0b5a3a70a	3096	#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3097	#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3098	#define MPU_PROTENSET1_PROTREG52_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3099
yihui	9:05f0b5a3a70a	3100	/* Bit 19 : Protection enable for region 51. */
yihui	9:05f0b5a3a70a	3101	#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /!< Position of PROTREG51 field. /
yihui	9:05f0b5a3a70a	3102	#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /!< Bit mask of PROTREG51 field. /
yihui	9:05f0b5a3a70a	3103	#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3104	#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3105	#define MPU_PROTENSET1_PROTREG51_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3106
yihui	9:05f0b5a3a70a	3107	/* Bit 18 : Protection enable for region 50. */
yihui	9:05f0b5a3a70a	3108	#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /!< Position of PROTREG50 field. /
yihui	9:05f0b5a3a70a	3109	#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /!< Bit mask of PROTREG50 field. /
yihui	9:05f0b5a3a70a	3110	#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3111	#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3112	#define MPU_PROTENSET1_PROTREG50_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3113
yihui	9:05f0b5a3a70a	3114	/* Bit 17 : Protection enable for region 49. */
yihui	9:05f0b5a3a70a	3115	#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /!< Position of PROTREG49 field. /
yihui	9:05f0b5a3a70a	3116	#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /!< Bit mask of PROTREG49 field. /
yihui	9:05f0b5a3a70a	3117	#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3118	#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3119	#define MPU_PROTENSET1_PROTREG49_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3120
yihui	9:05f0b5a3a70a	3121	/* Bit 16 : Protection enable for region 48. */
yihui	9:05f0b5a3a70a	3122	#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /!< Position of PROTREG48 field. /
yihui	9:05f0b5a3a70a	3123	#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /!< Bit mask of PROTREG48 field. /
yihui	9:05f0b5a3a70a	3124	#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3125	#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3126	#define MPU_PROTENSET1_PROTREG48_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3127
yihui	9:05f0b5a3a70a	3128	/* Bit 15 : Protection enable for region 47. */
yihui	9:05f0b5a3a70a	3129	#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /!< Position of PROTREG47 field. /
yihui	9:05f0b5a3a70a	3130	#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /!< Bit mask of PROTREG47 field. /
yihui	9:05f0b5a3a70a	3131	#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3132	#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3133	#define MPU_PROTENSET1_PROTREG47_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3134
yihui	9:05f0b5a3a70a	3135	/* Bit 14 : Protection enable for region 46. */
yihui	9:05f0b5a3a70a	3136	#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /!< Position of PROTREG46 field. /
yihui	9:05f0b5a3a70a	3137	#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /!< Bit mask of PROTREG46 field. /
yihui	9:05f0b5a3a70a	3138	#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3139	#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3140	#define MPU_PROTENSET1_PROTREG46_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3141
yihui	9:05f0b5a3a70a	3142	/* Bit 13 : Protection enable for region 45. */
yihui	9:05f0b5a3a70a	3143	#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /!< Position of PROTREG45 field. /
yihui	9:05f0b5a3a70a	3144	#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /!< Bit mask of PROTREG45 field. /
yihui	9:05f0b5a3a70a	3145	#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3146	#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3147	#define MPU_PROTENSET1_PROTREG45_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3148
yihui	9:05f0b5a3a70a	3149	/* Bit 12 : Protection enable for region 44. */
yihui	9:05f0b5a3a70a	3150	#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /!< Position of PROTREG44 field. /
yihui	9:05f0b5a3a70a	3151	#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /!< Bit mask of PROTREG44 field. /
yihui	9:05f0b5a3a70a	3152	#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3153	#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3154	#define MPU_PROTENSET1_PROTREG44_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3155
yihui	9:05f0b5a3a70a	3156	/* Bit 11 : Protection enable for region 43. */
yihui	9:05f0b5a3a70a	3157	#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /!< Position of PROTREG43 field. /
yihui	9:05f0b5a3a70a	3158	#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /!< Bit mask of PROTREG43 field. /
yihui	9:05f0b5a3a70a	3159	#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3160	#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3161	#define MPU_PROTENSET1_PROTREG43_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3162
yihui	9:05f0b5a3a70a	3163	/* Bit 10 : Protection enable for region 42. */
yihui	9:05f0b5a3a70a	3164	#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /!< Position of PROTREG42 field. /
yihui	9:05f0b5a3a70a	3165	#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /!< Bit mask of PROTREG42 field. /
yihui	9:05f0b5a3a70a	3166	#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3167	#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3168	#define MPU_PROTENSET1_PROTREG42_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3169
yihui	9:05f0b5a3a70a	3170	/* Bit 9 : Protection enable for region 41. */
yihui	9:05f0b5a3a70a	3171	#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /!< Position of PROTREG41 field. /
yihui	9:05f0b5a3a70a	3172	#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /!< Bit mask of PROTREG41 field. /
yihui	9:05f0b5a3a70a	3173	#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3174	#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3175	#define MPU_PROTENSET1_PROTREG41_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3176
yihui	9:05f0b5a3a70a	3177	/* Bit 8 : Protection enable for region 40. */
yihui	9:05f0b5a3a70a	3178	#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /!< Position of PROTREG40 field. /
yihui	9:05f0b5a3a70a	3179	#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /!< Bit mask of PROTREG40 field. /
yihui	9:05f0b5a3a70a	3180	#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3181	#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3182	#define MPU_PROTENSET1_PROTREG40_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3183
yihui	9:05f0b5a3a70a	3184	/* Bit 7 : Protection enable for region 39. */
yihui	9:05f0b5a3a70a	3185	#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /!< Position of PROTREG39 field. /
yihui	9:05f0b5a3a70a	3186	#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /!< Bit mask of PROTREG39 field. /
yihui	9:05f0b5a3a70a	3187	#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3188	#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3189	#define MPU_PROTENSET1_PROTREG39_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3190
yihui	9:05f0b5a3a70a	3191	/* Bit 6 : Protection enable for region 38. */
yihui	9:05f0b5a3a70a	3192	#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /!< Position of PROTREG38 field. /
yihui	9:05f0b5a3a70a	3193	#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /!< Bit mask of PROTREG38 field. /
yihui	9:05f0b5a3a70a	3194	#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3195	#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3196	#define MPU_PROTENSET1_PROTREG38_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3197
yihui	9:05f0b5a3a70a	3198	/* Bit 5 : Protection enable for region 37. */
yihui	9:05f0b5a3a70a	3199	#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /!< Position of PROTREG37 field. /
yihui	9:05f0b5a3a70a	3200	#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /!< Bit mask of PROTREG37 field. /
yihui	9:05f0b5a3a70a	3201	#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3202	#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3203	#define MPU_PROTENSET1_PROTREG37_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3204
yihui	9:05f0b5a3a70a	3205	/* Bit 4 : Protection enable for region 36. */
yihui	9:05f0b5a3a70a	3206	#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /!< Position of PROTREG36 field. /
yihui	9:05f0b5a3a70a	3207	#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /!< Bit mask of PROTREG36 field. /
yihui	9:05f0b5a3a70a	3208	#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3209	#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3210	#define MPU_PROTENSET1_PROTREG36_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3211
yihui	9:05f0b5a3a70a	3212	/* Bit 3 : Protection enable for region 35. */
yihui	9:05f0b5a3a70a	3213	#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /!< Position of PROTREG35 field. /
yihui	9:05f0b5a3a70a	3214	#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /!< Bit mask of PROTREG35 field. /
yihui	9:05f0b5a3a70a	3215	#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3216	#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3217	#define MPU_PROTENSET1_PROTREG35_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3218
yihui	9:05f0b5a3a70a	3219	/* Bit 2 : Protection enable for region 34. */
yihui	9:05f0b5a3a70a	3220	#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /!< Position of PROTREG34 field. /
yihui	9:05f0b5a3a70a	3221	#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /!< Bit mask of PROTREG34 field. /
yihui	9:05f0b5a3a70a	3222	#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3223	#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3224	#define MPU_PROTENSET1_PROTREG34_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3225
yihui	9:05f0b5a3a70a	3226	/* Bit 1 : Protection enable for region 33. */
yihui	9:05f0b5a3a70a	3227	#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /!< Position of PROTREG33 field. /
yihui	9:05f0b5a3a70a	3228	#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /!< Bit mask of PROTREG33 field. /
yihui	9:05f0b5a3a70a	3229	#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3230	#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3231	#define MPU_PROTENSET1_PROTREG33_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3232
yihui	9:05f0b5a3a70a	3233	/* Bit 0 : Protection enable for region 32. */
yihui	9:05f0b5a3a70a	3234	#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /!< Position of PROTREG32 field. /
yihui	9:05f0b5a3a70a	3235	#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /!< Bit mask of PROTREG32 field. /
yihui	9:05f0b5a3a70a	3236	#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3237	#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3238	#define MPU_PROTENSET1_PROTREG32_Set (1UL) /!< Enable protection on write. /
yihui	9:05f0b5a3a70a	3239
yihui	9:05f0b5a3a70a	3240	/* Register: MPU_DISABLEINDEBUG */
yihui	9:05f0b5a3a70a	3241	/* Description: Disable protection mechanism in debug mode. */
yihui	9:05f0b5a3a70a	3242
yihui	9:05f0b5a3a70a	3243	/* Bit 0 : Disable protection mechanism in debug mode. */
yihui	9:05f0b5a3a70a	3244	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /!< Position of DISABLEINDEBUG field. /
yihui	9:05f0b5a3a70a	3245	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /!< Bit mask of DISABLEINDEBUG field. /
yihui	9:05f0b5a3a70a	3246	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /!< Protection enabled. /
yihui	9:05f0b5a3a70a	3247	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /!< Protection disabled. /
yihui	9:05f0b5a3a70a	3248
yihui	9:05f0b5a3a70a	3249
yihui	9:05f0b5a3a70a	3250	/* Peripheral: NVMC */
yihui	9:05f0b5a3a70a	3251	/* Description: Non Volatile Memory Controller. */
yihui	9:05f0b5a3a70a	3252
yihui	9:05f0b5a3a70a	3253	/* Register: NVMC_READY */
yihui	9:05f0b5a3a70a	3254	/* Description: Ready flag. */
yihui	9:05f0b5a3a70a	3255
yihui	9:05f0b5a3a70a	3256	/* Bit 0 : NVMC ready. */
yihui	9:05f0b5a3a70a	3257	#define NVMC_READY_READY_Pos (0UL) /!< Position of READY field. /
yihui	9:05f0b5a3a70a	3258	#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /!< Bit mask of READY field. /
yihui	9:05f0b5a3a70a	3259	#define NVMC_READY_READY_Busy (0UL) /!< NVMC is busy (on-going write or erase operation). /
yihui	9:05f0b5a3a70a	3260	#define NVMC_READY_READY_Ready (1UL) /!< NVMC is ready. /
yihui	9:05f0b5a3a70a	3261
yihui	9:05f0b5a3a70a	3262	/* Register: NVMC_CONFIG */
yihui	9:05f0b5a3a70a	3263	/* Description: Configuration register. */
yihui	9:05f0b5a3a70a	3264
yihui	9:05f0b5a3a70a	3265	/* Bits 1..0 : Program write enable. */
yihui	9:05f0b5a3a70a	3266	#define NVMC_CONFIG_WEN_Pos (0UL) /!< Position of WEN field. /
yihui	9:05f0b5a3a70a	3267	#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /!< Bit mask of WEN field. /
yihui	9:05f0b5a3a70a	3268	#define NVMC_CONFIG_WEN_Ren (0x00UL) /!< Read only access. /
yihui	9:05f0b5a3a70a	3269	#define NVMC_CONFIG_WEN_Wen (0x01UL) /!< Write enabled. /
yihui	9:05f0b5a3a70a	3270	#define NVMC_CONFIG_WEN_Een (0x02UL) /!< Erase enabled. /
yihui	9:05f0b5a3a70a	3271
yihui	9:05f0b5a3a70a	3272	/* Register: NVMC_ERASEALL */
yihui	9:05f0b5a3a70a	3273	/* Description: Register for erasing all non-volatile user memory. */
yihui	9:05f0b5a3a70a	3274
yihui	9:05f0b5a3a70a	3275	/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
yihui	9:05f0b5a3a70a	3276	#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /!< Position of ERASEALL field. /
yihui	9:05f0b5a3a70a	3277	#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /!< Bit mask of ERASEALL field. /
yihui	9:05f0b5a3a70a	3278	#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /!< No operation. /
yihui	9:05f0b5a3a70a	3279	#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /!< Start chip erase. /
yihui	9:05f0b5a3a70a	3280
yihui	9:05f0b5a3a70a	3281	/* Register: NVMC_ERASEUICR */
yihui	9:05f0b5a3a70a	3282	/* Description: Register for start erasing User Information Congfiguration Registers. */
yihui	9:05f0b5a3a70a	3283
yihui	9:05f0b5a3a70a	3284	/* Bit 0 : It can only be used when all contents of code region 1 are erased. */
yihui	9:05f0b5a3a70a	3285	#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /!< Position of ERASEUICR field. /
yihui	9:05f0b5a3a70a	3286	#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /!< Bit mask of ERASEUICR field. /
yihui	9:05f0b5a3a70a	3287	#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /!< No operation. /
yihui	9:05f0b5a3a70a	3288	#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /!< Start UICR erase. /
yihui	9:05f0b5a3a70a	3289
yihui	9:05f0b5a3a70a	3290
yihui	9:05f0b5a3a70a	3291	/* Peripheral: POWER */
yihui	9:05f0b5a3a70a	3292	/* Description: Power Control. */
yihui	9:05f0b5a3a70a	3293
yihui	9:05f0b5a3a70a	3294	/* Register: POWER_INTENSET */
yihui	9:05f0b5a3a70a	3295	/* Description: Interrupt enable set register. */
yihui	9:05f0b5a3a70a	3296
yihui	9:05f0b5a3a70a	3297	/* Bit 2 : Enable interrupt on POFWARN event. */
yihui	9:05f0b5a3a70a	3298	#define POWER_INTENSET_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
yihui	9:05f0b5a3a70a	3299	#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /!< Bit mask of POFWARN field. /
yihui	9:05f0b5a3a70a	3300	#define POWER_INTENSET_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	3301	#define POWER_INTENSET_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	3302	#define POWER_INTENSET_POFWARN_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	3303
yihui	9:05f0b5a3a70a	3304	/* Register: POWER_INTENCLR */
yihui	9:05f0b5a3a70a	3305	/* Description: Interrupt enable clear register. */
yihui	9:05f0b5a3a70a	3306
yihui	9:05f0b5a3a70a	3307	/* Bit 2 : Disable interrupt on POFWARN event. */
yihui	9:05f0b5a3a70a	3308	#define POWER_INTENCLR_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
yihui	9:05f0b5a3a70a	3309	#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /!< Bit mask of POFWARN field. /
yihui	9:05f0b5a3a70a	3310	#define POWER_INTENCLR_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	3311	#define POWER_INTENCLR_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	3312	#define POWER_INTENCLR_POFWARN_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	3313
yihui	9:05f0b5a3a70a	3314	/* Register: POWER_RESETREAS */
yihui	9:05f0b5a3a70a	3315	/* Description: Reset reason. */
yihui	9:05f0b5a3a70a	3316
yihui	9:05f0b5a3a70a	3317	/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
yihui	9:05f0b5a3a70a	3318	#define POWER_RESETREAS_DIF_Pos (18UL) /!< Position of DIF field. /
yihui	9:05f0b5a3a70a	3319	#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /!< Bit mask of DIF field. /
yihui	9:05f0b5a3a70a	3320
yihui	9:05f0b5a3a70a	3321	/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
yihui	9:05f0b5a3a70a	3322	#define POWER_RESETREAS_LPCOMP_Pos (17UL) /!< Position of LPCOMP field. /
yihui	9:05f0b5a3a70a	3323	#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
yihui	9:05f0b5a3a70a	3324
yihui	9:05f0b5a3a70a	3325	/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
yihui	9:05f0b5a3a70a	3326	#define POWER_RESETREAS_OFF_Pos (16UL) /!< Position of OFF field. /
yihui	9:05f0b5a3a70a	3327	#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /!< Bit mask of OFF field. /
yihui	9:05f0b5a3a70a	3328
yihui	9:05f0b5a3a70a	3329	/* Bit 3 : Reset from CPU lock-up detected. */
yihui	9:05f0b5a3a70a	3330	#define POWER_RESETREAS_LOCKUP_Pos (3UL) /!< Position of LOCKUP field. /
yihui	9:05f0b5a3a70a	3331	#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /!< Bit mask of LOCKUP field. /
yihui	9:05f0b5a3a70a	3332
yihui	9:05f0b5a3a70a	3333	/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
yihui	9:05f0b5a3a70a	3334	#define POWER_RESETREAS_SREQ_Pos (2UL) /!< Position of SREQ field. /
yihui	9:05f0b5a3a70a	3335	#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /!< Bit mask of SREQ field. /
yihui	9:05f0b5a3a70a	3336
yihui	9:05f0b5a3a70a	3337	/* Bit 1 : Reset from watchdog detected. */
yihui	9:05f0b5a3a70a	3338	#define POWER_RESETREAS_DOG_Pos (1UL) /!< Position of DOG field. /
yihui	9:05f0b5a3a70a	3339	#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /!< Bit mask of DOG field. /
yihui	9:05f0b5a3a70a	3340
yihui	9:05f0b5a3a70a	3341	/* Bit 0 : Reset from pin-reset detected. */
yihui	9:05f0b5a3a70a	3342	#define POWER_RESETREAS_RESETPIN_Pos (0UL) /!< Position of RESETPIN field. /
yihui	9:05f0b5a3a70a	3343	#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /!< Bit mask of RESETPIN field. /
yihui	9:05f0b5a3a70a	3344
yihui	9:05f0b5a3a70a	3345	/* Register: POWER_SYSTEMOFF */
yihui	9:05f0b5a3a70a	3346	/* Description: System off register. */
yihui	9:05f0b5a3a70a	3347
yihui	9:05f0b5a3a70a	3348	/* Bit 0 : Enter system off mode. */
yihui	9:05f0b5a3a70a	3349	#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /!< Position of SYSTEMOFF field. /
yihui	9:05f0b5a3a70a	3350	#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /!< Bit mask of SYSTEMOFF field. /
yihui	9:05f0b5a3a70a	3351	#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /!< Enter system off mode. /
yihui	9:05f0b5a3a70a	3352
yihui	9:05f0b5a3a70a	3353	/* Register: POWER_POFCON */
yihui	9:05f0b5a3a70a	3354	/* Description: Power failure configuration. */
yihui	9:05f0b5a3a70a	3355
yihui	9:05f0b5a3a70a	3356	/* Bits 2..1 : Set threshold level. */
yihui	9:05f0b5a3a70a	3357	#define POWER_POFCON_THRESHOLD_Pos (1UL) /!< Position of THRESHOLD field. /
yihui	9:05f0b5a3a70a	3358	#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /!< Bit mask of THRESHOLD field. /
yihui	9:05f0b5a3a70a	3359	#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /!< Set threshold to 2.1Volts. /
yihui	9:05f0b5a3a70a	3360	#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /!< Set threshold to 2.3Volts. /
yihui	9:05f0b5a3a70a	3361	#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /!< Set threshold to 2.5Volts. /
yihui	9:05f0b5a3a70a	3362	#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /!< Set threshold to 2.7Volts. /
yihui	9:05f0b5a3a70a	3363
yihui	9:05f0b5a3a70a	3364	/* Bit 0 : Power failure comparator enable. */
yihui	9:05f0b5a3a70a	3365	#define POWER_POFCON_POF_Pos (0UL) /!< Position of POF field. /
yihui	9:05f0b5a3a70a	3366	#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /!< Bit mask of POF field. /
yihui	9:05f0b5a3a70a	3367	#define POWER_POFCON_POF_Disabled (0UL) /!< Disabled. /
yihui	9:05f0b5a3a70a	3368	#define POWER_POFCON_POF_Enabled (1UL) /!< Enabled. /
yihui	9:05f0b5a3a70a	3369
yihui	9:05f0b5a3a70a	3370	/* Register: POWER_GPREGRET */
yihui	9:05f0b5a3a70a	3371	/* Description: General purpose retention register. This register is a retained register. */
yihui	9:05f0b5a3a70a	3372
yihui	9:05f0b5a3a70a	3373	/* Bits 7..0 : General purpose retention register. */
yihui	9:05f0b5a3a70a	3374	#define POWER_GPREGRET_GPREGRET_Pos (0UL) /!< Position of GPREGRET field. /
yihui	9:05f0b5a3a70a	3375	#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /!< Bit mask of GPREGRET field. /
yihui	9:05f0b5a3a70a	3376
yihui	9:05f0b5a3a70a	3377	/* Register: POWER_RAMON */
yihui	9:05f0b5a3a70a	3378	/* Description: Ram on/off. */
yihui	9:05f0b5a3a70a	3379
yihui	9:05f0b5a3a70a	3380	/* Bit 19 : RAM block 3 behaviour in OFF mode. */
yihui	9:05f0b5a3a70a	3381	#define POWER_RAMON_OFFRAM3_Pos (19UL) /!< Position of OFFRAM3 field. /
yihui	9:05f0b5a3a70a	3382	#define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos) /!< Bit mask of OFFRAM3 field. /
yihui	9:05f0b5a3a70a	3383	#define POWER_RAMON_OFFRAM3_RAM3Off (0UL) /!< RAM block 3 OFF in OFF mode. /
yihui	9:05f0b5a3a70a	3384	#define POWER_RAMON_OFFRAM3_RAM3On (1UL) /!< RAM block 3 ON in OFF mode. /
yihui	9:05f0b5a3a70a	3385
yihui	9:05f0b5a3a70a	3386	/* Bit 18 : RAM block 2 behaviour in OFF mode. */
yihui	9:05f0b5a3a70a	3387	#define POWER_RAMON_OFFRAM2_Pos (18UL) /!< Position of OFFRAM2 field. /
yihui	9:05f0b5a3a70a	3388	#define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos) /!< Bit mask of OFFRAM2 field. /
yihui	9:05f0b5a3a70a	3389	#define POWER_RAMON_OFFRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in OFF mode. /
yihui	9:05f0b5a3a70a	3390	#define POWER_RAMON_OFFRAM2_RAM2On (1UL) /!< RAM block 2 ON in OFF mode. /
yihui	9:05f0b5a3a70a	3391
yihui	9:05f0b5a3a70a	3392	/* Bit 17 : RAM block 1 behaviour in OFF mode. */
yihui	9:05f0b5a3a70a	3393	#define POWER_RAMON_OFFRAM1_Pos (17UL) /!< Position of OFFRAM1 field. /
yihui	9:05f0b5a3a70a	3394	#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /!< Bit mask of OFFRAM1 field. /
yihui	9:05f0b5a3a70a	3395	#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in OFF mode. /
yihui	9:05f0b5a3a70a	3396	#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /!< RAM block 1 ON in OFF mode. /
yihui	9:05f0b5a3a70a	3397
yihui	9:05f0b5a3a70a	3398	/* Bit 16 : RAM block 0 behaviour in OFF mode. */
yihui	9:05f0b5a3a70a	3399	#define POWER_RAMON_OFFRAM0_Pos (16UL) /!< Position of OFFRAM0 field. /
yihui	9:05f0b5a3a70a	3400	#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /!< Bit mask of OFFRAM0 field. /
yihui	9:05f0b5a3a70a	3401	#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in OFF mode. /
yihui	9:05f0b5a3a70a	3402	#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /!< RAM block 0 ON in OFF mode. /
yihui	9:05f0b5a3a70a	3403
yihui	9:05f0b5a3a70a	3404	/* Bit 3 : RAM block 3 behaviour in ON mode. */
yihui	9:05f0b5a3a70a	3405	#define POWER_RAMON_ONRAM3_Pos (3UL) /!< Position of ONRAM3 field. /
yihui	9:05f0b5a3a70a	3406	#define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos) /!< Bit mask of ONRAM3 field. /
yihui	9:05f0b5a3a70a	3407	#define POWER_RAMON_ONRAM3_RAM3Off (0UL) /!< RAM block 3 OFF in ON mode. /
yihui	9:05f0b5a3a70a	3408	#define POWER_RAMON_ONRAM3_RAM3On (1UL) /!< RAM block 3 ON in ON mode. /
yihui	9:05f0b5a3a70a	3409
yihui	9:05f0b5a3a70a	3410	/* Bit 2 : RAM block 2 behaviour in ON mode. */
yihui	9:05f0b5a3a70a	3411	#define POWER_RAMON_ONRAM2_Pos (2UL) /!< Position of ONRAM2 field. /
yihui	9:05f0b5a3a70a	3412	#define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos) /!< Bit mask of ONRAM2 field. /
yihui	9:05f0b5a3a70a	3413	#define POWER_RAMON_ONRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in ON mode. /
yihui	9:05f0b5a3a70a	3414	#define POWER_RAMON_ONRAM2_RAM2On (1UL) /!< RAM block 2 ON in ON mode. /
yihui	9:05f0b5a3a70a	3415
yihui	9:05f0b5a3a70a	3416	/* Bit 1 : RAM block 1 behaviour in ON mode. */
yihui	9:05f0b5a3a70a	3417	#define POWER_RAMON_ONRAM1_Pos (1UL) /!< Position of ONRAM1 field. /
yihui	9:05f0b5a3a70a	3418	#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /!< Bit mask of ONRAM1 field. /
yihui	9:05f0b5a3a70a	3419	#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in ON mode. /
yihui	9:05f0b5a3a70a	3420	#define POWER_RAMON_ONRAM1_RAM1On (1UL) /!< RAM block 1 ON in ON mode. /
yihui	9:05f0b5a3a70a	3421
yihui	9:05f0b5a3a70a	3422	/* Bit 0 : RAM block 0 behaviour in ON mode. */
yihui	9:05f0b5a3a70a	3423	#define POWER_RAMON_ONRAM0_Pos (0UL) /!< Position of ONRAM0 field. /
yihui	9:05f0b5a3a70a	3424	#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /!< Bit mask of ONRAM0 field. /
yihui	9:05f0b5a3a70a	3425	#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in ON mode. /
yihui	9:05f0b5a3a70a	3426	#define POWER_RAMON_ONRAM0_RAM0On (1UL) /!< RAM block 0 ON in ON mode. /
yihui	9:05f0b5a3a70a	3427
yihui	9:05f0b5a3a70a	3428	/* Register: POWER_RESET */
yihui	9:05f0b5a3a70a	3429	/* Description: Pin reset functionality configuration register. This register is a retained register. */
yihui	9:05f0b5a3a70a	3430
yihui	9:05f0b5a3a70a	3431	/* Bit 0 : Enable pin reset in debug interface mode. */
yihui	9:05f0b5a3a70a	3432	#define POWER_RESET_RESET_Pos (0UL) /!< Position of RESET field. /
yihui	9:05f0b5a3a70a	3433	#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /!< Bit mask of RESET field. /
yihui	9:05f0b5a3a70a	3434	#define POWER_RESET_RESET_Disabled (0UL) /!< Pin reset in debug interface mode disabled. /
yihui	9:05f0b5a3a70a	3435	#define POWER_RESET_RESET_Enabled (1UL) /!< Pin reset in debug interface mode enabled. /
yihui	9:05f0b5a3a70a	3436
yihui	9:05f0b5a3a70a	3437	/* Register: POWER_DCDCEN */
yihui	9:05f0b5a3a70a	3438	/* Description: DCDC converter enable configuration register. */
yihui	9:05f0b5a3a70a	3439
yihui	9:05f0b5a3a70a	3440	/* Bit 0 : Enable DCDC converter. */
yihui	9:05f0b5a3a70a	3441	#define POWER_DCDCEN_DCDCEN_Pos (0UL) /!< Position of DCDCEN field. /
yihui	9:05f0b5a3a70a	3442	#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /!< Bit mask of DCDCEN field. /
yihui	9:05f0b5a3a70a	3443	#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /!< DCDC converter disabled. /
yihui	9:05f0b5a3a70a	3444	#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /!< DCDC converter enabled. /
yihui	9:05f0b5a3a70a	3445
yihui	9:05f0b5a3a70a	3446
yihui	9:05f0b5a3a70a	3447	/* Peripheral: PPI */
yihui	9:05f0b5a3a70a	3448	/* Description: PPI controller. */
yihui	9:05f0b5a3a70a	3449
yihui	9:05f0b5a3a70a	3450	/* Register: PPI_CHEN */
yihui	9:05f0b5a3a70a	3451	/* Description: Channel enable. */
yihui	9:05f0b5a3a70a	3452
yihui	9:05f0b5a3a70a	3453	/* Bit 31 : Enable PPI channel 31. */
yihui	9:05f0b5a3a70a	3454	#define PPI_CHEN_CH31_Pos (31UL) /!< Position of CH31 field. /
yihui	9:05f0b5a3a70a	3455	#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /!< Bit mask of CH31 field. /
yihui	9:05f0b5a3a70a	3456	#define PPI_CHEN_CH31_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3457	#define PPI_CHEN_CH31_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3458
yihui	9:05f0b5a3a70a	3459	/* Bit 30 : Enable PPI channel 30. */
yihui	9:05f0b5a3a70a	3460	#define PPI_CHEN_CH30_Pos (30UL) /!< Position of CH30 field. /
yihui	9:05f0b5a3a70a	3461	#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /!< Bit mask of CH30 field. /
yihui	9:05f0b5a3a70a	3462	#define PPI_CHEN_CH30_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3463	#define PPI_CHEN_CH30_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3464
yihui	9:05f0b5a3a70a	3465	/* Bit 29 : Enable PPI channel 29. */
yihui	9:05f0b5a3a70a	3466	#define PPI_CHEN_CH29_Pos (29UL) /!< Position of CH29 field. /
yihui	9:05f0b5a3a70a	3467	#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /!< Bit mask of CH29 field. /
yihui	9:05f0b5a3a70a	3468	#define PPI_CHEN_CH29_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3469	#define PPI_CHEN_CH29_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3470
yihui	9:05f0b5a3a70a	3471	/* Bit 28 : Enable PPI channel 28. */
yihui	9:05f0b5a3a70a	3472	#define PPI_CHEN_CH28_Pos (28UL) /!< Position of CH28 field. /
yihui	9:05f0b5a3a70a	3473	#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /!< Bit mask of CH28 field. /
yihui	9:05f0b5a3a70a	3474	#define PPI_CHEN_CH28_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3475	#define PPI_CHEN_CH28_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3476
yihui	9:05f0b5a3a70a	3477	/* Bit 27 : Enable PPI channel 27. */
yihui	9:05f0b5a3a70a	3478	#define PPI_CHEN_CH27_Pos (27UL) /!< Position of CH27 field. /
yihui	9:05f0b5a3a70a	3479	#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /!< Bit mask of CH27 field. /
yihui	9:05f0b5a3a70a	3480	#define PPI_CHEN_CH27_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3481	#define PPI_CHEN_CH27_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3482
yihui	9:05f0b5a3a70a	3483	/* Bit 26 : Enable PPI channel 26. */
yihui	9:05f0b5a3a70a	3484	#define PPI_CHEN_CH26_Pos (26UL) /!< Position of CH26 field. /
yihui	9:05f0b5a3a70a	3485	#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /!< Bit mask of CH26 field. /
yihui	9:05f0b5a3a70a	3486	#define PPI_CHEN_CH26_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3487	#define PPI_CHEN_CH26_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3488
yihui	9:05f0b5a3a70a	3489	/* Bit 25 : Enable PPI channel 25. */
yihui	9:05f0b5a3a70a	3490	#define PPI_CHEN_CH25_Pos (25UL) /!< Position of CH25 field. /
yihui	9:05f0b5a3a70a	3491	#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /!< Bit mask of CH25 field. /
yihui	9:05f0b5a3a70a	3492	#define PPI_CHEN_CH25_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3493	#define PPI_CHEN_CH25_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3494
yihui	9:05f0b5a3a70a	3495	/* Bit 24 : Enable PPI channel 24. */
yihui	9:05f0b5a3a70a	3496	#define PPI_CHEN_CH24_Pos (24UL) /!< Position of CH24 field. /
yihui	9:05f0b5a3a70a	3497	#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /!< Bit mask of CH24 field. /
yihui	9:05f0b5a3a70a	3498	#define PPI_CHEN_CH24_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3499	#define PPI_CHEN_CH24_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3500
yihui	9:05f0b5a3a70a	3501	/* Bit 23 : Enable PPI channel 23. */
yihui	9:05f0b5a3a70a	3502	#define PPI_CHEN_CH23_Pos (23UL) /!< Position of CH23 field. /
yihui	9:05f0b5a3a70a	3503	#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /!< Bit mask of CH23 field. /
yihui	9:05f0b5a3a70a	3504	#define PPI_CHEN_CH23_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3505	#define PPI_CHEN_CH23_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3506
yihui	9:05f0b5a3a70a	3507	/* Bit 22 : Enable PPI channel 22. */
yihui	9:05f0b5a3a70a	3508	#define PPI_CHEN_CH22_Pos (22UL) /!< Position of CH22 field. /
yihui	9:05f0b5a3a70a	3509	#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /!< Bit mask of CH22 field. /
yihui	9:05f0b5a3a70a	3510	#define PPI_CHEN_CH22_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3511	#define PPI_CHEN_CH22_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3512
yihui	9:05f0b5a3a70a	3513	/* Bit 21 : Enable PPI channel 21. */
yihui	9:05f0b5a3a70a	3514	#define PPI_CHEN_CH21_Pos (21UL) /!< Position of CH21 field. /
yihui	9:05f0b5a3a70a	3515	#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /!< Bit mask of CH21 field. /
yihui	9:05f0b5a3a70a	3516	#define PPI_CHEN_CH21_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3517	#define PPI_CHEN_CH21_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3518
yihui	9:05f0b5a3a70a	3519	/* Bit 20 : Enable PPI channel 20. */
yihui	9:05f0b5a3a70a	3520	#define PPI_CHEN_CH20_Pos (20UL) /!< Position of CH20 field. /
yihui	9:05f0b5a3a70a	3521	#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /!< Bit mask of CH20 field. /
yihui	9:05f0b5a3a70a	3522	#define PPI_CHEN_CH20_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3523	#define PPI_CHEN_CH20_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3524
yihui	9:05f0b5a3a70a	3525	/* Bit 15 : Enable PPI channel 15. */
yihui	9:05f0b5a3a70a	3526	#define PPI_CHEN_CH15_Pos (15UL) /!< Position of CH15 field. /
yihui	9:05f0b5a3a70a	3527	#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /!< Bit mask of CH15 field. /
yihui	9:05f0b5a3a70a	3528	#define PPI_CHEN_CH15_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3529	#define PPI_CHEN_CH15_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3530
yihui	9:05f0b5a3a70a	3531	/* Bit 14 : Enable PPI channel 14. */
yihui	9:05f0b5a3a70a	3532	#define PPI_CHEN_CH14_Pos (14UL) /!< Position of CH14 field. /
yihui	9:05f0b5a3a70a	3533	#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /!< Bit mask of CH14 field. /
yihui	9:05f0b5a3a70a	3534	#define PPI_CHEN_CH14_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3535	#define PPI_CHEN_CH14_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3536
yihui	9:05f0b5a3a70a	3537	/* Bit 13 : Enable PPI channel 13. */
yihui	9:05f0b5a3a70a	3538	#define PPI_CHEN_CH13_Pos (13UL) /!< Position of CH13 field. /
yihui	9:05f0b5a3a70a	3539	#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /!< Bit mask of CH13 field. /
yihui	9:05f0b5a3a70a	3540	#define PPI_CHEN_CH13_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3541	#define PPI_CHEN_CH13_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3542
yihui	9:05f0b5a3a70a	3543	/* Bit 12 : Enable PPI channel 12. */
yihui	9:05f0b5a3a70a	3544	#define PPI_CHEN_CH12_Pos (12UL) /!< Position of CH12 field. /
yihui	9:05f0b5a3a70a	3545	#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /!< Bit mask of CH12 field. /
yihui	9:05f0b5a3a70a	3546	#define PPI_CHEN_CH12_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3547	#define PPI_CHEN_CH12_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3548
yihui	9:05f0b5a3a70a	3549	/* Bit 11 : Enable PPI channel 11. */
yihui	9:05f0b5a3a70a	3550	#define PPI_CHEN_CH11_Pos (11UL) /!< Position of CH11 field. /
yihui	9:05f0b5a3a70a	3551	#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /!< Bit mask of CH11 field. /
yihui	9:05f0b5a3a70a	3552	#define PPI_CHEN_CH11_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3553	#define PPI_CHEN_CH11_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3554
yihui	9:05f0b5a3a70a	3555	/* Bit 10 : Enable PPI channel 10. */
yihui	9:05f0b5a3a70a	3556	#define PPI_CHEN_CH10_Pos (10UL) /!< Position of CH10 field. /
yihui	9:05f0b5a3a70a	3557	#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /!< Bit mask of CH10 field. /
yihui	9:05f0b5a3a70a	3558	#define PPI_CHEN_CH10_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3559	#define PPI_CHEN_CH10_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3560
yihui	9:05f0b5a3a70a	3561	/* Bit 9 : Enable PPI channel 9. */
yihui	9:05f0b5a3a70a	3562	#define PPI_CHEN_CH9_Pos (9UL) /!< Position of CH9 field. /
yihui	9:05f0b5a3a70a	3563	#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /!< Bit mask of CH9 field. /
yihui	9:05f0b5a3a70a	3564	#define PPI_CHEN_CH9_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3565	#define PPI_CHEN_CH9_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3566
yihui	9:05f0b5a3a70a	3567	/* Bit 8 : Enable PPI channel 8. */
yihui	9:05f0b5a3a70a	3568	#define PPI_CHEN_CH8_Pos (8UL) /!< Position of CH8 field. /
yihui	9:05f0b5a3a70a	3569	#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /!< Bit mask of CH8 field. /
yihui	9:05f0b5a3a70a	3570	#define PPI_CHEN_CH8_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3571	#define PPI_CHEN_CH8_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3572
yihui	9:05f0b5a3a70a	3573	/* Bit 7 : Enable PPI channel 7. */
yihui	9:05f0b5a3a70a	3574	#define PPI_CHEN_CH7_Pos (7UL) /!< Position of CH7 field. /
yihui	9:05f0b5a3a70a	3575	#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /!< Bit mask of CH7 field. /
yihui	9:05f0b5a3a70a	3576	#define PPI_CHEN_CH7_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3577	#define PPI_CHEN_CH7_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3578
yihui	9:05f0b5a3a70a	3579	/* Bit 6 : Enable PPI channel 6. */
yihui	9:05f0b5a3a70a	3580	#define PPI_CHEN_CH6_Pos (6UL) /!< Position of CH6 field. /
yihui	9:05f0b5a3a70a	3581	#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /!< Bit mask of CH6 field. /
yihui	9:05f0b5a3a70a	3582	#define PPI_CHEN_CH6_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3583	#define PPI_CHEN_CH6_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3584
yihui	9:05f0b5a3a70a	3585	/* Bit 5 : Enable PPI channel 5. */
yihui	9:05f0b5a3a70a	3586	#define PPI_CHEN_CH5_Pos (5UL) /!< Position of CH5 field. /
yihui	9:05f0b5a3a70a	3587	#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /!< Bit mask of CH5 field. /
yihui	9:05f0b5a3a70a	3588	#define PPI_CHEN_CH5_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3589	#define PPI_CHEN_CH5_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3590
yihui	9:05f0b5a3a70a	3591	/* Bit 4 : Enable PPI channel 4. */
yihui	9:05f0b5a3a70a	3592	#define PPI_CHEN_CH4_Pos (4UL) /!< Position of CH4 field. /
yihui	9:05f0b5a3a70a	3593	#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /!< Bit mask of CH4 field. /
yihui	9:05f0b5a3a70a	3594	#define PPI_CHEN_CH4_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3595	#define PPI_CHEN_CH4_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3596
yihui	9:05f0b5a3a70a	3597	/* Bit 3 : Enable PPI channel 3. */
yihui	9:05f0b5a3a70a	3598	#define PPI_CHEN_CH3_Pos (3UL) /!< Position of CH3 field. /
yihui	9:05f0b5a3a70a	3599	#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /!< Bit mask of CH3 field. /
yihui	9:05f0b5a3a70a	3600	#define PPI_CHEN_CH3_Disabled (0UL) /!< Channel disabled /
yihui	9:05f0b5a3a70a	3601	#define PPI_CHEN_CH3_Enabled (1UL) /!< Channel enabled /
yihui	9:05f0b5a3a70a	3602
yihui	9:05f0b5a3a70a	3603	/* Bit 2 : Enable PPI channel 2. */
yihui	9:05f0b5a3a70a	3604	#define PPI_CHEN_CH2_Pos (2UL) /!< Position of CH2 field. /
yihui	9:05f0b5a3a70a	3605	#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /!< Bit mask of CH2 field. /
yihui	9:05f0b5a3a70a	3606	#define PPI_CHEN_CH2_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3607	#define PPI_CHEN_CH2_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3608
yihui	9:05f0b5a3a70a	3609	/* Bit 1 : Enable PPI channel 1. */
yihui	9:05f0b5a3a70a	3610	#define PPI_CHEN_CH1_Pos (1UL) /!< Position of CH1 field. /
yihui	9:05f0b5a3a70a	3611	#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /!< Bit mask of CH1 field. /
yihui	9:05f0b5a3a70a	3612	#define PPI_CHEN_CH1_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3613	#define PPI_CHEN_CH1_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3614
yihui	9:05f0b5a3a70a	3615	/* Bit 0 : Enable PPI channel 0. */
yihui	9:05f0b5a3a70a	3616	#define PPI_CHEN_CH0_Pos (0UL) /!< Position of CH0 field. /
yihui	9:05f0b5a3a70a	3617	#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /!< Bit mask of CH0 field. /
yihui	9:05f0b5a3a70a	3618	#define PPI_CHEN_CH0_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3619	#define PPI_CHEN_CH0_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3620
yihui	9:05f0b5a3a70a	3621	/* Register: PPI_CHENSET */
yihui	9:05f0b5a3a70a	3622	/* Description: Channel enable set. */
yihui	9:05f0b5a3a70a	3623
yihui	9:05f0b5a3a70a	3624	/* Bit 31 : Enable PPI channel 31. */
yihui	9:05f0b5a3a70a	3625	#define PPI_CHENSET_CH31_Pos (31UL) /!< Position of CH31 field. /
yihui	9:05f0b5a3a70a	3626	#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /!< Bit mask of CH31 field. /
yihui	9:05f0b5a3a70a	3627	#define PPI_CHENSET_CH31_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3628	#define PPI_CHENSET_CH31_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3629	#define PPI_CHENSET_CH31_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3630
yihui	9:05f0b5a3a70a	3631	/* Bit 30 : Enable PPI channel 30. */
yihui	9:05f0b5a3a70a	3632	#define PPI_CHENSET_CH30_Pos (30UL) /!< Position of CH30 field. /
yihui	9:05f0b5a3a70a	3633	#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /!< Bit mask of CH30 field. /
yihui	9:05f0b5a3a70a	3634	#define PPI_CHENSET_CH30_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3635	#define PPI_CHENSET_CH30_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3636	#define PPI_CHENSET_CH30_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3637
yihui	9:05f0b5a3a70a	3638	/* Bit 29 : Enable PPI channel 29. */
yihui	9:05f0b5a3a70a	3639	#define PPI_CHENSET_CH29_Pos (29UL) /!< Position of CH29 field. /
yihui	9:05f0b5a3a70a	3640	#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /!< Bit mask of CH29 field. /
yihui	9:05f0b5a3a70a	3641	#define PPI_CHENSET_CH29_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3642	#define PPI_CHENSET_CH29_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3643	#define PPI_CHENSET_CH29_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3644
yihui	9:05f0b5a3a70a	3645	/* Bit 28 : Enable PPI channel 28. */
yihui	9:05f0b5a3a70a	3646	#define PPI_CHENSET_CH28_Pos (28UL) /!< Position of CH28 field. /
yihui	9:05f0b5a3a70a	3647	#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /!< Bit mask of CH28 field. /
yihui	9:05f0b5a3a70a	3648	#define PPI_CHENSET_CH28_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3649	#define PPI_CHENSET_CH28_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3650	#define PPI_CHENSET_CH28_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3651
yihui	9:05f0b5a3a70a	3652	/* Bit 27 : Enable PPI channel 27. */
yihui	9:05f0b5a3a70a	3653	#define PPI_CHENSET_CH27_Pos (27UL) /!< Position of CH27 field. /
yihui	9:05f0b5a3a70a	3654	#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /!< Bit mask of CH27 field. /
yihui	9:05f0b5a3a70a	3655	#define PPI_CHENSET_CH27_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3656	#define PPI_CHENSET_CH27_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3657	#define PPI_CHENSET_CH27_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3658
yihui	9:05f0b5a3a70a	3659	/* Bit 26 : Enable PPI channel 26. */
yihui	9:05f0b5a3a70a	3660	#define PPI_CHENSET_CH26_Pos (26UL) /!< Position of CH26 field. /
yihui	9:05f0b5a3a70a	3661	#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /!< Bit mask of CH26 field. /
yihui	9:05f0b5a3a70a	3662	#define PPI_CHENSET_CH26_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3663	#define PPI_CHENSET_CH26_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3664	#define PPI_CHENSET_CH26_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3665
yihui	9:05f0b5a3a70a	3666	/* Bit 25 : Enable PPI channel 25. */
yihui	9:05f0b5a3a70a	3667	#define PPI_CHENSET_CH25_Pos (25UL) /!< Position of CH25 field. /
yihui	9:05f0b5a3a70a	3668	#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /!< Bit mask of CH25 field. /
yihui	9:05f0b5a3a70a	3669	#define PPI_CHENSET_CH25_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3670	#define PPI_CHENSET_CH25_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3671	#define PPI_CHENSET_CH25_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3672
yihui	9:05f0b5a3a70a	3673	/* Bit 24 : Enable PPI channel 24. */
yihui	9:05f0b5a3a70a	3674	#define PPI_CHENSET_CH24_Pos (24UL) /!< Position of CH24 field. /
yihui	9:05f0b5a3a70a	3675	#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /!< Bit mask of CH24 field. /
yihui	9:05f0b5a3a70a	3676	#define PPI_CHENSET_CH24_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3677	#define PPI_CHENSET_CH24_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3678	#define PPI_CHENSET_CH24_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3679
yihui	9:05f0b5a3a70a	3680	/* Bit 23 : Enable PPI channel 23. */
yihui	9:05f0b5a3a70a	3681	#define PPI_CHENSET_CH23_Pos (23UL) /!< Position of CH23 field. /
yihui	9:05f0b5a3a70a	3682	#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /!< Bit mask of CH23 field. /
yihui	9:05f0b5a3a70a	3683	#define PPI_CHENSET_CH23_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3684	#define PPI_CHENSET_CH23_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3685	#define PPI_CHENSET_CH23_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3686
yihui	9:05f0b5a3a70a	3687	/* Bit 22 : Enable PPI channel 22. */
yihui	9:05f0b5a3a70a	3688	#define PPI_CHENSET_CH22_Pos (22UL) /!< Position of CH22 field. /
yihui	9:05f0b5a3a70a	3689	#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /!< Bit mask of CH22 field. /
yihui	9:05f0b5a3a70a	3690	#define PPI_CHENSET_CH22_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3691	#define PPI_CHENSET_CH22_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3692	#define PPI_CHENSET_CH22_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3693
yihui	9:05f0b5a3a70a	3694	/* Bit 21 : Enable PPI channel 21. */
yihui	9:05f0b5a3a70a	3695	#define PPI_CHENSET_CH21_Pos (21UL) /!< Position of CH21 field. /
yihui	9:05f0b5a3a70a	3696	#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /!< Bit mask of CH21 field. /
yihui	9:05f0b5a3a70a	3697	#define PPI_CHENSET_CH21_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3698	#define PPI_CHENSET_CH21_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3699	#define PPI_CHENSET_CH21_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3700
yihui	9:05f0b5a3a70a	3701	/* Bit 20 : Enable PPI channel 20. */
yihui	9:05f0b5a3a70a	3702	#define PPI_CHENSET_CH20_Pos (20UL) /!< Position of CH20 field. /
yihui	9:05f0b5a3a70a	3703	#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /!< Bit mask of CH20 field. /
yihui	9:05f0b5a3a70a	3704	#define PPI_CHENSET_CH20_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3705	#define PPI_CHENSET_CH20_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3706	#define PPI_CHENSET_CH20_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3707
yihui	9:05f0b5a3a70a	3708	/* Bit 15 : Enable PPI channel 15. */
yihui	9:05f0b5a3a70a	3709	#define PPI_CHENSET_CH15_Pos (15UL) /!< Position of CH15 field. /
yihui	9:05f0b5a3a70a	3710	#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /!< Bit mask of CH15 field. /
yihui	9:05f0b5a3a70a	3711	#define PPI_CHENSET_CH15_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3712	#define PPI_CHENSET_CH15_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3713	#define PPI_CHENSET_CH15_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3714
yihui	9:05f0b5a3a70a	3715	/* Bit 14 : Enable PPI channel 14. */
yihui	9:05f0b5a3a70a	3716	#define PPI_CHENSET_CH14_Pos (14UL) /!< Position of CH14 field. /
yihui	9:05f0b5a3a70a	3717	#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /!< Bit mask of CH14 field. /
yihui	9:05f0b5a3a70a	3718	#define PPI_CHENSET_CH14_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3719	#define PPI_CHENSET_CH14_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3720	#define PPI_CHENSET_CH14_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3721
yihui	9:05f0b5a3a70a	3722	/* Bit 13 : Enable PPI channel 13. */
yihui	9:05f0b5a3a70a	3723	#define PPI_CHENSET_CH13_Pos (13UL) /!< Position of CH13 field. /
yihui	9:05f0b5a3a70a	3724	#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /!< Bit mask of CH13 field. /
yihui	9:05f0b5a3a70a	3725	#define PPI_CHENSET_CH13_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3726	#define PPI_CHENSET_CH13_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3727	#define PPI_CHENSET_CH13_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3728
yihui	9:05f0b5a3a70a	3729	/* Bit 12 : Enable PPI channel 12. */
yihui	9:05f0b5a3a70a	3730	#define PPI_CHENSET_CH12_Pos (12UL) /!< Position of CH12 field. /
yihui	9:05f0b5a3a70a	3731	#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /!< Bit mask of CH12 field. /
yihui	9:05f0b5a3a70a	3732	#define PPI_CHENSET_CH12_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3733	#define PPI_CHENSET_CH12_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3734	#define PPI_CHENSET_CH12_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3735
yihui	9:05f0b5a3a70a	3736	/* Bit 11 : Enable PPI channel 11. */
yihui	9:05f0b5a3a70a	3737	#define PPI_CHENSET_CH11_Pos (11UL) /!< Position of CH11 field. /
yihui	9:05f0b5a3a70a	3738	#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /!< Bit mask of CH11 field. /
yihui	9:05f0b5a3a70a	3739	#define PPI_CHENSET_CH11_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3740	#define PPI_CHENSET_CH11_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3741	#define PPI_CHENSET_CH11_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3742
yihui	9:05f0b5a3a70a	3743	/* Bit 10 : Enable PPI channel 10. */
yihui	9:05f0b5a3a70a	3744	#define PPI_CHENSET_CH10_Pos (10UL) /!< Position of CH10 field. /
yihui	9:05f0b5a3a70a	3745	#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /!< Bit mask of CH10 field. /
yihui	9:05f0b5a3a70a	3746	#define PPI_CHENSET_CH10_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3747	#define PPI_CHENSET_CH10_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3748	#define PPI_CHENSET_CH10_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3749
yihui	9:05f0b5a3a70a	3750	/* Bit 9 : Enable PPI channel 9. */
yihui	9:05f0b5a3a70a	3751	#define PPI_CHENSET_CH9_Pos (9UL) /!< Position of CH9 field. /
yihui	9:05f0b5a3a70a	3752	#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /!< Bit mask of CH9 field. /
yihui	9:05f0b5a3a70a	3753	#define PPI_CHENSET_CH9_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3754	#define PPI_CHENSET_CH9_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3755	#define PPI_CHENSET_CH9_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3756
yihui	9:05f0b5a3a70a	3757	/* Bit 8 : Enable PPI channel 8. */
yihui	9:05f0b5a3a70a	3758	#define PPI_CHENSET_CH8_Pos (8UL) /!< Position of CH8 field. /
yihui	9:05f0b5a3a70a	3759	#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /!< Bit mask of CH8 field. /
yihui	9:05f0b5a3a70a	3760	#define PPI_CHENSET_CH8_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3761	#define PPI_CHENSET_CH8_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3762	#define PPI_CHENSET_CH8_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3763
yihui	9:05f0b5a3a70a	3764	/* Bit 7 : Enable PPI channel 7. */
yihui	9:05f0b5a3a70a	3765	#define PPI_CHENSET_CH7_Pos (7UL) /!< Position of CH7 field. /
yihui	9:05f0b5a3a70a	3766	#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /!< Bit mask of CH7 field. /
yihui	9:05f0b5a3a70a	3767	#define PPI_CHENSET_CH7_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3768	#define PPI_CHENSET_CH7_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3769	#define PPI_CHENSET_CH7_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3770
yihui	9:05f0b5a3a70a	3771	/* Bit 6 : Enable PPI channel 6. */
yihui	9:05f0b5a3a70a	3772	#define PPI_CHENSET_CH6_Pos (6UL) /!< Position of CH6 field. /
yihui	9:05f0b5a3a70a	3773	#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /!< Bit mask of CH6 field. /
yihui	9:05f0b5a3a70a	3774	#define PPI_CHENSET_CH6_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3775	#define PPI_CHENSET_CH6_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3776	#define PPI_CHENSET_CH6_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3777
yihui	9:05f0b5a3a70a	3778	/* Bit 5 : Enable PPI channel 5. */
yihui	9:05f0b5a3a70a	3779	#define PPI_CHENSET_CH5_Pos (5UL) /!< Position of CH5 field. /
yihui	9:05f0b5a3a70a	3780	#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /!< Bit mask of CH5 field. /
yihui	9:05f0b5a3a70a	3781	#define PPI_CHENSET_CH5_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3782	#define PPI_CHENSET_CH5_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3783	#define PPI_CHENSET_CH5_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3784
yihui	9:05f0b5a3a70a	3785	/* Bit 4 : Enable PPI channel 4. */
yihui	9:05f0b5a3a70a	3786	#define PPI_CHENSET_CH4_Pos (4UL) /!< Position of CH4 field. /
yihui	9:05f0b5a3a70a	3787	#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /!< Bit mask of CH4 field. /
yihui	9:05f0b5a3a70a	3788	#define PPI_CHENSET_CH4_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3789	#define PPI_CHENSET_CH4_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3790	#define PPI_CHENSET_CH4_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3791
yihui	9:05f0b5a3a70a	3792	/* Bit 3 : Enable PPI channel 3. */
yihui	9:05f0b5a3a70a	3793	#define PPI_CHENSET_CH3_Pos (3UL) /!< Position of CH3 field. /
yihui	9:05f0b5a3a70a	3794	#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /!< Bit mask of CH3 field. /
yihui	9:05f0b5a3a70a	3795	#define PPI_CHENSET_CH3_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3796	#define PPI_CHENSET_CH3_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3797	#define PPI_CHENSET_CH3_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3798
yihui	9:05f0b5a3a70a	3799	/* Bit 2 : Enable PPI channel 2. */
yihui	9:05f0b5a3a70a	3800	#define PPI_CHENSET_CH2_Pos (2UL) /!< Position of CH2 field. /
yihui	9:05f0b5a3a70a	3801	#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /!< Bit mask of CH2 field. /
yihui	9:05f0b5a3a70a	3802	#define PPI_CHENSET_CH2_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3803	#define PPI_CHENSET_CH2_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3804	#define PPI_CHENSET_CH2_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3805
yihui	9:05f0b5a3a70a	3806	/* Bit 1 : Enable PPI channel 1. */
yihui	9:05f0b5a3a70a	3807	#define PPI_CHENSET_CH1_Pos (1UL) /!< Position of CH1 field. /
yihui	9:05f0b5a3a70a	3808	#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /!< Bit mask of CH1 field. /
yihui	9:05f0b5a3a70a	3809	#define PPI_CHENSET_CH1_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3810	#define PPI_CHENSET_CH1_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3811	#define PPI_CHENSET_CH1_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3812
yihui	9:05f0b5a3a70a	3813	/* Bit 0 : Enable PPI channel 0. */
yihui	9:05f0b5a3a70a	3814	#define PPI_CHENSET_CH0_Pos (0UL) /!< Position of CH0 field. /
yihui	9:05f0b5a3a70a	3815	#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /!< Bit mask of CH0 field. /
yihui	9:05f0b5a3a70a	3816	#define PPI_CHENSET_CH0_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3817	#define PPI_CHENSET_CH0_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3818	#define PPI_CHENSET_CH0_Set (1UL) /!< Enable channel on write. /
yihui	9:05f0b5a3a70a	3819
yihui	9:05f0b5a3a70a	3820	/* Register: PPI_CHENCLR */
yihui	9:05f0b5a3a70a	3821	/* Description: Channel enable clear. */
yihui	9:05f0b5a3a70a	3822
yihui	9:05f0b5a3a70a	3823	/* Bit 31 : Disable PPI channel 31. */
yihui	9:05f0b5a3a70a	3824	#define PPI_CHENCLR_CH31_Pos (31UL) /!< Position of CH31 field. /
yihui	9:05f0b5a3a70a	3825	#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /!< Bit mask of CH31 field. /
yihui	9:05f0b5a3a70a	3826	#define PPI_CHENCLR_CH31_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3827	#define PPI_CHENCLR_CH31_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3828	#define PPI_CHENCLR_CH31_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3829
yihui	9:05f0b5a3a70a	3830	/* Bit 30 : Disable PPI channel 30. */
yihui	9:05f0b5a3a70a	3831	#define PPI_CHENCLR_CH30_Pos (30UL) /!< Position of CH30 field. /
yihui	9:05f0b5a3a70a	3832	#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /!< Bit mask of CH30 field. /
yihui	9:05f0b5a3a70a	3833	#define PPI_CHENCLR_CH30_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3834	#define PPI_CHENCLR_CH30_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3835	#define PPI_CHENCLR_CH30_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3836
yihui	9:05f0b5a3a70a	3837	/* Bit 29 : Disable PPI channel 29. */
yihui	9:05f0b5a3a70a	3838	#define PPI_CHENCLR_CH29_Pos (29UL) /!< Position of CH29 field. /
yihui	9:05f0b5a3a70a	3839	#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /!< Bit mask of CH29 field. /
yihui	9:05f0b5a3a70a	3840	#define PPI_CHENCLR_CH29_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3841	#define PPI_CHENCLR_CH29_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3842	#define PPI_CHENCLR_CH29_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3843
yihui	9:05f0b5a3a70a	3844	/* Bit 28 : Disable PPI channel 28. */
yihui	9:05f0b5a3a70a	3845	#define PPI_CHENCLR_CH28_Pos (28UL) /!< Position of CH28 field. /
yihui	9:05f0b5a3a70a	3846	#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /!< Bit mask of CH28 field. /
yihui	9:05f0b5a3a70a	3847	#define PPI_CHENCLR_CH28_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3848	#define PPI_CHENCLR_CH28_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3849	#define PPI_CHENCLR_CH28_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3850
yihui	9:05f0b5a3a70a	3851	/* Bit 27 : Disable PPI channel 27. */
yihui	9:05f0b5a3a70a	3852	#define PPI_CHENCLR_CH27_Pos (27UL) /!< Position of CH27 field. /
yihui	9:05f0b5a3a70a	3853	#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /!< Bit mask of CH27 field. /
yihui	9:05f0b5a3a70a	3854	#define PPI_CHENCLR_CH27_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3855	#define PPI_CHENCLR_CH27_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3856	#define PPI_CHENCLR_CH27_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3857
yihui	9:05f0b5a3a70a	3858	/* Bit 26 : Disable PPI channel 26. */
yihui	9:05f0b5a3a70a	3859	#define PPI_CHENCLR_CH26_Pos (26UL) /!< Position of CH26 field. /
yihui	9:05f0b5a3a70a	3860	#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /!< Bit mask of CH26 field. /
yihui	9:05f0b5a3a70a	3861	#define PPI_CHENCLR_CH26_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3862	#define PPI_CHENCLR_CH26_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3863	#define PPI_CHENCLR_CH26_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3864
yihui	9:05f0b5a3a70a	3865	/* Bit 25 : Disable PPI channel 25. */
yihui	9:05f0b5a3a70a	3866	#define PPI_CHENCLR_CH25_Pos (25UL) /!< Position of CH25 field. /
yihui	9:05f0b5a3a70a	3867	#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /!< Bit mask of CH25 field. /
yihui	9:05f0b5a3a70a	3868	#define PPI_CHENCLR_CH25_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3869	#define PPI_CHENCLR_CH25_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3870	#define PPI_CHENCLR_CH25_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3871
yihui	9:05f0b5a3a70a	3872	/* Bit 24 : Disable PPI channel 24. */
yihui	9:05f0b5a3a70a	3873	#define PPI_CHENCLR_CH24_Pos (24UL) /!< Position of CH24 field. /
yihui	9:05f0b5a3a70a	3874	#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /!< Bit mask of CH24 field. /
yihui	9:05f0b5a3a70a	3875	#define PPI_CHENCLR_CH24_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3876	#define PPI_CHENCLR_CH24_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3877	#define PPI_CHENCLR_CH24_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3878
yihui	9:05f0b5a3a70a	3879	/* Bit 23 : Disable PPI channel 23. */
yihui	9:05f0b5a3a70a	3880	#define PPI_CHENCLR_CH23_Pos (23UL) /!< Position of CH23 field. /
yihui	9:05f0b5a3a70a	3881	#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /!< Bit mask of CH23 field. /
yihui	9:05f0b5a3a70a	3882	#define PPI_CHENCLR_CH23_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3883	#define PPI_CHENCLR_CH23_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3884	#define PPI_CHENCLR_CH23_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3885
yihui	9:05f0b5a3a70a	3886	/* Bit 22 : Disable PPI channel 22. */
yihui	9:05f0b5a3a70a	3887	#define PPI_CHENCLR_CH22_Pos (22UL) /!< Position of CH22 field. /
yihui	9:05f0b5a3a70a	3888	#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /!< Bit mask of CH22 field. /
yihui	9:05f0b5a3a70a	3889	#define PPI_CHENCLR_CH22_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3890	#define PPI_CHENCLR_CH22_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3891	#define PPI_CHENCLR_CH22_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3892
yihui	9:05f0b5a3a70a	3893	/* Bit 21 : Disable PPI channel 21. */
yihui	9:05f0b5a3a70a	3894	#define PPI_CHENCLR_CH21_Pos (21UL) /!< Position of CH21 field. /
yihui	9:05f0b5a3a70a	3895	#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /!< Bit mask of CH21 field. /
yihui	9:05f0b5a3a70a	3896	#define PPI_CHENCLR_CH21_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3897	#define PPI_CHENCLR_CH21_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3898	#define PPI_CHENCLR_CH21_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3899
yihui	9:05f0b5a3a70a	3900	/* Bit 20 : Disable PPI channel 20. */
yihui	9:05f0b5a3a70a	3901	#define PPI_CHENCLR_CH20_Pos (20UL) /!< Position of CH20 field. /
yihui	9:05f0b5a3a70a	3902	#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /!< Bit mask of CH20 field. /
yihui	9:05f0b5a3a70a	3903	#define PPI_CHENCLR_CH20_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3904	#define PPI_CHENCLR_CH20_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3905	#define PPI_CHENCLR_CH20_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3906
yihui	9:05f0b5a3a70a	3907	/* Bit 15 : Disable PPI channel 15. */
yihui	9:05f0b5a3a70a	3908	#define PPI_CHENCLR_CH15_Pos (15UL) /!< Position of CH15 field. /
yihui	9:05f0b5a3a70a	3909	#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /!< Bit mask of CH15 field. /
yihui	9:05f0b5a3a70a	3910	#define PPI_CHENCLR_CH15_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3911	#define PPI_CHENCLR_CH15_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3912	#define PPI_CHENCLR_CH15_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3913
yihui	9:05f0b5a3a70a	3914	/* Bit 14 : Disable PPI channel 14. */
yihui	9:05f0b5a3a70a	3915	#define PPI_CHENCLR_CH14_Pos (14UL) /!< Position of CH14 field. /
yihui	9:05f0b5a3a70a	3916	#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /!< Bit mask of CH14 field. /
yihui	9:05f0b5a3a70a	3917	#define PPI_CHENCLR_CH14_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3918	#define PPI_CHENCLR_CH14_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3919	#define PPI_CHENCLR_CH14_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3920
yihui	9:05f0b5a3a70a	3921	/* Bit 13 : Disable PPI channel 13. */
yihui	9:05f0b5a3a70a	3922	#define PPI_CHENCLR_CH13_Pos (13UL) /!< Position of CH13 field. /
yihui	9:05f0b5a3a70a	3923	#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /!< Bit mask of CH13 field. /
yihui	9:05f0b5a3a70a	3924	#define PPI_CHENCLR_CH13_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3925	#define PPI_CHENCLR_CH13_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3926	#define PPI_CHENCLR_CH13_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3927
yihui	9:05f0b5a3a70a	3928	/* Bit 12 : Disable PPI channel 12. */
yihui	9:05f0b5a3a70a	3929	#define PPI_CHENCLR_CH12_Pos (12UL) /!< Position of CH12 field. /
yihui	9:05f0b5a3a70a	3930	#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /!< Bit mask of CH12 field. /
yihui	9:05f0b5a3a70a	3931	#define PPI_CHENCLR_CH12_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3932	#define PPI_CHENCLR_CH12_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3933	#define PPI_CHENCLR_CH12_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3934
yihui	9:05f0b5a3a70a	3935	/* Bit 11 : Disable PPI channel 11. */
yihui	9:05f0b5a3a70a	3936	#define PPI_CHENCLR_CH11_Pos (11UL) /!< Position of CH11 field. /
yihui	9:05f0b5a3a70a	3937	#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /!< Bit mask of CH11 field. /
yihui	9:05f0b5a3a70a	3938	#define PPI_CHENCLR_CH11_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3939	#define PPI_CHENCLR_CH11_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3940	#define PPI_CHENCLR_CH11_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3941
yihui	9:05f0b5a3a70a	3942	/* Bit 10 : Disable PPI channel 10. */
yihui	9:05f0b5a3a70a	3943	#define PPI_CHENCLR_CH10_Pos (10UL) /!< Position of CH10 field. /
yihui	9:05f0b5a3a70a	3944	#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /!< Bit mask of CH10 field. /
yihui	9:05f0b5a3a70a	3945	#define PPI_CHENCLR_CH10_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3946	#define PPI_CHENCLR_CH10_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3947	#define PPI_CHENCLR_CH10_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3948
yihui	9:05f0b5a3a70a	3949	/* Bit 9 : Disable PPI channel 9. */
yihui	9:05f0b5a3a70a	3950	#define PPI_CHENCLR_CH9_Pos (9UL) /!< Position of CH9 field. /
yihui	9:05f0b5a3a70a	3951	#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /!< Bit mask of CH9 field. /
yihui	9:05f0b5a3a70a	3952	#define PPI_CHENCLR_CH9_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3953	#define PPI_CHENCLR_CH9_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3954	#define PPI_CHENCLR_CH9_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3955
yihui	9:05f0b5a3a70a	3956	/* Bit 8 : Disable PPI channel 8. */
yihui	9:05f0b5a3a70a	3957	#define PPI_CHENCLR_CH8_Pos (8UL) /!< Position of CH8 field. /
yihui	9:05f0b5a3a70a	3958	#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /!< Bit mask of CH8 field. /
yihui	9:05f0b5a3a70a	3959	#define PPI_CHENCLR_CH8_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3960	#define PPI_CHENCLR_CH8_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3961	#define PPI_CHENCLR_CH8_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3962
yihui	9:05f0b5a3a70a	3963	/* Bit 7 : Disable PPI channel 7. */
yihui	9:05f0b5a3a70a	3964	#define PPI_CHENCLR_CH7_Pos (7UL) /!< Position of CH7 field. /
yihui	9:05f0b5a3a70a	3965	#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /!< Bit mask of CH7 field. /
yihui	9:05f0b5a3a70a	3966	#define PPI_CHENCLR_CH7_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3967	#define PPI_CHENCLR_CH7_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3968	#define PPI_CHENCLR_CH7_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3969
yihui	9:05f0b5a3a70a	3970	/* Bit 6 : Disable PPI channel 6. */
yihui	9:05f0b5a3a70a	3971	#define PPI_CHENCLR_CH6_Pos (6UL) /!< Position of CH6 field. /
yihui	9:05f0b5a3a70a	3972	#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /!< Bit mask of CH6 field. /
yihui	9:05f0b5a3a70a	3973	#define PPI_CHENCLR_CH6_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3974	#define PPI_CHENCLR_CH6_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3975	#define PPI_CHENCLR_CH6_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3976
yihui	9:05f0b5a3a70a	3977	/* Bit 5 : Disable PPI channel 5. */
yihui	9:05f0b5a3a70a	3978	#define PPI_CHENCLR_CH5_Pos (5UL) /!< Position of CH5 field. /
yihui	9:05f0b5a3a70a	3979	#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /!< Bit mask of CH5 field. /
yihui	9:05f0b5a3a70a	3980	#define PPI_CHENCLR_CH5_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3981	#define PPI_CHENCLR_CH5_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3982	#define PPI_CHENCLR_CH5_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3983
yihui	9:05f0b5a3a70a	3984	/* Bit 4 : Disable PPI channel 4. */
yihui	9:05f0b5a3a70a	3985	#define PPI_CHENCLR_CH4_Pos (4UL) /!< Position of CH4 field. /
yihui	9:05f0b5a3a70a	3986	#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /!< Bit mask of CH4 field. /
yihui	9:05f0b5a3a70a	3987	#define PPI_CHENCLR_CH4_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3988	#define PPI_CHENCLR_CH4_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3989	#define PPI_CHENCLR_CH4_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3990
yihui	9:05f0b5a3a70a	3991	/* Bit 3 : Disable PPI channel 3. */
yihui	9:05f0b5a3a70a	3992	#define PPI_CHENCLR_CH3_Pos (3UL) /!< Position of CH3 field. /
yihui	9:05f0b5a3a70a	3993	#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /!< Bit mask of CH3 field. /
yihui	9:05f0b5a3a70a	3994	#define PPI_CHENCLR_CH3_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	3995	#define PPI_CHENCLR_CH3_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	3996	#define PPI_CHENCLR_CH3_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	3997
yihui	9:05f0b5a3a70a	3998	/* Bit 2 : Disable PPI channel 2. */
yihui	9:05f0b5a3a70a	3999	#define PPI_CHENCLR_CH2_Pos (2UL) /!< Position of CH2 field. /
yihui	9:05f0b5a3a70a	4000	#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /!< Bit mask of CH2 field. /
yihui	9:05f0b5a3a70a	4001	#define PPI_CHENCLR_CH2_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	4002	#define PPI_CHENCLR_CH2_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	4003	#define PPI_CHENCLR_CH2_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	4004
yihui	9:05f0b5a3a70a	4005	/* Bit 1 : Disable PPI channel 1. */
yihui	9:05f0b5a3a70a	4006	#define PPI_CHENCLR_CH1_Pos (1UL) /!< Position of CH1 field. /
yihui	9:05f0b5a3a70a	4007	#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /!< Bit mask of CH1 field. /
yihui	9:05f0b5a3a70a	4008	#define PPI_CHENCLR_CH1_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	4009	#define PPI_CHENCLR_CH1_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	4010	#define PPI_CHENCLR_CH1_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	4011
yihui	9:05f0b5a3a70a	4012	/* Bit 0 : Disable PPI channel 0. */
yihui	9:05f0b5a3a70a	4013	#define PPI_CHENCLR_CH0_Pos (0UL) /!< Position of CH0 field. /
yihui	9:05f0b5a3a70a	4014	#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /!< Bit mask of CH0 field. /
yihui	9:05f0b5a3a70a	4015	#define PPI_CHENCLR_CH0_Disabled (0UL) /!< Channel disabled. /
yihui	9:05f0b5a3a70a	4016	#define PPI_CHENCLR_CH0_Enabled (1UL) /!< Channel enabled. /
yihui	9:05f0b5a3a70a	4017	#define PPI_CHENCLR_CH0_Clear (1UL) /!< Disable channel on write. /
yihui	9:05f0b5a3a70a	4018
yihui	9:05f0b5a3a70a	4019	/* Register: PPI_CHG */
yihui	9:05f0b5a3a70a	4020	/* Description: Channel group configuration. */
yihui	9:05f0b5a3a70a	4021
yihui	9:05f0b5a3a70a	4022	/* Bit 31 : Include CH31 in channel group. */
yihui	9:05f0b5a3a70a	4023	#define PPI_CHG_CH31_Pos (31UL) /!< Position of CH31 field. /
yihui	9:05f0b5a3a70a	4024	#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /!< Bit mask of CH31 field. /
yihui	9:05f0b5a3a70a	4025	#define PPI_CHG_CH31_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4026	#define PPI_CHG_CH31_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4027
yihui	9:05f0b5a3a70a	4028	/* Bit 30 : Include CH30 in channel group. */
yihui	9:05f0b5a3a70a	4029	#define PPI_CHG_CH30_Pos (30UL) /!< Position of CH30 field. /
yihui	9:05f0b5a3a70a	4030	#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /!< Bit mask of CH30 field. /
yihui	9:05f0b5a3a70a	4031	#define PPI_CHG_CH30_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4032	#define PPI_CHG_CH30_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4033
yihui	9:05f0b5a3a70a	4034	/* Bit 29 : Include CH29 in channel group. */
yihui	9:05f0b5a3a70a	4035	#define PPI_CHG_CH29_Pos (29UL) /!< Position of CH29 field. /
yihui	9:05f0b5a3a70a	4036	#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /!< Bit mask of CH29 field. /
yihui	9:05f0b5a3a70a	4037	#define PPI_CHG_CH29_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4038	#define PPI_CHG_CH29_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4039
yihui	9:05f0b5a3a70a	4040	/* Bit 28 : Include CH28 in channel group. */
yihui	9:05f0b5a3a70a	4041	#define PPI_CHG_CH28_Pos (28UL) /!< Position of CH28 field. /
yihui	9:05f0b5a3a70a	4042	#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /!< Bit mask of CH28 field. /
yihui	9:05f0b5a3a70a	4043	#define PPI_CHG_CH28_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4044	#define PPI_CHG_CH28_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4045
yihui	9:05f0b5a3a70a	4046	/* Bit 27 : Include CH27 in channel group. */
yihui	9:05f0b5a3a70a	4047	#define PPI_CHG_CH27_Pos (27UL) /!< Position of CH27 field. /
yihui	9:05f0b5a3a70a	4048	#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /!< Bit mask of CH27 field. /
yihui	9:05f0b5a3a70a	4049	#define PPI_CHG_CH27_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4050	#define PPI_CHG_CH27_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4051
yihui	9:05f0b5a3a70a	4052	/* Bit 26 : Include CH26 in channel group. */
yihui	9:05f0b5a3a70a	4053	#define PPI_CHG_CH26_Pos (26UL) /!< Position of CH26 field. /
yihui	9:05f0b5a3a70a	4054	#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /!< Bit mask of CH26 field. /
yihui	9:05f0b5a3a70a	4055	#define PPI_CHG_CH26_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4056	#define PPI_CHG_CH26_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4057
yihui	9:05f0b5a3a70a	4058	/* Bit 25 : Include CH25 in channel group. */
yihui	9:05f0b5a3a70a	4059	#define PPI_CHG_CH25_Pos (25UL) /!< Position of CH25 field. /
yihui	9:05f0b5a3a70a	4060	#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /!< Bit mask of CH25 field. /
yihui	9:05f0b5a3a70a	4061	#define PPI_CHG_CH25_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4062	#define PPI_CHG_CH25_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4063
yihui	9:05f0b5a3a70a	4064	/* Bit 24 : Include CH24 in channel group. */
yihui	9:05f0b5a3a70a	4065	#define PPI_CHG_CH24_Pos (24UL) /!< Position of CH24 field. /
yihui	9:05f0b5a3a70a	4066	#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /!< Bit mask of CH24 field. /
yihui	9:05f0b5a3a70a	4067	#define PPI_CHG_CH24_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4068	#define PPI_CHG_CH24_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4069
yihui	9:05f0b5a3a70a	4070	/* Bit 23 : Include CH23 in channel group. */
yihui	9:05f0b5a3a70a	4071	#define PPI_CHG_CH23_Pos (23UL) /!< Position of CH23 field. /
yihui	9:05f0b5a3a70a	4072	#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /!< Bit mask of CH23 field. /
yihui	9:05f0b5a3a70a	4073	#define PPI_CHG_CH23_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4074	#define PPI_CHG_CH23_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4075
yihui	9:05f0b5a3a70a	4076	/* Bit 22 : Include CH22 in channel group. */
yihui	9:05f0b5a3a70a	4077	#define PPI_CHG_CH22_Pos (22UL) /!< Position of CH22 field. /
yihui	9:05f0b5a3a70a	4078	#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /!< Bit mask of CH22 field. /
yihui	9:05f0b5a3a70a	4079	#define PPI_CHG_CH22_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4080	#define PPI_CHG_CH22_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4081
yihui	9:05f0b5a3a70a	4082	/* Bit 21 : Include CH21 in channel group. */
yihui	9:05f0b5a3a70a	4083	#define PPI_CHG_CH21_Pos (21UL) /!< Position of CH21 field. /
yihui	9:05f0b5a3a70a	4084	#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /!< Bit mask of CH21 field. /
yihui	9:05f0b5a3a70a	4085	#define PPI_CHG_CH21_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4086	#define PPI_CHG_CH21_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4087
yihui	9:05f0b5a3a70a	4088	/* Bit 20 : Include CH20 in channel group. */
yihui	9:05f0b5a3a70a	4089	#define PPI_CHG_CH20_Pos (20UL) /!< Position of CH20 field. /
yihui	9:05f0b5a3a70a	4090	#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /!< Bit mask of CH20 field. /
yihui	9:05f0b5a3a70a	4091	#define PPI_CHG_CH20_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4092	#define PPI_CHG_CH20_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4093
yihui	9:05f0b5a3a70a	4094	/* Bit 15 : Include CH15 in channel group. */
yihui	9:05f0b5a3a70a	4095	#define PPI_CHG_CH15_Pos (15UL) /!< Position of CH15 field. /
yihui	9:05f0b5a3a70a	4096	#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /!< Bit mask of CH15 field. /
yihui	9:05f0b5a3a70a	4097	#define PPI_CHG_CH15_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4098	#define PPI_CHG_CH15_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4099
yihui	9:05f0b5a3a70a	4100	/* Bit 14 : Include CH14 in channel group. */
yihui	9:05f0b5a3a70a	4101	#define PPI_CHG_CH14_Pos (14UL) /!< Position of CH14 field. /
yihui	9:05f0b5a3a70a	4102	#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /!< Bit mask of CH14 field. /
yihui	9:05f0b5a3a70a	4103	#define PPI_CHG_CH14_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4104	#define PPI_CHG_CH14_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4105
yihui	9:05f0b5a3a70a	4106	/* Bit 13 : Include CH13 in channel group. */
yihui	9:05f0b5a3a70a	4107	#define PPI_CHG_CH13_Pos (13UL) /!< Position of CH13 field. /
yihui	9:05f0b5a3a70a	4108	#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /!< Bit mask of CH13 field. /
yihui	9:05f0b5a3a70a	4109	#define PPI_CHG_CH13_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4110	#define PPI_CHG_CH13_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4111
yihui	9:05f0b5a3a70a	4112	/* Bit 12 : Include CH12 in channel group. */
yihui	9:05f0b5a3a70a	4113	#define PPI_CHG_CH12_Pos (12UL) /!< Position of CH12 field. /
yihui	9:05f0b5a3a70a	4114	#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /!< Bit mask of CH12 field. /
yihui	9:05f0b5a3a70a	4115	#define PPI_CHG_CH12_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4116	#define PPI_CHG_CH12_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4117
yihui	9:05f0b5a3a70a	4118	/* Bit 11 : Include CH11 in channel group. */
yihui	9:05f0b5a3a70a	4119	#define PPI_CHG_CH11_Pos (11UL) /!< Position of CH11 field. /
yihui	9:05f0b5a3a70a	4120	#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /!< Bit mask of CH11 field. /
yihui	9:05f0b5a3a70a	4121	#define PPI_CHG_CH11_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4122	#define PPI_CHG_CH11_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4123
yihui	9:05f0b5a3a70a	4124	/* Bit 10 : Include CH10 in channel group. */
yihui	9:05f0b5a3a70a	4125	#define PPI_CHG_CH10_Pos (10UL) /!< Position of CH10 field. /
yihui	9:05f0b5a3a70a	4126	#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /!< Bit mask of CH10 field. /
yihui	9:05f0b5a3a70a	4127	#define PPI_CHG_CH10_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4128	#define PPI_CHG_CH10_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4129
yihui	9:05f0b5a3a70a	4130	/* Bit 9 : Include CH9 in channel group. */
yihui	9:05f0b5a3a70a	4131	#define PPI_CHG_CH9_Pos (9UL) /!< Position of CH9 field. /
yihui	9:05f0b5a3a70a	4132	#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /!< Bit mask of CH9 field. /
yihui	9:05f0b5a3a70a	4133	#define PPI_CHG_CH9_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4134	#define PPI_CHG_CH9_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4135
yihui	9:05f0b5a3a70a	4136	/* Bit 8 : Include CH8 in channel group. */
yihui	9:05f0b5a3a70a	4137	#define PPI_CHG_CH8_Pos (8UL) /!< Position of CH8 field. /
yihui	9:05f0b5a3a70a	4138	#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /!< Bit mask of CH8 field. /
yihui	9:05f0b5a3a70a	4139	#define PPI_CHG_CH8_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4140	#define PPI_CHG_CH8_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4141
yihui	9:05f0b5a3a70a	4142	/* Bit 7 : Include CH7 in channel group. */
yihui	9:05f0b5a3a70a	4143	#define PPI_CHG_CH7_Pos (7UL) /!< Position of CH7 field. /
yihui	9:05f0b5a3a70a	4144	#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /!< Bit mask of CH7 field. /
yihui	9:05f0b5a3a70a	4145	#define PPI_CHG_CH7_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4146	#define PPI_CHG_CH7_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4147
yihui	9:05f0b5a3a70a	4148	/* Bit 6 : Include CH6 in channel group. */
yihui	9:05f0b5a3a70a	4149	#define PPI_CHG_CH6_Pos (6UL) /!< Position of CH6 field. /
yihui	9:05f0b5a3a70a	4150	#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /!< Bit mask of CH6 field. /
yihui	9:05f0b5a3a70a	4151	#define PPI_CHG_CH6_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4152	#define PPI_CHG_CH6_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4153
yihui	9:05f0b5a3a70a	4154	/* Bit 5 : Include CH5 in channel group. */
yihui	9:05f0b5a3a70a	4155	#define PPI_CHG_CH5_Pos (5UL) /!< Position of CH5 field. /
yihui	9:05f0b5a3a70a	4156	#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /!< Bit mask of CH5 field. /
yihui	9:05f0b5a3a70a	4157	#define PPI_CHG_CH5_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4158	#define PPI_CHG_CH5_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4159
yihui	9:05f0b5a3a70a	4160	/* Bit 4 : Include CH4 in channel group. */
yihui	9:05f0b5a3a70a	4161	#define PPI_CHG_CH4_Pos (4UL) /!< Position of CH4 field. /
yihui	9:05f0b5a3a70a	4162	#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /!< Bit mask of CH4 field. /
yihui	9:05f0b5a3a70a	4163	#define PPI_CHG_CH4_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4164	#define PPI_CHG_CH4_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4165
yihui	9:05f0b5a3a70a	4166	/* Bit 3 : Include CH3 in channel group. */
yihui	9:05f0b5a3a70a	4167	#define PPI_CHG_CH3_Pos (3UL) /!< Position of CH3 field. /
yihui	9:05f0b5a3a70a	4168	#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /!< Bit mask of CH3 field. /
yihui	9:05f0b5a3a70a	4169	#define PPI_CHG_CH3_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4170	#define PPI_CHG_CH3_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4171
yihui	9:05f0b5a3a70a	4172	/* Bit 2 : Include CH2 in channel group. */
yihui	9:05f0b5a3a70a	4173	#define PPI_CHG_CH2_Pos (2UL) /!< Position of CH2 field. /
yihui	9:05f0b5a3a70a	4174	#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /!< Bit mask of CH2 field. /
yihui	9:05f0b5a3a70a	4175	#define PPI_CHG_CH2_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4176	#define PPI_CHG_CH2_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4177
yihui	9:05f0b5a3a70a	4178	/* Bit 1 : Include CH1 in channel group. */
yihui	9:05f0b5a3a70a	4179	#define PPI_CHG_CH1_Pos (1UL) /!< Position of CH1 field. /
yihui	9:05f0b5a3a70a	4180	#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /!< Bit mask of CH1 field. /
yihui	9:05f0b5a3a70a	4181	#define PPI_CHG_CH1_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4182	#define PPI_CHG_CH1_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4183
yihui	9:05f0b5a3a70a	4184	/* Bit 0 : Include CH0 in channel group. */
yihui	9:05f0b5a3a70a	4185	#define PPI_CHG_CH0_Pos (0UL) /!< Position of CH0 field. /
yihui	9:05f0b5a3a70a	4186	#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /!< Bit mask of CH0 field. /
yihui	9:05f0b5a3a70a	4187	#define PPI_CHG_CH0_Excluded (0UL) /!< Channel excluded. /
yihui	9:05f0b5a3a70a	4188	#define PPI_CHG_CH0_Included (1UL) /!< Channel included. /
yihui	9:05f0b5a3a70a	4189
yihui	9:05f0b5a3a70a	4190
yihui	9:05f0b5a3a70a	4191	/* Peripheral: PU */
yihui	9:05f0b5a3a70a	4192	/* Description: Patch unit. */
yihui	9:05f0b5a3a70a	4193
yihui	9:05f0b5a3a70a	4194	/* Register: PU_PATCHADDR */
yihui	9:05f0b5a3a70a	4195	/* Description: Relative address of patch instructions. */
yihui	9:05f0b5a3a70a	4196
yihui	9:05f0b5a3a70a	4197	/* Bits 24..0 : Relative address of patch instructions. */
yihui	9:05f0b5a3a70a	4198	#define PU_PATCHADDR_PATCHADDR_Pos (0UL) /!< Position of PATCHADDR field. /
yihui	9:05f0b5a3a70a	4199	#define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /!< Bit mask of PATCHADDR field. /
yihui	9:05f0b5a3a70a	4200
yihui	9:05f0b5a3a70a	4201	/* Register: PU_PATCHEN */
yihui	9:05f0b5a3a70a	4202	/* Description: Patch enable register. */
yihui	9:05f0b5a3a70a	4203
yihui	9:05f0b5a3a70a	4204	/* Bit 7 : Patch 7 enabled. */
yihui	9:05f0b5a3a70a	4205	#define PU_PATCHEN_PATCH7_Pos (7UL) /!< Position of PATCH7 field. /
yihui	9:05f0b5a3a70a	4206	#define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /!< Bit mask of PATCH7 field. /
yihui	9:05f0b5a3a70a	4207	#define PU_PATCHEN_PATCH7_Disabled (0UL) /!< Patch disabled. /
yihui	9:05f0b5a3a70a	4208	#define PU_PATCHEN_PATCH7_Enabled (1UL) /!< Patch enabled. /
yihui	9:05f0b5a3a70a	4209
yihui	9:05f0b5a3a70a	4210	/* Bit 6 : Patch 6 enabled. */
yihui	9:05f0b5a3a70a	4211	#define PU_PATCHEN_PATCH6_Pos (6UL) /!< Position of PATCH6 field. /
yihui	9:05f0b5a3a70a	4212	#define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /!< Bit mask of PATCH6 field. /
yihui	9:05f0b5a3a70a	4213	#define PU_PATCHEN_PATCH6_Disabled (0UL) /!< Patch disabled. /
yihui	9:05f0b5a3a70a	4214	#define PU_PATCHEN_PATCH6_Enabled (1UL) /!< Patch enabled. /
yihui	9:05f0b5a3a70a	4215
yihui	9:05f0b5a3a70a	4216	/* Bit 5 : Patch 5 enabled. */
yihui	9:05f0b5a3a70a	4217	#define PU_PATCHEN_PATCH5_Pos (5UL) /!< Position of PATCH5 field. /
yihui	9:05f0b5a3a70a	4218	#define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /!< Bit mask of PATCH5 field. /
yihui	9:05f0b5a3a70a	4219	#define PU_PATCHEN_PATCH5_Disabled (0UL) /!< Patch disabled. /
yihui	9:05f0b5a3a70a	4220	#define PU_PATCHEN_PATCH5_Enabled (1UL) /!< Patch enabled. /
yihui	9:05f0b5a3a70a	4221
yihui	9:05f0b5a3a70a	4222	/* Bit 4 : Patch 4 enabled. */
yihui	9:05f0b5a3a70a	4223	#define PU_PATCHEN_PATCH4_Pos (4UL) /!< Position of PATCH4 field. /
yihui	9:05f0b5a3a70a	4224	#define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /!< Bit mask of PATCH4 field. /
yihui	9:05f0b5a3a70a	4225	#define PU_PATCHEN_PATCH4_Disabled (0UL) /!< Patch disabled. /
yihui	9:05f0b5a3a70a	4226	#define PU_PATCHEN_PATCH4_Enabled (1UL) /!< Patch enabled. /
yihui	9:05f0b5a3a70a	4227
yihui	9:05f0b5a3a70a	4228	/* Bit 3 : Patch 3 enabled. */
yihui	9:05f0b5a3a70a	4229	#define PU_PATCHEN_PATCH3_Pos (3UL) /!< Position of PATCH3 field. /
yihui	9:05f0b5a3a70a	4230	#define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /!< Bit mask of PATCH3 field. /
yihui	9:05f0b5a3a70a	4231	#define PU_PATCHEN_PATCH3_Disabled (0UL) /!< Patch disabled. /
yihui	9:05f0b5a3a70a	4232	#define PU_PATCHEN_PATCH3_Enabled (1UL) /!< Patch enabled. /
yihui	9:05f0b5a3a70a	4233
yihui	9:05f0b5a3a70a	4234	/* Bit 2 : Patch 2 enabled. */
yihui	9:05f0b5a3a70a	4235	#define PU_PATCHEN_PATCH2_Pos (2UL) /!< Position of PATCH2 field. /
yihui	9:05f0b5a3a70a	4236	#define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /!< Bit mask of PATCH2 field. /
yihui	9:05f0b5a3a70a	4237	#define PU_PATCHEN_PATCH2_Disabled (0UL) /!< Patch disabled. /
yihui	9:05f0b5a3a70a	4238	#define PU_PATCHEN_PATCH2_Enabled (1UL) /!< Patch enabled. /
yihui	9:05f0b5a3a70a	4239
yihui	9:05f0b5a3a70a	4240	/* Bit 1 : Patch 1 enabled. */
yihui	9:05f0b5a3a70a	4241	#define PU_PATCHEN_PATCH1_Pos (1UL) /!< Position of PATCH1 field. /
yihui	9:05f0b5a3a70a	4242	#define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /!< Bit mask of PATCH1 field. /
yihui	9:05f0b5a3a70a	4243	#define PU_PATCHEN_PATCH1_Disabled (0UL) /!< Patch disabled. /
yihui	9:05f0b5a3a70a	4244	#define PU_PATCHEN_PATCH1_Enabled (1UL) /!< Patch enabled. /
yihui	9:05f0b5a3a70a	4245
yihui	9:05f0b5a3a70a	4246	/* Bit 0 : Patch 0 enabled. */
yihui	9:05f0b5a3a70a	4247	#define PU_PATCHEN_PATCH0_Pos (0UL) /!< Position of PATCH0 field. /
yihui	9:05f0b5a3a70a	4248	#define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /!< Bit mask of PATCH0 field. /
yihui	9:05f0b5a3a70a	4249	#define PU_PATCHEN_PATCH0_Disabled (0UL) /!< Patch disabled. /
yihui	9:05f0b5a3a70a	4250	#define PU_PATCHEN_PATCH0_Enabled (1UL) /!< Patch enabled. /
yihui	9:05f0b5a3a70a	4251
yihui	9:05f0b5a3a70a	4252	/* Register: PU_PATCHENSET */
yihui	9:05f0b5a3a70a	4253	/* Description: Patch enable register. */
yihui	9:05f0b5a3a70a	4254
yihui	9:05f0b5a3a70a	4255	/* Bit 7 : Patch 7 enabled. */
yihui	9:05f0b5a3a70a	4256	#define PU_PATCHENSET_PATCH7_Pos (7UL) /!< Position of PATCH7 field. /
yihui	9:05f0b5a3a70a	4257	#define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /!< Bit mask of PATCH7 field. /
yihui	9:05f0b5a3a70a	4258	#define PU_PATCHENSET_PATCH7_Disabled (0UL) /!< Patch disabled. /
yihui	9:05f0b5a3a70a	4259	#define PU_PATCHENSET_PATCH7_Enabled (1UL) /!< Patch enabled. /
yihui	9:05f0b5a3a70a	4260	#define PU_PATCHENSET_PATCH7_Set (1UL) /!< Enable patch on write. /
yihui	9:05f0b5a3a70a	4261
yihui	9:05f0b5a3a70a	4262	/* Bit 6 : Patch 6 enabled. */
yihui	9:05f0b5a3a70a	4263	#define PU_PATCHENSET_PATCH6_Pos (6UL) /!< Position of PATCH6 field. /
yihui	9:05f0b5a3a70a	4264	#define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /!< Bit mask of PATCH6 field. /
yihui	9:05f0b5a3a70a	4265	#define PU_PATCHENSET_PATCH6_Disabled (0UL) /!< Patch disabled. /
yihui	9:05f0b5a3a70a	4266	#define PU_PATCHENSET_PATCH6_Enabled (1UL) /!< Patch enabled. /
yihui	9:05f0b5a3a70a	4267	#define PU_PATCHENSET_PATCH6_Set (1UL) /!< Enable patch on write. /
yihui	9:05f0b5a3a70a	4268
yihui	9:05f0b5a3a70a	4269	/* Bit 5 : Patch 5 enabled. */
yihui	9:05f0b5a3a70a	4270	#define PU_PATCHENSET_PATCH5_Pos (5UL) /!< Position of PATCH5 field. /
yihui	9:05f0b5a3a70a	4271	#define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /!< Bit mask of PATCH5 field. /
yihui	9:05f0b5a3a70a	4272	#define PU_PATCHENSET_PATCH5_Disabled (0UL) /!< Patch disabled. /
yihui	9:05f0b5a3a70a	4273	#define PU_PATCHENSET_PATCH5_Enabled (1UL) /!< Patch enabled. /
yihui	9:05f0b5a3a70a	4274	#define PU_PATCHENSET_PATCH5_Set (1UL) /!< Enable patch on write. /
yihui	9:05f0b5a3a70a	4275
yihui	9:05f0b5a3a70a	4276	/* Bit 4 : Patch 4 enabled. */
yihui	9:05f0b5a3a70a	4277	#define PU_PATCHENSET_PATCH4_Pos (4UL) /!< Position of PATCH4 field. /
yihui	9:05f0b5a3a70a	4278	#define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /!< Bit mask of PATCH4 field. /
yihui	9:05f0b5a3a70a	4279	#define PU_PATCHENSET_PATCH4_Disabled (0UL) /!< Patch disabled. /
yihui	9:05f0b5a3a70a	4280	#define PU_PATCHENSET_PATCH4_Enabled (1UL) /!< Patch enabled. /
yihui	9:05f0b5a3a70a	4281	#define PU_PATCHENSET_PATCH4_Set (1UL) /!< Enable patch on write. /
yihui	9:05f0b5a3a70a	4282
yihui	9:05f0b5a3a70a	4283	/* Bit 3 : Patch 3 enabled. */
yihui	9:05f0b5a3a70a	4284	#define PU_PATCHENSET_PATCH3_Pos (3UL) /!< Position of PATCH3 field. /
yihui	9:05f0b5a3a70a	4285	#define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /!< Bit mask of PATCH3 field. /
yihui	9:05f0b5a3a70a	4286	#define PU_PATCHENSET_PATCH3_Disabled (0UL) /!< Patch disabled. /
yihui	9:05f0b5a3a70a	4287	#define PU_PATCHENSET_PATCH3_Enabled (1UL) /!< Patch enabled. /
yihui	9:05f0b5a3a70a	4288	#define PU_PATCHENSET_PATCH3_Set (1UL) /!< Enable patch on write. /
yihui	9:05f0b5a3a70a	4289
yihui	9:05f0b5a3a70a	4290	/* Bit 2 : Patch 2 enabled. */
yihui	9:05f0b5a3a70a	4291	#define PU_PATCHENSET_PATCH2_Pos (2UL) /!< Position of PATCH2 field. /
yihui	9:05f0b5a3a70a	4292	#define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /!< Bit mask of PATCH2 field. /
yihui	9:05f0b5a3a70a	4293	#define PU_PATCHENSET_PATCH2_Disabled (0UL) /!< Patch disabled. /
yihui	9:05f0b5a3a70a	4294	#define PU_PATCHENSET_PATCH2_Enabled (1UL) /!< Patch enabled. /
yihui	9:05f0b5a3a70a	4295	#define PU_PATCHENSET_PATCH2_Set (1UL) /!< Enable patch on write. /
yihui	9:05f0b5a3a70a	4296
yihui	9:05f0b5a3a70a	4297	/* Bit 1 : Patch 1 enabled. */
yihui	9:05f0b5a3a70a	4298	#define PU_PATCHENSET_PATCH1_Pos (1UL) /!< Position of PATCH1 field. /
yihui	9:05f0b5a3a70a	4299	#define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /!< Bit mask of PATCH1 field. /
yihui	9:05f0b5a3a70a	4300	#define PU_PATCHENSET_PATCH1_Disabled (0UL) /!< Patch disabled. /
yihui	9:05f0b5a3a70a	4301	#define PU_PATCHENSET_PATCH1_Enabled (1UL) /!< Patch enabled. /
yihui	9:05f0b5a3a70a	4302	#define PU_PATCHENSET_PATCH1_Set (1UL) /!< Enable patch on write. /
yihui	9:05f0b5a3a70a	4303
yihui	9:05f0b5a3a70a	4304	/* Bit 0 : Patch 0 enabled. */
yihui	9:05f0b5a3a70a	4305	#define PU_PATCHENSET_PATCH0_Pos (0UL) /!< Position of PATCH0 field. /
yihui	9:05f0b5a3a70a	4306	#define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /!< Bit mask of PATCH0 field. /
yihui	9:05f0b5a3a70a	4307	#define PU_PATCHENSET_PATCH0_Disabled (0UL) /!< Patch disabled. /
yihui	9:05f0b5a3a70a	4308	#define PU_PATCHENSET_PATCH0_Enabled (1UL) /!< Patch enabled. /
yihui	9:05f0b5a3a70a	4309	#define PU_PATCHENSET_PATCH0_Set (1UL) /!< Enable patch on write. /
yihui	9:05f0b5a3a70a	4310
yihui	9:05f0b5a3a70a	4311	/* Register: PU_PATCHENCLR */
yihui	9:05f0b5a3a70a	4312	/* Description: Patch disable register. */
yihui	9:05f0b5a3a70a	4313
yihui	9:05f0b5a3a70a	4314	/* Bit 7 : Patch 7 enabled. */
yihui	9:05f0b5a3a70a	4315	#define PU_PATCHENCLR_PATCH7_Pos (7UL) /!< Position of PATCH7 field. /
yihui	9:05f0b5a3a70a	4316	#define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /!< Bit mask of PATCH7 field. /
yihui	9:05f0b5a3a70a	4317	#define PU_PATCHENCLR_PATCH7_Disabled (0UL) /!< Patch disabled. /
yihui	9:05f0b5a3a70a	4318	#define PU_PATCHENCLR_PATCH7_Enabled (1UL) /!< Patch enabled. /
yihui	9:05f0b5a3a70a	4319	#define PU_PATCHENCLR_PATCH7_Clear (1UL) /!< Disable patch on write. /
yihui	9:05f0b5a3a70a	4320
yihui	9:05f0b5a3a70a	4321	/* Bit 6 : Patch 6 enabled. */
yihui	9:05f0b5a3a70a	4322	#define PU_PATCHENCLR_PATCH6_Pos (6UL) /!< Position of PATCH6 field. /
yihui	9:05f0b5a3a70a	4323	#define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /!< Bit mask of PATCH6 field. /
yihui	9:05f0b5a3a70a	4324	#define PU_PATCHENCLR_PATCH6_Disabled (0UL) /!< Patch disabled. /
yihui	9:05f0b5a3a70a	4325	#define PU_PATCHENCLR_PATCH6_Enabled (1UL) /!< Patch enabled. /
yihui	9:05f0b5a3a70a	4326	#define PU_PATCHENCLR_PATCH6_Clear (1UL) /!< Disable patch on write. /
yihui	9:05f0b5a3a70a	4327
yihui	9:05f0b5a3a70a	4328	/* Bit 5 : Patch 5 enabled. */
yihui	9:05f0b5a3a70a	4329	#define PU_PATCHENCLR_PATCH5_Pos (5UL) /!< Position of PATCH5 field. /
yihui	9:05f0b5a3a70a	4330	#define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /!< Bit mask of PATCH5 field. /
yihui	9:05f0b5a3a70a	4331	#define PU_PATCHENCLR_PATCH5_Disabled (0UL) /!< Patch disabled. /
yihui	9:05f0b5a3a70a	4332	#define PU_PATCHENCLR_PATCH5_Enabled (1UL) /!< Patch enabled. /
yihui	9:05f0b5a3a70a	4333	#define PU_PATCHENCLR_PATCH5_Clear (1UL) /!< Disable patch on write. /
yihui	9:05f0b5a3a70a	4334
yihui	9:05f0b5a3a70a	4335	/* Bit 4 : Patch 4 enabled. */
yihui	9:05f0b5a3a70a	4336	#define PU_PATCHENCLR_PATCH4_Pos (4UL) /!< Position of PATCH4 field. /
yihui	9:05f0b5a3a70a	4337	#define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /!< Bit mask of PATCH4 field. /
yihui	9:05f0b5a3a70a	4338	#define PU_PATCHENCLR_PATCH4_Disabled (0UL) /!< Patch disabled. /
yihui	9:05f0b5a3a70a	4339	#define PU_PATCHENCLR_PATCH4_Enabled (1UL) /!< Patch enabled. /
yihui	9:05f0b5a3a70a	4340	#define PU_PATCHENCLR_PATCH4_Clear (1UL) /!< Disable patch on write. /
yihui	9:05f0b5a3a70a	4341
yihui	9:05f0b5a3a70a	4342	/* Bit 3 : Patch 3 enabled. */
yihui	9:05f0b5a3a70a	4343	#define PU_PATCHENCLR_PATCH3_Pos (3UL) /!< Position of PATCH3 field. /
yihui	9:05f0b5a3a70a	4344	#define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /!< Bit mask of PATCH3 field. /
yihui	9:05f0b5a3a70a	4345	#define PU_PATCHENCLR_PATCH3_Disabled (0UL) /!< Patch disabled. /
yihui	9:05f0b5a3a70a	4346	#define PU_PATCHENCLR_PATCH3_Enabled (1UL) /!< Patch enabled. /
yihui	9:05f0b5a3a70a	4347	#define PU_PATCHENCLR_PATCH3_Clear (1UL) /!< Disable patch on write. /
yihui	9:05f0b5a3a70a	4348
yihui	9:05f0b5a3a70a	4349	/* Bit 2 : Patch 2 enabled. */
yihui	9:05f0b5a3a70a	4350	#define PU_PATCHENCLR_PATCH2_Pos (2UL) /!< Position of PATCH2 field. /
yihui	9:05f0b5a3a70a	4351	#define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /!< Bit mask of PATCH2 field. /
yihui	9:05f0b5a3a70a	4352	#define PU_PATCHENCLR_PATCH2_Disabled (0UL) /!< Patch disabled. /
yihui	9:05f0b5a3a70a	4353	#define PU_PATCHENCLR_PATCH2_Enabled (1UL) /!< Patch enabled. /
yihui	9:05f0b5a3a70a	4354	#define PU_PATCHENCLR_PATCH2_Clear (1UL) /!< Disable patch on write. /
yihui	9:05f0b5a3a70a	4355
yihui	9:05f0b5a3a70a	4356	/* Bit 1 : Patch 1 enabled. */
yihui	9:05f0b5a3a70a	4357	#define PU_PATCHENCLR_PATCH1_Pos (1UL) /!< Position of PATCH1 field. /
yihui	9:05f0b5a3a70a	4358	#define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /!< Bit mask of PATCH1 field. /
yihui	9:05f0b5a3a70a	4359	#define PU_PATCHENCLR_PATCH1_Disabled (0UL) /!< Patch disabled. /
yihui	9:05f0b5a3a70a	4360	#define PU_PATCHENCLR_PATCH1_Enabled (1UL) /!< Patch enabled. /
yihui	9:05f0b5a3a70a	4361	#define PU_PATCHENCLR_PATCH1_Clear (1UL) /!< Disable patch on write. /
yihui	9:05f0b5a3a70a	4362
yihui	9:05f0b5a3a70a	4363	/* Bit 0 : Patch 0 enabled. */
yihui	9:05f0b5a3a70a	4364	#define PU_PATCHENCLR_PATCH0_Pos (0UL) /!< Position of PATCH0 field. /
yihui	9:05f0b5a3a70a	4365	#define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /!< Bit mask of PATCH0 field. /
yihui	9:05f0b5a3a70a	4366	#define PU_PATCHENCLR_PATCH0_Disabled (0UL) /!< Patch disabled. /
yihui	9:05f0b5a3a70a	4367	#define PU_PATCHENCLR_PATCH0_Enabled (1UL) /!< Patch enabled. /
yihui	9:05f0b5a3a70a	4368	#define PU_PATCHENCLR_PATCH0_Clear (1UL) /!< Disable patch on write. /
yihui	9:05f0b5a3a70a	4369
yihui	9:05f0b5a3a70a	4370
yihui	9:05f0b5a3a70a	4371	/* Peripheral: QDEC */
yihui	9:05f0b5a3a70a	4372	/* Description: Rotary decoder. */
yihui	9:05f0b5a3a70a	4373
yihui	9:05f0b5a3a70a	4374	/* Register: QDEC_SHORTS */
yihui	9:05f0b5a3a70a	4375	/* Description: Shortcut for the QDEC. */
yihui	9:05f0b5a3a70a	4376
yihui	9:05f0b5a3a70a	4377	/* Bit 1 : Short-cut between SAMPLERDY event and STOP task. */
yihui	9:05f0b5a3a70a	4378	#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /!< Position of SAMPLERDY_STOP field. /
yihui	9:05f0b5a3a70a	4379	#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /!< Bit mask of SAMPLERDY_STOP field. /
yihui	9:05f0b5a3a70a	4380	#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	4381	#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	4382
yihui	9:05f0b5a3a70a	4383	/* Bit 0 : Short-cut between REPORTRDY event and READCLRACC task. */
yihui	9:05f0b5a3a70a	4384	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /!< Position of REPORTRDY_READCLRACC field. /
yihui	9:05f0b5a3a70a	4385	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /!< Bit mask of REPORTRDY_READCLRACC field. /
yihui	9:05f0b5a3a70a	4386	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	4387	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	4388
yihui	9:05f0b5a3a70a	4389	/* Register: QDEC_INTENSET */
yihui	9:05f0b5a3a70a	4390	/* Description: Interrupt enable set register. */
yihui	9:05f0b5a3a70a	4391
yihui	9:05f0b5a3a70a	4392	/* Bit 2 : Enable interrupt on ACCOF event. */
yihui	9:05f0b5a3a70a	4393	#define QDEC_INTENSET_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
yihui	9:05f0b5a3a70a	4394	#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /!< Bit mask of ACCOF field. /
yihui	9:05f0b5a3a70a	4395	#define QDEC_INTENSET_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	4396	#define QDEC_INTENSET_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	4397	#define QDEC_INTENSET_ACCOF_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	4398
yihui	9:05f0b5a3a70a	4399	/* Bit 1 : Enable interrupt on REPORTRDY event. */
yihui	9:05f0b5a3a70a	4400	#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
yihui	9:05f0b5a3a70a	4401	#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
yihui	9:05f0b5a3a70a	4402	#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	4403	#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	4404	#define QDEC_INTENSET_REPORTRDY_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	4405
yihui	9:05f0b5a3a70a	4406	/* Bit 0 : Enable interrupt on SAMPLERDY event. */
yihui	9:05f0b5a3a70a	4407	#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
yihui	9:05f0b5a3a70a	4408	#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
yihui	9:05f0b5a3a70a	4409	#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	4410	#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	4411	#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	4412
yihui	9:05f0b5a3a70a	4413	/* Register: QDEC_INTENCLR */
yihui	9:05f0b5a3a70a	4414	/* Description: Interrupt enable clear register. */
yihui	9:05f0b5a3a70a	4415
yihui	9:05f0b5a3a70a	4416	/* Bit 2 : Disable interrupt on ACCOF event. */
yihui	9:05f0b5a3a70a	4417	#define QDEC_INTENCLR_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
yihui	9:05f0b5a3a70a	4418	#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /!< Bit mask of ACCOF field. /
yihui	9:05f0b5a3a70a	4419	#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	4420	#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	4421	#define QDEC_INTENCLR_ACCOF_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	4422
yihui	9:05f0b5a3a70a	4423	/* Bit 1 : Disable interrupt on REPORTRDY event. */
yihui	9:05f0b5a3a70a	4424	#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
yihui	9:05f0b5a3a70a	4425	#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
yihui	9:05f0b5a3a70a	4426	#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	4427	#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	4428	#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	4429
yihui	9:05f0b5a3a70a	4430	/* Bit 0 : Disable interrupt on SAMPLERDY event. */
yihui	9:05f0b5a3a70a	4431	#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
yihui	9:05f0b5a3a70a	4432	#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
yihui	9:05f0b5a3a70a	4433	#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	4434	#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	4435	#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	4436
yihui	9:05f0b5a3a70a	4437	/* Register: QDEC_ENABLE */
yihui	9:05f0b5a3a70a	4438	/* Description: Enable the QDEC. */
yihui	9:05f0b5a3a70a	4439
yihui	9:05f0b5a3a70a	4440	/* Bit 0 : Enable or disable QDEC. */
yihui	9:05f0b5a3a70a	4441	#define QDEC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
yihui	9:05f0b5a3a70a	4442	#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
yihui	9:05f0b5a3a70a	4443	#define QDEC_ENABLE_ENABLE_Disabled (0UL) /!< Disabled QDEC. /
yihui	9:05f0b5a3a70a	4444	#define QDEC_ENABLE_ENABLE_Enabled (1UL) /!< Enable QDEC. /
yihui	9:05f0b5a3a70a	4445
yihui	9:05f0b5a3a70a	4446	/* Register: QDEC_LEDPOL */
yihui	9:05f0b5a3a70a	4447	/* Description: LED output pin polarity. */
yihui	9:05f0b5a3a70a	4448
yihui	9:05f0b5a3a70a	4449	/* Bit 0 : LED output pin polarity. */
yihui	9:05f0b5a3a70a	4450	#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /!< Position of LEDPOL field. /
yihui	9:05f0b5a3a70a	4451	#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /!< Bit mask of LEDPOL field. /
yihui	9:05f0b5a3a70a	4452	#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /!< LED output is active low. /
yihui	9:05f0b5a3a70a	4453	#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /!< LED output is active high. /
yihui	9:05f0b5a3a70a	4454
yihui	9:05f0b5a3a70a	4455	/* Register: QDEC_SAMPLEPER */
yihui	9:05f0b5a3a70a	4456	/* Description: Sample period. */
yihui	9:05f0b5a3a70a	4457
yihui	9:05f0b5a3a70a	4458	/* Bits 2..0 : Sample period. */
yihui	9:05f0b5a3a70a	4459	#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /!< Position of SAMPLEPER field. /
yihui	9:05f0b5a3a70a	4460	#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /!< Bit mask of SAMPLEPER field. /
yihui	9:05f0b5a3a70a	4461	#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /!< 128us sample period. /
yihui	9:05f0b5a3a70a	4462	#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /!< 256us sample period. /
yihui	9:05f0b5a3a70a	4463	#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /!< 512us sample period. /
yihui	9:05f0b5a3a70a	4464	#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /!< 1024us sample period. /
yihui	9:05f0b5a3a70a	4465	#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /!< 2048us sample period. /
yihui	9:05f0b5a3a70a	4466	#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /!< 4096us sample period. /
yihui	9:05f0b5a3a70a	4467	#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /!< 8192us sample period. /
yihui	9:05f0b5a3a70a	4468	#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /!< 16384us sample period. /
yihui	9:05f0b5a3a70a	4469
yihui	9:05f0b5a3a70a	4470	/* Register: QDEC_SAMPLE */
yihui	9:05f0b5a3a70a	4471	/* Description: Motion sample value. */
yihui	9:05f0b5a3a70a	4472
yihui	9:05f0b5a3a70a	4473	/* Bits 31..0 : Last sample taken in compliment to 2. */
yihui	9:05f0b5a3a70a	4474	#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /!< Position of SAMPLE field. /
yihui	9:05f0b5a3a70a	4475	#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /!< Bit mask of SAMPLE field. /
yihui	9:05f0b5a3a70a	4476
yihui	9:05f0b5a3a70a	4477	/* Register: QDEC_REPORTPER */
yihui	9:05f0b5a3a70a	4478	/* Description: Number of samples to generate an EVENT_REPORTRDY. */
yihui	9:05f0b5a3a70a	4479
yihui	9:05f0b5a3a70a	4480	/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
yihui	9:05f0b5a3a70a	4481	#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /!< Position of REPORTPER field. /
yihui	9:05f0b5a3a70a	4482	#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /!< Bit mask of REPORTPER field. /
yihui	9:05f0b5a3a70a	4483	#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /!< 10 samples per report. /
yihui	9:05f0b5a3a70a	4484	#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /!< 40 samples per report. /
yihui	9:05f0b5a3a70a	4485	#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /!< 80 samples per report. /
yihui	9:05f0b5a3a70a	4486	#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /!< 120 samples per report. /
yihui	9:05f0b5a3a70a	4487	#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /!< 160 samples per report. /
yihui	9:05f0b5a3a70a	4488	#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /!< 200 samples per report. /
yihui	9:05f0b5a3a70a	4489	#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /!< 240 samples per report. /
yihui	9:05f0b5a3a70a	4490	#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /!< 280 samples per report. /
yihui	9:05f0b5a3a70a	4491
yihui	9:05f0b5a3a70a	4492	/* Register: QDEC_DBFEN */
yihui	9:05f0b5a3a70a	4493	/* Description: Enable debouncer input filters. */
yihui	9:05f0b5a3a70a	4494
yihui	9:05f0b5a3a70a	4495	/* Bit 0 : Enable debounce input filters. */
yihui	9:05f0b5a3a70a	4496	#define QDEC_DBFEN_DBFEN_Pos (0UL) /!< Position of DBFEN field. /
yihui	9:05f0b5a3a70a	4497	#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /!< Bit mask of DBFEN field. /
yihui	9:05f0b5a3a70a	4498	#define QDEC_DBFEN_DBFEN_Disabled (0UL) /!< Debounce input filters disabled. /
yihui	9:05f0b5a3a70a	4499	#define QDEC_DBFEN_DBFEN_Enabled (1UL) /!< Debounce input filters enabled. /
yihui	9:05f0b5a3a70a	4500
yihui	9:05f0b5a3a70a	4501	/* Register: QDEC_LEDPRE */
yihui	9:05f0b5a3a70a	4502	/* Description: Time LED is switched ON before the sample. */
yihui	9:05f0b5a3a70a	4503
yihui	9:05f0b5a3a70a	4504	/* Bits 7..0 : Period in us the LED in switched on prior to sampling. */
yihui	9:05f0b5a3a70a	4505	#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /!< Position of LEDPRE field. /
yihui	9:05f0b5a3a70a	4506	#define QDEC_LEDPRE_LEDPRE_Msk (0xFFUL << QDEC_LEDPRE_LEDPRE_Pos) /!< Bit mask of LEDPRE field. /
yihui	9:05f0b5a3a70a	4507
yihui	9:05f0b5a3a70a	4508	/* Register: QDEC_ACCDBL */
yihui	9:05f0b5a3a70a	4509	/* Description: Accumulated double (error) transitions register. */
yihui	9:05f0b5a3a70a	4510
yihui	9:05f0b5a3a70a	4511	/* Bits 3..0 : Accumulated double (error) transitions. */
yihui	9:05f0b5a3a70a	4512	#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /!< Position of ACCDBL field. /
yihui	9:05f0b5a3a70a	4513	#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /!< Bit mask of ACCDBL field. /
yihui	9:05f0b5a3a70a	4514
yihui	9:05f0b5a3a70a	4515	/* Register: QDEC_ACCDBLREAD */
yihui	9:05f0b5a3a70a	4516	/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
yihui	9:05f0b5a3a70a	4517
yihui	9:05f0b5a3a70a	4518	/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
yihui	9:05f0b5a3a70a	4519	#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /!< Position of ACCDBLREAD field. /
yihui	9:05f0b5a3a70a	4520	#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /!< Bit mask of ACCDBLREAD field. /
yihui	9:05f0b5a3a70a	4521
yihui	9:05f0b5a3a70a	4522	/* Register: QDEC_POWER */
yihui	9:05f0b5a3a70a	4523	/* Description: Peripheral power control. */
yihui	9:05f0b5a3a70a	4524
yihui	9:05f0b5a3a70a	4525	/* Bit 0 : Peripheral power control. */
yihui	9:05f0b5a3a70a	4526	#define QDEC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
yihui	9:05f0b5a3a70a	4527	#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
yihui	9:05f0b5a3a70a	4528	#define QDEC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
yihui	9:05f0b5a3a70a	4529	#define QDEC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
yihui	9:05f0b5a3a70a	4530
yihui	9:05f0b5a3a70a	4531
yihui	9:05f0b5a3a70a	4532	/* Peripheral: RADIO */
yihui	9:05f0b5a3a70a	4533	/* Description: The radio. */
yihui	9:05f0b5a3a70a	4534
yihui	9:05f0b5a3a70a	4535	/* Register: RADIO_SHORTS */
yihui	9:05f0b5a3a70a	4536	/* Description: Shortcut for the radio. */
yihui	9:05f0b5a3a70a	4537
yihui	9:05f0b5a3a70a	4538	/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
yihui	9:05f0b5a3a70a	4539	#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /!< Position of DISABLED_RSSISTOP field. /
yihui	9:05f0b5a3a70a	4540	#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /!< Bit mask of DISABLED_RSSISTOP field. /
yihui	9:05f0b5a3a70a	4541	#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	4542	#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	4543
yihui	9:05f0b5a3a70a	4544	/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
yihui	9:05f0b5a3a70a	4545	#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /!< Position of ADDRESS_BCSTART field. /
yihui	9:05f0b5a3a70a	4546	#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /!< Bit mask of ADDRESS_BCSTART field. /
yihui	9:05f0b5a3a70a	4547	#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	4548	#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	4549
yihui	9:05f0b5a3a70a	4550	/* Bit 5 : Shortcut between END event and START task. */
yihui	9:05f0b5a3a70a	4551	#define RADIO_SHORTS_END_START_Pos (5UL) /!< Position of END_START field. /
yihui	9:05f0b5a3a70a	4552	#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /!< Bit mask of END_START field. /
yihui	9:05f0b5a3a70a	4553	#define RADIO_SHORTS_END_START_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	4554	#define RADIO_SHORTS_END_START_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	4555
yihui	9:05f0b5a3a70a	4556	/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
yihui	9:05f0b5a3a70a	4557	#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /!< Position of ADDRESS_RSSISTART field. /
yihui	9:05f0b5a3a70a	4558	#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /!< Bit mask of ADDRESS_RSSISTART field. /
yihui	9:05f0b5a3a70a	4559	#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	4560	#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	4561
yihui	9:05f0b5a3a70a	4562	/* Bit 3 : Shortcut between DISABLED event and RXEN task. */
yihui	9:05f0b5a3a70a	4563	#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /!< Position of DISABLED_RXEN field. /
yihui	9:05f0b5a3a70a	4564	#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /!< Bit mask of DISABLED_RXEN field. /
yihui	9:05f0b5a3a70a	4565	#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	4566	#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	4567
yihui	9:05f0b5a3a70a	4568	/* Bit 2 : Shortcut between DISABLED event and TXEN task. */
yihui	9:05f0b5a3a70a	4569	#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /!< Position of DISABLED_TXEN field. /
yihui	9:05f0b5a3a70a	4570	#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /!< Bit mask of DISABLED_TXEN field. /
yihui	9:05f0b5a3a70a	4571	#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	4572	#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	4573
yihui	9:05f0b5a3a70a	4574	/* Bit 1 : Shortcut between END event and DISABLE task. */
yihui	9:05f0b5a3a70a	4575	#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /!< Position of END_DISABLE field. /
yihui	9:05f0b5a3a70a	4576	#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /!< Bit mask of END_DISABLE field. /
yihui	9:05f0b5a3a70a	4577	#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	4578	#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	4579
yihui	9:05f0b5a3a70a	4580	/* Bit 0 : Shortcut between READY event and START task. */
yihui	9:05f0b5a3a70a	4581	#define RADIO_SHORTS_READY_START_Pos (0UL) /!< Position of READY_START field. /
yihui	9:05f0b5a3a70a	4582	#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /!< Bit mask of READY_START field. /
yihui	9:05f0b5a3a70a	4583	#define RADIO_SHORTS_READY_START_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	4584	#define RADIO_SHORTS_READY_START_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	4585
yihui	9:05f0b5a3a70a	4586	/* Register: RADIO_INTENSET */
yihui	9:05f0b5a3a70a	4587	/* Description: Interrupt enable set register. */
yihui	9:05f0b5a3a70a	4588
yihui	9:05f0b5a3a70a	4589	/* Bit 10 : Enable interrupt on BCMATCH event. */
yihui	9:05f0b5a3a70a	4590	#define RADIO_INTENSET_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
yihui	9:05f0b5a3a70a	4591	#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
yihui	9:05f0b5a3a70a	4592	#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	4593	#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	4594	#define RADIO_INTENSET_BCMATCH_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	4595
yihui	9:05f0b5a3a70a	4596	/* Bit 7 : Enable interrupt on RSSIEND event. */
yihui	9:05f0b5a3a70a	4597	#define RADIO_INTENSET_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
yihui	9:05f0b5a3a70a	4598	#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
yihui	9:05f0b5a3a70a	4599	#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	4600	#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	4601	#define RADIO_INTENSET_RSSIEND_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	4602
yihui	9:05f0b5a3a70a	4603	/* Bit 6 : Enable interrupt on DEVMISS event. */
yihui	9:05f0b5a3a70a	4604	#define RADIO_INTENSET_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
yihui	9:05f0b5a3a70a	4605	#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
yihui	9:05f0b5a3a70a	4606	#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	4607	#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	4608	#define RADIO_INTENSET_DEVMISS_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	4609
yihui	9:05f0b5a3a70a	4610	/* Bit 5 : Enable interrupt on DEVMATCH event. */
yihui	9:05f0b5a3a70a	4611	#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
yihui	9:05f0b5a3a70a	4612	#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
yihui	9:05f0b5a3a70a	4613	#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	4614	#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	4615	#define RADIO_INTENSET_DEVMATCH_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	4616
yihui	9:05f0b5a3a70a	4617	/* Bit 4 : Enable interrupt on DISABLED event. */
yihui	9:05f0b5a3a70a	4618	#define RADIO_INTENSET_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
yihui	9:05f0b5a3a70a	4619	#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /!< Bit mask of DISABLED field. /
yihui	9:05f0b5a3a70a	4620	#define RADIO_INTENSET_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	4621	#define RADIO_INTENSET_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	4622	#define RADIO_INTENSET_DISABLED_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	4623
yihui	9:05f0b5a3a70a	4624	/* Bit 3 : Enable interrupt on END event. */
yihui	9:05f0b5a3a70a	4625	#define RADIO_INTENSET_END_Pos (3UL) /!< Position of END field. /
yihui	9:05f0b5a3a70a	4626	#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /!< Bit mask of END field. /
yihui	9:05f0b5a3a70a	4627	#define RADIO_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	4628	#define RADIO_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	4629	#define RADIO_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	4630
yihui	9:05f0b5a3a70a	4631	/* Bit 2 : Enable interrupt on PAYLOAD event. */
yihui	9:05f0b5a3a70a	4632	#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
yihui	9:05f0b5a3a70a	4633	#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
yihui	9:05f0b5a3a70a	4634	#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	4635	#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	4636	#define RADIO_INTENSET_PAYLOAD_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	4637
yihui	9:05f0b5a3a70a	4638	/* Bit 1 : Enable interrupt on ADDRESS event. */
yihui	9:05f0b5a3a70a	4639	#define RADIO_INTENSET_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
yihui	9:05f0b5a3a70a	4640	#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
yihui	9:05f0b5a3a70a	4641	#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	4642	#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	4643	#define RADIO_INTENSET_ADDRESS_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	4644
yihui	9:05f0b5a3a70a	4645	/* Bit 0 : Enable interrupt on READY event. */
yihui	9:05f0b5a3a70a	4646	#define RADIO_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
yihui	9:05f0b5a3a70a	4647	#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /!< Bit mask of READY field. /
yihui	9:05f0b5a3a70a	4648	#define RADIO_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	4649	#define RADIO_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	4650	#define RADIO_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	4651
yihui	9:05f0b5a3a70a	4652	/* Register: RADIO_INTENCLR */
yihui	9:05f0b5a3a70a	4653	/* Description: Interrupt enable clear register. */
yihui	9:05f0b5a3a70a	4654
yihui	9:05f0b5a3a70a	4655	/* Bit 10 : Disable interrupt on BCMATCH event. */
yihui	9:05f0b5a3a70a	4656	#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
yihui	9:05f0b5a3a70a	4657	#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
yihui	9:05f0b5a3a70a	4658	#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	4659	#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	4660	#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	4661
yihui	9:05f0b5a3a70a	4662	/* Bit 7 : Disable interrupt on RSSIEND event. */
yihui	9:05f0b5a3a70a	4663	#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
yihui	9:05f0b5a3a70a	4664	#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
yihui	9:05f0b5a3a70a	4665	#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	4666	#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	4667	#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	4668
yihui	9:05f0b5a3a70a	4669	/* Bit 6 : Disable interrupt on DEVMISS event. */
yihui	9:05f0b5a3a70a	4670	#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
yihui	9:05f0b5a3a70a	4671	#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
yihui	9:05f0b5a3a70a	4672	#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	4673	#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	4674	#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	4675
yihui	9:05f0b5a3a70a	4676	/* Bit 5 : Disable interrupt on DEVMATCH event. */
yihui	9:05f0b5a3a70a	4677	#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
yihui	9:05f0b5a3a70a	4678	#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
yihui	9:05f0b5a3a70a	4679	#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	4680	#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	4681	#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	4682
yihui	9:05f0b5a3a70a	4683	/* Bit 4 : Disable interrupt on DISABLED event. */
yihui	9:05f0b5a3a70a	4684	#define RADIO_INTENCLR_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
yihui	9:05f0b5a3a70a	4685	#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /!< Bit mask of DISABLED field. /
yihui	9:05f0b5a3a70a	4686	#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	4687	#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	4688	#define RADIO_INTENCLR_DISABLED_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	4689
yihui	9:05f0b5a3a70a	4690	/* Bit 3 : Disable interrupt on END event. */
yihui	9:05f0b5a3a70a	4691	#define RADIO_INTENCLR_END_Pos (3UL) /!< Position of END field. /
yihui	9:05f0b5a3a70a	4692	#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /!< Bit mask of END field. /
yihui	9:05f0b5a3a70a	4693	#define RADIO_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	4694	#define RADIO_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	4695	#define RADIO_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	4696
yihui	9:05f0b5a3a70a	4697	/* Bit 2 : Disable interrupt on PAYLOAD event. */
yihui	9:05f0b5a3a70a	4698	#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
yihui	9:05f0b5a3a70a	4699	#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
yihui	9:05f0b5a3a70a	4700	#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	4701	#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	4702	#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	4703
yihui	9:05f0b5a3a70a	4704	/* Bit 1 : Disable interrupt on ADDRESS event. */
yihui	9:05f0b5a3a70a	4705	#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
yihui	9:05f0b5a3a70a	4706	#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
yihui	9:05f0b5a3a70a	4707	#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	4708	#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	4709	#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	4710
yihui	9:05f0b5a3a70a	4711	/* Bit 0 : Disable interrupt on READY event. */
yihui	9:05f0b5a3a70a	4712	#define RADIO_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
yihui	9:05f0b5a3a70a	4713	#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
yihui	9:05f0b5a3a70a	4714	#define RADIO_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	4715	#define RADIO_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	4716	#define RADIO_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	4717
yihui	9:05f0b5a3a70a	4718	/* Register: RADIO_CRCSTATUS */
yihui	9:05f0b5a3a70a	4719	/* Description: CRC status of received packet. */
yihui	9:05f0b5a3a70a	4720
yihui	9:05f0b5a3a70a	4721	/* Bit 0 : CRC status of received packet. */
yihui	9:05f0b5a3a70a	4722	#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /!< Position of CRCSTATUS field. /
yihui	9:05f0b5a3a70a	4723	#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /!< Bit mask of CRCSTATUS field. /
yihui	9:05f0b5a3a70a	4724	#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /!< Packet received with CRC error. /
yihui	9:05f0b5a3a70a	4725	#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /!< Packet received with CRC ok. /
yihui	9:05f0b5a3a70a	4726
yihui	9:05f0b5a3a70a	4727	/* Register: RADIO_RXMATCH */
yihui	9:05f0b5a3a70a	4728	/* Description: Received address. */
yihui	9:05f0b5a3a70a	4729
yihui	9:05f0b5a3a70a	4730	/* Bits 2..0 : Logical address in which previous packet was received. */
yihui	9:05f0b5a3a70a	4731	#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /!< Position of RXMATCH field. /
yihui	9:05f0b5a3a70a	4732	#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /!< Bit mask of RXMATCH field. /
yihui	9:05f0b5a3a70a	4733
yihui	9:05f0b5a3a70a	4734	/* Register: RADIO_RXCRC */
yihui	9:05f0b5a3a70a	4735	/* Description: Received CRC. */
yihui	9:05f0b5a3a70a	4736
yihui	9:05f0b5a3a70a	4737	/* Bits 23..0 : CRC field of previously received packet. */
yihui	9:05f0b5a3a70a	4738	#define RADIO_RXCRC_RXCRC_Pos (0UL) /!< Position of RXCRC field. /
yihui	9:05f0b5a3a70a	4739	#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /!< Bit mask of RXCRC field. /
yihui	9:05f0b5a3a70a	4740
yihui	9:05f0b5a3a70a	4741	/* Register: RADIO_DAI */
yihui	9:05f0b5a3a70a	4742	/* Description: Device address match index. */
yihui	9:05f0b5a3a70a	4743
yihui	9:05f0b5a3a70a	4744	/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that got an address match. */
yihui	9:05f0b5a3a70a	4745	#define RADIO_DAI_DAI_Pos (0UL) /!< Position of DAI field. /
yihui	9:05f0b5a3a70a	4746	#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /!< Bit mask of DAI field. /
yihui	9:05f0b5a3a70a	4747
yihui	9:05f0b5a3a70a	4748	/* Register: RADIO_FREQUENCY */
yihui	9:05f0b5a3a70a	4749	/* Description: Frequency. */
yihui	9:05f0b5a3a70a	4750
yihui	9:05f0b5a3a70a	4751	/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */
yihui	9:05f0b5a3a70a	4752	#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
yihui	9:05f0b5a3a70a	4753	#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
yihui	9:05f0b5a3a70a	4754
yihui	9:05f0b5a3a70a	4755	/* Register: RADIO_TXPOWER */
yihui	9:05f0b5a3a70a	4756	/* Description: Output power. */
yihui	9:05f0b5a3a70a	4757
yihui	9:05f0b5a3a70a	4758	/* Bits 7..0 : Radio output power. Decision point: TXEN task. */
yihui	9:05f0b5a3a70a	4759	#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /!< Position of TXPOWER field. /
yihui	9:05f0b5a3a70a	4760	#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /!< Bit mask of TXPOWER field. /
yihui	9:05f0b5a3a70a	4761	#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /!< +4dBm. /
yihui	9:05f0b5a3a70a	4762	#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /!< 0dBm. /
yihui	9:05f0b5a3a70a	4763	#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /!< -4dBm. /
yihui	9:05f0b5a3a70a	4764	#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /!< -8dBm. /
yihui	9:05f0b5a3a70a	4765	#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /!< -12dBm. /
yihui	9:05f0b5a3a70a	4766	#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /!< -16dBm. /
yihui	9:05f0b5a3a70a	4767	#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /!< -20dBm. /
yihui	9:05f0b5a3a70a	4768	#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /!< -30dBm. /
yihui	9:05f0b5a3a70a	4769
yihui	9:05f0b5a3a70a	4770	/* Register: RADIO_MODE */
yihui	9:05f0b5a3a70a	4771	/* Description: Data rate and modulation. */
yihui	9:05f0b5a3a70a	4772
yihui	9:05f0b5a3a70a	4773	/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
yihui	9:05f0b5a3a70a	4774	#define RADIO_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
yihui	9:05f0b5a3a70a	4775	#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /!< Bit mask of MODE field. /
yihui	9:05f0b5a3a70a	4776	#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /!< 1Mbit/s Nordic propietary radio mode. /
yihui	9:05f0b5a3a70a	4777	#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /!< 2Mbit/s Nordic propietary radio mode. /
yihui	9:05f0b5a3a70a	4778	#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /!< 250kbit/s Nordic propietary radio mode. /
yihui	9:05f0b5a3a70a	4779	#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /!< 1Mbit/s Bluetooth Low Energy /
yihui	9:05f0b5a3a70a	4780
yihui	9:05f0b5a3a70a	4781	/* Register: RADIO_PCNF0 */
yihui	9:05f0b5a3a70a	4782	/* Description: Packet configuration 0. */
yihui	9:05f0b5a3a70a	4783
yihui	9:05f0b5a3a70a	4784	/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
yihui	9:05f0b5a3a70a	4785	#define RADIO_PCNF0_S1LEN_Pos (16UL) /!< Position of S1LEN field. /
yihui	9:05f0b5a3a70a	4786	#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /!< Bit mask of S1LEN field. /
yihui	9:05f0b5a3a70a	4787
yihui	9:05f0b5a3a70a	4788	/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
yihui	9:05f0b5a3a70a	4789	#define RADIO_PCNF0_S0LEN_Pos (8UL) /!< Position of S0LEN field. /
yihui	9:05f0b5a3a70a	4790	#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /!< Bit mask of S0LEN field. /
yihui	9:05f0b5a3a70a	4791
yihui	9:05f0b5a3a70a	4792	/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
yihui	9:05f0b5a3a70a	4793	#define RADIO_PCNF0_LFLEN_Pos (0UL) /!< Position of LFLEN field. /
yihui	9:05f0b5a3a70a	4794	#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /!< Bit mask of LFLEN field. /
yihui	9:05f0b5a3a70a	4795
yihui	9:05f0b5a3a70a	4796	/* Register: RADIO_PCNF1 */
yihui	9:05f0b5a3a70a	4797	/* Description: Packet configuration 1. */
yihui	9:05f0b5a3a70a	4798
yihui	9:05f0b5a3a70a	4799	/* Bit 25 : Packet whitening enable. */
yihui	9:05f0b5a3a70a	4800	#define RADIO_PCNF1_WHITEEN_Pos (25UL) /!< Position of WHITEEN field. /
yihui	9:05f0b5a3a70a	4801	#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /!< Bit mask of WHITEEN field. /
yihui	9:05f0b5a3a70a	4802	#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /!< Whitening disabled. /
yihui	9:05f0b5a3a70a	4803	#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /!< Whitening enabled. /
yihui	9:05f0b5a3a70a	4804
yihui	9:05f0b5a3a70a	4805	/* Bit 24 : On air endianness of packet length field. Decision point: START task. */
yihui	9:05f0b5a3a70a	4806	#define RADIO_PCNF1_ENDIAN_Pos (24UL) /!< Position of ENDIAN field. /
yihui	9:05f0b5a3a70a	4807	#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /!< Bit mask of ENDIAN field. /
yihui	9:05f0b5a3a70a	4808	#define RADIO_PCNF1_ENDIAN_Little (0UL) /!< Least significant bit on air first /
yihui	9:05f0b5a3a70a	4809	#define RADIO_PCNF1_ENDIAN_Big (1UL) /!< Most significant bit on air first /
yihui	9:05f0b5a3a70a	4810
yihui	9:05f0b5a3a70a	4811	/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
yihui	9:05f0b5a3a70a	4812	#define RADIO_PCNF1_BALEN_Pos (16UL) /!< Position of BALEN field. /
yihui	9:05f0b5a3a70a	4813	#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /!< Bit mask of BALEN field. /
yihui	9:05f0b5a3a70a	4814
yihui	9:05f0b5a3a70a	4815	/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
yihui	9:05f0b5a3a70a	4816	#define RADIO_PCNF1_STATLEN_Pos (8UL) /!< Position of STATLEN field. /
yihui	9:05f0b5a3a70a	4817	#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /!< Bit mask of STATLEN field. /
yihui	9:05f0b5a3a70a	4818
yihui	9:05f0b5a3a70a	4819	/* Bits 7..0 : Maximum length of packet payload in number of bytes. */
yihui	9:05f0b5a3a70a	4820	#define RADIO_PCNF1_MAXLEN_Pos (0UL) /!< Position of MAXLEN field. /
yihui	9:05f0b5a3a70a	4821	#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /!< Bit mask of MAXLEN field. /
yihui	9:05f0b5a3a70a	4822
yihui	9:05f0b5a3a70a	4823	/* Register: RADIO_PREFIX0 */
yihui	9:05f0b5a3a70a	4824	/* Description: Prefixes bytes for logical addresses 0 to 3. */
yihui	9:05f0b5a3a70a	4825
yihui	9:05f0b5a3a70a	4826	/* Bits 31..24 : Address prefix 3. Decision point: START task. */
yihui	9:05f0b5a3a70a	4827	#define RADIO_PREFIX0_AP3_Pos (24UL) /!< Position of AP3 field. /
yihui	9:05f0b5a3a70a	4828	#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /!< Bit mask of AP3 field. /
yihui	9:05f0b5a3a70a	4829
yihui	9:05f0b5a3a70a	4830	/* Bits 23..16 : Address prefix 2. Decision point: START task. */
yihui	9:05f0b5a3a70a	4831	#define RADIO_PREFIX0_AP2_Pos (16UL) /!< Position of AP2 field. /
yihui	9:05f0b5a3a70a	4832	#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /!< Bit mask of AP2 field. /
yihui	9:05f0b5a3a70a	4833
yihui	9:05f0b5a3a70a	4834	/* Bits 15..8 : Address prefix 1. Decision point: START task. */
yihui	9:05f0b5a3a70a	4835	#define RADIO_PREFIX0_AP1_Pos (8UL) /!< Position of AP1 field. /
yihui	9:05f0b5a3a70a	4836	#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /!< Bit mask of AP1 field. /
yihui	9:05f0b5a3a70a	4837
yihui	9:05f0b5a3a70a	4838	/* Bits 7..0 : Address prefix 0. Decision point: START task. */
yihui	9:05f0b5a3a70a	4839	#define RADIO_PREFIX0_AP0_Pos (0UL) /!< Position of AP0 field. /
yihui	9:05f0b5a3a70a	4840	#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /!< Bit mask of AP0 field. /
yihui	9:05f0b5a3a70a	4841
yihui	9:05f0b5a3a70a	4842	/* Register: RADIO_PREFIX1 */
yihui	9:05f0b5a3a70a	4843	/* Description: Prefixes bytes for logical addresses 4 to 7. */
yihui	9:05f0b5a3a70a	4844
yihui	9:05f0b5a3a70a	4845	/* Bits 31..24 : Address prefix 7. Decision point: START task. */
yihui	9:05f0b5a3a70a	4846	#define RADIO_PREFIX1_AP7_Pos (24UL) /!< Position of AP7 field. /
yihui	9:05f0b5a3a70a	4847	#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /!< Bit mask of AP7 field. /
yihui	9:05f0b5a3a70a	4848
yihui	9:05f0b5a3a70a	4849	/* Bits 23..16 : Address prefix 6. Decision point: START task. */
yihui	9:05f0b5a3a70a	4850	#define RADIO_PREFIX1_AP6_Pos (16UL) /!< Position of AP6 field. /
yihui	9:05f0b5a3a70a	4851	#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /!< Bit mask of AP6 field. /
yihui	9:05f0b5a3a70a	4852
yihui	9:05f0b5a3a70a	4853	/* Bits 15..8 : Address prefix 5. Decision point: START task. */
yihui	9:05f0b5a3a70a	4854	#define RADIO_PREFIX1_AP5_Pos (8UL) /!< Position of AP5 field. /
yihui	9:05f0b5a3a70a	4855	#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /!< Bit mask of AP5 field. /
yihui	9:05f0b5a3a70a	4856
yihui	9:05f0b5a3a70a	4857	/* Bits 7..0 : Address prefix 4. Decision point: START task. */
yihui	9:05f0b5a3a70a	4858	#define RADIO_PREFIX1_AP4_Pos (0UL) /!< Position of AP4 field. /
yihui	9:05f0b5a3a70a	4859	#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /!< Bit mask of AP4 field. /
yihui	9:05f0b5a3a70a	4860
yihui	9:05f0b5a3a70a	4861	/* Register: RADIO_TXADDRESS */
yihui	9:05f0b5a3a70a	4862	/* Description: Transmit address select. */
yihui	9:05f0b5a3a70a	4863
yihui	9:05f0b5a3a70a	4864	/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
yihui	9:05f0b5a3a70a	4865	#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /!< Position of TXADDRESS field. /
yihui	9:05f0b5a3a70a	4866	#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /!< Bit mask of TXADDRESS field. /
yihui	9:05f0b5a3a70a	4867
yihui	9:05f0b5a3a70a	4868	/* Register: RADIO_RXADDRESSES */
yihui	9:05f0b5a3a70a	4869	/* Description: Receive address select. */
yihui	9:05f0b5a3a70a	4870
yihui	9:05f0b5a3a70a	4871	/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
yihui	9:05f0b5a3a70a	4872	#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /!< Position of ADDR7 field. /
yihui	9:05f0b5a3a70a	4873	#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /!< Bit mask of ADDR7 field. /
yihui	9:05f0b5a3a70a	4874	#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /!< Reception disabled. /
yihui	9:05f0b5a3a70a	4875	#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /!< Reception enabled. /
yihui	9:05f0b5a3a70a	4876
yihui	9:05f0b5a3a70a	4877	/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
yihui	9:05f0b5a3a70a	4878	#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /!< Position of ADDR6 field. /
yihui	9:05f0b5a3a70a	4879	#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /!< Bit mask of ADDR6 field. /
yihui	9:05f0b5a3a70a	4880	#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /!< Reception disabled. /
yihui	9:05f0b5a3a70a	4881	#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /!< Reception enabled. /
yihui	9:05f0b5a3a70a	4882
yihui	9:05f0b5a3a70a	4883	/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
yihui	9:05f0b5a3a70a	4884	#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /!< Position of ADDR5 field. /
yihui	9:05f0b5a3a70a	4885	#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /!< Bit mask of ADDR5 field. /
yihui	9:05f0b5a3a70a	4886	#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /!< Reception disabled. /
yihui	9:05f0b5a3a70a	4887	#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /!< Reception enabled. /
yihui	9:05f0b5a3a70a	4888
yihui	9:05f0b5a3a70a	4889	/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
yihui	9:05f0b5a3a70a	4890	#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /!< Position of ADDR4 field. /
yihui	9:05f0b5a3a70a	4891	#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /!< Bit mask of ADDR4 field. /
yihui	9:05f0b5a3a70a	4892	#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /!< Reception disabled. /
yihui	9:05f0b5a3a70a	4893	#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /!< Reception enabled. /
yihui	9:05f0b5a3a70a	4894
yihui	9:05f0b5a3a70a	4895	/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
yihui	9:05f0b5a3a70a	4896	#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /!< Position of ADDR3 field. /
yihui	9:05f0b5a3a70a	4897	#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /!< Bit mask of ADDR3 field. /
yihui	9:05f0b5a3a70a	4898	#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /!< Reception disabled. /
yihui	9:05f0b5a3a70a	4899	#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /!< Reception enabled. /
yihui	9:05f0b5a3a70a	4900
yihui	9:05f0b5a3a70a	4901	/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
yihui	9:05f0b5a3a70a	4902	#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /!< Position of ADDR2 field. /
yihui	9:05f0b5a3a70a	4903	#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /!< Bit mask of ADDR2 field. /
yihui	9:05f0b5a3a70a	4904	#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /!< Reception disabled. /
yihui	9:05f0b5a3a70a	4905	#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /!< Reception enabled. /
yihui	9:05f0b5a3a70a	4906
yihui	9:05f0b5a3a70a	4907	/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
yihui	9:05f0b5a3a70a	4908	#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /!< Position of ADDR1 field. /
yihui	9:05f0b5a3a70a	4909	#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /!< Bit mask of ADDR1 field. /
yihui	9:05f0b5a3a70a	4910	#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /!< Reception disabled. /
yihui	9:05f0b5a3a70a	4911	#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /!< Reception enabled. /
yihui	9:05f0b5a3a70a	4912
yihui	9:05f0b5a3a70a	4913	/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
yihui	9:05f0b5a3a70a	4914	#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /!< Position of ADDR0 field. /
yihui	9:05f0b5a3a70a	4915	#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /!< Bit mask of ADDR0 field. /
yihui	9:05f0b5a3a70a	4916	#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /!< Reception disabled. /
yihui	9:05f0b5a3a70a	4917	#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /!< Reception enabled. /
yihui	9:05f0b5a3a70a	4918
yihui	9:05f0b5a3a70a	4919	/* Register: RADIO_CRCCNF */
yihui	9:05f0b5a3a70a	4920	/* Description: CRC configuration. */
yihui	9:05f0b5a3a70a	4921
yihui	9:05f0b5a3a70a	4922	/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
yihui	9:05f0b5a3a70a	4923	#define RADIO_CRCCNF_SKIP_ADDR_Pos (8UL) /!< Position of SKIP_ADDR field. /
yihui	9:05f0b5a3a70a	4924	#define RADIO_CRCCNF_SKIP_ADDR_Msk (0x1UL << RADIO_CRCCNF_SKIP_ADDR_Pos) /!< Bit mask of SKIP_ADDR field. /
yihui	9:05f0b5a3a70a	4925	#define RADIO_CRCCNF_SKIP_ADDR_Include (0UL) /!< Include packet address in CRC calculation. /
yihui	9:05f0b5a3a70a	4926	#define RADIO_CRCCNF_SKIP_ADDR_Skip (1UL) /!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. /
yihui	9:05f0b5a3a70a	4927
yihui	9:05f0b5a3a70a	4928	/* Bits 1..0 : CRC length. Decision point: START task. */
yihui	9:05f0b5a3a70a	4929	#define RADIO_CRCCNF_LEN_Pos (0UL) /!< Position of LEN field. /
yihui	9:05f0b5a3a70a	4930	#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /!< Bit mask of LEN field. /
yihui	9:05f0b5a3a70a	4931	#define RADIO_CRCCNF_LEN_Disabled (0UL) /!< CRC calculation disabled. /
yihui	9:05f0b5a3a70a	4932	#define RADIO_CRCCNF_LEN_One (1UL) /!< One byte long CRC. /
yihui	9:05f0b5a3a70a	4933	#define RADIO_CRCCNF_LEN_Two (2UL) /!< Two bytes long CRC. /
yihui	9:05f0b5a3a70a	4934	#define RADIO_CRCCNF_LEN_Three (3UL) /!< Three bytes long CRC. /
yihui	9:05f0b5a3a70a	4935
yihui	9:05f0b5a3a70a	4936	/* Register: RADIO_CRCPOLY */
yihui	9:05f0b5a3a70a	4937	/* Description: CRC polynomial. */
yihui	9:05f0b5a3a70a	4938
yihui	9:05f0b5a3a70a	4939	/* Bits 23..1 : CRC polynomial. Decision point: START task. */
yihui	9:05f0b5a3a70a	4940	#define RADIO_CRCPOLY_CRCPOLY_Pos (1UL) /!< Position of CRCPOLY field. /
yihui	9:05f0b5a3a70a	4941	#define RADIO_CRCPOLY_CRCPOLY_Msk (0x7FFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /!< Bit mask of CRCPOLY field. /
yihui	9:05f0b5a3a70a	4942
yihui	9:05f0b5a3a70a	4943	/* Register: RADIO_CRCINIT */
yihui	9:05f0b5a3a70a	4944	/* Description: CRC initial value. */
yihui	9:05f0b5a3a70a	4945
yihui	9:05f0b5a3a70a	4946	/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
yihui	9:05f0b5a3a70a	4947	#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /!< Position of CRCINIT field. /
yihui	9:05f0b5a3a70a	4948	#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /!< Bit mask of CRCINIT field. /
yihui	9:05f0b5a3a70a	4949
yihui	9:05f0b5a3a70a	4950	/* Register: RADIO_TEST */
yihui	9:05f0b5a3a70a	4951	/* Description: Test features enable register. */
yihui	9:05f0b5a3a70a	4952
yihui	9:05f0b5a3a70a	4953	/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
yihui	9:05f0b5a3a70a	4954	#define RADIO_TEST_PLL_LOCK_Pos (1UL) /!< Position of PLL_LOCK field. /
yihui	9:05f0b5a3a70a	4955	#define RADIO_TEST_PLL_LOCK_Msk (0x1UL << RADIO_TEST_PLL_LOCK_Pos) /!< Bit mask of PLL_LOCK field. /
yihui	9:05f0b5a3a70a	4956	#define RADIO_TEST_PLL_LOCK_Disabled (0UL) /!< PLL lock disabled. /
yihui	9:05f0b5a3a70a	4957	#define RADIO_TEST_PLL_LOCK_Enabled (1UL) /!< PLL lock enabled. /
yihui	9:05f0b5a3a70a	4958
yihui	9:05f0b5a3a70a	4959	/* Bit 0 : Constant carrier. Decision point: TXEN task. */
yihui	9:05f0b5a3a70a	4960	#define RADIO_TEST_CONST_CARRIER_Pos (0UL) /!< Position of CONST_CARRIER field. /
yihui	9:05f0b5a3a70a	4961	#define RADIO_TEST_CONST_CARRIER_Msk (0x1UL << RADIO_TEST_CONST_CARRIER_Pos) /!< Bit mask of CONST_CARRIER field. /
yihui	9:05f0b5a3a70a	4962	#define RADIO_TEST_CONST_CARRIER_Disabled (0UL) /!< Constant carrier disabled. /
yihui	9:05f0b5a3a70a	4963	#define RADIO_TEST_CONST_CARRIER_Enabled (1UL) /!< Constant carrier enabled. /
yihui	9:05f0b5a3a70a	4964
yihui	9:05f0b5a3a70a	4965	/* Register: RADIO_TIFS */
yihui	9:05f0b5a3a70a	4966	/* Description: Inter Frame Spacing in microseconds. */
yihui	9:05f0b5a3a70a	4967
yihui	9:05f0b5a3a70a	4968	/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
yihui	9:05f0b5a3a70a	4969	#define RADIO_TIFS_TIFS_Pos (0UL) /!< Position of TIFS field. /
yihui	9:05f0b5a3a70a	4970	#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /!< Bit mask of TIFS field. /
yihui	9:05f0b5a3a70a	4971
yihui	9:05f0b5a3a70a	4972	/* Register: RADIO_RSSISAMPLE */
yihui	9:05f0b5a3a70a	4973	/* Description: RSSI sample. */
yihui	9:05f0b5a3a70a	4974
yihui	9:05f0b5a3a70a	4975	/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
yihui	9:05f0b5a3a70a	4976	#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /!< Position of RSSISAMPLE field. /
yihui	9:05f0b5a3a70a	4977	#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /!< Bit mask of RSSISAMPLE field. /
yihui	9:05f0b5a3a70a	4978
yihui	9:05f0b5a3a70a	4979	/* Register: RADIO_STATE */
yihui	9:05f0b5a3a70a	4980	/* Description: Current radio state. */
yihui	9:05f0b5a3a70a	4981
yihui	9:05f0b5a3a70a	4982	/* Bits 3..0 : Current radio state. */
yihui	9:05f0b5a3a70a	4983	#define RADIO_STATE_STATE_Pos (0UL) /!< Position of STATE field. /
yihui	9:05f0b5a3a70a	4984	#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /!< Bit mask of STATE field. /
yihui	9:05f0b5a3a70a	4985	#define RADIO_STATE_STATE_Disabled (0x00UL) /!< Radio is in the Disabled state. /
yihui	9:05f0b5a3a70a	4986	#define RADIO_STATE_STATE_RxRu (0x01UL) /!< Radio is in the Rx Ramp Up state. /
yihui	9:05f0b5a3a70a	4987	#define RADIO_STATE_STATE_RxIdle (0x02UL) /!< Radio is in the Rx Idle state. /
yihui	9:05f0b5a3a70a	4988	#define RADIO_STATE_STATE_Rx (0x03UL) /!< Radio is in the Rx state. /
yihui	9:05f0b5a3a70a	4989	#define RADIO_STATE_STATE_RxDisable (0x04UL) /!< Radio is in the Rx Disable state. /
yihui	9:05f0b5a3a70a	4990	#define RADIO_STATE_STATE_TxRu (0x09UL) /!< Radio is in the Tx Ramp Up state. /
yihui	9:05f0b5a3a70a	4991	#define RADIO_STATE_STATE_TxIdle (0x0AUL) /!< Radio is in the Tx Idle state. /
yihui	9:05f0b5a3a70a	4992	#define RADIO_STATE_STATE_Tx (0x0BUL) /!< Radio is in the Tx state. /
yihui	9:05f0b5a3a70a	4993	#define RADIO_STATE_STATE_TxDisable (0x0CUL) /!< Radio is in the Tx Disable state. /
yihui	9:05f0b5a3a70a	4994
yihui	9:05f0b5a3a70a	4995	/* Register: RADIO_DATAWHITEIV */
yihui	9:05f0b5a3a70a	4996	/* Description: Data whitening initial value. */
yihui	9:05f0b5a3a70a	4997
yihui	9:05f0b5a3a70a	4998	/* Bits 5..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
yihui	9:05f0b5a3a70a	4999	#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /!< Position of DATAWHITEIV field. /
yihui	9:05f0b5a3a70a	5000	#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x3FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /!< Bit mask of DATAWHITEIV field. /
yihui	9:05f0b5a3a70a	5001
yihui	9:05f0b5a3a70a	5002	/* Register: RADIO_DAP */
yihui	9:05f0b5a3a70a	5003	/* Description: Device address prefix. */
yihui	9:05f0b5a3a70a	5004
yihui	9:05f0b5a3a70a	5005	/* Bits 15..0 : Device address prefix. */
yihui	9:05f0b5a3a70a	5006	#define RADIO_DAP_DAP_Pos (0UL) /!< Position of DAP field. /
yihui	9:05f0b5a3a70a	5007	#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /!< Bit mask of DAP field. /
yihui	9:05f0b5a3a70a	5008
yihui	9:05f0b5a3a70a	5009	/* Register: RADIO_DACNF */
yihui	9:05f0b5a3a70a	5010	/* Description: Device address match configuration. */
yihui	9:05f0b5a3a70a	5011
yihui	9:05f0b5a3a70a	5012	/* Bit 15 : TxAdd for device address 7. */
yihui	9:05f0b5a3a70a	5013	#define RADIO_DACNF_TXADD7_Pos (15UL) /!< Position of TXADD7 field. /
yihui	9:05f0b5a3a70a	5014	#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /!< Bit mask of TXADD7 field. /
yihui	9:05f0b5a3a70a	5015
yihui	9:05f0b5a3a70a	5016	/* Bit 14 : TxAdd for device address 6. */
yihui	9:05f0b5a3a70a	5017	#define RADIO_DACNF_TXADD6_Pos (14UL) /!< Position of TXADD6 field. /
yihui	9:05f0b5a3a70a	5018	#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /!< Bit mask of TXADD6 field. /
yihui	9:05f0b5a3a70a	5019
yihui	9:05f0b5a3a70a	5020	/* Bit 13 : TxAdd for device address 5. */
yihui	9:05f0b5a3a70a	5021	#define RADIO_DACNF_TXADD5_Pos (13UL) /!< Position of TXADD5 field. /
yihui	9:05f0b5a3a70a	5022	#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /!< Bit mask of TXADD5 field. /
yihui	9:05f0b5a3a70a	5023
yihui	9:05f0b5a3a70a	5024	/* Bit 12 : TxAdd for device address 4. */
yihui	9:05f0b5a3a70a	5025	#define RADIO_DACNF_TXADD4_Pos (12UL) /!< Position of TXADD4 field. /
yihui	9:05f0b5a3a70a	5026	#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /!< Bit mask of TXADD4 field. /
yihui	9:05f0b5a3a70a	5027
yihui	9:05f0b5a3a70a	5028	/* Bit 11 : TxAdd for device address 3. */
yihui	9:05f0b5a3a70a	5029	#define RADIO_DACNF_TXADD3_Pos (11UL) /!< Position of TXADD3 field. /
yihui	9:05f0b5a3a70a	5030	#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /!< Bit mask of TXADD3 field. /
yihui	9:05f0b5a3a70a	5031
yihui	9:05f0b5a3a70a	5032	/* Bit 10 : TxAdd for device address 2. */
yihui	9:05f0b5a3a70a	5033	#define RADIO_DACNF_TXADD2_Pos (10UL) /!< Position of TXADD2 field. /
yihui	9:05f0b5a3a70a	5034	#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /!< Bit mask of TXADD2 field. /
yihui	9:05f0b5a3a70a	5035
yihui	9:05f0b5a3a70a	5036	/* Bit 9 : TxAdd for device address 1. */
yihui	9:05f0b5a3a70a	5037	#define RADIO_DACNF_TXADD1_Pos (9UL) /!< Position of TXADD1 field. /
yihui	9:05f0b5a3a70a	5038	#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /!< Bit mask of TXADD1 field. /
yihui	9:05f0b5a3a70a	5039
yihui	9:05f0b5a3a70a	5040	/* Bit 8 : TxAdd for device address 0. */
yihui	9:05f0b5a3a70a	5041	#define RADIO_DACNF_TXADD0_Pos (8UL) /!< Position of TXADD0 field. /
yihui	9:05f0b5a3a70a	5042	#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /!< Bit mask of TXADD0 field. /
yihui	9:05f0b5a3a70a	5043
yihui	9:05f0b5a3a70a	5044	/* Bit 7 : Enable or disable device address matching using device address 7. */
yihui	9:05f0b5a3a70a	5045	#define RADIO_DACNF_ENA7_Pos (7UL) /!< Position of ENA7 field. /
yihui	9:05f0b5a3a70a	5046	#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /!< Bit mask of ENA7 field. /
yihui	9:05f0b5a3a70a	5047	#define RADIO_DACNF_ENA7_Disabled (0UL) /!< Disabled. /
yihui	9:05f0b5a3a70a	5048	#define RADIO_DACNF_ENA7_Enabled (1UL) /!< Enabled. /
yihui	9:05f0b5a3a70a	5049
yihui	9:05f0b5a3a70a	5050	/* Bit 6 : Enable or disable device address matching using device address 6. */
yihui	9:05f0b5a3a70a	5051	#define RADIO_DACNF_ENA6_Pos (6UL) /!< Position of ENA6 field. /
yihui	9:05f0b5a3a70a	5052	#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /!< Bit mask of ENA6 field. /
yihui	9:05f0b5a3a70a	5053	#define RADIO_DACNF_ENA6_Disabled (0UL) /!< Disabled. /
yihui	9:05f0b5a3a70a	5054	#define RADIO_DACNF_ENA6_Enabled (1UL) /!< Enabled. /
yihui	9:05f0b5a3a70a	5055
yihui	9:05f0b5a3a70a	5056	/* Bit 5 : Enable or disable device address matching using device address 5. */
yihui	9:05f0b5a3a70a	5057	#define RADIO_DACNF_ENA5_Pos (5UL) /!< Position of ENA5 field. /
yihui	9:05f0b5a3a70a	5058	#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /!< Bit mask of ENA5 field. /
yihui	9:05f0b5a3a70a	5059	#define RADIO_DACNF_ENA5_Disabled (0UL) /!< Disabled. /
yihui	9:05f0b5a3a70a	5060	#define RADIO_DACNF_ENA5_Enabled (1UL) /!< Enabled. /
yihui	9:05f0b5a3a70a	5061
yihui	9:05f0b5a3a70a	5062	/* Bit 4 : Enable or disable device address matching using device address 4. */
yihui	9:05f0b5a3a70a	5063	#define RADIO_DACNF_ENA4_Pos (4UL) /!< Position of ENA4 field. /
yihui	9:05f0b5a3a70a	5064	#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /!< Bit mask of ENA4 field. /
yihui	9:05f0b5a3a70a	5065	#define RADIO_DACNF_ENA4_Disabled (0UL) /!< Disabled. /
yihui	9:05f0b5a3a70a	5066	#define RADIO_DACNF_ENA4_Enabled (1UL) /!< Enabled. /
yihui	9:05f0b5a3a70a	5067
yihui	9:05f0b5a3a70a	5068	/* Bit 3 : Enable or disable device address matching using device address 3. */
yihui	9:05f0b5a3a70a	5069	#define RADIO_DACNF_ENA3_Pos (3UL) /!< Position of ENA3 field. /
yihui	9:05f0b5a3a70a	5070	#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /!< Bit mask of ENA3 field. /
yihui	9:05f0b5a3a70a	5071	#define RADIO_DACNF_ENA3_Disabled (0UL) /!< Disabled. /
yihui	9:05f0b5a3a70a	5072	#define RADIO_DACNF_ENA3_Enabled (1UL) /!< Enabled. /
yihui	9:05f0b5a3a70a	5073
yihui	9:05f0b5a3a70a	5074	/* Bit 2 : Enable or disable device address matching using device address 2. */
yihui	9:05f0b5a3a70a	5075	#define RADIO_DACNF_ENA2_Pos (2UL) /!< Position of ENA2 field. /
yihui	9:05f0b5a3a70a	5076	#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /!< Bit mask of ENA2 field. /
yihui	9:05f0b5a3a70a	5077	#define RADIO_DACNF_ENA2_Disabled (0UL) /!< Disabled. /
yihui	9:05f0b5a3a70a	5078	#define RADIO_DACNF_ENA2_Enabled (1UL) /!< Enabled. /
yihui	9:05f0b5a3a70a	5079
yihui	9:05f0b5a3a70a	5080	/* Bit 1 : Enable or disable device address matching using device address 1. */
yihui	9:05f0b5a3a70a	5081	#define RADIO_DACNF_ENA1_Pos (1UL) /!< Position of ENA1 field. /
yihui	9:05f0b5a3a70a	5082	#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /!< Bit mask of ENA1 field. /
yihui	9:05f0b5a3a70a	5083	#define RADIO_DACNF_ENA1_Disabled (0UL) /!< Disabled. /
yihui	9:05f0b5a3a70a	5084	#define RADIO_DACNF_ENA1_Enabled (1UL) /!< Enabled. /
yihui	9:05f0b5a3a70a	5085
yihui	9:05f0b5a3a70a	5086	/* Bit 0 : Enable or disable device address matching using device address 0. */
yihui	9:05f0b5a3a70a	5087	#define RADIO_DACNF_ENA0_Pos (0UL) /!< Position of ENA0 field. /
yihui	9:05f0b5a3a70a	5088	#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /!< Bit mask of ENA0 field. /
yihui	9:05f0b5a3a70a	5089	#define RADIO_DACNF_ENA0_Disabled (0UL) /!< Disabled. /
yihui	9:05f0b5a3a70a	5090	#define RADIO_DACNF_ENA0_Enabled (1UL) /!< Enabled. /
yihui	9:05f0b5a3a70a	5091
yihui	9:05f0b5a3a70a	5092	/* Register: RADIO_OVERRIDE0 */
yihui	9:05f0b5a3a70a	5093	/* Description: Trim value override register 0. */
yihui	9:05f0b5a3a70a	5094
yihui	9:05f0b5a3a70a	5095	/* Bits 31..0 : Trim value override register 0. */
yihui	9:05f0b5a3a70a	5096	#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /!< Position of OVERRIDE0 field. /
yihui	9:05f0b5a3a70a	5097	#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /!< Bit mask of OVERRIDE0 field. /
yihui	9:05f0b5a3a70a	5098
yihui	9:05f0b5a3a70a	5099	/* Register: RADIO_OVERRIDE1 */
yihui	9:05f0b5a3a70a	5100	/* Description: Trim value override register 1. */
yihui	9:05f0b5a3a70a	5101
yihui	9:05f0b5a3a70a	5102	/* Bits 31..0 : Trim value override register 1. */
yihui	9:05f0b5a3a70a	5103	#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /!< Position of OVERRIDE1 field. /
yihui	9:05f0b5a3a70a	5104	#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /!< Bit mask of OVERRIDE1 field. /
yihui	9:05f0b5a3a70a	5105
yihui	9:05f0b5a3a70a	5106	/* Register: RADIO_OVERRIDE2 */
yihui	9:05f0b5a3a70a	5107	/* Description: Trim value override register 2. */
yihui	9:05f0b5a3a70a	5108
yihui	9:05f0b5a3a70a	5109	/* Bits 31..0 : Trim value override register 2. */
yihui	9:05f0b5a3a70a	5110	#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /!< Position of OVERRIDE2 field. /
yihui	9:05f0b5a3a70a	5111	#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /!< Bit mask of OVERRIDE2 field. /
yihui	9:05f0b5a3a70a	5112
yihui	9:05f0b5a3a70a	5113	/* Register: RADIO_OVERRIDE3 */
yihui	9:05f0b5a3a70a	5114	/* Description: Trim value override register 3. */
yihui	9:05f0b5a3a70a	5115
yihui	9:05f0b5a3a70a	5116	/* Bits 31..0 : Trim value override register 3. */
yihui	9:05f0b5a3a70a	5117	#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /!< Position of OVERRIDE3 field. /
yihui	9:05f0b5a3a70a	5118	#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /!< Bit mask of OVERRIDE3 field. /
yihui	9:05f0b5a3a70a	5119
yihui	9:05f0b5a3a70a	5120	/* Register: RADIO_OVERRIDE4 */
yihui	9:05f0b5a3a70a	5121	/* Description: Trim value override register 4. */
yihui	9:05f0b5a3a70a	5122
yihui	9:05f0b5a3a70a	5123	/* Bit 31 : Enable or disable override of default trim values. */
yihui	9:05f0b5a3a70a	5124	#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /!< Position of ENABLE field. /
yihui	9:05f0b5a3a70a	5125	#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /!< Bit mask of ENABLE field. /
yihui	9:05f0b5a3a70a	5126	#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /!< Override trim values disabled. /
yihui	9:05f0b5a3a70a	5127	#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /!< Override trim values enabled. /
yihui	9:05f0b5a3a70a	5128
yihui	9:05f0b5a3a70a	5129	/* Bits 27..0 : Trim value override register 4. */
yihui	9:05f0b5a3a70a	5130	#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /!< Position of OVERRIDE4 field. /
yihui	9:05f0b5a3a70a	5131	#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /!< Bit mask of OVERRIDE4 field. /
yihui	9:05f0b5a3a70a	5132
yihui	9:05f0b5a3a70a	5133	/* Register: RADIO_POWER */
yihui	9:05f0b5a3a70a	5134	/* Description: Peripheral power control. */
yihui	9:05f0b5a3a70a	5135
yihui	9:05f0b5a3a70a	5136	/* Bit 0 : Peripheral power control. */
yihui	9:05f0b5a3a70a	5137	#define RADIO_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
yihui	9:05f0b5a3a70a	5138	#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /!< Bit mask of POWER field. /
yihui	9:05f0b5a3a70a	5139	#define RADIO_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
yihui	9:05f0b5a3a70a	5140	#define RADIO_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
yihui	9:05f0b5a3a70a	5141
yihui	9:05f0b5a3a70a	5142
yihui	9:05f0b5a3a70a	5143	/* Peripheral: RNG */
yihui	9:05f0b5a3a70a	5144	/* Description: Random Number Generator. */
yihui	9:05f0b5a3a70a	5145
yihui	9:05f0b5a3a70a	5146	/* Register: RNG_SHORTS */
yihui	9:05f0b5a3a70a	5147	/* Description: Shortcut for the RNG. */
yihui	9:05f0b5a3a70a	5148
yihui	9:05f0b5a3a70a	5149	/* Bit 0 : Short-cut between VALRDY event and STOP task. */
yihui	9:05f0b5a3a70a	5150	#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /!< Position of VALRDY_STOP field. /
yihui	9:05f0b5a3a70a	5151	#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /!< Bit mask of VALRDY_STOP field. /
yihui	9:05f0b5a3a70a	5152	#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	5153	#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	5154
yihui	9:05f0b5a3a70a	5155	/* Register: RNG_INTENSET */
yihui	9:05f0b5a3a70a	5156	/* Description: Interrupt enable set register */
yihui	9:05f0b5a3a70a	5157
yihui	9:05f0b5a3a70a	5158	/* Bit 0 : Enable interrupt on VALRDY event. */
yihui	9:05f0b5a3a70a	5159	#define RNG_INTENSET_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
yihui	9:05f0b5a3a70a	5160	#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /!< Bit mask of VALRDY field. /
yihui	9:05f0b5a3a70a	5161	#define RNG_INTENSET_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5162	#define RNG_INTENSET_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5163	#define RNG_INTENSET_VALRDY_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	5164
yihui	9:05f0b5a3a70a	5165	/* Register: RNG_INTENCLR */
yihui	9:05f0b5a3a70a	5166	/* Description: Interrupt enable clear register */
yihui	9:05f0b5a3a70a	5167
yihui	9:05f0b5a3a70a	5168	/* Bit 0 : Disable interrupt on VALRDY event. */
yihui	9:05f0b5a3a70a	5169	#define RNG_INTENCLR_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
yihui	9:05f0b5a3a70a	5170	#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /!< Bit mask of VALRDY field. /
yihui	9:05f0b5a3a70a	5171	#define RNG_INTENCLR_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5172	#define RNG_INTENCLR_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5173	#define RNG_INTENCLR_VALRDY_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	5174
yihui	9:05f0b5a3a70a	5175	/* Register: RNG_CONFIG */
yihui	9:05f0b5a3a70a	5176	/* Description: Configuration register. */
yihui	9:05f0b5a3a70a	5177
yihui	9:05f0b5a3a70a	5178	/* Bit 0 : Digital error correction enable. */
yihui	9:05f0b5a3a70a	5179	#define RNG_CONFIG_DERCEN_Pos (0UL) /!< Position of DERCEN field. /
yihui	9:05f0b5a3a70a	5180	#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /!< Bit mask of DERCEN field. /
yihui	9:05f0b5a3a70a	5181	#define RNG_CONFIG_DERCEN_Disabled (0UL) /!< Digital error correction disabled. /
yihui	9:05f0b5a3a70a	5182	#define RNG_CONFIG_DERCEN_Enabled (1UL) /!< Digital error correction enabled. /
yihui	9:05f0b5a3a70a	5183
yihui	9:05f0b5a3a70a	5184	/* Register: RNG_VALUE */
yihui	9:05f0b5a3a70a	5185	/* Description: RNG random number. */
yihui	9:05f0b5a3a70a	5186
yihui	9:05f0b5a3a70a	5187	/* Bits 7..0 : Generated random number. */
yihui	9:05f0b5a3a70a	5188	#define RNG_VALUE_VALUE_Pos (0UL) /!< Position of VALUE field. /
yihui	9:05f0b5a3a70a	5189	#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /!< Bit mask of VALUE field. /
yihui	9:05f0b5a3a70a	5190
yihui	9:05f0b5a3a70a	5191	/* Register: RNG_POWER */
yihui	9:05f0b5a3a70a	5192	/* Description: Peripheral power control. */
yihui	9:05f0b5a3a70a	5193
yihui	9:05f0b5a3a70a	5194	/* Bit 0 : Peripheral power control. */
yihui	9:05f0b5a3a70a	5195	#define RNG_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
yihui	9:05f0b5a3a70a	5196	#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /!< Bit mask of POWER field. /
yihui	9:05f0b5a3a70a	5197	#define RNG_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
yihui	9:05f0b5a3a70a	5198	#define RNG_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
yihui	9:05f0b5a3a70a	5199
yihui	9:05f0b5a3a70a	5200
yihui	9:05f0b5a3a70a	5201	/* Peripheral: RTC */
yihui	9:05f0b5a3a70a	5202	/* Description: Real time counter 0. */
yihui	9:05f0b5a3a70a	5203
yihui	9:05f0b5a3a70a	5204	/* Register: RTC_INTENSET */
yihui	9:05f0b5a3a70a	5205	/* Description: Interrupt enable set register. */
yihui	9:05f0b5a3a70a	5206
yihui	9:05f0b5a3a70a	5207	/* Bit 19 : Enable interrupt on COMPARE[3] event. */
yihui	9:05f0b5a3a70a	5208	#define RTC_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
yihui	9:05f0b5a3a70a	5209	#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
yihui	9:05f0b5a3a70a	5210	#define RTC_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5211	#define RTC_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5212	#define RTC_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	5213
yihui	9:05f0b5a3a70a	5214	/* Bit 18 : Enable interrupt on COMPARE[2] event. */
yihui	9:05f0b5a3a70a	5215	#define RTC_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
yihui	9:05f0b5a3a70a	5216	#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
yihui	9:05f0b5a3a70a	5217	#define RTC_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5218	#define RTC_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5219	#define RTC_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	5220
yihui	9:05f0b5a3a70a	5221	/* Bit 17 : Enable interrupt on COMPARE[1] event. */
yihui	9:05f0b5a3a70a	5222	#define RTC_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
yihui	9:05f0b5a3a70a	5223	#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
yihui	9:05f0b5a3a70a	5224	#define RTC_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5225	#define RTC_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5226	#define RTC_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	5227
yihui	9:05f0b5a3a70a	5228	/* Bit 16 : Enable interrupt on COMPARE[0] event. */
yihui	9:05f0b5a3a70a	5229	#define RTC_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
yihui	9:05f0b5a3a70a	5230	#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
yihui	9:05f0b5a3a70a	5231	#define RTC_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5232	#define RTC_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5233	#define RTC_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	5234
yihui	9:05f0b5a3a70a	5235	/* Bit 1 : Enable interrupt on OVRFLW event. */
yihui	9:05f0b5a3a70a	5236	#define RTC_INTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
yihui	9:05f0b5a3a70a	5237	#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
yihui	9:05f0b5a3a70a	5238	#define RTC_INTENSET_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5239	#define RTC_INTENSET_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5240	#define RTC_INTENSET_OVRFLW_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	5241
yihui	9:05f0b5a3a70a	5242	/* Bit 0 : Enable interrupt on TICK event. */
yihui	9:05f0b5a3a70a	5243	#define RTC_INTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
yihui	9:05f0b5a3a70a	5244	#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /!< Bit mask of TICK field. /
yihui	9:05f0b5a3a70a	5245	#define RTC_INTENSET_TICK_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5246	#define RTC_INTENSET_TICK_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5247	#define RTC_INTENSET_TICK_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	5248
yihui	9:05f0b5a3a70a	5249	/* Register: RTC_INTENCLR */
yihui	9:05f0b5a3a70a	5250	/* Description: Interrupt enable clear register. */
yihui	9:05f0b5a3a70a	5251
yihui	9:05f0b5a3a70a	5252	/* Bit 19 : Disable interrupt on COMPARE[3] event. */
yihui	9:05f0b5a3a70a	5253	#define RTC_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
yihui	9:05f0b5a3a70a	5254	#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
yihui	9:05f0b5a3a70a	5255	#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5256	#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5257	#define RTC_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	5258
yihui	9:05f0b5a3a70a	5259	/* Bit 18 : Disable interrupt on COMPARE[2] event. */
yihui	9:05f0b5a3a70a	5260	#define RTC_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
yihui	9:05f0b5a3a70a	5261	#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
yihui	9:05f0b5a3a70a	5262	#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5263	#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5264	#define RTC_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	5265
yihui	9:05f0b5a3a70a	5266	/* Bit 17 : Disable interrupt on COMPARE[1] event. */
yihui	9:05f0b5a3a70a	5267	#define RTC_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
yihui	9:05f0b5a3a70a	5268	#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
yihui	9:05f0b5a3a70a	5269	#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5270	#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5271	#define RTC_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	5272
yihui	9:05f0b5a3a70a	5273	/* Bit 16 : Disable interrupt on COMPARE[0] event. */
yihui	9:05f0b5a3a70a	5274	#define RTC_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
yihui	9:05f0b5a3a70a	5275	#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
yihui	9:05f0b5a3a70a	5276	#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5277	#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5278	#define RTC_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	5279
yihui	9:05f0b5a3a70a	5280	/* Bit 1 : Disable interrupt on OVRFLW event. */
yihui	9:05f0b5a3a70a	5281	#define RTC_INTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
yihui	9:05f0b5a3a70a	5282	#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
yihui	9:05f0b5a3a70a	5283	#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5284	#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5285	#define RTC_INTENCLR_OVRFLW_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	5286
yihui	9:05f0b5a3a70a	5287	/* Bit 0 : Disable interrupt on TICK event. */
yihui	9:05f0b5a3a70a	5288	#define RTC_INTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
yihui	9:05f0b5a3a70a	5289	#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
yihui	9:05f0b5a3a70a	5290	#define RTC_INTENCLR_TICK_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5291	#define RTC_INTENCLR_TICK_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5292	#define RTC_INTENCLR_TICK_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	5293
yihui	9:05f0b5a3a70a	5294	/* Register: RTC_EVTEN */
yihui	9:05f0b5a3a70a	5295	/* Description: Configures event enable routing to PPI for each RTC event. */
yihui	9:05f0b5a3a70a	5296
yihui	9:05f0b5a3a70a	5297	/* Bit 19 : COMPARE[3] event enable. */
yihui	9:05f0b5a3a70a	5298	#define RTC_EVTEN_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
yihui	9:05f0b5a3a70a	5299	#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
yihui	9:05f0b5a3a70a	5300	#define RTC_EVTEN_COMPARE3_Disabled (0UL) /!< Event disabled. /
yihui	9:05f0b5a3a70a	5301	#define RTC_EVTEN_COMPARE3_Enabled (1UL) /!< Event enabled. /
yihui	9:05f0b5a3a70a	5302
yihui	9:05f0b5a3a70a	5303	/* Bit 18 : COMPARE[2] event enable. */
yihui	9:05f0b5a3a70a	5304	#define RTC_EVTEN_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
yihui	9:05f0b5a3a70a	5305	#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
yihui	9:05f0b5a3a70a	5306	#define RTC_EVTEN_COMPARE2_Disabled (0UL) /!< Event disabled. /
yihui	9:05f0b5a3a70a	5307	#define RTC_EVTEN_COMPARE2_Enabled (1UL) /!< Event enabled. /
yihui	9:05f0b5a3a70a	5308
yihui	9:05f0b5a3a70a	5309	/* Bit 17 : COMPARE[1] event enable. */
yihui	9:05f0b5a3a70a	5310	#define RTC_EVTEN_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
yihui	9:05f0b5a3a70a	5311	#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
yihui	9:05f0b5a3a70a	5312	#define RTC_EVTEN_COMPARE1_Disabled (0UL) /!< Event disabled. /
yihui	9:05f0b5a3a70a	5313	#define RTC_EVTEN_COMPARE1_Enabled (1UL) /!< Event enabled. /
yihui	9:05f0b5a3a70a	5314
yihui	9:05f0b5a3a70a	5315	/* Bit 16 : COMPARE[0] event enable. */
yihui	9:05f0b5a3a70a	5316	#define RTC_EVTEN_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
yihui	9:05f0b5a3a70a	5317	#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
yihui	9:05f0b5a3a70a	5318	#define RTC_EVTEN_COMPARE0_Disabled (0UL) /!< Event disabled. /
yihui	9:05f0b5a3a70a	5319	#define RTC_EVTEN_COMPARE0_Enabled (1UL) /!< Event enabled. /
yihui	9:05f0b5a3a70a	5320
yihui	9:05f0b5a3a70a	5321	/* Bit 1 : OVRFLW event enable. */
yihui	9:05f0b5a3a70a	5322	#define RTC_EVTEN_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
yihui	9:05f0b5a3a70a	5323	#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
yihui	9:05f0b5a3a70a	5324	#define RTC_EVTEN_OVRFLW_Disabled (0UL) /!< Event disabled. /
yihui	9:05f0b5a3a70a	5325	#define RTC_EVTEN_OVRFLW_Enabled (1UL) /!< Event enabled. /
yihui	9:05f0b5a3a70a	5326
yihui	9:05f0b5a3a70a	5327	/* Bit 0 : TICK event enable. */
yihui	9:05f0b5a3a70a	5328	#define RTC_EVTEN_TICK_Pos (0UL) /!< Position of TICK field. /
yihui	9:05f0b5a3a70a	5329	#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /!< Bit mask of TICK field. /
yihui	9:05f0b5a3a70a	5330	#define RTC_EVTEN_TICK_Disabled (0UL) /!< Event disabled. /
yihui	9:05f0b5a3a70a	5331	#define RTC_EVTEN_TICK_Enabled (1UL) /!< Event enabled. /
yihui	9:05f0b5a3a70a	5332
yihui	9:05f0b5a3a70a	5333	/* Register: RTC_EVTENSET */
yihui	9:05f0b5a3a70a	5334	/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
yihui	9:05f0b5a3a70a	5335
yihui	9:05f0b5a3a70a	5336	/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
yihui	9:05f0b5a3a70a	5337	#define RTC_EVTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
yihui	9:05f0b5a3a70a	5338	#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
yihui	9:05f0b5a3a70a	5339	#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /!< Event disabled. /
yihui	9:05f0b5a3a70a	5340	#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /!< Event enabled. /
yihui	9:05f0b5a3a70a	5341	#define RTC_EVTENSET_COMPARE3_Set (1UL) /!< Enable event on write. /
yihui	9:05f0b5a3a70a	5342
yihui	9:05f0b5a3a70a	5343	/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
yihui	9:05f0b5a3a70a	5344	#define RTC_EVTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
yihui	9:05f0b5a3a70a	5345	#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
yihui	9:05f0b5a3a70a	5346	#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /!< Event disabled. /
yihui	9:05f0b5a3a70a	5347	#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /!< Event enabled. /
yihui	9:05f0b5a3a70a	5348	#define RTC_EVTENSET_COMPARE2_Set (1UL) /!< Enable event on write. /
yihui	9:05f0b5a3a70a	5349
yihui	9:05f0b5a3a70a	5350	/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
yihui	9:05f0b5a3a70a	5351	#define RTC_EVTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
yihui	9:05f0b5a3a70a	5352	#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
yihui	9:05f0b5a3a70a	5353	#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /!< Event disabled. /
yihui	9:05f0b5a3a70a	5354	#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /!< Event enabled. /
yihui	9:05f0b5a3a70a	5355	#define RTC_EVTENSET_COMPARE1_Set (1UL) /!< Enable event on write. /
yihui	9:05f0b5a3a70a	5356
yihui	9:05f0b5a3a70a	5357	/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
yihui	9:05f0b5a3a70a	5358	#define RTC_EVTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
yihui	9:05f0b5a3a70a	5359	#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
yihui	9:05f0b5a3a70a	5360	#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /!< Event disabled. /
yihui	9:05f0b5a3a70a	5361	#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /!< Event enabled. /
yihui	9:05f0b5a3a70a	5362	#define RTC_EVTENSET_COMPARE0_Set (1UL) /!< Enable event on write. /
yihui	9:05f0b5a3a70a	5363
yihui	9:05f0b5a3a70a	5364	/* Bit 1 : Enable routing to PPI of OVRFLW event. */
yihui	9:05f0b5a3a70a	5365	#define RTC_EVTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
yihui	9:05f0b5a3a70a	5366	#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
yihui	9:05f0b5a3a70a	5367	#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /!< Event disabled. /
yihui	9:05f0b5a3a70a	5368	#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /!< Event enabled. /
yihui	9:05f0b5a3a70a	5369	#define RTC_EVTENSET_OVRFLW_Set (1UL) /!< Enable event on write. /
yihui	9:05f0b5a3a70a	5370
yihui	9:05f0b5a3a70a	5371	/* Bit 0 : Enable routing to PPI of TICK event. */
yihui	9:05f0b5a3a70a	5372	#define RTC_EVTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
yihui	9:05f0b5a3a70a	5373	#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /!< Bit mask of TICK field. /
yihui	9:05f0b5a3a70a	5374	#define RTC_EVTENSET_TICK_Disabled (0UL) /!< Event disabled. /
yihui	9:05f0b5a3a70a	5375	#define RTC_EVTENSET_TICK_Enabled (1UL) /!< Event enabled. /
yihui	9:05f0b5a3a70a	5376	#define RTC_EVTENSET_TICK_Set (1UL) /!< Enable event on write. /
yihui	9:05f0b5a3a70a	5377
yihui	9:05f0b5a3a70a	5378	/* Register: RTC_EVTENCLR */
yihui	9:05f0b5a3a70a	5379	/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
yihui	9:05f0b5a3a70a	5380
yihui	9:05f0b5a3a70a	5381	/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
yihui	9:05f0b5a3a70a	5382	#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
yihui	9:05f0b5a3a70a	5383	#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
yihui	9:05f0b5a3a70a	5384	#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /!< Event disabled. /
yihui	9:05f0b5a3a70a	5385	#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /!< Event enabled. /
yihui	9:05f0b5a3a70a	5386	#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /!< Disable event on write. /
yihui	9:05f0b5a3a70a	5387
yihui	9:05f0b5a3a70a	5388	/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
yihui	9:05f0b5a3a70a	5389	#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
yihui	9:05f0b5a3a70a	5390	#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
yihui	9:05f0b5a3a70a	5391	#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /!< Event disabled. /
yihui	9:05f0b5a3a70a	5392	#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /!< Event enabled. /
yihui	9:05f0b5a3a70a	5393	#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /!< Disable event on write. /
yihui	9:05f0b5a3a70a	5394
yihui	9:05f0b5a3a70a	5395	/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
yihui	9:05f0b5a3a70a	5396	#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
yihui	9:05f0b5a3a70a	5397	#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
yihui	9:05f0b5a3a70a	5398	#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /!< Event disabled. /
yihui	9:05f0b5a3a70a	5399	#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /!< Event enabled. /
yihui	9:05f0b5a3a70a	5400	#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /!< Disable event on write. /
yihui	9:05f0b5a3a70a	5401
yihui	9:05f0b5a3a70a	5402	/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
yihui	9:05f0b5a3a70a	5403	#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
yihui	9:05f0b5a3a70a	5404	#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
yihui	9:05f0b5a3a70a	5405	#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /!< Event disabled. /
yihui	9:05f0b5a3a70a	5406	#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /!< Event enabled. /
yihui	9:05f0b5a3a70a	5407	#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /!< Disable event on write. /
yihui	9:05f0b5a3a70a	5408
yihui	9:05f0b5a3a70a	5409	/* Bit 1 : Disable routing to PPI of OVRFLW event. */
yihui	9:05f0b5a3a70a	5410	#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
yihui	9:05f0b5a3a70a	5411	#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
yihui	9:05f0b5a3a70a	5412	#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /!< Event disabled. /
yihui	9:05f0b5a3a70a	5413	#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /!< Event enabled. /
yihui	9:05f0b5a3a70a	5414	#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /!< Disable event on write. /
yihui	9:05f0b5a3a70a	5415
yihui	9:05f0b5a3a70a	5416	/* Bit 0 : Disable routing to PPI of TICK event. */
yihui	9:05f0b5a3a70a	5417	#define RTC_EVTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
yihui	9:05f0b5a3a70a	5418	#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
yihui	9:05f0b5a3a70a	5419	#define RTC_EVTENCLR_TICK_Disabled (0UL) /!< Event disabled. /
yihui	9:05f0b5a3a70a	5420	#define RTC_EVTENCLR_TICK_Enabled (1UL) /!< Event enabled. /
yihui	9:05f0b5a3a70a	5421	#define RTC_EVTENCLR_TICK_Clear (1UL) /!< Disable event on write. /
yihui	9:05f0b5a3a70a	5422
yihui	9:05f0b5a3a70a	5423	/* Register: RTC_COUNTER */
yihui	9:05f0b5a3a70a	5424	/* Description: Current COUNTER value. */
yihui	9:05f0b5a3a70a	5425
yihui	9:05f0b5a3a70a	5426	/* Bits 23..0 : Counter value. */
yihui	9:05f0b5a3a70a	5427	#define RTC_COUNTER_COUNTER_Pos (0UL) /!< Position of COUNTER field. /
yihui	9:05f0b5a3a70a	5428	#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /!< Bit mask of COUNTER field. /
yihui	9:05f0b5a3a70a	5429
yihui	9:05f0b5a3a70a	5430	/* Register: RTC_PRESCALER */
yihui	9:05f0b5a3a70a	5431	/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
yihui	9:05f0b5a3a70a	5432
yihui	9:05f0b5a3a70a	5433	/* Bits 11..0 : RTC PRESCALER value. */
yihui	9:05f0b5a3a70a	5434	#define RTC_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
yihui	9:05f0b5a3a70a	5435	#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
yihui	9:05f0b5a3a70a	5436
yihui	9:05f0b5a3a70a	5437	/* Register: RTC_CC */
yihui	9:05f0b5a3a70a	5438	/* Description: Capture/compare registers. */
yihui	9:05f0b5a3a70a	5439
yihui	9:05f0b5a3a70a	5440	/* Bits 23..0 : Compare value. */
yihui	9:05f0b5a3a70a	5441	#define RTC_CC_COMPARE_Pos (0UL) /!< Position of COMPARE field. /
yihui	9:05f0b5a3a70a	5442	#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /!< Bit mask of COMPARE field. /
yihui	9:05f0b5a3a70a	5443
yihui	9:05f0b5a3a70a	5444	/* Register: RTC_POWER */
yihui	9:05f0b5a3a70a	5445	/* Description: Peripheral power control. */
yihui	9:05f0b5a3a70a	5446
yihui	9:05f0b5a3a70a	5447	/* Bit 0 : Peripheral power control. */
yihui	9:05f0b5a3a70a	5448	#define RTC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
yihui	9:05f0b5a3a70a	5449	#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
yihui	9:05f0b5a3a70a	5450	#define RTC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
yihui	9:05f0b5a3a70a	5451	#define RTC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
yihui	9:05f0b5a3a70a	5452
yihui	9:05f0b5a3a70a	5453
yihui	9:05f0b5a3a70a	5454	/* Peripheral: SPI */
yihui	9:05f0b5a3a70a	5455	/* Description: SPI master 0. */
yihui	9:05f0b5a3a70a	5456
yihui	9:05f0b5a3a70a	5457	/* Register: SPI_INTENSET */
yihui	9:05f0b5a3a70a	5458	/* Description: Interrupt enable set register. */
yihui	9:05f0b5a3a70a	5459
yihui	9:05f0b5a3a70a	5460	/* Bit 2 : Enable interrupt on READY event. */
yihui	9:05f0b5a3a70a	5461	#define SPI_INTENSET_READY_Pos (2UL) /!< Position of READY field. /
yihui	9:05f0b5a3a70a	5462	#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /!< Bit mask of READY field. /
yihui	9:05f0b5a3a70a	5463	#define SPI_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5464	#define SPI_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5465	#define SPI_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	5466
yihui	9:05f0b5a3a70a	5467	/* Register: SPI_INTENCLR */
yihui	9:05f0b5a3a70a	5468	/* Description: Interrupt enable clear register. */
yihui	9:05f0b5a3a70a	5469
yihui	9:05f0b5a3a70a	5470	/* Bit 2 : Disable interrupt on READY event. */
yihui	9:05f0b5a3a70a	5471	#define SPI_INTENCLR_READY_Pos (2UL) /!< Position of READY field. /
yihui	9:05f0b5a3a70a	5472	#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
yihui	9:05f0b5a3a70a	5473	#define SPI_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5474	#define SPI_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5475	#define SPI_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	5476
yihui	9:05f0b5a3a70a	5477	/* Register: SPI_ENABLE */
yihui	9:05f0b5a3a70a	5478	/* Description: Enable SPI. */
yihui	9:05f0b5a3a70a	5479
yihui	9:05f0b5a3a70a	5480	/* Bits 2..0 : Enable or disable SPI. */
yihui	9:05f0b5a3a70a	5481	#define SPI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
yihui	9:05f0b5a3a70a	5482	#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
yihui	9:05f0b5a3a70a	5483	#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPI. /
yihui	9:05f0b5a3a70a	5484	#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable SPI. /
yihui	9:05f0b5a3a70a	5485
yihui	9:05f0b5a3a70a	5486	/* Register: SPI_RXD */
yihui	9:05f0b5a3a70a	5487	/* Description: RX data. */
yihui	9:05f0b5a3a70a	5488
yihui	9:05f0b5a3a70a	5489	/* Bits 7..0 : RX data from last transfer. */
yihui	9:05f0b5a3a70a	5490	#define SPI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
yihui	9:05f0b5a3a70a	5491	#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
yihui	9:05f0b5a3a70a	5492
yihui	9:05f0b5a3a70a	5493	/* Register: SPI_TXD */
yihui	9:05f0b5a3a70a	5494	/* Description: TX data. */
yihui	9:05f0b5a3a70a	5495
yihui	9:05f0b5a3a70a	5496	/* Bits 7..0 : TX data for next transfer. */
yihui	9:05f0b5a3a70a	5497	#define SPI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
yihui	9:05f0b5a3a70a	5498	#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
yihui	9:05f0b5a3a70a	5499
yihui	9:05f0b5a3a70a	5500	/* Register: SPI_FREQUENCY */
yihui	9:05f0b5a3a70a	5501	/* Description: SPI frequency */
yihui	9:05f0b5a3a70a	5502
yihui	9:05f0b5a3a70a	5503	/* Bits 31..0 : SPI data rate. */
yihui	9:05f0b5a3a70a	5504	#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
yihui	9:05f0b5a3a70a	5505	#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
yihui	9:05f0b5a3a70a	5506	#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125kbps. /
yihui	9:05f0b5a3a70a	5507	#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250kbps. /
yihui	9:05f0b5a3a70a	5508	#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500kbps. /
yihui	9:05f0b5a3a70a	5509	#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1Mbps. /
yihui	9:05f0b5a3a70a	5510	#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2Mbps. /
yihui	9:05f0b5a3a70a	5511	#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4Mbps. /
yihui	9:05f0b5a3a70a	5512	#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8Mbps. /
yihui	9:05f0b5a3a70a	5513
yihui	9:05f0b5a3a70a	5514	/* Register: SPI_CONFIG */
yihui	9:05f0b5a3a70a	5515	/* Description: Configuration register. */
yihui	9:05f0b5a3a70a	5516
yihui	9:05f0b5a3a70a	5517	/* Bit 2 : Serial clock (SCK) polarity. */
yihui	9:05f0b5a3a70a	5518	#define SPI_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
yihui	9:05f0b5a3a70a	5519	#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
yihui	9:05f0b5a3a70a	5520	#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
yihui	9:05f0b5a3a70a	5521	#define SPI_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
yihui	9:05f0b5a3a70a	5522
yihui	9:05f0b5a3a70a	5523	/* Bit 1 : Serial clock (SCK) phase. */
yihui	9:05f0b5a3a70a	5524	#define SPI_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
yihui	9:05f0b5a3a70a	5525	#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
yihui	9:05f0b5a3a70a	5526	#define SPI_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
yihui	9:05f0b5a3a70a	5527	#define SPI_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
yihui	9:05f0b5a3a70a	5528
yihui	9:05f0b5a3a70a	5529	/* Bit 0 : Bit order. */
yihui	9:05f0b5a3a70a	5530	#define SPI_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
yihui	9:05f0b5a3a70a	5531	#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
yihui	9:05f0b5a3a70a	5532	#define SPI_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
yihui	9:05f0b5a3a70a	5533	#define SPI_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
yihui	9:05f0b5a3a70a	5534
yihui	9:05f0b5a3a70a	5535	/* Register: SPI_POWER */
yihui	9:05f0b5a3a70a	5536	/* Description: Peripheral power control. */
yihui	9:05f0b5a3a70a	5537
yihui	9:05f0b5a3a70a	5538	/* Bit 0 : Peripheral power control. */
yihui	9:05f0b5a3a70a	5539	#define SPI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
yihui	9:05f0b5a3a70a	5540	#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
yihui	9:05f0b5a3a70a	5541	#define SPI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
yihui	9:05f0b5a3a70a	5542	#define SPI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
yihui	9:05f0b5a3a70a	5543
yihui	9:05f0b5a3a70a	5544
yihui	9:05f0b5a3a70a	5545	/* Peripheral: SPIS */
yihui	9:05f0b5a3a70a	5546	/* Description: SPI slave 1. */
yihui	9:05f0b5a3a70a	5547
yihui	9:05f0b5a3a70a	5548	/* Register: SPIS_SHORTS */
yihui	9:05f0b5a3a70a	5549	/* Description: Shortcuts for SPIS. */
yihui	9:05f0b5a3a70a	5550
yihui	9:05f0b5a3a70a	5551	/* Bit 2 : Shortcut between END event and the ACQUIRE task. */
yihui	9:05f0b5a3a70a	5552	#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /!< Position of END_ACQUIRE field. /
yihui	9:05f0b5a3a70a	5553	#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /!< Bit mask of END_ACQUIRE field. /
yihui	9:05f0b5a3a70a	5554	#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	5555	#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	5556
yihui	9:05f0b5a3a70a	5557	/* Register: SPIS_INTENSET */
yihui	9:05f0b5a3a70a	5558	/* Description: Interrupt enable set register. */
yihui	9:05f0b5a3a70a	5559
yihui	9:05f0b5a3a70a	5560	/* Bit 10 : Enable interrupt on ACQUIRED event. */
yihui	9:05f0b5a3a70a	5561	#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
yihui	9:05f0b5a3a70a	5562	#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
yihui	9:05f0b5a3a70a	5563	#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5564	#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5565	#define SPIS_INTENSET_ACQUIRED_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	5566
yihui	9:05f0b5a3a70a	5567	/* Bit 1 : Enable interrupt on END event. */
yihui	9:05f0b5a3a70a	5568	#define SPIS_INTENSET_END_Pos (1UL) /!< Position of END field. /
yihui	9:05f0b5a3a70a	5569	#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /!< Bit mask of END field. /
yihui	9:05f0b5a3a70a	5570	#define SPIS_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5571	#define SPIS_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5572	#define SPIS_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	5573
yihui	9:05f0b5a3a70a	5574	/* Register: SPIS_INTENCLR */
yihui	9:05f0b5a3a70a	5575	/* Description: Interrupt enable clear register. */
yihui	9:05f0b5a3a70a	5576
yihui	9:05f0b5a3a70a	5577	/* Bit 10 : Disable interrupt on ACQUIRED event. */
yihui	9:05f0b5a3a70a	5578	#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
yihui	9:05f0b5a3a70a	5579	#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
yihui	9:05f0b5a3a70a	5580	#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5581	#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5582	#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	5583
yihui	9:05f0b5a3a70a	5584	/* Bit 1 : Disable interrupt on END event. */
yihui	9:05f0b5a3a70a	5585	#define SPIS_INTENCLR_END_Pos (1UL) /!< Position of END field. /
yihui	9:05f0b5a3a70a	5586	#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /!< Bit mask of END field. /
yihui	9:05f0b5a3a70a	5587	#define SPIS_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5588	#define SPIS_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5589	#define SPIS_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	5590
yihui	9:05f0b5a3a70a	5591	/* Register: SPIS_SEMSTAT */
yihui	9:05f0b5a3a70a	5592	/* Description: Semaphore status. */
yihui	9:05f0b5a3a70a	5593
yihui	9:05f0b5a3a70a	5594	/* Bits 1..0 : Semaphore status. */
yihui	9:05f0b5a3a70a	5595	#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /!< Position of SEMSTAT field. /
yihui	9:05f0b5a3a70a	5596	#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /!< Bit mask of SEMSTAT field. /
yihui	9:05f0b5a3a70a	5597	#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /!< Semaphore is free. /
yihui	9:05f0b5a3a70a	5598	#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /!< Semaphore is assigned to the CPU. /
yihui	9:05f0b5a3a70a	5599	#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /!< Semaphore is assigned to the SPIS. /
yihui	9:05f0b5a3a70a	5600	#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. /
yihui	9:05f0b5a3a70a	5601
yihui	9:05f0b5a3a70a	5602	/* Register: SPIS_STATUS */
yihui	9:05f0b5a3a70a	5603	/* Description: Status from last transaction. */
yihui	9:05f0b5a3a70a	5604
yihui	9:05f0b5a3a70a	5605	/* Bit 1 : RX buffer overflow detected, and prevented. */
yihui	9:05f0b5a3a70a	5606	#define SPIS_STATUS_OVERFLOW_Pos (1UL) /!< Position of OVERFLOW field. /
yihui	9:05f0b5a3a70a	5607	#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /!< Bit mask of OVERFLOW field. /
yihui	9:05f0b5a3a70a	5608	#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /!< Error not present. /
yihui	9:05f0b5a3a70a	5609	#define SPIS_STATUS_OVERFLOW_Present (1UL) /!< Error present. /
yihui	9:05f0b5a3a70a	5610	#define SPIS_STATUS_OVERFLOW_Clear (1UL) /!< Clear on write. /
yihui	9:05f0b5a3a70a	5611
yihui	9:05f0b5a3a70a	5612	/* Bit 0 : TX buffer overread detected, and prevented. */
yihui	9:05f0b5a3a70a	5613	#define SPIS_STATUS_OVERREAD_Pos (0UL) /!< Position of OVERREAD field. /
yihui	9:05f0b5a3a70a	5614	#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /!< Bit mask of OVERREAD field. /
yihui	9:05f0b5a3a70a	5615	#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /!< Error not present. /
yihui	9:05f0b5a3a70a	5616	#define SPIS_STATUS_OVERREAD_Present (1UL) /!< Error present. /
yihui	9:05f0b5a3a70a	5617	#define SPIS_STATUS_OVERREAD_Clear (1UL) /!< Clear on write. /
yihui	9:05f0b5a3a70a	5618
yihui	9:05f0b5a3a70a	5619	/* Register: SPIS_ENABLE */
yihui	9:05f0b5a3a70a	5620	/* Description: Enable SPIS. */
yihui	9:05f0b5a3a70a	5621
yihui	9:05f0b5a3a70a	5622	/* Bits 2..0 : Enable or disable SPIS. */
yihui	9:05f0b5a3a70a	5623	#define SPIS_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
yihui	9:05f0b5a3a70a	5624	#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
yihui	9:05f0b5a3a70a	5625	#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIS. /
yihui	9:05f0b5a3a70a	5626	#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /!< Enable SPIS. /
yihui	9:05f0b5a3a70a	5627
yihui	9:05f0b5a3a70a	5628	/* Register: SPIS_MAXRX */
yihui	9:05f0b5a3a70a	5629	/* Description: Maximum number of bytes in the receive buffer. */
yihui	9:05f0b5a3a70a	5630
yihui	9:05f0b5a3a70a	5631	/* Bits 7..0 : Maximum number of bytes in the receive buffer. */
yihui	9:05f0b5a3a70a	5632	#define SPIS_MAXRX_MAXRX_Pos (0UL) /!< Position of MAXRX field. /
yihui	9:05f0b5a3a70a	5633	#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /!< Bit mask of MAXRX field. /
yihui	9:05f0b5a3a70a	5634
yihui	9:05f0b5a3a70a	5635	/* Register: SPIS_AMOUNTRX */
yihui	9:05f0b5a3a70a	5636	/* Description: Number of bytes received in last granted transaction. */
yihui	9:05f0b5a3a70a	5637
yihui	9:05f0b5a3a70a	5638	/* Bits 7..0 : Number of bytes received in last granted transaction. */
yihui	9:05f0b5a3a70a	5639	#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /!< Position of AMOUNTRX field. /
yihui	9:05f0b5a3a70a	5640	#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /!< Bit mask of AMOUNTRX field. /
yihui	9:05f0b5a3a70a	5641
yihui	9:05f0b5a3a70a	5642	/* Register: SPIS_MAXTX */
yihui	9:05f0b5a3a70a	5643	/* Description: Maximum number of bytes in the transmit buffer. */
yihui	9:05f0b5a3a70a	5644
yihui	9:05f0b5a3a70a	5645	/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
yihui	9:05f0b5a3a70a	5646	#define SPIS_MAXTX_MAXTX_Pos (0UL) /!< Position of MAXTX field. /
yihui	9:05f0b5a3a70a	5647	#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /!< Bit mask of MAXTX field. /
yihui	9:05f0b5a3a70a	5648
yihui	9:05f0b5a3a70a	5649	/* Register: SPIS_AMOUNTTX */
yihui	9:05f0b5a3a70a	5650	/* Description: Number of bytes transmitted in last granted transaction. */
yihui	9:05f0b5a3a70a	5651
yihui	9:05f0b5a3a70a	5652	/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
yihui	9:05f0b5a3a70a	5653	#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /!< Position of AMOUNTTX field. /
yihui	9:05f0b5a3a70a	5654	#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /!< Bit mask of AMOUNTTX field. /
yihui	9:05f0b5a3a70a	5655
yihui	9:05f0b5a3a70a	5656	/* Register: SPIS_CONFIG */
yihui	9:05f0b5a3a70a	5657	/* Description: Configuration register. */
yihui	9:05f0b5a3a70a	5658
yihui	9:05f0b5a3a70a	5659	/* Bit 2 : Serial clock (SCK) polarity. */
yihui	9:05f0b5a3a70a	5660	#define SPIS_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
yihui	9:05f0b5a3a70a	5661	#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
yihui	9:05f0b5a3a70a	5662	#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
yihui	9:05f0b5a3a70a	5663	#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
yihui	9:05f0b5a3a70a	5664
yihui	9:05f0b5a3a70a	5665	/* Bit 1 : Serial clock (SCK) phase. */
yihui	9:05f0b5a3a70a	5666	#define SPIS_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
yihui	9:05f0b5a3a70a	5667	#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
yihui	9:05f0b5a3a70a	5668	#define SPIS_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
yihui	9:05f0b5a3a70a	5669	#define SPIS_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
yihui	9:05f0b5a3a70a	5670
yihui	9:05f0b5a3a70a	5671	/* Bit 0 : Bit order. */
yihui	9:05f0b5a3a70a	5672	#define SPIS_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
yihui	9:05f0b5a3a70a	5673	#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
yihui	9:05f0b5a3a70a	5674	#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
yihui	9:05f0b5a3a70a	5675	#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
yihui	9:05f0b5a3a70a	5676
yihui	9:05f0b5a3a70a	5677	/* Register: SPIS_DEF */
yihui	9:05f0b5a3a70a	5678	/* Description: Default character. */
yihui	9:05f0b5a3a70a	5679
yihui	9:05f0b5a3a70a	5680	/* Bits 7..0 : Default character. */
yihui	9:05f0b5a3a70a	5681	#define SPIS_DEF_DEF_Pos (0UL) /!< Position of DEF field. /
yihui	9:05f0b5a3a70a	5682	#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /!< Bit mask of DEF field. /
yihui	9:05f0b5a3a70a	5683
yihui	9:05f0b5a3a70a	5684	/* Register: SPIS_ORC */
yihui	9:05f0b5a3a70a	5685	/* Description: Over-read character. */
yihui	9:05f0b5a3a70a	5686
yihui	9:05f0b5a3a70a	5687	/* Bits 7..0 : Over-read character. */
yihui	9:05f0b5a3a70a	5688	#define SPIS_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
yihui	9:05f0b5a3a70a	5689	#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /!< Bit mask of ORC field. /
yihui	9:05f0b5a3a70a	5690
yihui	9:05f0b5a3a70a	5691	/* Register: SPIS_POWER */
yihui	9:05f0b5a3a70a	5692	/* Description: Peripheral power control. */
yihui	9:05f0b5a3a70a	5693
yihui	9:05f0b5a3a70a	5694	/* Bit 0 : Peripheral power control. */
yihui	9:05f0b5a3a70a	5695	#define SPIS_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
yihui	9:05f0b5a3a70a	5696	#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /!< Bit mask of POWER field. /
yihui	9:05f0b5a3a70a	5697	#define SPIS_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
yihui	9:05f0b5a3a70a	5698	#define SPIS_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
yihui	9:05f0b5a3a70a	5699
yihui	9:05f0b5a3a70a	5700
yihui	9:05f0b5a3a70a	5701	/* Peripheral: TEMP */
yihui	9:05f0b5a3a70a	5702	/* Description: Temperature Sensor. */
yihui	9:05f0b5a3a70a	5703
yihui	9:05f0b5a3a70a	5704	/* Register: TEMP_INTENSET */
yihui	9:05f0b5a3a70a	5705	/* Description: Interrupt enable set register. */
yihui	9:05f0b5a3a70a	5706
yihui	9:05f0b5a3a70a	5707	/* Bit 0 : Enable interrupt on DATARDY event. */
yihui	9:05f0b5a3a70a	5708	#define TEMP_INTENSET_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
yihui	9:05f0b5a3a70a	5709	#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /!< Bit mask of DATARDY field. /
yihui	9:05f0b5a3a70a	5710	#define TEMP_INTENSET_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5711	#define TEMP_INTENSET_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5712	#define TEMP_INTENSET_DATARDY_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	5713
yihui	9:05f0b5a3a70a	5714	/* Register: TEMP_INTENCLR */
yihui	9:05f0b5a3a70a	5715	/* Description: Interrupt enable clear register. */
yihui	9:05f0b5a3a70a	5716
yihui	9:05f0b5a3a70a	5717	/* Bit 0 : Disable interrupt on DATARDY event. */
yihui	9:05f0b5a3a70a	5718	#define TEMP_INTENCLR_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
yihui	9:05f0b5a3a70a	5719	#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /!< Bit mask of DATARDY field. /
yihui	9:05f0b5a3a70a	5720	#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5721	#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5722	#define TEMP_INTENCLR_DATARDY_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	5723
yihui	9:05f0b5a3a70a	5724	/* Register: TEMP_POWER */
yihui	9:05f0b5a3a70a	5725	/* Description: Peripheral power control. */
yihui	9:05f0b5a3a70a	5726
yihui	9:05f0b5a3a70a	5727	/* Bit 0 : Peripheral power control. */
yihui	9:05f0b5a3a70a	5728	#define TEMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
yihui	9:05f0b5a3a70a	5729	#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
yihui	9:05f0b5a3a70a	5730	#define TEMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
yihui	9:05f0b5a3a70a	5731	#define TEMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
yihui	9:05f0b5a3a70a	5732
yihui	9:05f0b5a3a70a	5733
yihui	9:05f0b5a3a70a	5734	/* Peripheral: TIMER */
yihui	9:05f0b5a3a70a	5735	/* Description: Timer 0. */
yihui	9:05f0b5a3a70a	5736
yihui	9:05f0b5a3a70a	5737	/* Register: TIMER_SHORTS */
yihui	9:05f0b5a3a70a	5738	/* Description: Shortcuts for Timer. */
yihui	9:05f0b5a3a70a	5739
yihui	9:05f0b5a3a70a	5740	/* Bit 11 : Shortcut between CC[3] event and the STOP task. */
yihui	9:05f0b5a3a70a	5741	#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /!< Position of COMPARE3_STOP field. /
yihui	9:05f0b5a3a70a	5742	#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /!< Bit mask of COMPARE3_STOP field. /
yihui	9:05f0b5a3a70a	5743	#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	5744	#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	5745
yihui	9:05f0b5a3a70a	5746	/* Bit 10 : Shortcut between CC[2] event and the STOP task. */
yihui	9:05f0b5a3a70a	5747	#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /!< Position of COMPARE2_STOP field. /
yihui	9:05f0b5a3a70a	5748	#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /!< Bit mask of COMPARE2_STOP field. /
yihui	9:05f0b5a3a70a	5749	#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	5750	#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	5751
yihui	9:05f0b5a3a70a	5752	/* Bit 9 : Shortcut between CC[1] event and the STOP task. */
yihui	9:05f0b5a3a70a	5753	#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /!< Position of COMPARE1_STOP field. /
yihui	9:05f0b5a3a70a	5754	#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /!< Bit mask of COMPARE1_STOP field. /
yihui	9:05f0b5a3a70a	5755	#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	5756	#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	5757
yihui	9:05f0b5a3a70a	5758	/* Bit 8 : Shortcut between CC[0] event and the STOP task. */
yihui	9:05f0b5a3a70a	5759	#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /!< Position of COMPARE0_STOP field. /
yihui	9:05f0b5a3a70a	5760	#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /!< Bit mask of COMPARE0_STOP field. /
yihui	9:05f0b5a3a70a	5761	#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	5762	#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	5763
yihui	9:05f0b5a3a70a	5764	/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
yihui	9:05f0b5a3a70a	5765	#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /!< Position of COMPARE3_CLEAR field. /
yihui	9:05f0b5a3a70a	5766	#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /!< Bit mask of COMPARE3_CLEAR field. /
yihui	9:05f0b5a3a70a	5767	#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	5768	#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	5769
yihui	9:05f0b5a3a70a	5770	/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
yihui	9:05f0b5a3a70a	5771	#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /!< Position of COMPARE2_CLEAR field. /
yihui	9:05f0b5a3a70a	5772	#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /!< Bit mask of COMPARE2_CLEAR field. /
yihui	9:05f0b5a3a70a	5773	#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	5774	#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	5775
yihui	9:05f0b5a3a70a	5776	/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
yihui	9:05f0b5a3a70a	5777	#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /!< Position of COMPARE1_CLEAR field. /
yihui	9:05f0b5a3a70a	5778	#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /!< Bit mask of COMPARE1_CLEAR field. /
yihui	9:05f0b5a3a70a	5779	#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	5780	#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	5781
yihui	9:05f0b5a3a70a	5782	/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
yihui	9:05f0b5a3a70a	5783	#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /!< Position of COMPARE0_CLEAR field. /
yihui	9:05f0b5a3a70a	5784	#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /!< Bit mask of COMPARE0_CLEAR field. /
yihui	9:05f0b5a3a70a	5785	#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	5786	#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	5787
yihui	9:05f0b5a3a70a	5788	/* Register: TIMER_INTENSET */
yihui	9:05f0b5a3a70a	5789	/* Description: Interrupt enable set register. */
yihui	9:05f0b5a3a70a	5790
yihui	9:05f0b5a3a70a	5791	/* Bit 19 : Enable interrupt on COMPARE[3] */
yihui	9:05f0b5a3a70a	5792	#define TIMER_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
yihui	9:05f0b5a3a70a	5793	#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
yihui	9:05f0b5a3a70a	5794	#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5795	#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5796	#define TIMER_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	5797
yihui	9:05f0b5a3a70a	5798	/* Bit 18 : Enable interrupt on COMPARE[2] */
yihui	9:05f0b5a3a70a	5799	#define TIMER_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
yihui	9:05f0b5a3a70a	5800	#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
yihui	9:05f0b5a3a70a	5801	#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5802	#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5803	#define TIMER_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	5804
yihui	9:05f0b5a3a70a	5805	/* Bit 17 : Enable interrupt on COMPARE[1] */
yihui	9:05f0b5a3a70a	5806	#define TIMER_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
yihui	9:05f0b5a3a70a	5807	#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
yihui	9:05f0b5a3a70a	5808	#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5809	#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5810	#define TIMER_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	5811
yihui	9:05f0b5a3a70a	5812	/* Bit 16 : Enable interrupt on COMPARE[0] */
yihui	9:05f0b5a3a70a	5813	#define TIMER_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
yihui	9:05f0b5a3a70a	5814	#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
yihui	9:05f0b5a3a70a	5815	#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5816	#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5817	#define TIMER_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	5818
yihui	9:05f0b5a3a70a	5819	/* Register: TIMER_INTENCLR */
yihui	9:05f0b5a3a70a	5820	/* Description: Interrupt enable clear register. */
yihui	9:05f0b5a3a70a	5821
yihui	9:05f0b5a3a70a	5822	/* Bit 19 : Disable interrupt on COMPARE[3] */
yihui	9:05f0b5a3a70a	5823	#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
yihui	9:05f0b5a3a70a	5824	#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
yihui	9:05f0b5a3a70a	5825	#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5826	#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5827	#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	5828
yihui	9:05f0b5a3a70a	5829	/* Bit 18 : Disable interrupt on COMPARE[2] */
yihui	9:05f0b5a3a70a	5830	#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
yihui	9:05f0b5a3a70a	5831	#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
yihui	9:05f0b5a3a70a	5832	#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5833	#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5834	#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	5835
yihui	9:05f0b5a3a70a	5836	/* Bit 17 : Disable interrupt on COMPARE[1] */
yihui	9:05f0b5a3a70a	5837	#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
yihui	9:05f0b5a3a70a	5838	#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
yihui	9:05f0b5a3a70a	5839	#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5840	#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5841	#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	5842
yihui	9:05f0b5a3a70a	5843	/* Bit 16 : Disable interrupt on COMPARE[0] */
yihui	9:05f0b5a3a70a	5844	#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
yihui	9:05f0b5a3a70a	5845	#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
yihui	9:05f0b5a3a70a	5846	#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5847	#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5848	#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	5849
yihui	9:05f0b5a3a70a	5850	/* Register: TIMER_MODE */
yihui	9:05f0b5a3a70a	5851	/* Description: Timer Mode selection. */
yihui	9:05f0b5a3a70a	5852
yihui	9:05f0b5a3a70a	5853	/* Bit 0 : Select Normal or Counter mode. */
yihui	9:05f0b5a3a70a	5854	#define TIMER_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
yihui	9:05f0b5a3a70a	5855	#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /!< Bit mask of MODE field. /
yihui	9:05f0b5a3a70a	5856	#define TIMER_MODE_MODE_Timer (0UL) /!< Timer in Normal mode. /
yihui	9:05f0b5a3a70a	5857	#define TIMER_MODE_MODE_Counter (1UL) /!< Timer in Counter mode. /
yihui	9:05f0b5a3a70a	5858
yihui	9:05f0b5a3a70a	5859	/* Register: TIMER_BITMODE */
yihui	9:05f0b5a3a70a	5860	/* Description: Sets timer behaviour. */
yihui	9:05f0b5a3a70a	5861
yihui	9:05f0b5a3a70a	5862	/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
yihui	9:05f0b5a3a70a	5863	#define TIMER_BITMODE_BITMODE_Pos (0UL) /!< Position of BITMODE field. /
yihui	9:05f0b5a3a70a	5864	#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /!< Bit mask of BITMODE field. /
yihui	9:05f0b5a3a70a	5865	#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /!< 16-bit timer behaviour. /
yihui	9:05f0b5a3a70a	5866	#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /!< 8-bit timer behaviour. /
yihui	9:05f0b5a3a70a	5867	#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /!< 24-bit timer behaviour. /
yihui	9:05f0b5a3a70a	5868	#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /!< 32-bit timer behaviour. /
yihui	9:05f0b5a3a70a	5869
yihui	9:05f0b5a3a70a	5870	/* Register: TIMER_PRESCALER */
yihui	9:05f0b5a3a70a	5871	/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
yihui	9:05f0b5a3a70a	5872
yihui	9:05f0b5a3a70a	5873	/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
yihui	9:05f0b5a3a70a	5874	#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
yihui	9:05f0b5a3a70a	5875	#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
yihui	9:05f0b5a3a70a	5876
yihui	9:05f0b5a3a70a	5877	/* Register: TIMER_POWER */
yihui	9:05f0b5a3a70a	5878	/* Description: Peripheral power control. */
yihui	9:05f0b5a3a70a	5879
yihui	9:05f0b5a3a70a	5880	/* Bit 0 : Peripheral power control. */
yihui	9:05f0b5a3a70a	5881	#define TIMER_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
yihui	9:05f0b5a3a70a	5882	#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /!< Bit mask of POWER field. /
yihui	9:05f0b5a3a70a	5883	#define TIMER_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
yihui	9:05f0b5a3a70a	5884	#define TIMER_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
yihui	9:05f0b5a3a70a	5885
yihui	9:05f0b5a3a70a	5886
yihui	9:05f0b5a3a70a	5887	/* Peripheral: TWI */
yihui	9:05f0b5a3a70a	5888	/* Description: Two-wire interface master 0. */
yihui	9:05f0b5a3a70a	5889
yihui	9:05f0b5a3a70a	5890	/* Register: TWI_SHORTS */
yihui	9:05f0b5a3a70a	5891	/* Description: Shortcuts for TWI. */
yihui	9:05f0b5a3a70a	5892
yihui	9:05f0b5a3a70a	5893	/* Bit 1 : Shortcut between BB event and the STOP task. */
yihui	9:05f0b5a3a70a	5894	#define TWI_SHORTS_BB_STOP_Pos (1UL) /!< Position of BB_STOP field. /
yihui	9:05f0b5a3a70a	5895	#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /!< Bit mask of BB_STOP field. /
yihui	9:05f0b5a3a70a	5896	#define TWI_SHORTS_BB_STOP_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	5897	#define TWI_SHORTS_BB_STOP_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	5898
yihui	9:05f0b5a3a70a	5899	/* Bit 0 : Shortcut between BB event and the SUSPEND task. */
yihui	9:05f0b5a3a70a	5900	#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /!< Position of BB_SUSPEND field. /
yihui	9:05f0b5a3a70a	5901	#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /!< Bit mask of BB_SUSPEND field. /
yihui	9:05f0b5a3a70a	5902	#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	5903	#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	5904
yihui	9:05f0b5a3a70a	5905	/* Register: TWI_INTENSET */
yihui	9:05f0b5a3a70a	5906	/* Description: Interrupt enable set register. */
yihui	9:05f0b5a3a70a	5907
yihui	9:05f0b5a3a70a	5908	/* Bit 14 : Enable interrupt on BB event. */
yihui	9:05f0b5a3a70a	5909	#define TWI_INTENSET_BB_Pos (14UL) /!< Position of BB field. /
yihui	9:05f0b5a3a70a	5910	#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /!< Bit mask of BB field. /
yihui	9:05f0b5a3a70a	5911	#define TWI_INTENSET_BB_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5912	#define TWI_INTENSET_BB_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5913	#define TWI_INTENSET_BB_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	5914
yihui	9:05f0b5a3a70a	5915	/* Bit 9 : Enable interrupt on ERROR event. */
yihui	9:05f0b5a3a70a	5916	#define TWI_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
yihui	9:05f0b5a3a70a	5917	#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
yihui	9:05f0b5a3a70a	5918	#define TWI_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5919	#define TWI_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5920	#define TWI_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	5921
yihui	9:05f0b5a3a70a	5922	/* Bit 7 : Enable interrupt on TXDSENT event. */
yihui	9:05f0b5a3a70a	5923	#define TWI_INTENSET_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
yihui	9:05f0b5a3a70a	5924	#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
yihui	9:05f0b5a3a70a	5925	#define TWI_INTENSET_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5926	#define TWI_INTENSET_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5927	#define TWI_INTENSET_TXDSENT_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	5928
yihui	9:05f0b5a3a70a	5929	/* Bit 2 : Enable interrupt on READY event. */
yihui	9:05f0b5a3a70a	5930	#define TWI_INTENSET_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
yihui	9:05f0b5a3a70a	5931	#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
yihui	9:05f0b5a3a70a	5932	#define TWI_INTENSET_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5933	#define TWI_INTENSET_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5934	#define TWI_INTENSET_RXDREADY_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	5935
yihui	9:05f0b5a3a70a	5936	/* Bit 1 : Enable interrupt on STOPPED event. */
yihui	9:05f0b5a3a70a	5937	#define TWI_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
yihui	9:05f0b5a3a70a	5938	#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
yihui	9:05f0b5a3a70a	5939	#define TWI_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5940	#define TWI_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5941	#define TWI_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	5942
yihui	9:05f0b5a3a70a	5943	/* Register: TWI_INTENCLR */
yihui	9:05f0b5a3a70a	5944	/* Description: Interrupt enable clear register. */
yihui	9:05f0b5a3a70a	5945
yihui	9:05f0b5a3a70a	5946	/* Bit 14 : Disable interrupt on BB event. */
yihui	9:05f0b5a3a70a	5947	#define TWI_INTENCLR_BB_Pos (14UL) /!< Position of BB field. /
yihui	9:05f0b5a3a70a	5948	#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /!< Bit mask of BB field. /
yihui	9:05f0b5a3a70a	5949	#define TWI_INTENCLR_BB_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5950	#define TWI_INTENCLR_BB_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5951	#define TWI_INTENCLR_BB_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	5952
yihui	9:05f0b5a3a70a	5953	/* Bit 9 : Disable interrupt on ERROR event. */
yihui	9:05f0b5a3a70a	5954	#define TWI_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
yihui	9:05f0b5a3a70a	5955	#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
yihui	9:05f0b5a3a70a	5956	#define TWI_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5957	#define TWI_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5958	#define TWI_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	5959
yihui	9:05f0b5a3a70a	5960	/* Bit 7 : Disable interrupt on TXDSENT event. */
yihui	9:05f0b5a3a70a	5961	#define TWI_INTENCLR_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
yihui	9:05f0b5a3a70a	5962	#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
yihui	9:05f0b5a3a70a	5963	#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5964	#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5965	#define TWI_INTENCLR_TXDSENT_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	5966
yihui	9:05f0b5a3a70a	5967	/* Bit 2 : Disable interrupt on RXDREADY event. */
yihui	9:05f0b5a3a70a	5968	#define TWI_INTENCLR_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
yihui	9:05f0b5a3a70a	5969	#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
yihui	9:05f0b5a3a70a	5970	#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5971	#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5972	#define TWI_INTENCLR_RXDREADY_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	5973
yihui	9:05f0b5a3a70a	5974	/* Bit 1 : Disable interrupt on STOPPED event. */
yihui	9:05f0b5a3a70a	5975	#define TWI_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
yihui	9:05f0b5a3a70a	5976	#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
yihui	9:05f0b5a3a70a	5977	#define TWI_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	5978	#define TWI_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	5979	#define TWI_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	5980
yihui	9:05f0b5a3a70a	5981	/* Register: TWI_ERRORSRC */
yihui	9:05f0b5a3a70a	5982	/* Description: Two-wire error source. Write error field to 1 to clear error. */
yihui	9:05f0b5a3a70a	5983
yihui	9:05f0b5a3a70a	5984	/* Bit 2 : NACK received after sending a data byte. */
yihui	9:05f0b5a3a70a	5985	#define TWI_ERRORSRC_DNACK_Pos (2UL) /!< Position of DNACK field. /
yihui	9:05f0b5a3a70a	5986	#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /!< Bit mask of DNACK field. /
yihui	9:05f0b5a3a70a	5987	#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /!< Error not present. /
yihui	9:05f0b5a3a70a	5988	#define TWI_ERRORSRC_DNACK_Present (1UL) /!< Error present. /
yihui	9:05f0b5a3a70a	5989	#define TWI_ERRORSRC_DNACK_Clear (1UL) /!< Clear error on write. /
yihui	9:05f0b5a3a70a	5990
yihui	9:05f0b5a3a70a	5991	/* Bit 1 : NACK received after sending the address. */
yihui	9:05f0b5a3a70a	5992	#define TWI_ERRORSRC_ANACK_Pos (1UL) /!< Position of ANACK field. /
yihui	9:05f0b5a3a70a	5993	#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /!< Bit mask of ANACK field. /
yihui	9:05f0b5a3a70a	5994	#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /!< Error not present. /
yihui	9:05f0b5a3a70a	5995	#define TWI_ERRORSRC_ANACK_Present (1UL) /!< Error present. /
yihui	9:05f0b5a3a70a	5996	#define TWI_ERRORSRC_ANACK_Clear (1UL) /!< Clear error on write. /
yihui	9:05f0b5a3a70a	5997
yihui	9:05f0b5a3a70a	5998	/* Register: TWI_ENABLE */
yihui	9:05f0b5a3a70a	5999	/* Description: Enable two-wire master. */
yihui	9:05f0b5a3a70a	6000
yihui	9:05f0b5a3a70a	6001	/* Bits 2..0 : Enable or disable W2M */
yihui	9:05f0b5a3a70a	6002	#define TWI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
yihui	9:05f0b5a3a70a	6003	#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
yihui	9:05f0b5a3a70a	6004	#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled. /
yihui	9:05f0b5a3a70a	6005	#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /!< Enabled. /
yihui	9:05f0b5a3a70a	6006
yihui	9:05f0b5a3a70a	6007	/* Register: TWI_RXD */
yihui	9:05f0b5a3a70a	6008	/* Description: RX data register. */
yihui	9:05f0b5a3a70a	6009
yihui	9:05f0b5a3a70a	6010	/* Bits 7..0 : RX data from last transfer. */
yihui	9:05f0b5a3a70a	6011	#define TWI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
yihui	9:05f0b5a3a70a	6012	#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
yihui	9:05f0b5a3a70a	6013
yihui	9:05f0b5a3a70a	6014	/* Register: TWI_TXD */
yihui	9:05f0b5a3a70a	6015	/* Description: TX data register. */
yihui	9:05f0b5a3a70a	6016
yihui	9:05f0b5a3a70a	6017	/* Bits 7..0 : TX data for next transfer. */
yihui	9:05f0b5a3a70a	6018	#define TWI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
yihui	9:05f0b5a3a70a	6019	#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
yihui	9:05f0b5a3a70a	6020
yihui	9:05f0b5a3a70a	6021	/* Register: TWI_FREQUENCY */
yihui	9:05f0b5a3a70a	6022	/* Description: Two-wire frequency. */
yihui	9:05f0b5a3a70a	6023
yihui	9:05f0b5a3a70a	6024	/* Bits 31..0 : Two-wire master clock frequency. */
yihui	9:05f0b5a3a70a	6025	#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
yihui	9:05f0b5a3a70a	6026	#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
yihui	9:05f0b5a3a70a	6027	#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /!< 100 kbps. /
yihui	9:05f0b5a3a70a	6028	#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
yihui	9:05f0b5a3a70a	6029	#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /!< 400 kbps. /
yihui	9:05f0b5a3a70a	6030
yihui	9:05f0b5a3a70a	6031	/* Register: TWI_ADDRESS */
yihui	9:05f0b5a3a70a	6032	/* Description: Address used in the two-wire transfer. */
yihui	9:05f0b5a3a70a	6033
yihui	9:05f0b5a3a70a	6034	/* Bits 6..0 : Two-wire address. */
yihui	9:05f0b5a3a70a	6035	#define TWI_ADDRESS_ADDRESS_Pos (0UL) /!< Position of ADDRESS field. /
yihui	9:05f0b5a3a70a	6036	#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
yihui	9:05f0b5a3a70a	6037
yihui	9:05f0b5a3a70a	6038	/* Register: TWI_POWER */
yihui	9:05f0b5a3a70a	6039	/* Description: Peripheral power control. */
yihui	9:05f0b5a3a70a	6040
yihui	9:05f0b5a3a70a	6041	/* Bit 0 : Peripheral power control. */
yihui	9:05f0b5a3a70a	6042	#define TWI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
yihui	9:05f0b5a3a70a	6043	#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
yihui	9:05f0b5a3a70a	6044	#define TWI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
yihui	9:05f0b5a3a70a	6045	#define TWI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
yihui	9:05f0b5a3a70a	6046
yihui	9:05f0b5a3a70a	6047
yihui	9:05f0b5a3a70a	6048	/* Peripheral: UART */
yihui	9:05f0b5a3a70a	6049	/* Description: Universal Asynchronous Receiver/Transmitter. */
yihui	9:05f0b5a3a70a	6050
yihui	9:05f0b5a3a70a	6051	/* Register: UART_SHORTS */
yihui	9:05f0b5a3a70a	6052	/* Description: Shortcuts for TWI. */
yihui	9:05f0b5a3a70a	6053
yihui	9:05f0b5a3a70a	6054	/* Bit 4 : Shortcut between NCTS event and the STOPRX task. */
yihui	9:05f0b5a3a70a	6055	#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /!< Position of NCTS_STOPRX field. /
yihui	9:05f0b5a3a70a	6056	#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /!< Bit mask of NCTS_STOPRX field. /
yihui	9:05f0b5a3a70a	6057	#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	6058	#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	6059
yihui	9:05f0b5a3a70a	6060	/* Bit 3 : Shortcut between CTS event and the STARTRX task. */
yihui	9:05f0b5a3a70a	6061	#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /!< Position of CTS_STARTRX field. /
yihui	9:05f0b5a3a70a	6062	#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /!< Bit mask of CTS_STARTRX field. /
yihui	9:05f0b5a3a70a	6063	#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /!< Shortcut disabled. /
yihui	9:05f0b5a3a70a	6064	#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /!< Shortcut enabled. /
yihui	9:05f0b5a3a70a	6065
yihui	9:05f0b5a3a70a	6066	/* Register: UART_INTENSET */
yihui	9:05f0b5a3a70a	6067	/* Description: Interrupt enable set register. */
yihui	9:05f0b5a3a70a	6068
yihui	9:05f0b5a3a70a	6069	/* Bit 17 : Enable interrupt on RXTO event. */
yihui	9:05f0b5a3a70a	6070	#define UART_INTENSET_RXTO_Pos (17UL) /!< Position of RXTO field. /
yihui	9:05f0b5a3a70a	6071	#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /!< Bit mask of RXTO field. /
yihui	9:05f0b5a3a70a	6072	#define UART_INTENSET_RXTO_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	6073	#define UART_INTENSET_RXTO_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	6074	#define UART_INTENSET_RXTO_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	6075
yihui	9:05f0b5a3a70a	6076	/* Bit 9 : Enable interrupt on ERROR event. */
yihui	9:05f0b5a3a70a	6077	#define UART_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
yihui	9:05f0b5a3a70a	6078	#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
yihui	9:05f0b5a3a70a	6079	#define UART_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	6080	#define UART_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	6081	#define UART_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	6082
yihui	9:05f0b5a3a70a	6083	/* Bit 7 : Enable interrupt on TXRDY event. */
yihui	9:05f0b5a3a70a	6084	#define UART_INTENSET_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
yihui	9:05f0b5a3a70a	6085	#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
yihui	9:05f0b5a3a70a	6086	#define UART_INTENSET_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	6087	#define UART_INTENSET_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	6088	#define UART_INTENSET_TXDRDY_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	6089
yihui	9:05f0b5a3a70a	6090	/* Bit 2 : Enable interrupt on RXRDY event. */
yihui	9:05f0b5a3a70a	6091	#define UART_INTENSET_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
yihui	9:05f0b5a3a70a	6092	#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
yihui	9:05f0b5a3a70a	6093	#define UART_INTENSET_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	6094	#define UART_INTENSET_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	6095	#define UART_INTENSET_RXDRDY_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	6096
yihui	9:05f0b5a3a70a	6097	/* Bit 1 : Enable interrupt on NCTS event. */
yihui	9:05f0b5a3a70a	6098	#define UART_INTENSET_NCTS_Pos (1UL) /!< Position of NCTS field. /
yihui	9:05f0b5a3a70a	6099	#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /!< Bit mask of NCTS field. /
yihui	9:05f0b5a3a70a	6100	#define UART_INTENSET_NCTS_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	6101	#define UART_INTENSET_NCTS_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	6102	#define UART_INTENSET_NCTS_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	6103
yihui	9:05f0b5a3a70a	6104	/* Bit 0 : Enable interrupt on CTS event. */
yihui	9:05f0b5a3a70a	6105	#define UART_INTENSET_CTS_Pos (0UL) /!< Position of CTS field. /
yihui	9:05f0b5a3a70a	6106	#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /!< Bit mask of CTS field. /
yihui	9:05f0b5a3a70a	6107	#define UART_INTENSET_CTS_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	6108	#define UART_INTENSET_CTS_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	6109	#define UART_INTENSET_CTS_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	6110
yihui	9:05f0b5a3a70a	6111	/* Register: UART_INTENCLR */
yihui	9:05f0b5a3a70a	6112	/* Description: Interrupt enable clear register. */
yihui	9:05f0b5a3a70a	6113
yihui	9:05f0b5a3a70a	6114	/* Bit 17 : Disable interrupt on RXTO event. */
yihui	9:05f0b5a3a70a	6115	#define UART_INTENCLR_RXTO_Pos (17UL) /!< Position of RXTO field. /
yihui	9:05f0b5a3a70a	6116	#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /!< Bit mask of RXTO field. /
yihui	9:05f0b5a3a70a	6117	#define UART_INTENCLR_RXTO_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	6118	#define UART_INTENCLR_RXTO_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	6119	#define UART_INTENCLR_RXTO_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	6120
yihui	9:05f0b5a3a70a	6121	/* Bit 9 : Disable interrupt on ERROR event. */
yihui	9:05f0b5a3a70a	6122	#define UART_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
yihui	9:05f0b5a3a70a	6123	#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
yihui	9:05f0b5a3a70a	6124	#define UART_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	6125	#define UART_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	6126	#define UART_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	6127
yihui	9:05f0b5a3a70a	6128	/* Bit 7 : Disable interrupt on TXRDY event. */
yihui	9:05f0b5a3a70a	6129	#define UART_INTENCLR_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
yihui	9:05f0b5a3a70a	6130	#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
yihui	9:05f0b5a3a70a	6131	#define UART_INTENCLR_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	6132	#define UART_INTENCLR_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	6133	#define UART_INTENCLR_TXDRDY_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	6134
yihui	9:05f0b5a3a70a	6135	/* Bit 2 : Disable interrupt on RXRDY event. */
yihui	9:05f0b5a3a70a	6136	#define UART_INTENCLR_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
yihui	9:05f0b5a3a70a	6137	#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
yihui	9:05f0b5a3a70a	6138	#define UART_INTENCLR_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	6139	#define UART_INTENCLR_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	6140	#define UART_INTENCLR_RXDRDY_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	6141
yihui	9:05f0b5a3a70a	6142	/* Bit 1 : Disable interrupt on NCTS event. */
yihui	9:05f0b5a3a70a	6143	#define UART_INTENCLR_NCTS_Pos (1UL) /!< Position of NCTS field. /
yihui	9:05f0b5a3a70a	6144	#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /!< Bit mask of NCTS field. /
yihui	9:05f0b5a3a70a	6145	#define UART_INTENCLR_NCTS_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	6146	#define UART_INTENCLR_NCTS_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	6147	#define UART_INTENCLR_NCTS_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	6148
yihui	9:05f0b5a3a70a	6149	/* Bit 0 : Disable interrupt on CTS event. */
yihui	9:05f0b5a3a70a	6150	#define UART_INTENCLR_CTS_Pos (0UL) /!< Position of CTS field. /
yihui	9:05f0b5a3a70a	6151	#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /!< Bit mask of CTS field. /
yihui	9:05f0b5a3a70a	6152	#define UART_INTENCLR_CTS_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	6153	#define UART_INTENCLR_CTS_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	6154	#define UART_INTENCLR_CTS_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	6155
yihui	9:05f0b5a3a70a	6156	/* Register: UART_ERRORSRC */
yihui	9:05f0b5a3a70a	6157	/* Description: Error source. Write error field to 1 to clear error. */
yihui	9:05f0b5a3a70a	6158
yihui	9:05f0b5a3a70a	6159	/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
yihui	9:05f0b5a3a70a	6160	#define UART_ERRORSRC_BREAK_Pos (3UL) /!< Position of BREAK field. /
yihui	9:05f0b5a3a70a	6161	#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /!< Bit mask of BREAK field. /
yihui	9:05f0b5a3a70a	6162	#define UART_ERRORSRC_BREAK_NotPresent (0UL) /!< Error not present. /
yihui	9:05f0b5a3a70a	6163	#define UART_ERRORSRC_BREAK_Present (1UL) /!< Error present. /
yihui	9:05f0b5a3a70a	6164	#define UART_ERRORSRC_BREAK_Clear (1UL) /!< Clear error on write. /
yihui	9:05f0b5a3a70a	6165
yihui	9:05f0b5a3a70a	6166	/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
yihui	9:05f0b5a3a70a	6167	#define UART_ERRORSRC_FRAMING_Pos (2UL) /!< Position of FRAMING field. /
yihui	9:05f0b5a3a70a	6168	#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /!< Bit mask of FRAMING field. /
yihui	9:05f0b5a3a70a	6169	#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /!< Error not present. /
yihui	9:05f0b5a3a70a	6170	#define UART_ERRORSRC_FRAMING_Present (1UL) /!< Error present. /
yihui	9:05f0b5a3a70a	6171	#define UART_ERRORSRC_FRAMING_Clear (1UL) /!< Clear error on write. /
yihui	9:05f0b5a3a70a	6172
yihui	9:05f0b5a3a70a	6173	/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
yihui	9:05f0b5a3a70a	6174	#define UART_ERRORSRC_PARITY_Pos (1UL) /!< Position of PARITY field. /
yihui	9:05f0b5a3a70a	6175	#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /!< Bit mask of PARITY field. /
yihui	9:05f0b5a3a70a	6176	#define UART_ERRORSRC_PARITY_NotPresent (0UL) /!< Error not present. /
yihui	9:05f0b5a3a70a	6177	#define UART_ERRORSRC_PARITY_Present (1UL) /!< Error present. /
yihui	9:05f0b5a3a70a	6178	#define UART_ERRORSRC_PARITY_Clear (1UL) /!< Clear error on write. /
yihui	9:05f0b5a3a70a	6179
yihui	9:05f0b5a3a70a	6180	/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
yihui	9:05f0b5a3a70a	6181	#define UART_ERRORSRC_OVERRUN_Pos (0UL) /!< Position of OVERRUN field. /
yihui	9:05f0b5a3a70a	6182	#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /!< Bit mask of OVERRUN field. /
yihui	9:05f0b5a3a70a	6183	#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /!< Error not present. /
yihui	9:05f0b5a3a70a	6184	#define UART_ERRORSRC_OVERRUN_Present (1UL) /!< Error present. /
yihui	9:05f0b5a3a70a	6185	#define UART_ERRORSRC_OVERRUN_Clear (1UL) /!< Clear error on write. /
yihui	9:05f0b5a3a70a	6186
yihui	9:05f0b5a3a70a	6187	/* Register: UART_ENABLE */
yihui	9:05f0b5a3a70a	6188	/* Description: Enable UART and acquire IOs. */
yihui	9:05f0b5a3a70a	6189
yihui	9:05f0b5a3a70a	6190	/* Bits 2..0 : Enable or disable UART and acquire IOs. */
yihui	9:05f0b5a3a70a	6191	#define UART_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
yihui	9:05f0b5a3a70a	6192	#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
yihui	9:05f0b5a3a70a	6193	#define UART_ENABLE_ENABLE_Disabled (0x00UL) /!< UART disabled. /
yihui	9:05f0b5a3a70a	6194	#define UART_ENABLE_ENABLE_Enabled (0x04UL) /!< UART enabled. /
yihui	9:05f0b5a3a70a	6195
yihui	9:05f0b5a3a70a	6196	/* Register: UART_RXD */
yihui	9:05f0b5a3a70a	6197	/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consummed. If read when no character available, the UART will stop working. */
yihui	9:05f0b5a3a70a	6198
yihui	9:05f0b5a3a70a	6199	/* Bits 7..0 : RX data from previous transfer. Double buffered. */
yihui	9:05f0b5a3a70a	6200	#define UART_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
yihui	9:05f0b5a3a70a	6201	#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /!< Bit mask of RXD field. /
yihui	9:05f0b5a3a70a	6202
yihui	9:05f0b5a3a70a	6203	/* Register: UART_TXD */
yihui	9:05f0b5a3a70a	6204	/* Description: TXD register. */
yihui	9:05f0b5a3a70a	6205
yihui	9:05f0b5a3a70a	6206	/* Bits 7..0 : TX data for transfer. */
yihui	9:05f0b5a3a70a	6207	#define UART_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
yihui	9:05f0b5a3a70a	6208	#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /!< Bit mask of TXD field. /
yihui	9:05f0b5a3a70a	6209
yihui	9:05f0b5a3a70a	6210	/* Register: UART_BAUDRATE */
yihui	9:05f0b5a3a70a	6211	/* Description: UART Baudrate. */
yihui	9:05f0b5a3a70a	6212
yihui	9:05f0b5a3a70a	6213	/* Bits 31..0 : UART baudrate. */
yihui	9:05f0b5a3a70a	6214	#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /!< Position of BAUDRATE field. /
yihui	9:05f0b5a3a70a	6215	#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /!< Bit mask of BAUDRATE field. /
yihui	9:05f0b5a3a70a	6216	#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /!< 1200 baud. /
yihui	9:05f0b5a3a70a	6217	#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /!< 2400 baud. /
yihui	9:05f0b5a3a70a	6218	#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /!< 4800 baud. /
yihui	9:05f0b5a3a70a	6219	#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /!< 9600 baud. /
yihui	9:05f0b5a3a70a	6220	#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /!< 14400 baud. /
yihui	9:05f0b5a3a70a	6221	#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /!< 19200 baud. /
yihui	9:05f0b5a3a70a	6222	#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /!< 28800 baud. /
yihui	9:05f0b5a3a70a	6223	#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /!< 38400 baud. /
yihui	9:05f0b5a3a70a	6224	#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /!< 57600 baud. /
yihui	9:05f0b5a3a70a	6225	#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /!< 76800 baud. /
yihui	9:05f0b5a3a70a	6226	#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /!< 115200 baud. /
yihui	9:05f0b5a3a70a	6227	#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /!< 230400 baud. /
yihui	9:05f0b5a3a70a	6228	#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /!< 250000 baud. /
yihui	9:05f0b5a3a70a	6229	#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /!< 460800 baud. /
yihui	9:05f0b5a3a70a	6230	#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBEDFA4UL) /!< 921600 baud. /
yihui	9:05f0b5a3a70a	6231	#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /!< 1M baud. /
yihui	9:05f0b5a3a70a	6232
yihui	9:05f0b5a3a70a	6233	/* Register: UART_CONFIG */
yihui	9:05f0b5a3a70a	6234	/* Description: Configuration of parity and hardware flow control register. */
yihui	9:05f0b5a3a70a	6235
yihui	9:05f0b5a3a70a	6236	/* Bits 3..1 : Include parity bit. */
yihui	9:05f0b5a3a70a	6237	#define UART_CONFIG_PARITY_Pos (1UL) /!< Position of PARITY field. /
yihui	9:05f0b5a3a70a	6238	#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /!< Bit mask of PARITY field. /
yihui	9:05f0b5a3a70a	6239	#define UART_CONFIG_PARITY_Excluded (0UL) /!< Parity bit excluded. /
yihui	9:05f0b5a3a70a	6240	#define UART_CONFIG_PARITY_Included (7UL) /!< Parity bit included. /
yihui	9:05f0b5a3a70a	6241
yihui	9:05f0b5a3a70a	6242	/* Bit 0 : Hardware flow control. */
yihui	9:05f0b5a3a70a	6243	#define UART_CONFIG_HWFC_Pos (0UL) /!< Position of HWFC field. /
yihui	9:05f0b5a3a70a	6244	#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /!< Bit mask of HWFC field. /
yihui	9:05f0b5a3a70a	6245	#define UART_CONFIG_HWFC_Disabled (0UL) /!< Hardware flow control disabled. /
yihui	9:05f0b5a3a70a	6246	#define UART_CONFIG_HWFC_Enabled (1UL) /!< Hardware flow control enabled. /
yihui	9:05f0b5a3a70a	6247
yihui	9:05f0b5a3a70a	6248	/* Register: UART_POWER */
yihui	9:05f0b5a3a70a	6249	/* Description: Peripheral power control. */
yihui	9:05f0b5a3a70a	6250
yihui	9:05f0b5a3a70a	6251	/* Bit 0 : Peripheral power control. */
yihui	9:05f0b5a3a70a	6252	#define UART_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
yihui	9:05f0b5a3a70a	6253	#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /!< Bit mask of POWER field. /
yihui	9:05f0b5a3a70a	6254	#define UART_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
yihui	9:05f0b5a3a70a	6255	#define UART_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
yihui	9:05f0b5a3a70a	6256
yihui	9:05f0b5a3a70a	6257
yihui	9:05f0b5a3a70a	6258	/* Peripheral: UICR */
yihui	9:05f0b5a3a70a	6259	/* Description: User Information Configuration. */
yihui	9:05f0b5a3a70a	6260
yihui	9:05f0b5a3a70a	6261	/* Register: UICR_RBPCONF */
yihui	9:05f0b5a3a70a	6262	/* Description: Readback protection configuration. */
yihui	9:05f0b5a3a70a	6263
yihui	9:05f0b5a3a70a	6264	/* Bits 15..8 : Readback protect all code in the device. */
yihui	9:05f0b5a3a70a	6265	#define UICR_RBPCONF_PALL_Pos (8UL) /!< Position of PALL field. /
yihui	9:05f0b5a3a70a	6266	#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /!< Bit mask of PALL field. /
yihui	9:05f0b5a3a70a	6267	#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /!< Disabled. /
yihui	9:05f0b5a3a70a	6268	#define UICR_RBPCONF_PALL_Enabled (0x00UL) /!< Enabled. /
yihui	9:05f0b5a3a70a	6269
yihui	9:05f0b5a3a70a	6270	/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
yihui	9:05f0b5a3a70a	6271	#define UICR_RBPCONF_PR0_Pos (0UL) /!< Position of PR0 field. /
yihui	9:05f0b5a3a70a	6272	#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /!< Bit mask of PR0 field. /
yihui	9:05f0b5a3a70a	6273	#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /!< Disabled. /
yihui	9:05f0b5a3a70a	6274	#define UICR_RBPCONF_PR0_Enabled (0x00UL) /!< Enabled. /
yihui	9:05f0b5a3a70a	6275
yihui	9:05f0b5a3a70a	6276	/* Register: UICR_XTALFREQ */
yihui	9:05f0b5a3a70a	6277	/* Description: Reset value for CLOCK XTALFREQ register. */
yihui	9:05f0b5a3a70a	6278
yihui	9:05f0b5a3a70a	6279	/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
yihui	9:05f0b5a3a70a	6280	#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
yihui	9:05f0b5a3a70a	6281	#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
yihui	9:05f0b5a3a70a	6282	#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz Xtal is used. /
yihui	9:05f0b5a3a70a	6283	#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz Xtal is used. /
yihui	9:05f0b5a3a70a	6284
yihui	9:05f0b5a3a70a	6285	/* Register: UICR_FWID */
yihui	9:05f0b5a3a70a	6286	/* Description: Firmware ID. */
yihui	9:05f0b5a3a70a	6287
yihui	9:05f0b5a3a70a	6288	/* Bits 15..0 : Identification number for the firmware loaded into the chip. */
yihui	9:05f0b5a3a70a	6289	#define UICR_FWID_FWID_Pos (0UL) /!< Position of FWID field. /
yihui	9:05f0b5a3a70a	6290	#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /!< Bit mask of FWID field. /
yihui	9:05f0b5a3a70a	6291
yihui	9:05f0b5a3a70a	6292
yihui	9:05f0b5a3a70a	6293	/* Peripheral: WDT */
yihui	9:05f0b5a3a70a	6294	/* Description: Watchdog Timer. */
yihui	9:05f0b5a3a70a	6295
yihui	9:05f0b5a3a70a	6296	/* Register: WDT_INTENSET */
yihui	9:05f0b5a3a70a	6297	/* Description: Interrupt enable set register. */
yihui	9:05f0b5a3a70a	6298
yihui	9:05f0b5a3a70a	6299	/* Bit 0 : Enable interrupt on TIMEOUT event. */
yihui	9:05f0b5a3a70a	6300	#define WDT_INTENSET_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
yihui	9:05f0b5a3a70a	6301	#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
yihui	9:05f0b5a3a70a	6302	#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	6303	#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	6304	#define WDT_INTENSET_TIMEOUT_Set (1UL) /!< Enable interrupt on write. /
yihui	9:05f0b5a3a70a	6305
yihui	9:05f0b5a3a70a	6306	/* Register: WDT_INTENCLR */
yihui	9:05f0b5a3a70a	6307	/* Description: Interrupt enable clear register. */
yihui	9:05f0b5a3a70a	6308
yihui	9:05f0b5a3a70a	6309	/* Bit 0 : Disable interrupt on TIMEOUT event. */
yihui	9:05f0b5a3a70a	6310	#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
yihui	9:05f0b5a3a70a	6311	#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
yihui	9:05f0b5a3a70a	6312	#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
yihui	9:05f0b5a3a70a	6313	#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
yihui	9:05f0b5a3a70a	6314	#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /!< Disable interrupt on write. /
yihui	9:05f0b5a3a70a	6315
yihui	9:05f0b5a3a70a	6316	/* Register: WDT_RUNSTATUS */
yihui	9:05f0b5a3a70a	6317	/* Description: Watchdog running status. */
yihui	9:05f0b5a3a70a	6318
yihui	9:05f0b5a3a70a	6319	/* Bit 0 : Watchdog running status. */
yihui	9:05f0b5a3a70a	6320	#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /!< Position of RUNSTATUS field. /
yihui	9:05f0b5a3a70a	6321	#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /!< Bit mask of RUNSTATUS field. /
yihui	9:05f0b5a3a70a	6322	#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /!< Watchdog timer is not running. /
yihui	9:05f0b5a3a70a	6323	#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /!< Watchdog timer is running. /
yihui	9:05f0b5a3a70a	6324
yihui	9:05f0b5a3a70a	6325	/* Register: WDT_REQSTATUS */
yihui	9:05f0b5a3a70a	6326	/* Description: Request status. */
yihui	9:05f0b5a3a70a	6327
yihui	9:05f0b5a3a70a	6328	/* Bit 7 : Request status for RR[7]. */
yihui	9:05f0b5a3a70a	6329	#define WDT_REQSTATUS_RR7_Pos (7UL) /!< Position of RR7 field. /
yihui	9:05f0b5a3a70a	6330	#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /!< Bit mask of RR7 field. /
yihui	9:05f0b5a3a70a	6331	#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /!< RR[7] register is not enabled or has already requested reload. /
yihui	9:05f0b5a3a70a	6332	#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /!< RR[7] register is enabled and has not jet requested. /
yihui	9:05f0b5a3a70a	6333
yihui	9:05f0b5a3a70a	6334	/* Bit 6 : Request status for RR[6]. */
yihui	9:05f0b5a3a70a	6335	#define WDT_REQSTATUS_RR6_Pos (6UL) /!< Position of RR6 field. /
yihui	9:05f0b5a3a70a	6336	#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /!< Bit mask of RR6 field. /
yihui	9:05f0b5a3a70a	6337	#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /!< RR[6] register is not enabled or has already requested reload. /
yihui	9:05f0b5a3a70a	6338	#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /!< RR[6] register is enabled and has not jet requested. /
yihui	9:05f0b5a3a70a	6339
yihui	9:05f0b5a3a70a	6340	/* Bit 5 : Request status for RR[5]. */
yihui	9:05f0b5a3a70a	6341	#define WDT_REQSTATUS_RR5_Pos (5UL) /!< Position of RR5 field. /
yihui	9:05f0b5a3a70a	6342	#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /!< Bit mask of RR5 field. /
yihui	9:05f0b5a3a70a	6343	#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /!< RR[5] register is not enabled or has already requested reload. /
yihui	9:05f0b5a3a70a	6344	#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /!< RR[5] register is enabled and has not jet requested. /
yihui	9:05f0b5a3a70a	6345
yihui	9:05f0b5a3a70a	6346	/* Bit 4 : Request status for RR[4]. */
yihui	9:05f0b5a3a70a	6347	#define WDT_REQSTATUS_RR4_Pos (4UL) /!< Position of RR4 field. /
yihui	9:05f0b5a3a70a	6348	#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /!< Bit mask of RR4 field. /
yihui	9:05f0b5a3a70a	6349	#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /!< RR[4] register is not enabled or has already requested reload. /
yihui	9:05f0b5a3a70a	6350	#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /!< RR[4] register is enabled and has not jet requested. /
yihui	9:05f0b5a3a70a	6351
yihui	9:05f0b5a3a70a	6352	/* Bit 3 : Request status for RR[3]. */
yihui	9:05f0b5a3a70a	6353	#define WDT_REQSTATUS_RR3_Pos (3UL) /!< Position of RR3 field. /
yihui	9:05f0b5a3a70a	6354	#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /!< Bit mask of RR3 field. /
yihui	9:05f0b5a3a70a	6355	#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /!< RR[3] register is not enabled or has already requested reload. /
yihui	9:05f0b5a3a70a	6356	#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /!< RR[3] register is enabled and has not jet requested. /
yihui	9:05f0b5a3a70a	6357
yihui	9:05f0b5a3a70a	6358	/* Bit 2 : Request status for RR[2]. */
yihui	9:05f0b5a3a70a	6359	#define WDT_REQSTATUS_RR2_Pos (2UL) /!< Position of RR2 field. /
yihui	9:05f0b5a3a70a	6360	#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /!< Bit mask of RR2 field. /
yihui	9:05f0b5a3a70a	6361	#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /!< RR[2] register is not enabled or has already requested reload. /
yihui	9:05f0b5a3a70a	6362	#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /!< RR[2] register is enabled and has not jet requested. /
yihui	9:05f0b5a3a70a	6363
yihui	9:05f0b5a3a70a	6364	/* Bit 1 : Request status for RR[1]. */
yihui	9:05f0b5a3a70a	6365	#define WDT_REQSTATUS_RR1_Pos (1UL) /!< Position of RR1 field. /
yihui	9:05f0b5a3a70a	6366	#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /!< Bit mask of RR1 field. /
yihui	9:05f0b5a3a70a	6367	#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /!< RR[1] register is not enabled or has already requested reload. /
yihui	9:05f0b5a3a70a	6368	#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /!< RR[1] register is enabled and has not jet requested. /
yihui	9:05f0b5a3a70a	6369
yihui	9:05f0b5a3a70a	6370	/* Bit 0 : Request status for RR[0]. */
yihui	9:05f0b5a3a70a	6371	#define WDT_REQSTATUS_RR0_Pos (0UL) /!< Position of RR0 field. /
yihui	9:05f0b5a3a70a	6372	#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /!< Bit mask of RR0 field. /
yihui	9:05f0b5a3a70a	6373	#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /!< RR[0] register is not enabled or has already requested reload. /
yihui	9:05f0b5a3a70a	6374	#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /!< RR[0] register is enabled and has not jet requested. /
yihui	9:05f0b5a3a70a	6375
yihui	9:05f0b5a3a70a	6376	/* Register: WDT_RREN */
yihui	9:05f0b5a3a70a	6377	/* Description: Reload request enable. */
yihui	9:05f0b5a3a70a	6378
yihui	9:05f0b5a3a70a	6379	/* Bit 7 : Enable or disable RR[7] register. */
yihui	9:05f0b5a3a70a	6380	#define WDT_RREN_RR7_Pos (7UL) /!< Position of RR7 field. /
yihui	9:05f0b5a3a70a	6381	#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /!< Bit mask of RR7 field. /
yihui	9:05f0b5a3a70a	6382	#define WDT_RREN_RR7_Disabled (0UL) /!< RR[7] register is disabled. /
yihui	9:05f0b5a3a70a	6383	#define WDT_RREN_RR7_Enabled (1UL) /!< RR[7] register is enabled. /
yihui	9:05f0b5a3a70a	6384
yihui	9:05f0b5a3a70a	6385	/* Bit 6 : Enable or disable RR[6] register. */
yihui	9:05f0b5a3a70a	6386	#define WDT_RREN_RR6_Pos (6UL) /!< Position of RR6 field. /
yihui	9:05f0b5a3a70a	6387	#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /!< Bit mask of RR6 field. /
yihui	9:05f0b5a3a70a	6388	#define WDT_RREN_RR6_Disabled (0UL) /!< RR[6] register is disabled. /
yihui	9:05f0b5a3a70a	6389	#define WDT_RREN_RR6_Enabled (1UL) /!< RR[6] register is enabled. /
yihui	9:05f0b5a3a70a	6390
yihui	9:05f0b5a3a70a	6391	/* Bit 5 : Enable or disable RR[5] register. */
yihui	9:05f0b5a3a70a	6392	#define WDT_RREN_RR5_Pos (5UL) /!< Position of RR5 field. /
yihui	9:05f0b5a3a70a	6393	#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /!< Bit mask of RR5 field. /
yihui	9:05f0b5a3a70a	6394	#define WDT_RREN_RR5_Disabled (0UL) /!< RR[5] register is disabled. /
yihui	9:05f0b5a3a70a	6395	#define WDT_RREN_RR5_Enabled (1UL) /!< RR[5] register is enabled. /
yihui	9:05f0b5a3a70a	6396
yihui	9:05f0b5a3a70a	6397	/* Bit 4 : Enable or disable RR[4] register. */
yihui	9:05f0b5a3a70a	6398	#define WDT_RREN_RR4_Pos (4UL) /!< Position of RR4 field. /
yihui	9:05f0b5a3a70a	6399	#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /!< Bit mask of RR4 field. /
yihui	9:05f0b5a3a70a	6400	#define WDT_RREN_RR4_Disabled (0UL) /!< RR[4] register is disabled. /
yihui	9:05f0b5a3a70a	6401	#define WDT_RREN_RR4_Enabled (1UL) /!< RR[4] register is enabled. /
yihui	9:05f0b5a3a70a	6402
yihui	9:05f0b5a3a70a	6403	/* Bit 3 : Enable or disable RR[3] register. */
yihui	9:05f0b5a3a70a	6404	#define WDT_RREN_RR3_Pos (3UL) /!< Position of RR3 field. /
yihui	9:05f0b5a3a70a	6405	#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /!< Bit mask of RR3 field. /
yihui	9:05f0b5a3a70a	6406	#define WDT_RREN_RR3_Disabled (0UL) /!< RR[3] register is disabled. /
yihui	9:05f0b5a3a70a	6407	#define WDT_RREN_RR3_Enabled (1UL) /!< RR[3] register is enabled. /
yihui	9:05f0b5a3a70a	6408
yihui	9:05f0b5a3a70a	6409	/* Bit 2 : Enable or disable RR[2] register. */
yihui	9:05f0b5a3a70a	6410	#define WDT_RREN_RR2_Pos (2UL) /!< Position of RR2 field. /
yihui	9:05f0b5a3a70a	6411	#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /!< Bit mask of RR2 field. /
yihui	9:05f0b5a3a70a	6412	#define WDT_RREN_RR2_Disabled (0UL) /!< RR[2] register is disabled. /
yihui	9:05f0b5a3a70a	6413	#define WDT_RREN_RR2_Enabled (1UL) /!< RR[2] register is enabled. /
yihui	9:05f0b5a3a70a	6414
yihui	9:05f0b5a3a70a	6415	/* Bit 1 : Enable or disable RR[1] register. */
yihui	9:05f0b5a3a70a	6416	#define WDT_RREN_RR1_Pos (1UL) /!< Position of RR1 field. /
yihui	9:05f0b5a3a70a	6417	#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /!< Bit mask of RR1 field. /
yihui	9:05f0b5a3a70a	6418	#define WDT_RREN_RR1_Disabled (0UL) /!< RR[1] register is disabled. /
yihui	9:05f0b5a3a70a	6419	#define WDT_RREN_RR1_Enabled (1UL) /!< RR[1] register is enabled. /
yihui	9:05f0b5a3a70a	6420
yihui	9:05f0b5a3a70a	6421	/* Bit 0 : Enable or disable RR[0] register. */
yihui	9:05f0b5a3a70a	6422	#define WDT_RREN_RR0_Pos (0UL) /!< Position of RR0 field. /
yihui	9:05f0b5a3a70a	6423	#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /!< Bit mask of RR0 field. /
yihui	9:05f0b5a3a70a	6424	#define WDT_RREN_RR0_Disabled (0UL) /!< RR[0] register is disabled. /
yihui	9:05f0b5a3a70a	6425	#define WDT_RREN_RR0_Enabled (1UL) /!< RR[0] register is enabled. /
yihui	9:05f0b5a3a70a	6426
yihui	9:05f0b5a3a70a	6427	/* Register: WDT_CONFIG */
yihui	9:05f0b5a3a70a	6428	/* Description: Configuration register. */
yihui	9:05f0b5a3a70a	6429
yihui	9:05f0b5a3a70a	6430	/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
yihui	9:05f0b5a3a70a	6431	#define WDT_CONFIG_HALT_Pos (3UL) /!< Position of HALT field. /
yihui	9:05f0b5a3a70a	6432	#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /!< Bit mask of HALT field. /
yihui	9:05f0b5a3a70a	6433	#define WDT_CONFIG_HALT_Pause (0UL) /!< Pause watchdog while the CPU is halted by the debugger. /
yihui	9:05f0b5a3a70a	6434	#define WDT_CONFIG_HALT_Run (1UL) /!< Do not pause watchdog while the CPU is halted by the debugger. /
yihui	9:05f0b5a3a70a	6435
yihui	9:05f0b5a3a70a	6436	/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
yihui	9:05f0b5a3a70a	6437	#define WDT_CONFIG_SLEEP_Pos (0UL) /!< Position of SLEEP field. /
yihui	9:05f0b5a3a70a	6438	#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /!< Bit mask of SLEEP field. /
yihui	9:05f0b5a3a70a	6439	#define WDT_CONFIG_SLEEP_Pause (0UL) /!< Pause watchdog while the CPU is asleep. /
yihui	9:05f0b5a3a70a	6440	#define WDT_CONFIG_SLEEP_Run (1UL) /!< Do not pause watchdog while the CPU is asleep. /
yihui	9:05f0b5a3a70a	6441
yihui	9:05f0b5a3a70a	6442	/* Register: WDT_RR */
yihui	9:05f0b5a3a70a	6443	/* Description: Reload requests registers. */
yihui	9:05f0b5a3a70a	6444
yihui	9:05f0b5a3a70a	6445	/* Bits 31..0 : Reload register. */
yihui	9:05f0b5a3a70a	6446	#define WDT_RR_RR_Pos (0UL) /!< Position of RR field. /
yihui	9:05f0b5a3a70a	6447	#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /!< Bit mask of RR field. /
yihui	9:05f0b5a3a70a	6448	#define WDT_RR_RR_Reload (0x6E524635UL) /!< Value to request a reload of the watchdog timer. /
yihui	9:05f0b5a3a70a	6449
yihui	9:05f0b5a3a70a	6450	/* Register: WDT_POWER */
yihui	9:05f0b5a3a70a	6451	/* Description: Peripheral power control. */
yihui	9:05f0b5a3a70a	6452
yihui	9:05f0b5a3a70a	6453	/* Bit 0 : Peripheral power control. */
yihui	9:05f0b5a3a70a	6454	#define WDT_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
yihui	9:05f0b5a3a70a	6455	#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /!< Bit mask of POWER field. /
yihui	9:05f0b5a3a70a	6456	#define WDT_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
yihui	9:05f0b5a3a70a	6457	#define WDT_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
yihui	9:05f0b5a3a70a	6458
yihui	9:05f0b5a3a70a	6459
yihui	9:05f0b5a3a70a	6460	/lint --flb "Leave library region" /
yihui	9:05f0b5a3a70a	6461	#endif

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Type:	Program
Created:	29 Oct 2014
Imports:	4
Forks:	1
Commits:	11
Dependents:	0
Dependencies:	2
Followers:	1

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mbed-src/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51_bitfields.h@10:22480ac31879, 2014-11-27 (annotated)

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