Yihui Xiong / BLE_NODE_TEST

Test code for Grove Node BLE

Dependencies:   BLE_API nRF51822

Fork of BLE_LoopbackUART by Bluetooth Low Energy

mbed-src/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51.h@10:22480ac31879, 2014-11-27 (annotated)

Committer:
yihui
Date:
Thu Nov 27 09:30:36 2014 +0000
Revision:
10:22480ac31879
Parent:
9:05f0b5a3a70a 
change to new revision hardware

Who changed what in which revision?

UserRevisionLine numberNew contents of line
yihui 9:05f0b5a3a70a 1 /* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
yihui 9:05f0b5a3a70a 2 *
yihui 9:05f0b5a3a70a 3 * The information contained herein is property of Nordic Semiconductor ASA.
yihui 9:05f0b5a3a70a 4 * Terms and conditions of usage are described in detail in NORDIC
yihui 9:05f0b5a3a70a 5 * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
yihui 9:05f0b5a3a70a 6 *
yihui 9:05f0b5a3a70a 7 * Licensees are granted free, non-transferable use of the information. NO
yihui 9:05f0b5a3a70a 8 * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
yihui 9:05f0b5a3a70a 9 * the file.
yihui 9:05f0b5a3a70a 10 *
yihui 9:05f0b5a3a70a 11 */
yihui 9:05f0b5a3a70a 12
yihui 9:05f0b5a3a70a 13
yihui 9:05f0b5a3a70a 14
yihui 9:05f0b5a3a70a 15 /** @addtogroup Nordic Semiconductor
yihui 9:05f0b5a3a70a 16 * @{
yihui 9:05f0b5a3a70a 17 */
yihui 9:05f0b5a3a70a 18
yihui 9:05f0b5a3a70a 19 /** @addtogroup nRF51
yihui 9:05f0b5a3a70a 20 * @{
yihui 9:05f0b5a3a70a 21 */
yihui 9:05f0b5a3a70a 22
yihui 9:05f0b5a3a70a 23 #ifndef NRF51_H
yihui 9:05f0b5a3a70a 24 #define NRF51_H
yihui 9:05f0b5a3a70a 25
yihui 9:05f0b5a3a70a 26 #ifdef __cplusplus
yihui 9:05f0b5a3a70a 27 extern "C" {
yihui 9:05f0b5a3a70a 28 #endif
yihui 9:05f0b5a3a70a 29
yihui 9:05f0b5a3a70a 30
yihui 9:05f0b5a3a70a 31 /* ------------------------- Interrupt Number Definition ------------------------ */
yihui 9:05f0b5a3a70a 32
yihui 9:05f0b5a3a70a 33 typedef enum {
yihui 9:05f0b5a3a70a 34 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
yihui 9:05f0b5a3a70a 35 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
yihui 9:05f0b5a3a70a 36 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
yihui 9:05f0b5a3a70a 37 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
yihui 9:05f0b5a3a70a 38 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
yihui 9:05f0b5a3a70a 39 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
yihui 9:05f0b5a3a70a 40 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
yihui 9:05f0b5a3a70a 41 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
yihui 9:05f0b5a3a70a 42 /* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
yihui 9:05f0b5a3a70a 43 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
yihui 9:05f0b5a3a70a 44 RADIO_IRQn = 1, /*!< 1 RADIO */
yihui 9:05f0b5a3a70a 45 UART0_IRQn = 2, /*!< 2 UART0 */
yihui 9:05f0b5a3a70a 46 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
yihui 9:05f0b5a3a70a 47 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
yihui 9:05f0b5a3a70a 48 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
yihui 9:05f0b5a3a70a 49 ADC_IRQn = 7, /*!< 7 ADC */
yihui 9:05f0b5a3a70a 50 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
yihui 9:05f0b5a3a70a 51 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
yihui 9:05f0b5a3a70a 52 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
yihui 9:05f0b5a3a70a 53 RTC0_IRQn = 11, /*!< 11 RTC0 */
yihui 9:05f0b5a3a70a 54 TEMP_IRQn = 12, /*!< 12 TEMP */
yihui 9:05f0b5a3a70a 55 RNG_IRQn = 13, /*!< 13 RNG */
yihui 9:05f0b5a3a70a 56 ECB_IRQn = 14, /*!< 14 ECB */
yihui 9:05f0b5a3a70a 57 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
yihui 9:05f0b5a3a70a 58 WDT_IRQn = 16, /*!< 16 WDT */
yihui 9:05f0b5a3a70a 59 RTC1_IRQn = 17, /*!< 17 RTC1 */
yihui 9:05f0b5a3a70a 60 QDEC_IRQn = 18, /*!< 18 QDEC */
yihui 9:05f0b5a3a70a 61 LPCOMP_COMP_IRQn = 19, /*!< 19 LPCOMP_COMP */
yihui 9:05f0b5a3a70a 62 SWI0_IRQn = 20, /*!< 20 SWI0 */
yihui 9:05f0b5a3a70a 63 SWI1_IRQn = 21, /*!< 21 SWI1 */
yihui 9:05f0b5a3a70a 64 SWI2_IRQn = 22, /*!< 22 SWI2 */
yihui 9:05f0b5a3a70a 65 SWI3_IRQn = 23, /*!< 23 SWI3 */
yihui 9:05f0b5a3a70a 66 SWI4_IRQn = 24, /*!< 24 SWI4 */
yihui 9:05f0b5a3a70a 67 SWI5_IRQn = 25 /*!< 25 SWI5 */
yihui 9:05f0b5a3a70a 68 } IRQn_Type;
yihui 9:05f0b5a3a70a 69
yihui 9:05f0b5a3a70a 70
yihui 9:05f0b5a3a70a 71 /** @addtogroup Configuration_of_CMSIS
yihui 9:05f0b5a3a70a 72 * @{
yihui 9:05f0b5a3a70a 73 */
yihui 9:05f0b5a3a70a 74
yihui 9:05f0b5a3a70a 75
yihui 9:05f0b5a3a70a 76 /* ================================================================================ */
yihui 9:05f0b5a3a70a 77 /* ================ Processor and Core Peripheral Section ================ */
yihui 9:05f0b5a3a70a 78 /* ================================================================================ */
yihui 9:05f0b5a3a70a 79
yihui 9:05f0b5a3a70a 80 /* ----------------Configuration of the cm0 Processor and Core Peripherals---------------- */
yihui 9:05f0b5a3a70a 81 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
yihui 9:05f0b5a3a70a 82 #define __MPU_PRESENT 0 /*!< MPU present or not */
yihui 9:05f0b5a3a70a 83 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
yihui 9:05f0b5a3a70a 84 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
yihui 9:05f0b5a3a70a 85 /** @} */ /* End of group Configuration_of_CMSIS */
yihui 9:05f0b5a3a70a 86
yihui 9:05f0b5a3a70a 87 #include <core_cm0.h> /*!< Cortex-M0 processor and core peripherals */
yihui 9:05f0b5a3a70a 88 #include "system_nrf51822.h" /*!< nRF51 System */
yihui 9:05f0b5a3a70a 89
yihui 9:05f0b5a3a70a 90
yihui 9:05f0b5a3a70a 91 /* ================================================================================ */
yihui 9:05f0b5a3a70a 92 /* ================ Device Specific Peripheral Section ================ */
yihui 9:05f0b5a3a70a 93 /* ================================================================================ */
yihui 9:05f0b5a3a70a 94
yihui 9:05f0b5a3a70a 95
yihui 9:05f0b5a3a70a 96 /** @addtogroup Device_Peripheral_Registers
yihui 9:05f0b5a3a70a 97 * @{
yihui 9:05f0b5a3a70a 98 */
yihui 9:05f0b5a3a70a 99
yihui 9:05f0b5a3a70a 100
yihui 9:05f0b5a3a70a 101 /* ------------------- Start of section using anonymous unions ------------------ */
yihui 9:05f0b5a3a70a 102 #if defined(__CC_ARM)
yihui 9:05f0b5a3a70a 103 #pragma push
yihui 9:05f0b5a3a70a 104 #pragma anon_unions
yihui 9:05f0b5a3a70a 105 #elif defined(__ICCARM__)
yihui 9:05f0b5a3a70a 106 #pragma language=extended
yihui 9:05f0b5a3a70a 107 #elif defined(__GNUC__)
yihui 9:05f0b5a3a70a 108 /* anonymous unions are enabled by default */
yihui 9:05f0b5a3a70a 109 #elif defined(__TMS470__)
yihui 9:05f0b5a3a70a 110 /* anonymous unions are enabled by default */
yihui 9:05f0b5a3a70a 111 #elif defined(__TASKING__)
yihui 9:05f0b5a3a70a 112 #pragma warning 586
yihui 9:05f0b5a3a70a 113 #else
yihui 9:05f0b5a3a70a 114 #warning Not supported compiler type
yihui 9:05f0b5a3a70a 115 #endif
yihui 9:05f0b5a3a70a 116
yihui 9:05f0b5a3a70a 117
yihui 9:05f0b5a3a70a 118 typedef struct {
yihui 9:05f0b5a3a70a 119 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
yihui 9:05f0b5a3a70a 120 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
yihui 9:05f0b5a3a70a 121 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
yihui 9:05f0b5a3a70a 122 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
yihui 9:05f0b5a3a70a 123 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
yihui 9:05f0b5a3a70a 124 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
yihui 9:05f0b5a3a70a 125 } AMLI_RAMPRI_Type;
yihui 9:05f0b5a3a70a 126
yihui 9:05f0b5a3a70a 127 typedef struct {
yihui 9:05f0b5a3a70a 128 __O uint32_t EN; /*!< Enable channel group. */
yihui 9:05f0b5a3a70a 129 __O uint32_t DIS; /*!< Disable channel group. */
yihui 9:05f0b5a3a70a 130 } PPI_TASKS_CHG_Type;
yihui 9:05f0b5a3a70a 131
yihui 9:05f0b5a3a70a 132 typedef struct {
yihui 9:05f0b5a3a70a 133 __IO uint32_t EEP; /*!< Channel event end-point. */
yihui 9:05f0b5a3a70a 134 __IO uint32_t TEP; /*!< Channel task end-point. */
yihui 9:05f0b5a3a70a 135 } PPI_CH_Type;
yihui 9:05f0b5a3a70a 136
yihui 9:05f0b5a3a70a 137
yihui 9:05f0b5a3a70a 138 /* ================================================================================ */
yihui 9:05f0b5a3a70a 139 /* ================ POWER ================ */
yihui 9:05f0b5a3a70a 140 /* ================================================================================ */
yihui 9:05f0b5a3a70a 141
yihui 9:05f0b5a3a70a 142
yihui 9:05f0b5a3a70a 143 /**
yihui 9:05f0b5a3a70a 144 * @brief Power Control. (POWER)
yihui 9:05f0b5a3a70a 145 */
yihui 9:05f0b5a3a70a 146
yihui 9:05f0b5a3a70a 147 typedef struct { /*!< POWER Structure */
yihui 9:05f0b5a3a70a 148 __I uint32_t RESERVED0[30];
yihui 9:05f0b5a3a70a 149 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
yihui 9:05f0b5a3a70a 150 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
yihui 9:05f0b5a3a70a 151 __I uint32_t RESERVED1[34];
yihui 9:05f0b5a3a70a 152 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
yihui 9:05f0b5a3a70a 153 __I uint32_t RESERVED2[126];
yihui 9:05f0b5a3a70a 154 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
yihui 9:05f0b5a3a70a 155 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
yihui 9:05f0b5a3a70a 156 __I uint32_t RESERVED3[61];
yihui 9:05f0b5a3a70a 157 __IO uint32_t RESETREAS; /*!< Reset reason. */
yihui 9:05f0b5a3a70a 158 __I uint32_t RESERVED4[63];
yihui 9:05f0b5a3a70a 159 __O uint32_t SYSTEMOFF; /*!< System off register. */
yihui 9:05f0b5a3a70a 160 __I uint32_t RESERVED5[3];
yihui 9:05f0b5a3a70a 161 __IO uint32_t POFCON; /*!< Power failure configuration. */
yihui 9:05f0b5a3a70a 162 __I uint32_t RESERVED6[2];
yihui 9:05f0b5a3a70a 163 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
yihui 9:05f0b5a3a70a 164 register. */
yihui 9:05f0b5a3a70a 165 __I uint32_t RESERVED7;
yihui 9:05f0b5a3a70a 166 __IO uint32_t RAMON; /*!< Ram on/off. */
yihui 9:05f0b5a3a70a 167 __I uint32_t RESERVED8[7];
yihui 9:05f0b5a3a70a 168 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
yihui 9:05f0b5a3a70a 169 is a retained register. */
yihui 9:05f0b5a3a70a 170 __I uint32_t RESERVED9[12];
yihui 9:05f0b5a3a70a 171 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
yihui 9:05f0b5a3a70a 172 } NRF_POWER_Type;
yihui 9:05f0b5a3a70a 173
yihui 9:05f0b5a3a70a 174
yihui 9:05f0b5a3a70a 175 /* ================================================================================ */
yihui 9:05f0b5a3a70a 176 /* ================ CLOCK ================ */
yihui 9:05f0b5a3a70a 177 /* ================================================================================ */
yihui 9:05f0b5a3a70a 178
yihui 9:05f0b5a3a70a 179
yihui 9:05f0b5a3a70a 180 /**
yihui 9:05f0b5a3a70a 181 * @brief Clock control. (CLOCK)
yihui 9:05f0b5a3a70a 182 */
yihui 9:05f0b5a3a70a 183
yihui 9:05f0b5a3a70a 184 typedef struct { /*!< CLOCK Structure */
yihui 9:05f0b5a3a70a 185 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
yihui 9:05f0b5a3a70a 186 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
yihui 9:05f0b5a3a70a 187 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
yihui 9:05f0b5a3a70a 188 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
yihui 9:05f0b5a3a70a 189 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
yihui 9:05f0b5a3a70a 190 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
yihui 9:05f0b5a3a70a 191 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
yihui 9:05f0b5a3a70a 192 __I uint32_t RESERVED0[57];
yihui 9:05f0b5a3a70a 193 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
yihui 9:05f0b5a3a70a 194 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
yihui 9:05f0b5a3a70a 195 __I uint32_t RESERVED1;
yihui 9:05f0b5a3a70a 196 __IO uint32_t EVENTS_DONE; /*!< Callibration of LFCLK RC oscillator completed. */
yihui 9:05f0b5a3a70a 197 __IO uint32_t EVENTS_CTTO; /*!< Callibration timer timeout. */
yihui 9:05f0b5a3a70a 198 __I uint32_t RESERVED2[124];
yihui 9:05f0b5a3a70a 199 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
yihui 9:05f0b5a3a70a 200 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
yihui 9:05f0b5a3a70a 201 __I uint32_t RESERVED3[64];
yihui 9:05f0b5a3a70a 202 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
yihui 9:05f0b5a3a70a 203 __I uint32_t RESERVED4[2];
yihui 9:05f0b5a3a70a 204 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
yihui 9:05f0b5a3a70a 205 __I uint32_t RESERVED5[63];
yihui 9:05f0b5a3a70a 206 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
yihui 9:05f0b5a3a70a 207 __I uint32_t RESERVED6[7];
yihui 9:05f0b5a3a70a 208 __IO uint32_t CTIV; /*!< Calibration timer interval. */
yihui 9:05f0b5a3a70a 209 __I uint32_t RESERVED7[5];
yihui 9:05f0b5a3a70a 210 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
yihui 9:05f0b5a3a70a 211 } NRF_CLOCK_Type;
yihui 9:05f0b5a3a70a 212
yihui 9:05f0b5a3a70a 213
yihui 9:05f0b5a3a70a 214 /* ================================================================================ */
yihui 9:05f0b5a3a70a 215 /* ================ MPU ================ */
yihui 9:05f0b5a3a70a 216 /* ================================================================================ */
yihui 9:05f0b5a3a70a 217
yihui 9:05f0b5a3a70a 218
yihui 9:05f0b5a3a70a 219 /**
yihui 9:05f0b5a3a70a 220 * @brief Memory Protection Unit. (MPU)
yihui 9:05f0b5a3a70a 221 */
yihui 9:05f0b5a3a70a 222
yihui 9:05f0b5a3a70a 223 typedef struct { /*!< MPU Structure */
yihui 9:05f0b5a3a70a 224 __I uint32_t RESERVED0[330];
yihui 9:05f0b5a3a70a 225 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
yihui 9:05f0b5a3a70a 226 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
yihui 9:05f0b5a3a70a 227 __I uint32_t RESERVED1[52];
yihui 9:05f0b5a3a70a 228 __IO uint32_t PROTENSET0; /*!< Protection bit enable set register for low addresses. */
yihui 9:05f0b5a3a70a 229 __IO uint32_t PROTENSET1; /*!< Protection bit enable set register for high addresses. */
yihui 9:05f0b5a3a70a 230 __IO uint32_t DISABLEINDEBUG; /*!< Disable protection mechanism in debug mode. */
yihui 9:05f0b5a3a70a 231 } NRF_MPU_Type;
yihui 9:05f0b5a3a70a 232
yihui 9:05f0b5a3a70a 233
yihui 9:05f0b5a3a70a 234 /* ================================================================================ */
yihui 9:05f0b5a3a70a 235 /* ================ PU ================ */
yihui 9:05f0b5a3a70a 236 /* ================================================================================ */
yihui 9:05f0b5a3a70a 237
yihui 9:05f0b5a3a70a 238
yihui 9:05f0b5a3a70a 239 /**
yihui 9:05f0b5a3a70a 240 * @brief Patch unit. (PU)
yihui 9:05f0b5a3a70a 241 */
yihui 9:05f0b5a3a70a 242
yihui 9:05f0b5a3a70a 243 typedef struct { /*!< PU Structure */
yihui 9:05f0b5a3a70a 244 __I uint32_t RESERVED0[448];
yihui 9:05f0b5a3a70a 245 __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
yihui 9:05f0b5a3a70a 246 __I uint32_t RESERVED1[24];
yihui 9:05f0b5a3a70a 247 __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
yihui 9:05f0b5a3a70a 248 __I uint32_t RESERVED2[24];
yihui 9:05f0b5a3a70a 249 __IO uint32_t PATCHEN; /*!< Patch enable register. */
yihui 9:05f0b5a3a70a 250 __IO uint32_t PATCHENSET; /*!< Patch enable register. */
yihui 9:05f0b5a3a70a 251 __IO uint32_t PATCHENCLR; /*!< Patch disable register. */
yihui 9:05f0b5a3a70a 252 } NRF_PU_Type;
yihui 9:05f0b5a3a70a 253
yihui 9:05f0b5a3a70a 254
yihui 9:05f0b5a3a70a 255 /* ================================================================================ */
yihui 9:05f0b5a3a70a 256 /* ================ AMLI ================ */
yihui 9:05f0b5a3a70a 257 /* ================================================================================ */
yihui 9:05f0b5a3a70a 258
yihui 9:05f0b5a3a70a 259
yihui 9:05f0b5a3a70a 260 /**
yihui 9:05f0b5a3a70a 261 * @brief AHB Multi-Layer Interface. (AMLI)
yihui 9:05f0b5a3a70a 262 */
yihui 9:05f0b5a3a70a 263
yihui 9:05f0b5a3a70a 264 typedef struct { /*!< AMLI Structure */
yihui 9:05f0b5a3a70a 265 __I uint32_t RESERVED0[896];
yihui 9:05f0b5a3a70a 266 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
yihui 9:05f0b5a3a70a 267 } NRF_AMLI_Type;
yihui 9:05f0b5a3a70a 268
yihui 9:05f0b5a3a70a 269
yihui 9:05f0b5a3a70a 270 /* ================================================================================ */
yihui 9:05f0b5a3a70a 271 /* ================ RADIO ================ */
yihui 9:05f0b5a3a70a 272 /* ================================================================================ */
yihui 9:05f0b5a3a70a 273
yihui 9:05f0b5a3a70a 274
yihui 9:05f0b5a3a70a 275 /**
yihui 9:05f0b5a3a70a 276 * @brief The radio. (RADIO)
yihui 9:05f0b5a3a70a 277 */
yihui 9:05f0b5a3a70a 278
yihui 9:05f0b5a3a70a 279 typedef struct { /*!< RADIO Structure */
yihui 9:05f0b5a3a70a 280 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
yihui 9:05f0b5a3a70a 281 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
yihui 9:05f0b5a3a70a 282 __O uint32_t TASKS_START; /*!< Start radio. */
yihui 9:05f0b5a3a70a 283 __O uint32_t TASKS_STOP; /*!< Stop radio. */
yihui 9:05f0b5a3a70a 284 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
yihui 9:05f0b5a3a70a 285 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
yihui 9:05f0b5a3a70a 286 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
yihui 9:05f0b5a3a70a 287 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
yihui 9:05f0b5a3a70a 288 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
yihui 9:05f0b5a3a70a 289 __I uint32_t RESERVED0[55];
yihui 9:05f0b5a3a70a 290 __IO uint32_t EVENTS_READY; /*!< Ready event. */
yihui 9:05f0b5a3a70a 291 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
yihui 9:05f0b5a3a70a 292 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
yihui 9:05f0b5a3a70a 293 __IO uint32_t EVENTS_END; /*!< End event. */
yihui 9:05f0b5a3a70a 294 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
yihui 9:05f0b5a3a70a 295 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
yihui 9:05f0b5a3a70a 296 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
yihui 9:05f0b5a3a70a 297 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
yihui 9:05f0b5a3a70a 298 sample is ready for readout at the RSSISAMPLE register. */
yihui 9:05f0b5a3a70a 299 __I uint32_t RESERVED1[2];
yihui 9:05f0b5a3a70a 300 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */
yihui 9:05f0b5a3a70a 301 __I uint32_t RESERVED2[53];
yihui 9:05f0b5a3a70a 302 __IO uint32_t SHORTS; /*!< Shortcut for the radio. */
yihui 9:05f0b5a3a70a 303 __I uint32_t RESERVED3[64];
yihui 9:05f0b5a3a70a 304 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
yihui 9:05f0b5a3a70a 305 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
yihui 9:05f0b5a3a70a 306 __I uint32_t RESERVED4[61];
yihui 9:05f0b5a3a70a 307 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
yihui 9:05f0b5a3a70a 308 __I uint32_t RESERVED5;
yihui 9:05f0b5a3a70a 309 __I uint32_t RXMATCH; /*!< Received address. */
yihui 9:05f0b5a3a70a 310 __I uint32_t RXCRC; /*!< Received CRC. */
yihui 9:05f0b5a3a70a 311 __IO uint32_t DAI; /*!< Device address match index. */
yihui 9:05f0b5a3a70a 312 __I uint32_t RESERVED6[60];
yihui 9:05f0b5a3a70a 313 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
yihui 9:05f0b5a3a70a 314 __IO uint32_t FREQUENCY; /*!< Frequency. */
yihui 9:05f0b5a3a70a 315 __IO uint32_t TXPOWER; /*!< Output power. */
yihui 9:05f0b5a3a70a 316 __IO uint32_t MODE; /*!< Data rate and modulation. */
yihui 9:05f0b5a3a70a 317 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
yihui 9:05f0b5a3a70a 318 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
yihui 9:05f0b5a3a70a 319 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
yihui 9:05f0b5a3a70a 320 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
yihui 9:05f0b5a3a70a 321 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
yihui 9:05f0b5a3a70a 322 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
yihui 9:05f0b5a3a70a 323 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
yihui 9:05f0b5a3a70a 324 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
yihui 9:05f0b5a3a70a 325 __IO uint32_t CRCCNF; /*!< CRC configuration. */
yihui 9:05f0b5a3a70a 326 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
yihui 9:05f0b5a3a70a 327 __IO uint32_t CRCINIT; /*!< CRC initial value. */
yihui 9:05f0b5a3a70a 328 __IO uint32_t TEST; /*!< Test features enable register. */
yihui 9:05f0b5a3a70a 329 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
yihui 9:05f0b5a3a70a 330 __IO uint32_t RSSISAMPLE; /*!< RSSI sample. */
yihui 9:05f0b5a3a70a 331 __I uint32_t RESERVED7;
yihui 9:05f0b5a3a70a 332 __I uint32_t STATE; /*!< Current radio state. */
yihui 9:05f0b5a3a70a 333 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
yihui 9:05f0b5a3a70a 334 __I uint32_t RESERVED8[2];
yihui 9:05f0b5a3a70a 335 __IO uint32_t BCC; /*!< Bit counter compare. */
yihui 9:05f0b5a3a70a 336 __I uint32_t RESERVED9[39];
yihui 9:05f0b5a3a70a 337 __IO uint32_t DAB[8]; /*!< Device address base segment. */
yihui 9:05f0b5a3a70a 338 __IO uint32_t DAP[8]; /*!< Device address prefix. */
yihui 9:05f0b5a3a70a 339 __IO uint32_t DACNF; /*!< Device address match configuration. */
yihui 9:05f0b5a3a70a 340 __I uint32_t RESERVED10[56];
yihui 9:05f0b5a3a70a 341 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
yihui 9:05f0b5a3a70a 342 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
yihui 9:05f0b5a3a70a 343 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
yihui 9:05f0b5a3a70a 344 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
yihui 9:05f0b5a3a70a 345 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
yihui 9:05f0b5a3a70a 346 __I uint32_t RESERVED11[561];
yihui 9:05f0b5a3a70a 347 __IO uint32_t POWER; /*!< Peripheral power control. */
yihui 9:05f0b5a3a70a 348 } NRF_RADIO_Type;
yihui 9:05f0b5a3a70a 349
yihui 9:05f0b5a3a70a 350
yihui 9:05f0b5a3a70a 351 /* ================================================================================ */
yihui 9:05f0b5a3a70a 352 /* ================ UART ================ */
yihui 9:05f0b5a3a70a 353 /* ================================================================================ */
yihui 9:05f0b5a3a70a 354
yihui 9:05f0b5a3a70a 355
yihui 9:05f0b5a3a70a 356 /**
yihui 9:05f0b5a3a70a 357 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
yihui 9:05f0b5a3a70a 358 */
yihui 9:05f0b5a3a70a 359
yihui 9:05f0b5a3a70a 360 typedef struct { /*!< UART Structure */
yihui 9:05f0b5a3a70a 361 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
yihui 9:05f0b5a3a70a 362 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
yihui 9:05f0b5a3a70a 363 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
yihui 9:05f0b5a3a70a 364 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
yihui 9:05f0b5a3a70a 365 __I uint32_t RESERVED0[3];
yihui 9:05f0b5a3a70a 366 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
yihui 9:05f0b5a3a70a 367 __I uint32_t RESERVED1[56];
yihui 9:05f0b5a3a70a 368 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
yihui 9:05f0b5a3a70a 369 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
yihui 9:05f0b5a3a70a 370 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
yihui 9:05f0b5a3a70a 371 __I uint32_t RESERVED2[4];
yihui 9:05f0b5a3a70a 372 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
yihui 9:05f0b5a3a70a 373 __I uint32_t RESERVED3;
yihui 9:05f0b5a3a70a 374 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
yihui 9:05f0b5a3a70a 375 __I uint32_t RESERVED4[7];
yihui 9:05f0b5a3a70a 376 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
yihui 9:05f0b5a3a70a 377 __I uint32_t RESERVED5[46];
yihui 9:05f0b5a3a70a 378 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
yihui 9:05f0b5a3a70a 379 __I uint32_t RESERVED6[64];
yihui 9:05f0b5a3a70a 380 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
yihui 9:05f0b5a3a70a 381 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
yihui 9:05f0b5a3a70a 382 __I uint32_t RESERVED7[93];
yihui 9:05f0b5a3a70a 383 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
yihui 9:05f0b5a3a70a 384 __I uint32_t RESERVED8[31];
yihui 9:05f0b5a3a70a 385 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
yihui 9:05f0b5a3a70a 386 __I uint32_t RESERVED9;
yihui 9:05f0b5a3a70a 387 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
yihui 9:05f0b5a3a70a 388 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
yihui 9:05f0b5a3a70a 389 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
yihui 9:05f0b5a3a70a 390 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
yihui 9:05f0b5a3a70a 391 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
yihui 9:05f0b5a3a70a 392 Once read the character is consummed. If read when no character
yihui 9:05f0b5a3a70a 393 available, the UART will stop working. */
yihui 9:05f0b5a3a70a 394 __O uint32_t TXD; /*!< TXD register. */
yihui 9:05f0b5a3a70a 395 __I uint32_t RESERVED10;
yihui 9:05f0b5a3a70a 396 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
yihui 9:05f0b5a3a70a 397 __I uint32_t RESERVED11[17];
yihui 9:05f0b5a3a70a 398 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
yihui 9:05f0b5a3a70a 399 __I uint32_t RESERVED12[675];
yihui 9:05f0b5a3a70a 400 __IO uint32_t POWER; /*!< Peripheral power control. */
yihui 9:05f0b5a3a70a 401 } NRF_UART_Type;
yihui 9:05f0b5a3a70a 402
yihui 9:05f0b5a3a70a 403
yihui 9:05f0b5a3a70a 404 /* ================================================================================ */
yihui 9:05f0b5a3a70a 405 /* ================ SPI ================ */
yihui 9:05f0b5a3a70a 406 /* ================================================================================ */
yihui 9:05f0b5a3a70a 407
yihui 9:05f0b5a3a70a 408
yihui 9:05f0b5a3a70a 409 /**
yihui 9:05f0b5a3a70a 410 * @brief SPI master 0. (SPI)
yihui 9:05f0b5a3a70a 411 */
yihui 9:05f0b5a3a70a 412
yihui 9:05f0b5a3a70a 413 typedef struct { /*!< SPI Structure */
yihui 9:05f0b5a3a70a 414 __I uint32_t RESERVED0[66];
yihui 9:05f0b5a3a70a 415 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
yihui 9:05f0b5a3a70a 416 __I uint32_t RESERVED1[126];
yihui 9:05f0b5a3a70a 417 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
yihui 9:05f0b5a3a70a 418 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
yihui 9:05f0b5a3a70a 419 __I uint32_t RESERVED2[125];
yihui 9:05f0b5a3a70a 420 __IO uint32_t ENABLE; /*!< Enable SPI. */
yihui 9:05f0b5a3a70a 421 __I uint32_t RESERVED3;
yihui 9:05f0b5a3a70a 422 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
yihui 9:05f0b5a3a70a 423 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
yihui 9:05f0b5a3a70a 424 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
yihui 9:05f0b5a3a70a 425 __I uint32_t RESERVED4;
yihui 9:05f0b5a3a70a 426 __IO uint32_t RXD; /*!< RX data. */
yihui 9:05f0b5a3a70a 427 __IO uint32_t TXD; /*!< TX data. */
yihui 9:05f0b5a3a70a 428 __I uint32_t RESERVED5;
yihui 9:05f0b5a3a70a 429 __IO uint32_t FREQUENCY; /*!< SPI frequency */
yihui 9:05f0b5a3a70a 430 __I uint32_t RESERVED6[11];
yihui 9:05f0b5a3a70a 431 __IO uint32_t CONFIG; /*!< Configuration register. */
yihui 9:05f0b5a3a70a 432 __I uint32_t RESERVED7[681];
yihui 9:05f0b5a3a70a 433 __IO uint32_t POWER; /*!< Peripheral power control. */
yihui 9:05f0b5a3a70a 434 } NRF_SPI_Type;
yihui 9:05f0b5a3a70a 435
yihui 9:05f0b5a3a70a 436
yihui 9:05f0b5a3a70a 437 /* ================================================================================ */
yihui 9:05f0b5a3a70a 438 /* ================ TWI ================ */
yihui 9:05f0b5a3a70a 439 /* ================================================================================ */
yihui 9:05f0b5a3a70a 440
yihui 9:05f0b5a3a70a 441
yihui 9:05f0b5a3a70a 442 /**
yihui 9:05f0b5a3a70a 443 * @brief Two-wire interface master 0. (TWI)
yihui 9:05f0b5a3a70a 444 */
yihui 9:05f0b5a3a70a 445
yihui 9:05f0b5a3a70a 446 typedef struct { /*!< TWI Structure */
yihui 9:05f0b5a3a70a 447 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
yihui 9:05f0b5a3a70a 448 __I uint32_t RESERVED0;
yihui 9:05f0b5a3a70a 449 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
yihui 9:05f0b5a3a70a 450 __I uint32_t RESERVED1[2];
yihui 9:05f0b5a3a70a 451 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
yihui 9:05f0b5a3a70a 452 __I uint32_t RESERVED2;
yihui 9:05f0b5a3a70a 453 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
yihui 9:05f0b5a3a70a 454 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
yihui 9:05f0b5a3a70a 455 __I uint32_t RESERVED3[56];
yihui 9:05f0b5a3a70a 456 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
yihui 9:05f0b5a3a70a 457 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
yihui 9:05f0b5a3a70a 458 __I uint32_t RESERVED4[4];
yihui 9:05f0b5a3a70a 459 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
yihui 9:05f0b5a3a70a 460 __I uint32_t RESERVED5;
yihui 9:05f0b5a3a70a 461 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
yihui 9:05f0b5a3a70a 462 __I uint32_t RESERVED6[4];
yihui 9:05f0b5a3a70a 463 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
yihui 9:05f0b5a3a70a 464 __I uint32_t RESERVED7[49];
yihui 9:05f0b5a3a70a 465 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
yihui 9:05f0b5a3a70a 466 __I uint32_t RESERVED8[64];
yihui 9:05f0b5a3a70a 467 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
yihui 9:05f0b5a3a70a 468 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
yihui 9:05f0b5a3a70a 469 __I uint32_t RESERVED9[110];
yihui 9:05f0b5a3a70a 470 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
yihui 9:05f0b5a3a70a 471 __I uint32_t RESERVED10[14];
yihui 9:05f0b5a3a70a 472 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
yihui 9:05f0b5a3a70a 473 __I uint32_t RESERVED11;
yihui 9:05f0b5a3a70a 474 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
yihui 9:05f0b5a3a70a 475 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
yihui 9:05f0b5a3a70a 476 __I uint32_t RESERVED12[2];
yihui 9:05f0b5a3a70a 477 __IO uint32_t RXD; /*!< RX data register. */
yihui 9:05f0b5a3a70a 478 __IO uint32_t TXD; /*!< TX data register. */
yihui 9:05f0b5a3a70a 479 __I uint32_t RESERVED13;
yihui 9:05f0b5a3a70a 480 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
yihui 9:05f0b5a3a70a 481 __I uint32_t RESERVED14[24];
yihui 9:05f0b5a3a70a 482 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
yihui 9:05f0b5a3a70a 483 __I uint32_t RESERVED15[668];
yihui 9:05f0b5a3a70a 484 __IO uint32_t POWER; /*!< Peripheral power control. */
yihui 9:05f0b5a3a70a 485 } NRF_TWI_Type;
yihui 9:05f0b5a3a70a 486
yihui 9:05f0b5a3a70a 487
yihui 9:05f0b5a3a70a 488 /* ================================================================================ */
yihui 9:05f0b5a3a70a 489 /* ================ SPIS ================ */
yihui 9:05f0b5a3a70a 490 /* ================================================================================ */
yihui 9:05f0b5a3a70a 491
yihui 9:05f0b5a3a70a 492
yihui 9:05f0b5a3a70a 493 /**
yihui 9:05f0b5a3a70a 494 * @brief SPI slave 1. (SPIS)
yihui 9:05f0b5a3a70a 495 */
yihui 9:05f0b5a3a70a 496
yihui 9:05f0b5a3a70a 497 typedef struct { /*!< SPIS Structure */
yihui 9:05f0b5a3a70a 498 __I uint32_t RESERVED0[9];
yihui 9:05f0b5a3a70a 499 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
yihui 9:05f0b5a3a70a 500 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
yihui 9:05f0b5a3a70a 501 __I uint32_t RESERVED1[54];
yihui 9:05f0b5a3a70a 502 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
yihui 9:05f0b5a3a70a 503 __I uint32_t RESERVED2[8];
yihui 9:05f0b5a3a70a 504 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
yihui 9:05f0b5a3a70a 505 __I uint32_t RESERVED3[53];
yihui 9:05f0b5a3a70a 506 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
yihui 9:05f0b5a3a70a 507 __I uint32_t RESERVED4[64];
yihui 9:05f0b5a3a70a 508 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
yihui 9:05f0b5a3a70a 509 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
yihui 9:05f0b5a3a70a 510 __I uint32_t RESERVED5[61];
yihui 9:05f0b5a3a70a 511 __I uint32_t SEMSTAT; /*!< Semaphore status. */
yihui 9:05f0b5a3a70a 512 __I uint32_t RESERVED6[15];
yihui 9:05f0b5a3a70a 513 __IO uint32_t STATUS; /*!< Status from last transaction. */
yihui 9:05f0b5a3a70a 514 __I uint32_t RESERVED7[47];
yihui 9:05f0b5a3a70a 515 __IO uint32_t ENABLE; /*!< Enable SPIS. */
yihui 9:05f0b5a3a70a 516 __I uint32_t RESERVED8;
yihui 9:05f0b5a3a70a 517 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
yihui 9:05f0b5a3a70a 518 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
yihui 9:05f0b5a3a70a 519 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
yihui 9:05f0b5a3a70a 520 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
yihui 9:05f0b5a3a70a 521 __I uint32_t RESERVED9[7];
yihui 9:05f0b5a3a70a 522 __IO uint32_t RXDPTR; /*!< RX data pointer. */
yihui 9:05f0b5a3a70a 523 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
yihui 9:05f0b5a3a70a 524 __IO uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
yihui 9:05f0b5a3a70a 525 __I uint32_t RESERVED10;
yihui 9:05f0b5a3a70a 526 __IO uint32_t TXDPTR; /*!< TX data pointer. */
yihui 9:05f0b5a3a70a 527 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
yihui 9:05f0b5a3a70a 528 __IO uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
yihui 9:05f0b5a3a70a 529 __I uint32_t RESERVED11;
yihui 9:05f0b5a3a70a 530 __IO uint32_t CONFIG; /*!< Configuration register. */
yihui 9:05f0b5a3a70a 531 __I uint32_t RESERVED12;
yihui 9:05f0b5a3a70a 532 __IO uint32_t DEF; /*!< Default character. */
yihui 9:05f0b5a3a70a 533 __I uint32_t RESERVED13[24];
yihui 9:05f0b5a3a70a 534 __IO uint32_t ORC; /*!< Over-read character. */
yihui 9:05f0b5a3a70a 535 __I uint32_t RESERVED14[654];
yihui 9:05f0b5a3a70a 536 __IO uint32_t POWER; /*!< Peripheral power control. */
yihui 9:05f0b5a3a70a 537 } NRF_SPIS_Type;
yihui 9:05f0b5a3a70a 538
yihui 9:05f0b5a3a70a 539
yihui 9:05f0b5a3a70a 540 /* ================================================================================ */
yihui 9:05f0b5a3a70a 541 /* ================ GPIOTE ================ */
yihui 9:05f0b5a3a70a 542 /* ================================================================================ */
yihui 9:05f0b5a3a70a 543
yihui 9:05f0b5a3a70a 544
yihui 9:05f0b5a3a70a 545 /**
yihui 9:05f0b5a3a70a 546 * @brief GPIO tasks and events. (GPIOTE)
yihui 9:05f0b5a3a70a 547 */
yihui 9:05f0b5a3a70a 548
yihui 9:05f0b5a3a70a 549 typedef struct { /*!< GPIOTE Structure */
yihui 9:05f0b5a3a70a 550 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
yihui 9:05f0b5a3a70a 551 __I uint32_t RESERVED0[60];
yihui 9:05f0b5a3a70a 552 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
yihui 9:05f0b5a3a70a 553 __I uint32_t RESERVED1[27];
yihui 9:05f0b5a3a70a 554 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
yihui 9:05f0b5a3a70a 555 __I uint32_t RESERVED2[97];
yihui 9:05f0b5a3a70a 556 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
yihui 9:05f0b5a3a70a 557 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
yihui 9:05f0b5a3a70a 558 __I uint32_t RESERVED3[129];
yihui 9:05f0b5a3a70a 559 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
yihui 9:05f0b5a3a70a 560 __I uint32_t RESERVED4[695];
yihui 9:05f0b5a3a70a 561 __IO uint32_t POWER; /*!< Peripheral power control. */
yihui 9:05f0b5a3a70a 562 } NRF_GPIOTE_Type;
yihui 9:05f0b5a3a70a 563
yihui 9:05f0b5a3a70a 564
yihui 9:05f0b5a3a70a 565 /* ================================================================================ */
yihui 9:05f0b5a3a70a 566 /* ================ ADC ================ */
yihui 9:05f0b5a3a70a 567 /* ================================================================================ */
yihui 9:05f0b5a3a70a 568
yihui 9:05f0b5a3a70a 569
yihui 9:05f0b5a3a70a 570 /**
yihui 9:05f0b5a3a70a 571 * @brief Analog to digital converter. (ADC)
yihui 9:05f0b5a3a70a 572 */
yihui 9:05f0b5a3a70a 573
yihui 9:05f0b5a3a70a 574 typedef struct { /*!< ADC Structure */
yihui 9:05f0b5a3a70a 575 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
yihui 9:05f0b5a3a70a 576 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
yihui 9:05f0b5a3a70a 577 __I uint32_t RESERVED0[62];
yihui 9:05f0b5a3a70a 578 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
yihui 9:05f0b5a3a70a 579 __I uint32_t RESERVED1[128];
yihui 9:05f0b5a3a70a 580 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
yihui 9:05f0b5a3a70a 581 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
yihui 9:05f0b5a3a70a 582 __I uint32_t RESERVED2[61];
yihui 9:05f0b5a3a70a 583 __I uint32_t BUSY; /*!< ADC busy register. */
yihui 9:05f0b5a3a70a 584 __I uint32_t RESERVED3[63];
yihui 9:05f0b5a3a70a 585 __IO uint32_t ENABLE; /*!< ADC enable. */
yihui 9:05f0b5a3a70a 586 __IO uint32_t CONFIG; /*!< ADC configuration register. */
yihui 9:05f0b5a3a70a 587 __I uint32_t RESULT; /*!< Result of ADC conversion. */
yihui 9:05f0b5a3a70a 588 __I uint32_t RESERVED4[700];
yihui 9:05f0b5a3a70a 589 __IO uint32_t POWER; /*!< Peripheral power control. */
yihui 9:05f0b5a3a70a 590 } NRF_ADC_Type;
yihui 9:05f0b5a3a70a 591
yihui 9:05f0b5a3a70a 592
yihui 9:05f0b5a3a70a 593 /* ================================================================================ */
yihui 9:05f0b5a3a70a 594 /* ================ TIMER ================ */
yihui 9:05f0b5a3a70a 595 /* ================================================================================ */
yihui 9:05f0b5a3a70a 596
yihui 9:05f0b5a3a70a 597
yihui 9:05f0b5a3a70a 598 /**
yihui 9:05f0b5a3a70a 599 * @brief Timer 0. (TIMER)
yihui 9:05f0b5a3a70a 600 */
yihui 9:05f0b5a3a70a 601
yihui 9:05f0b5a3a70a 602 typedef struct { /*!< TIMER Structure */
yihui 9:05f0b5a3a70a 603 __O uint32_t TASKS_START; /*!< Start Timer. */
yihui 9:05f0b5a3a70a 604 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
yihui 9:05f0b5a3a70a 605 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
yihui 9:05f0b5a3a70a 606 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
yihui 9:05f0b5a3a70a 607 __I uint32_t RESERVED0[12];
yihui 9:05f0b5a3a70a 608 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
yihui 9:05f0b5a3a70a 609 __I uint32_t RESERVED1[60];
yihui 9:05f0b5a3a70a 610 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
yihui 9:05f0b5a3a70a 611 __I uint32_t RESERVED2[44];
yihui 9:05f0b5a3a70a 612 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
yihui 9:05f0b5a3a70a 613 __I uint32_t RESERVED3[64];
yihui 9:05f0b5a3a70a 614 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
yihui 9:05f0b5a3a70a 615 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
yihui 9:05f0b5a3a70a 616 __I uint32_t RESERVED4[126];
yihui 9:05f0b5a3a70a 617 __IO uint32_t MODE; /*!< Timer Mode selection. */
yihui 9:05f0b5a3a70a 618 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
yihui 9:05f0b5a3a70a 619 __I uint32_t RESERVED5;
yihui 9:05f0b5a3a70a 620 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
yihui 9:05f0b5a3a70a 621 clock frequency is divided by 2^SCALE. */
yihui 9:05f0b5a3a70a 622 __I uint32_t RESERVED6[11];
yihui 9:05f0b5a3a70a 623 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
yihui 9:05f0b5a3a70a 624 __I uint32_t RESERVED7[683];
yihui 9:05f0b5a3a70a 625 __IO uint32_t POWER; /*!< Peripheral power control. */
yihui 9:05f0b5a3a70a 626 } NRF_TIMER_Type;
yihui 9:05f0b5a3a70a 627
yihui 9:05f0b5a3a70a 628
yihui 9:05f0b5a3a70a 629 /* ================================================================================ */
yihui 9:05f0b5a3a70a 630 /* ================ RTC ================ */
yihui 9:05f0b5a3a70a 631 /* ================================================================================ */
yihui 9:05f0b5a3a70a 632
yihui 9:05f0b5a3a70a 633
yihui 9:05f0b5a3a70a 634 /**
yihui 9:05f0b5a3a70a 635 * @brief Real time counter 0. (RTC)
yihui 9:05f0b5a3a70a 636 */
yihui 9:05f0b5a3a70a 637
yihui 9:05f0b5a3a70a 638 typedef struct { /*!< RTC Structure */
yihui 9:05f0b5a3a70a 639 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
yihui 9:05f0b5a3a70a 640 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
yihui 9:05f0b5a3a70a 641 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
yihui 9:05f0b5a3a70a 642 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
yihui 9:05f0b5a3a70a 643 __I uint32_t RESERVED0[60];
yihui 9:05f0b5a3a70a 644 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
yihui 9:05f0b5a3a70a 645 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
yihui 9:05f0b5a3a70a 646 __I uint32_t RESERVED1[14];
yihui 9:05f0b5a3a70a 647 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
yihui 9:05f0b5a3a70a 648 __I uint32_t RESERVED2[109];
yihui 9:05f0b5a3a70a 649 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
yihui 9:05f0b5a3a70a 650 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
yihui 9:05f0b5a3a70a 651 __I uint32_t RESERVED3[13];
yihui 9:05f0b5a3a70a 652 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
yihui 9:05f0b5a3a70a 653 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
yihui 9:05f0b5a3a70a 654 the value of EVTEN. */
yihui 9:05f0b5a3a70a 655 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
yihui 9:05f0b5a3a70a 656 gives the value of EVTEN. */
yihui 9:05f0b5a3a70a 657 __I uint32_t RESERVED4[110];
yihui 9:05f0b5a3a70a 658 __IO uint32_t COUNTER; /*!< Current COUNTER value. */
yihui 9:05f0b5a3a70a 659 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
yihui 9:05f0b5a3a70a 660 Must be written when RTC is STOPed. */
yihui 9:05f0b5a3a70a 661 __I uint32_t RESERVED5[13];
yihui 9:05f0b5a3a70a 662 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
yihui 9:05f0b5a3a70a 663 __I uint32_t RESERVED6[683];
yihui 9:05f0b5a3a70a 664 __IO uint32_t POWER; /*!< Peripheral power control. */
yihui 9:05f0b5a3a70a 665 } NRF_RTC_Type;
yihui 9:05f0b5a3a70a 666
yihui 9:05f0b5a3a70a 667
yihui 9:05f0b5a3a70a 668 /* ================================================================================ */
yihui 9:05f0b5a3a70a 669 /* ================ TEMP ================ */
yihui 9:05f0b5a3a70a 670 /* ================================================================================ */
yihui 9:05f0b5a3a70a 671
yihui 9:05f0b5a3a70a 672
yihui 9:05f0b5a3a70a 673 /**
yihui 9:05f0b5a3a70a 674 * @brief Temperature Sensor. (TEMP)
yihui 9:05f0b5a3a70a 675 */
yihui 9:05f0b5a3a70a 676
yihui 9:05f0b5a3a70a 677 typedef struct { /*!< TEMP Structure */
yihui 9:05f0b5a3a70a 678 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
yihui 9:05f0b5a3a70a 679 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
yihui 9:05f0b5a3a70a 680 __I uint32_t RESERVED0[62];
yihui 9:05f0b5a3a70a 681 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
yihui 9:05f0b5a3a70a 682 __I uint32_t RESERVED1[128];
yihui 9:05f0b5a3a70a 683 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
yihui 9:05f0b5a3a70a 684 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
yihui 9:05f0b5a3a70a 685 __I uint32_t RESERVED2[127];
yihui 9:05f0b5a3a70a 686 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
yihui 9:05f0b5a3a70a 687 __I uint32_t RESERVED3[700];
yihui 9:05f0b5a3a70a 688 __IO uint32_t POWER; /*!< Peripheral power control. */
yihui 9:05f0b5a3a70a 689 } NRF_TEMP_Type;
yihui 9:05f0b5a3a70a 690
yihui 9:05f0b5a3a70a 691
yihui 9:05f0b5a3a70a 692 /* ================================================================================ */
yihui 9:05f0b5a3a70a 693 /* ================ RNG ================ */
yihui 9:05f0b5a3a70a 694 /* ================================================================================ */
yihui 9:05f0b5a3a70a 695
yihui 9:05f0b5a3a70a 696
yihui 9:05f0b5a3a70a 697 /**
yihui 9:05f0b5a3a70a 698 * @brief Random Number Generator. (RNG)
yihui 9:05f0b5a3a70a 699 */
yihui 9:05f0b5a3a70a 700
yihui 9:05f0b5a3a70a 701 typedef struct { /*!< RNG Structure */
yihui 9:05f0b5a3a70a 702 __O uint32_t TASKS_START; /*!< Start the random number generator. */
yihui 9:05f0b5a3a70a 703 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
yihui 9:05f0b5a3a70a 704 __I uint32_t RESERVED0[62];
yihui 9:05f0b5a3a70a 705 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
yihui 9:05f0b5a3a70a 706 __I uint32_t RESERVED1[63];
yihui 9:05f0b5a3a70a 707 __IO uint32_t SHORTS; /*!< Shortcut for the RNG. */
yihui 9:05f0b5a3a70a 708 __I uint32_t RESERVED2[64];
yihui 9:05f0b5a3a70a 709 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
yihui 9:05f0b5a3a70a 710 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
yihui 9:05f0b5a3a70a 711 __I uint32_t RESERVED3[126];
yihui 9:05f0b5a3a70a 712 __IO uint32_t CONFIG; /*!< Configuration register. */
yihui 9:05f0b5a3a70a 713 __I uint32_t VALUE; /*!< RNG random number. */
yihui 9:05f0b5a3a70a 714 __I uint32_t RESERVED4[700];
yihui 9:05f0b5a3a70a 715 __IO uint32_t POWER; /*!< Peripheral power control. */
yihui 9:05f0b5a3a70a 716 } NRF_RNG_Type;
yihui 9:05f0b5a3a70a 717
yihui 9:05f0b5a3a70a 718
yihui 9:05f0b5a3a70a 719 /* ================================================================================ */
yihui 9:05f0b5a3a70a 720 /* ================ ECB ================ */
yihui 9:05f0b5a3a70a 721 /* ================================================================================ */
yihui 9:05f0b5a3a70a 722
yihui 9:05f0b5a3a70a 723
yihui 9:05f0b5a3a70a 724 /**
yihui 9:05f0b5a3a70a 725 * @brief AES ECB Mode Encryption. (ECB)
yihui 9:05f0b5a3a70a 726 */
yihui 9:05f0b5a3a70a 727
yihui 9:05f0b5a3a70a 728 typedef struct { /*!< ECB Structure */
yihui 9:05f0b5a3a70a 729 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
yihui 9:05f0b5a3a70a 730 will not initiate a new encryption and the ERRORECB event will
yihui 9:05f0b5a3a70a 731 be triggered. */
yihui 9:05f0b5a3a70a 732 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
yihui 9:05f0b5a3a70a 733 this will will trigger the ERRORECB event. */
yihui 9:05f0b5a3a70a 734 __I uint32_t RESERVED0[62];
yihui 9:05f0b5a3a70a 735 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
yihui 9:05f0b5a3a70a 736 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
yihui 9:05f0b5a3a70a 737 error. */
yihui 9:05f0b5a3a70a 738 __I uint32_t RESERVED1[127];
yihui 9:05f0b5a3a70a 739 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
yihui 9:05f0b5a3a70a 740 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
yihui 9:05f0b5a3a70a 741 __I uint32_t RESERVED2[126];
yihui 9:05f0b5a3a70a 742 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
yihui 9:05f0b5a3a70a 743 __I uint32_t RESERVED3[701];
yihui 9:05f0b5a3a70a 744 __IO uint32_t POWER; /*!< Peripheral power control. */
yihui 9:05f0b5a3a70a 745 } NRF_ECB_Type;
yihui 9:05f0b5a3a70a 746
yihui 9:05f0b5a3a70a 747
yihui 9:05f0b5a3a70a 748 /* ================================================================================ */
yihui 9:05f0b5a3a70a 749 /* ================ AAR ================ */
yihui 9:05f0b5a3a70a 750 /* ================================================================================ */
yihui 9:05f0b5a3a70a 751
yihui 9:05f0b5a3a70a 752
yihui 9:05f0b5a3a70a 753 /**
yihui 9:05f0b5a3a70a 754 * @brief Accelerated Address Resolver. (AAR)
yihui 9:05f0b5a3a70a 755 */
yihui 9:05f0b5a3a70a 756
yihui 9:05f0b5a3a70a 757 typedef struct { /*!< AAR Structure */
yihui 9:05f0b5a3a70a 758 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
yihui 9:05f0b5a3a70a 759 data structure. */
yihui 9:05f0b5a3a70a 760 __I uint32_t RESERVED0;
yihui 9:05f0b5a3a70a 761 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
yihui 9:05f0b5a3a70a 762 __I uint32_t RESERVED1[61];
yihui 9:05f0b5a3a70a 763 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
yihui 9:05f0b5a3a70a 764 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
yihui 9:05f0b5a3a70a 765 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
yihui 9:05f0b5a3a70a 766 __I uint32_t RESERVED2[126];
yihui 9:05f0b5a3a70a 767 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
yihui 9:05f0b5a3a70a 768 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
yihui 9:05f0b5a3a70a 769 __I uint32_t RESERVED3[61];
yihui 9:05f0b5a3a70a 770 __I uint32_t STATUS; /*!< Resolution status. */
yihui 9:05f0b5a3a70a 771 __I uint32_t RESERVED4[63];
yihui 9:05f0b5a3a70a 772 __IO uint32_t ENABLE; /*!< Enable AAR. */
yihui 9:05f0b5a3a70a 773 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
yihui 9:05f0b5a3a70a 774 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
yihui 9:05f0b5a3a70a 775 __I uint32_t RESERVED5;
yihui 9:05f0b5a3a70a 776 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
yihui 9:05f0b5a3a70a 777 __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during
yihui 9:05f0b5a3a70a 778 resolution. A minimum of 3 bytes must be reserved. */
yihui 9:05f0b5a3a70a 779 __I uint32_t RESERVED6[697];
yihui 9:05f0b5a3a70a 780 __IO uint32_t POWER; /*!< Peripheral power control. */
yihui 9:05f0b5a3a70a 781 } NRF_AAR_Type;
yihui 9:05f0b5a3a70a 782
yihui 9:05f0b5a3a70a 783
yihui 9:05f0b5a3a70a 784 /* ================================================================================ */
yihui 9:05f0b5a3a70a 785 /* ================ CCM ================ */
yihui 9:05f0b5a3a70a 786 /* ================================================================================ */
yihui 9:05f0b5a3a70a 787
yihui 9:05f0b5a3a70a 788
yihui 9:05f0b5a3a70a 789 /**
yihui 9:05f0b5a3a70a 790 * @brief AES CCM Mode Encryption. (CCM)
yihui 9:05f0b5a3a70a 791 */
yihui 9:05f0b5a3a70a 792
yihui 9:05f0b5a3a70a 793 typedef struct { /*!< CCM Structure */
yihui 9:05f0b5a3a70a 794 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
yihui 9:05f0b5a3a70a 795 itself when completed. */
yihui 9:05f0b5a3a70a 796 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
yihui 9:05f0b5a3a70a 797 completed. */
yihui 9:05f0b5a3a70a 798 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
yihui 9:05f0b5a3a70a 799 __I uint32_t RESERVED0[61];
yihui 9:05f0b5a3a70a 800 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
yihui 9:05f0b5a3a70a 801 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
yihui 9:05f0b5a3a70a 802 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
yihui 9:05f0b5a3a70a 803 __I uint32_t RESERVED1[61];
yihui 9:05f0b5a3a70a 804 __IO uint32_t SHORTS; /*!< Shortcut for the CCM. */
yihui 9:05f0b5a3a70a 805 __I uint32_t RESERVED2[64];
yihui 9:05f0b5a3a70a 806 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
yihui 9:05f0b5a3a70a 807 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
yihui 9:05f0b5a3a70a 808 __I uint32_t RESERVED3[61];
yihui 9:05f0b5a3a70a 809 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
yihui 9:05f0b5a3a70a 810 __I uint32_t RESERVED4[63];
yihui 9:05f0b5a3a70a 811 __IO uint32_t ENABLE; /*!< CCM enable. */
yihui 9:05f0b5a3a70a 812 __IO uint32_t MODE; /*!< Operation mode. */
yihui 9:05f0b5a3a70a 813 __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector. */
yihui 9:05f0b5a3a70a 814 __IO uint32_t INPTR; /*!< Pointer to input packet. */
yihui 9:05f0b5a3a70a 815 __IO uint32_t OUTPTR; /*!< Pointer to output packet. */
yihui 9:05f0b5a3a70a 816 __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during
yihui 9:05f0b5a3a70a 817 resolution. A minimum of 43 bytes must be reserved. */
yihui 9:05f0b5a3a70a 818 __I uint32_t RESERVED5[697];
yihui 9:05f0b5a3a70a 819 __IO uint32_t POWER; /*!< Peripheral power control. */
yihui 9:05f0b5a3a70a 820 } NRF_CCM_Type;
yihui 9:05f0b5a3a70a 821
yihui 9:05f0b5a3a70a 822
yihui 9:05f0b5a3a70a 823 /* ================================================================================ */
yihui 9:05f0b5a3a70a 824 /* ================ WDT ================ */
yihui 9:05f0b5a3a70a 825 /* ================================================================================ */
yihui 9:05f0b5a3a70a 826
yihui 9:05f0b5a3a70a 827
yihui 9:05f0b5a3a70a 828 /**
yihui 9:05f0b5a3a70a 829 * @brief Watchdog Timer. (WDT)
yihui 9:05f0b5a3a70a 830 */
yihui 9:05f0b5a3a70a 831
yihui 9:05f0b5a3a70a 832 typedef struct { /*!< WDT Structure */
yihui 9:05f0b5a3a70a 833 __O uint32_t TASKS_START; /*!< Start the watchdog. */
yihui 9:05f0b5a3a70a 834 __I uint32_t RESERVED0[63];
yihui 9:05f0b5a3a70a 835 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
yihui 9:05f0b5a3a70a 836 __I uint32_t RESERVED1[128];
yihui 9:05f0b5a3a70a 837 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
yihui 9:05f0b5a3a70a 838 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
yihui 9:05f0b5a3a70a 839 __I uint32_t RESERVED2[61];
yihui 9:05f0b5a3a70a 840 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
yihui 9:05f0b5a3a70a 841 __I uint32_t REQSTATUS; /*!< Request status. */
yihui 9:05f0b5a3a70a 842 __I uint32_t RESERVED3[63];
yihui 9:05f0b5a3a70a 843 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
yihui 9:05f0b5a3a70a 844 __IO uint32_t RREN; /*!< Reload request enable. */
yihui 9:05f0b5a3a70a 845 __IO uint32_t CONFIG; /*!< Configuration register. */
yihui 9:05f0b5a3a70a 846 __I uint32_t RESERVED4[60];
yihui 9:05f0b5a3a70a 847 __O uint32_t RR[8]; /*!< Reload requests registers. */
yihui 9:05f0b5a3a70a 848 __I uint32_t RESERVED5[631];
yihui 9:05f0b5a3a70a 849 __IO uint32_t POWER; /*!< Peripheral power control. */
yihui 9:05f0b5a3a70a 850 } NRF_WDT_Type;
yihui 9:05f0b5a3a70a 851
yihui 9:05f0b5a3a70a 852
yihui 9:05f0b5a3a70a 853 /* ================================================================================ */
yihui 9:05f0b5a3a70a 854 /* ================ QDEC ================ */
yihui 9:05f0b5a3a70a 855 /* ================================================================================ */
yihui 9:05f0b5a3a70a 856
yihui 9:05f0b5a3a70a 857
yihui 9:05f0b5a3a70a 858 /**
yihui 9:05f0b5a3a70a 859 * @brief Rotary decoder. (QDEC)
yihui 9:05f0b5a3a70a 860 */
yihui 9:05f0b5a3a70a 861
yihui 9:05f0b5a3a70a 862 typedef struct { /*!< QDEC Structure */
yihui 9:05f0b5a3a70a 863 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
yihui 9:05f0b5a3a70a 864 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
yihui 9:05f0b5a3a70a 865 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
yihui 9:05f0b5a3a70a 866 and clears the ACC registers. */
yihui 9:05f0b5a3a70a 867 __I uint32_t RESERVED0[61];
yihui 9:05f0b5a3a70a 868 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
yihui 9:05f0b5a3a70a 869 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
yihui 9:05f0b5a3a70a 870 ACC register different than zero. */
yihui 9:05f0b5a3a70a 871 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
yihui 9:05f0b5a3a70a 872 __I uint32_t RESERVED1[61];
yihui 9:05f0b5a3a70a 873 __IO uint32_t SHORTS; /*!< Shortcut for the QDEC. */
yihui 9:05f0b5a3a70a 874 __I uint32_t RESERVED2[64];
yihui 9:05f0b5a3a70a 875 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
yihui 9:05f0b5a3a70a 876 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
yihui 9:05f0b5a3a70a 877 __I uint32_t RESERVED3[125];
yihui 9:05f0b5a3a70a 878 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
yihui 9:05f0b5a3a70a 879 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
yihui 9:05f0b5a3a70a 880 __IO uint32_t SAMPLEPER; /*!< Sample period. */
yihui 9:05f0b5a3a70a 881 __I int32_t SAMPLE; /*!< Motion sample value. */
yihui 9:05f0b5a3a70a 882 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
yihui 9:05f0b5a3a70a 883 __I int32_t ACC; /*!< Accumulated valid transitions register. */
yihui 9:05f0b5a3a70a 884 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
yihui 9:05f0b5a3a70a 885 task. */
yihui 9:05f0b5a3a70a 886 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
yihui 9:05f0b5a3a70a 887 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
yihui 9:05f0b5a3a70a 888 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
yihui 9:05f0b5a3a70a 889 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
yihui 9:05f0b5a3a70a 890 __I uint32_t RESERVED4[5];
yihui 9:05f0b5a3a70a 891 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
yihui 9:05f0b5a3a70a 892 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
yihui 9:05f0b5a3a70a 893 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
yihui 9:05f0b5a3a70a 894 task. */
yihui 9:05f0b5a3a70a 895 __I uint32_t RESERVED5[684];
yihui 9:05f0b5a3a70a 896 __IO uint32_t POWER; /*!< Peripheral power control. */
yihui 9:05f0b5a3a70a 897 } NRF_QDEC_Type;
yihui 9:05f0b5a3a70a 898
yihui 9:05f0b5a3a70a 899
yihui 9:05f0b5a3a70a 900 /* ================================================================================ */
yihui 9:05f0b5a3a70a 901 /* ================ LPCOMP ================ */
yihui 9:05f0b5a3a70a 902 /* ================================================================================ */
yihui 9:05f0b5a3a70a 903
yihui 9:05f0b5a3a70a 904
yihui 9:05f0b5a3a70a 905 /**
yihui 9:05f0b5a3a70a 906 * @brief Wakeup Comparator. (LPCOMP)
yihui 9:05f0b5a3a70a 907 */
yihui 9:05f0b5a3a70a 908
yihui 9:05f0b5a3a70a 909 typedef struct { /*!< LPCOMP Structure */
yihui 9:05f0b5a3a70a 910 __O uint32_t TASKS_START; /*!< Start the comparator. */
yihui 9:05f0b5a3a70a 911 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
yihui 9:05f0b5a3a70a 912 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
yihui 9:05f0b5a3a70a 913 __I uint32_t RESERVED0[61];
yihui 9:05f0b5a3a70a 914 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
yihui 9:05f0b5a3a70a 915 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
yihui 9:05f0b5a3a70a 916 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
yihui 9:05f0b5a3a70a 917 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
yihui 9:05f0b5a3a70a 918 __I uint32_t RESERVED1[60];
yihui 9:05f0b5a3a70a 919 __IO uint32_t SHORTS; /*!< Shortcut for the LPCOMP. */
yihui 9:05f0b5a3a70a 920 __I uint32_t RESERVED2[64];
yihui 9:05f0b5a3a70a 921 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
yihui 9:05f0b5a3a70a 922 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
yihui 9:05f0b5a3a70a 923 __I uint32_t RESERVED3[61];
yihui 9:05f0b5a3a70a 924 __I uint32_t RESULT; /*!< Result of last compare. */
yihui 9:05f0b5a3a70a 925 __I uint32_t RESERVED4[63];
yihui 9:05f0b5a3a70a 926 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
yihui 9:05f0b5a3a70a 927 __IO uint32_t PSEL; /*!< Input pin select. */
yihui 9:05f0b5a3a70a 928 __IO uint32_t REFSEL; /*!< Reference select. */
yihui 9:05f0b5a3a70a 929 __IO uint32_t EXTREFSEL; /*!< External reference select. */
yihui 9:05f0b5a3a70a 930 __I uint32_t RESERVED5[4];
yihui 9:05f0b5a3a70a 931 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
yihui 9:05f0b5a3a70a 932 __I uint32_t RESERVED6[694];
yihui 9:05f0b5a3a70a 933 __IO uint32_t POWER; /*!< Peripheral power control. */
yihui 9:05f0b5a3a70a 934 } NRF_LPCOMP_Type;
yihui 9:05f0b5a3a70a 935
yihui 9:05f0b5a3a70a 936
yihui 9:05f0b5a3a70a 937 /* ================================================================================ */
yihui 9:05f0b5a3a70a 938 /* ================ COMP ================ */
yihui 9:05f0b5a3a70a 939 /* ================================================================================ */
yihui 9:05f0b5a3a70a 940
yihui 9:05f0b5a3a70a 941
yihui 9:05f0b5a3a70a 942 /**
yihui 9:05f0b5a3a70a 943 * @brief Comparator. (COMP)
yihui 9:05f0b5a3a70a 944 */
yihui 9:05f0b5a3a70a 945
yihui 9:05f0b5a3a70a 946 typedef struct { /*!< COMP Structure */
yihui 9:05f0b5a3a70a 947 __O uint32_t TASKS_START; /*!< Start the comparator. */
yihui 9:05f0b5a3a70a 948 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
yihui 9:05f0b5a3a70a 949 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
yihui 9:05f0b5a3a70a 950 __I uint32_t RESERVED0[61];
yihui 9:05f0b5a3a70a 951 __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid. */
yihui 9:05f0b5a3a70a 952 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
yihui 9:05f0b5a3a70a 953 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
yihui 9:05f0b5a3a70a 954 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
yihui 9:05f0b5a3a70a 955 __I uint32_t RESERVED1[60];
yihui 9:05f0b5a3a70a 956 __IO uint32_t SHORTS; /*!< Shortcut for the COMP. */
yihui 9:05f0b5a3a70a 957 __I uint32_t RESERVED2[64];
yihui 9:05f0b5a3a70a 958 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
yihui 9:05f0b5a3a70a 959 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
yihui 9:05f0b5a3a70a 960 __I uint32_t RESERVED3[61];
yihui 9:05f0b5a3a70a 961 __I uint32_t RESULT; /*!< Compare result. */
yihui 9:05f0b5a3a70a 962 __I uint32_t RESERVED4[63];
yihui 9:05f0b5a3a70a 963 __IO uint32_t ENABLE; /*!< Enable the COMP. */
yihui 9:05f0b5a3a70a 964 __IO uint32_t PSEL; /*!< Input pin select. */
yihui 9:05f0b5a3a70a 965 __IO uint32_t REFSEL; /*!< Reference select. */
yihui 9:05f0b5a3a70a 966 __IO uint32_t EXTREFSEL; /*!< External reference select. */
yihui 9:05f0b5a3a70a 967 __I uint32_t RESERVED5[8];
yihui 9:05f0b5a3a70a 968 __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit. */
yihui 9:05f0b5a3a70a 969 __IO uint32_t MODE; /*!< Mode configuration. */
yihui 9:05f0b5a3a70a 970 __I uint32_t RESERVED6[689];
yihui 9:05f0b5a3a70a 971 __IO uint32_t POWER; /*!< Peripheral power control. */
yihui 9:05f0b5a3a70a 972 } NRF_COMP_Type;
yihui 9:05f0b5a3a70a 973
yihui 9:05f0b5a3a70a 974
yihui 9:05f0b5a3a70a 975 /* ================================================================================ */
yihui 9:05f0b5a3a70a 976 /* ================ SWI ================ */
yihui 9:05f0b5a3a70a 977 /* ================================================================================ */
yihui 9:05f0b5a3a70a 978
yihui 9:05f0b5a3a70a 979
yihui 9:05f0b5a3a70a 980 /**
yihui 9:05f0b5a3a70a 981 * @brief SW Interrupts. (SWI)
yihui 9:05f0b5a3a70a 982 */
yihui 9:05f0b5a3a70a 983
yihui 9:05f0b5a3a70a 984 typedef struct { /*!< SWI Structure */
yihui 9:05f0b5a3a70a 985 __I uint32_t UNUSED; /*!< Unused. */
yihui 9:05f0b5a3a70a 986 } NRF_SWI_Type;
yihui 9:05f0b5a3a70a 987
yihui 9:05f0b5a3a70a 988
yihui 9:05f0b5a3a70a 989 /* ================================================================================ */
yihui 9:05f0b5a3a70a 990 /* ================ NVMC ================ */
yihui 9:05f0b5a3a70a 991 /* ================================================================================ */
yihui 9:05f0b5a3a70a 992
yihui 9:05f0b5a3a70a 993
yihui 9:05f0b5a3a70a 994 /**
yihui 9:05f0b5a3a70a 995 * @brief Non Volatile Memory Controller. (NVMC)
yihui 9:05f0b5a3a70a 996 */
yihui 9:05f0b5a3a70a 997
yihui 9:05f0b5a3a70a 998 typedef struct { /*!< NVMC Structure */
yihui 9:05f0b5a3a70a 999 __I uint32_t RESERVED0[256];
yihui 9:05f0b5a3a70a 1000 __I uint32_t READY; /*!< Ready flag. */
yihui 9:05f0b5a3a70a 1001 __I uint32_t RESERVED1[64];
yihui 9:05f0b5a3a70a 1002 __IO uint32_t CONFIG; /*!< Configuration register. */
yihui 9:05f0b5a3a70a 1003 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
yihui 9:05f0b5a3a70a 1004 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
yihui 9:05f0b5a3a70a 1005 __IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */
yihui 9:05f0b5a3a70a 1006 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
yihui 9:05f0b5a3a70a 1007 } NRF_NVMC_Type;
yihui 9:05f0b5a3a70a 1008
yihui 9:05f0b5a3a70a 1009
yihui 9:05f0b5a3a70a 1010 /* ================================================================================ */
yihui 9:05f0b5a3a70a 1011 /* ================ PPI ================ */
yihui 9:05f0b5a3a70a 1012 /* ================================================================================ */
yihui 9:05f0b5a3a70a 1013
yihui 9:05f0b5a3a70a 1014
yihui 9:05f0b5a3a70a 1015 /**
yihui 9:05f0b5a3a70a 1016 * @brief PPI controller. (PPI)
yihui 9:05f0b5a3a70a 1017 */
yihui 9:05f0b5a3a70a 1018
yihui 9:05f0b5a3a70a 1019 typedef struct { /*!< PPI Structure */
yihui 9:05f0b5a3a70a 1020 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
yihui 9:05f0b5a3a70a 1021 __I uint32_t RESERVED0[312];
yihui 9:05f0b5a3a70a 1022 __IO uint32_t CHEN; /*!< Channel enable. */
yihui 9:05f0b5a3a70a 1023 __IO uint32_t CHENSET; /*!< Channel enable set. */
yihui 9:05f0b5a3a70a 1024 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
yihui 9:05f0b5a3a70a 1025 __I uint32_t RESERVED1;
yihui 9:05f0b5a3a70a 1026 PPI_CH_Type CH[16]; /*!< PPI Channel. */
yihui 9:05f0b5a3a70a 1027 __I uint32_t RESERVED2[156];
yihui 9:05f0b5a3a70a 1028 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
yihui 9:05f0b5a3a70a 1029 } NRF_PPI_Type;
yihui 9:05f0b5a3a70a 1030
yihui 9:05f0b5a3a70a 1031
yihui 9:05f0b5a3a70a 1032 /* ================================================================================ */
yihui 9:05f0b5a3a70a 1033 /* ================ FICR ================ */
yihui 9:05f0b5a3a70a 1034 /* ================================================================================ */
yihui 9:05f0b5a3a70a 1035
yihui 9:05f0b5a3a70a 1036
yihui 9:05f0b5a3a70a 1037 /**
yihui 9:05f0b5a3a70a 1038 * @brief Factory Information Configuration. (FICR)
yihui 9:05f0b5a3a70a 1039 */
yihui 9:05f0b5a3a70a 1040
yihui 9:05f0b5a3a70a 1041 typedef struct { /*!< FICR Structure */
yihui 9:05f0b5a3a70a 1042 __I uint32_t RESERVED0[4];
yihui 9:05f0b5a3a70a 1043 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
yihui 9:05f0b5a3a70a 1044 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
yihui 9:05f0b5a3a70a 1045 __I uint32_t RESERVED1[4];
yihui 9:05f0b5a3a70a 1046 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
yihui 9:05f0b5a3a70a 1047 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
yihui 9:05f0b5a3a70a 1048 __I uint32_t RESERVED2;
yihui 9:05f0b5a3a70a 1049 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
yihui 9:05f0b5a3a70a 1050 __I uint32_t SIZERAMBLOCK[4]; /*!< Size of RAM block in bytes. */
yihui 9:05f0b5a3a70a 1051 __I uint32_t RESERVED3[5];
yihui 9:05f0b5a3a70a 1052 __I uint32_t CONFIGID; /*!< Configuration identifier. */
yihui 9:05f0b5a3a70a 1053 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
yihui 9:05f0b5a3a70a 1054 __I uint32_t RESERVED4[6];
yihui 9:05f0b5a3a70a 1055 __I uint32_t ER[4]; /*!< Encryption root. */
yihui 9:05f0b5a3a70a 1056 __I uint32_t IR[4]; /*!< Identity root. */
yihui 9:05f0b5a3a70a 1057 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
yihui 9:05f0b5a3a70a 1058 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
yihui 9:05f0b5a3a70a 1059 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
yihui 9:05f0b5a3a70a 1060 __I uint32_t RESERVED5[15];
yihui 9:05f0b5a3a70a 1061 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
yihui 9:05f0b5a3a70a 1062 mode. */
yihui 9:05f0b5a3a70a 1063 } NRF_FICR_Type;
yihui 9:05f0b5a3a70a 1064
yihui 9:05f0b5a3a70a 1065
yihui 9:05f0b5a3a70a 1066 /* ================================================================================ */
yihui 9:05f0b5a3a70a 1067 /* ================ UICR ================ */
yihui 9:05f0b5a3a70a 1068 /* ================================================================================ */
yihui 9:05f0b5a3a70a 1069
yihui 9:05f0b5a3a70a 1070
yihui 9:05f0b5a3a70a 1071 /**
yihui 9:05f0b5a3a70a 1072 * @brief User Information Configuration. (UICR)
yihui 9:05f0b5a3a70a 1073 */
yihui 9:05f0b5a3a70a 1074
yihui 9:05f0b5a3a70a 1075 typedef struct { /*!< UICR Structure */
yihui 9:05f0b5a3a70a 1076 __IO uint32_t CLENR0; /*!< Length of code region 0. */
yihui 9:05f0b5a3a70a 1077 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
yihui 9:05f0b5a3a70a 1078 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
yihui 9:05f0b5a3a70a 1079 __I uint32_t RESERVED0;
yihui 9:05f0b5a3a70a 1080 __I uint32_t FWID; /*!< Firmware ID. */
yihui 9:05f0b5a3a70a 1081 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
yihui 9:05f0b5a3a70a 1082 } NRF_UICR_Type;
yihui 9:05f0b5a3a70a 1083
yihui 9:05f0b5a3a70a 1084
yihui 9:05f0b5a3a70a 1085 /* ================================================================================ */
yihui 9:05f0b5a3a70a 1086 /* ================ GPIO ================ */
yihui 9:05f0b5a3a70a 1087 /* ================================================================================ */
yihui 9:05f0b5a3a70a 1088
yihui 9:05f0b5a3a70a 1089
yihui 9:05f0b5a3a70a 1090 /**
yihui 9:05f0b5a3a70a 1091 * @brief General purpose input and output. (GPIO)
yihui 9:05f0b5a3a70a 1092 */
yihui 9:05f0b5a3a70a 1093
yihui 9:05f0b5a3a70a 1094 typedef struct { /*!< GPIO Structure */
yihui 9:05f0b5a3a70a 1095 __I uint32_t RESERVED0[321];
yihui 9:05f0b5a3a70a 1096 __IO uint32_t OUT; /*!< Write GPIO port. */
yihui 9:05f0b5a3a70a 1097 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
yihui 9:05f0b5a3a70a 1098 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
yihui 9:05f0b5a3a70a 1099 __I uint32_t IN; /*!< Read GPIO port. */
yihui 9:05f0b5a3a70a 1100 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
yihui 9:05f0b5a3a70a 1101 __IO uint32_t DIRSET; /*!< DIR set register. */
yihui 9:05f0b5a3a70a 1102 __IO uint32_t DIRCLR; /*!< DIR clear register. */
yihui 9:05f0b5a3a70a 1103 __I uint32_t RESERVED1[120];
yihui 9:05f0b5a3a70a 1104 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
yihui 9:05f0b5a3a70a 1105 } NRF_GPIO_Type;
yihui 9:05f0b5a3a70a 1106
yihui 9:05f0b5a3a70a 1107
yihui 9:05f0b5a3a70a 1108 /* -------------------- End of section using anonymous unions ------------------- */
yihui 9:05f0b5a3a70a 1109 #if defined(__CC_ARM)
yihui 9:05f0b5a3a70a 1110 #pragma pop
yihui 9:05f0b5a3a70a 1111 #elif defined(__ICCARM__)
yihui 9:05f0b5a3a70a 1112 /* leave anonymous unions enabled */
yihui 9:05f0b5a3a70a 1113 #elif defined(__GNUC__)
yihui 9:05f0b5a3a70a 1114 /* anonymous unions are enabled by default */
yihui 9:05f0b5a3a70a 1115 #elif defined(__TMS470__)
yihui 9:05f0b5a3a70a 1116 /* anonymous unions are enabled by default */
yihui 9:05f0b5a3a70a 1117 #elif defined(__TASKING__)
yihui 9:05f0b5a3a70a 1118 #pragma warning restore
yihui 9:05f0b5a3a70a 1119 #else
yihui 9:05f0b5a3a70a 1120 #warning Not supported compiler type
yihui 9:05f0b5a3a70a 1121 #endif
yihui 9:05f0b5a3a70a 1122
yihui 9:05f0b5a3a70a 1123
yihui 9:05f0b5a3a70a 1124
yihui 9:05f0b5a3a70a 1125
yihui 9:05f0b5a3a70a 1126 /* ================================================================================ */
yihui 9:05f0b5a3a70a 1127 /* ================ Peripheral memory map ================ */
yihui 9:05f0b5a3a70a 1128 /* ================================================================================ */
yihui 9:05f0b5a3a70a 1129
yihui 9:05f0b5a3a70a 1130 #define NRF_POWER_BASE 0x40000000UL
yihui 9:05f0b5a3a70a 1131 #define NRF_CLOCK_BASE 0x40000000UL
yihui 9:05f0b5a3a70a 1132 #define NRF_MPU_BASE 0x40000000UL
yihui 9:05f0b5a3a70a 1133 #define NRF_PU_BASE 0x40000000UL
yihui 9:05f0b5a3a70a 1134 #define NRF_AMLI_BASE 0x40000000UL
yihui 9:05f0b5a3a70a 1135 #define NRF_RADIO_BASE 0x40001000UL
yihui 9:05f0b5a3a70a 1136 #define NRF_UART0_BASE 0x40002000UL
yihui 9:05f0b5a3a70a 1137 #define NRF_SPI0_BASE 0x40003000UL
yihui 9:05f0b5a3a70a 1138 #define NRF_TWI0_BASE 0x40003000UL
yihui 9:05f0b5a3a70a 1139 #define NRF_SPI1_BASE 0x40004000UL
yihui 9:05f0b5a3a70a 1140 #define NRF_TWI1_BASE 0x40004000UL
yihui 9:05f0b5a3a70a 1141 #define NRF_SPIS1_BASE 0x40004000UL
yihui 9:05f0b5a3a70a 1142 #define NRF_GPIOTE_BASE 0x40006000UL
yihui 9:05f0b5a3a70a 1143 #define NRF_ADC_BASE 0x40007000UL
yihui 9:05f0b5a3a70a 1144 #define NRF_TIMER0_BASE 0x40008000UL
yihui 9:05f0b5a3a70a 1145 #define NRF_TIMER1_BASE 0x40009000UL
yihui 9:05f0b5a3a70a 1146 #define NRF_TIMER2_BASE 0x4000A000UL
yihui 9:05f0b5a3a70a 1147 #define NRF_RTC0_BASE 0x4000B000UL
yihui 9:05f0b5a3a70a 1148 #define NRF_TEMP_BASE 0x4000C000UL
yihui 9:05f0b5a3a70a 1149 #define NRF_RNG_BASE 0x4000D000UL
yihui 9:05f0b5a3a70a 1150 #define NRF_ECB_BASE 0x4000E000UL
yihui 9:05f0b5a3a70a 1151 #define NRF_AAR_BASE 0x4000F000UL
yihui 9:05f0b5a3a70a 1152 #define NRF_CCM_BASE 0x4000F000UL
yihui 9:05f0b5a3a70a 1153 #define NRF_WDT_BASE 0x40010000UL
yihui 9:05f0b5a3a70a 1154 #define NRF_RTC1_BASE 0x40011000UL
yihui 9:05f0b5a3a70a 1155 #define NRF_QDEC_BASE 0x40012000UL
yihui 9:05f0b5a3a70a 1156 #define NRF_LPCOMP_BASE 0x40013000UL
yihui 9:05f0b5a3a70a 1157 #define NRF_COMP_BASE 0x40013000UL
yihui 9:05f0b5a3a70a 1158 #define NRF_SWI_BASE 0x40014000UL
yihui 9:05f0b5a3a70a 1159 #define NRF_NVMC_BASE 0x4001E000UL
yihui 9:05f0b5a3a70a 1160 #define NRF_PPI_BASE 0x4001F000UL
yihui 9:05f0b5a3a70a 1161 #define NRF_FICR_BASE 0x10000000UL
yihui 9:05f0b5a3a70a 1162 #define NRF_UICR_BASE 0x10001000UL
yihui 9:05f0b5a3a70a 1163 #define NRF_GPIO_BASE 0x50000000UL
yihui 9:05f0b5a3a70a 1164
yihui 9:05f0b5a3a70a 1165
yihui 9:05f0b5a3a70a 1166 /* ================================================================================ */
yihui 9:05f0b5a3a70a 1167 /* ================ Peripheral declaration ================ */
yihui 9:05f0b5a3a70a 1168 /* ================================================================================ */
yihui 9:05f0b5a3a70a 1169
yihui 9:05f0b5a3a70a 1170 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
yihui 9:05f0b5a3a70a 1171 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
yihui 9:05f0b5a3a70a 1172 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
yihui 9:05f0b5a3a70a 1173 #define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
yihui 9:05f0b5a3a70a 1174 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
yihui 9:05f0b5a3a70a 1175 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
yihui 9:05f0b5a3a70a 1176 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
yihui 9:05f0b5a3a70a 1177 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
yihui 9:05f0b5a3a70a 1178 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
yihui 9:05f0b5a3a70a 1179 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
yihui 9:05f0b5a3a70a 1180 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
yihui 9:05f0b5a3a70a 1181 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
yihui 9:05f0b5a3a70a 1182 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
yihui 9:05f0b5a3a70a 1183 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
yihui 9:05f0b5a3a70a 1184 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
yihui 9:05f0b5a3a70a 1185 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
yihui 9:05f0b5a3a70a 1186 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
yihui 9:05f0b5a3a70a 1187 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
yihui 9:05f0b5a3a70a 1188 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
yihui 9:05f0b5a3a70a 1189 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
yihui 9:05f0b5a3a70a 1190 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
yihui 9:05f0b5a3a70a 1191 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
yihui 9:05f0b5a3a70a 1192 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
yihui 9:05f0b5a3a70a 1193 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
yihui 9:05f0b5a3a70a 1194 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
yihui 9:05f0b5a3a70a 1195 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
yihui 9:05f0b5a3a70a 1196 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
yihui 9:05f0b5a3a70a 1197 #define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE)
yihui 9:05f0b5a3a70a 1198 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
yihui 9:05f0b5a3a70a 1199 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
yihui 9:05f0b5a3a70a 1200 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
yihui 9:05f0b5a3a70a 1201 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
yihui 9:05f0b5a3a70a 1202 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
yihui 9:05f0b5a3a70a 1203 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
yihui 9:05f0b5a3a70a 1204
yihui 9:05f0b5a3a70a 1205
yihui 9:05f0b5a3a70a 1206 /** @} */ /* End of group Device_Peripheral_Registers */
yihui 9:05f0b5a3a70a 1207 /** @} */ /* End of group nRF51 */
yihui 9:05f0b5a3a70a 1208 /** @} */ /* End of group Nordic Semiconductor */
yihui 9:05f0b5a3a70a 1209
yihui 9:05f0b5a3a70a 1210 #ifdef __cplusplus
yihui 9:05f0b5a3a70a 1211 }
yihui 9:05f0b5a3a70a 1212 #endif
yihui 9:05f0b5a3a70a 1213
yihui 9:05f0b5a3a70a 1214
yihui 9:05f0b5a3a70a 1215 #endif /* nRF51_H */
yihui 9:05f0b5a3a70a 1216