Yihui Xiong / BLE_NODE_TEST

Test code for Grove Node BLE

Dependencies:   BLE_API nRF51822

Fork of BLE_LoopbackUART by Bluetooth Low Energy

mbed-src/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.c@10:22480ac31879, 2014-11-27 (annotated)

Committer:
yihui
Date:
Thu Nov 27 09:30:36 2014 +0000
Revision:
10:22480ac31879
Parent:
9:05f0b5a3a70a 
change to new revision hardware

Who changed what in which revision?

UserRevisionLine numberNew contents of line
yihui 9:05f0b5a3a70a 1 /* mbed Microcontroller Library
yihui 9:05f0b5a3a70a 2 * CMSIS-style functionality to support dynamic vectors
yihui 9:05f0b5a3a70a 3 *******************************************************************************
yihui 9:05f0b5a3a70a 4 * Copyright (c) 2011 ARM Limited. All rights reserved.
yihui 9:05f0b5a3a70a 5 * All rights reserved.
yihui 9:05f0b5a3a70a 6 *
yihui 9:05f0b5a3a70a 7 * Redistribution and use in source and binary forms, with or without
yihui 9:05f0b5a3a70a 8 * modification, are permitted provided that the following conditions are met:
yihui 9:05f0b5a3a70a 9 *
yihui 9:05f0b5a3a70a 10 * 1. Redistributions of source code must retain the above copyright notice,
yihui 9:05f0b5a3a70a 11 * this list of conditions and the following disclaimer.
yihui 9:05f0b5a3a70a 12 * 2. Redistributions in binary form must reproduce the above copyright notice,
yihui 9:05f0b5a3a70a 13 * this list of conditions and the following disclaimer in the documentation
yihui 9:05f0b5a3a70a 14 * and/or other materials provided with the distribution.
yihui 9:05f0b5a3a70a 15 * 3. Neither the name of ARM Limited nor the names of its contributors
yihui 9:05f0b5a3a70a 16 * may be used to endorse or promote products derived from this software
yihui 9:05f0b5a3a70a 17 * without specific prior written permission.
yihui 9:05f0b5a3a70a 18 *
yihui 9:05f0b5a3a70a 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
yihui 9:05f0b5a3a70a 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
yihui 9:05f0b5a3a70a 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
yihui 9:05f0b5a3a70a 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
yihui 9:05f0b5a3a70a 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
yihui 9:05f0b5a3a70a 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
yihui 9:05f0b5a3a70a 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
yihui 9:05f0b5a3a70a 26 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
yihui 9:05f0b5a3a70a 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
yihui 9:05f0b5a3a70a 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
yihui 9:05f0b5a3a70a 29 *******************************************************************************
yihui 9:05f0b5a3a70a 30 */
yihui 9:05f0b5a3a70a 31 #include "cmsis_nvic.h"
yihui 9:05f0b5a3a70a 32
yihui 9:05f0b5a3a70a 33 /* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
yihui 9:05f0b5a3a70a 34 * whilst the vector table may only be something like 48 entries (192 bytes, 0xC0),
yihui 9:05f0b5a3a70a 35 * the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF
yihui 9:05f0b5a3a70a 36 * to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0
yihui 9:05f0b5a3a70a 37 *
yihui 9:05f0b5a3a70a 38 * If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH
yihui 9:05f0b5a3a70a 39 * above the vector table before 0x200 will actually go to RAM. So we need to provide
yihui 9:05f0b5a3a70a 40 * a solution where the compiler gets the right results based on the memory map
yihui 9:05f0b5a3a70a 41 *
yihui 9:05f0b5a3a70a 42 * Option 1 - We allocate and copy 0x200 of RAM rather than just the table
yihui 9:05f0b5a3a70a 43 * - const data and instructions before 0x200 will be copied to and fetched/exec from RAM
yihui 9:05f0b5a3a70a 44 * - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0
yihui 9:05f0b5a3a70a 45 *
yihui 9:05f0b5a3a70a 46 * Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there
yihui 9:05f0b5a3a70a 47 * - No flash accesses will go to ram, as there will be nothing there
yihui 9:05f0b5a3a70a 48 * - RAM only needs to be allocated for the vectors, as all other ram addresses are normal
yihui 9:05f0b5a3a70a 49 * - RAM overhead: 0, FLASH overhead: 320 bytes
yihui 9:05f0b5a3a70a 50 *
yihui 9:05f0b5a3a70a 51 * Option 2 is the one to go for, as RAM is the most valuable resource
yihui 9:05f0b5a3a70a 52 */
yihui 9:05f0b5a3a70a 53
yihui 9:05f0b5a3a70a 54
yihui 9:05f0b5a3a70a 55 #define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM
yihui 9:05f0b5a3a70a 56 #define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
yihui 9:05f0b5a3a70a 57 /*
yihui 9:05f0b5a3a70a 58 void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
yihui 9:05f0b5a3a70a 59 uint32_t *vectors = (uint32_t*)SCB->VTOR;
yihui 9:05f0b5a3a70a 60 uint32_t i;
yihui 9:05f0b5a3a70a 61
yihui 9:05f0b5a3a70a 62 // Copy and switch to dynamic vectors if the first time called
yihui 9:05f0b5a3a70a 63 if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
yihui 9:05f0b5a3a70a 64 uint32_t *old_vectors = vectors;
yihui 9:05f0b5a3a70a 65 vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
yihui 9:05f0b5a3a70a 66 for (i=0; i<NVIC_NUM_VECTORS; i++) {
yihui 9:05f0b5a3a70a 67 vectors[i] = old_vectors[i];
yihui 9:05f0b5a3a70a 68 }
yihui 9:05f0b5a3a70a 69 SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
yihui 9:05f0b5a3a70a 70 }
yihui 9:05f0b5a3a70a 71 vectors[IRQn + 16] = vector;
yihui 9:05f0b5a3a70a 72 }
yihui 9:05f0b5a3a70a 73
yihui 9:05f0b5a3a70a 74 uint32_t NVIC_GetVector(IRQn_Type IRQn) {
yihui 9:05f0b5a3a70a 75 uint32_t *vectors = (uint32_t*)SCB->VTOR;
yihui 9:05f0b5a3a70a 76 return vectors[IRQn + 16];
yihui 9:05f0b5a3a70a 77 }*/
yihui 9:05f0b5a3a70a 78
yihui 9:05f0b5a3a70a 79 void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
yihui 9:05f0b5a3a70a 80 // int i;
yihui 9:05f0b5a3a70a 81 // Space for dynamic vectors, initialised to allocate in R/W
yihui 9:05f0b5a3a70a 82 static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
yihui 9:05f0b5a3a70a 83 /*
yihui 9:05f0b5a3a70a 84 // Copy and switch to dynamic vectors if first time called
yihui 9:05f0b5a3a70a 85 if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {
yihui 9:05f0b5a3a70a 86 uint32_t *old_vectors = (uint32_t *)0; // FLASH vectors are at 0x0
yihui 9:05f0b5a3a70a 87 for(i = 0; i < NVIC_NUM_VECTORS; i++) {
yihui 9:05f0b5a3a70a 88 vectors[i] = old_vectors[i];
yihui 9:05f0b5a3a70a 89 }
yihui 9:05f0b5a3a70a 90 LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block
yihui 9:05f0b5a3a70a 91 }*/
yihui 9:05f0b5a3a70a 92
yihui 9:05f0b5a3a70a 93 // Set the vector
yihui 9:05f0b5a3a70a 94 vectors[IRQn + 16] = vector;
yihui 9:05f0b5a3a70a 95 }
yihui 9:05f0b5a3a70a 96
yihui 9:05f0b5a3a70a 97 uint32_t NVIC_GetVector(IRQn_Type IRQn) {
yihui 9:05f0b5a3a70a 98 // We can always read vectors at 0x0, as the addresses are remapped
yihui 9:05f0b5a3a70a 99 uint32_t *vectors = (uint32_t*)0;
yihui 9:05f0b5a3a70a 100
yihui 9:05f0b5a3a70a 101 // Return the vector
yihui 9:05f0b5a3a70a 102 return vectors[IRQn + 16];
yihui 9:05f0b5a3a70a 103 }