Yuji Notsu / Mbed 2 deprecated MARMEX_Oled_GPS_3

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Dependencies:   TextLCD mbed

PowerControl/EthernetPowerControl.cpp@0:97f8ed953c0d, 2011-07-02 (annotated)

Committer:
y_notsu
Date:
Sat Jul 02 22:05:27 2011 +0000
Revision:
0:97f8ed953c0d
rev.0.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
y_notsu 0:97f8ed953c0d 1 #include "EthernetPowerControl.h"
y_notsu 0:97f8ed953c0d 2
y_notsu 0:97f8ed953c0d 3 static void write_PHY (unsigned int PhyReg, unsigned short Value) {
y_notsu 0:97f8ed953c0d 4 /* Write a data 'Value' to PHY register 'PhyReg'. */
y_notsu 0:97f8ed953c0d 5 unsigned int tout;
y_notsu 0:97f8ed953c0d 6 /* Hardware MII Management for LPC176x devices. */
y_notsu 0:97f8ed953c0d 7 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
y_notsu 0:97f8ed953c0d 8 LPC_EMAC->MWTD = Value;
y_notsu 0:97f8ed953c0d 9
y_notsu 0:97f8ed953c0d 10 /* Wait utill operation completed */
y_notsu 0:97f8ed953c0d 11 for (tout = 0; tout < MII_WR_TOUT; tout++) {
y_notsu 0:97f8ed953c0d 12 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
y_notsu 0:97f8ed953c0d 13 break;
y_notsu 0:97f8ed953c0d 14 }
y_notsu 0:97f8ed953c0d 15 }
y_notsu 0:97f8ed953c0d 16 }
y_notsu 0:97f8ed953c0d 17
y_notsu 0:97f8ed953c0d 18 static unsigned short read_PHY (unsigned int PhyReg) {
y_notsu 0:97f8ed953c0d 19 /* Read a PHY register 'PhyReg'. */
y_notsu 0:97f8ed953c0d 20 unsigned int tout, val;
y_notsu 0:97f8ed953c0d 21
y_notsu 0:97f8ed953c0d 22 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
y_notsu 0:97f8ed953c0d 23 LPC_EMAC->MCMD = MCMD_READ;
y_notsu 0:97f8ed953c0d 24
y_notsu 0:97f8ed953c0d 25 /* Wait until operation completed */
y_notsu 0:97f8ed953c0d 26 for (tout = 0; tout < MII_RD_TOUT; tout++) {
y_notsu 0:97f8ed953c0d 27 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
y_notsu 0:97f8ed953c0d 28 break;
y_notsu 0:97f8ed953c0d 29 }
y_notsu 0:97f8ed953c0d 30 }
y_notsu 0:97f8ed953c0d 31 LPC_EMAC->MCMD = 0;
y_notsu 0:97f8ed953c0d 32 val = LPC_EMAC->MRDD;
y_notsu 0:97f8ed953c0d 33
y_notsu 0:97f8ed953c0d 34 return (val);
y_notsu 0:97f8ed953c0d 35 }
y_notsu 0:97f8ed953c0d 36
y_notsu 0:97f8ed953c0d 37 void EMAC_Init()
y_notsu 0:97f8ed953c0d 38 {
y_notsu 0:97f8ed953c0d 39 unsigned int tout,regv;
y_notsu 0:97f8ed953c0d 40 /* Power Up the EMAC controller. */
y_notsu 0:97f8ed953c0d 41 Peripheral_PowerUp(LPC1768_PCONP_PCENET);
y_notsu 0:97f8ed953c0d 42
y_notsu 0:97f8ed953c0d 43 LPC_PINCON->PINSEL2 = 0x50150105;
y_notsu 0:97f8ed953c0d 44 LPC_PINCON->PINSEL3 &= ~0x0000000F;
y_notsu 0:97f8ed953c0d 45 LPC_PINCON->PINSEL3 |= 0x00000005;
y_notsu 0:97f8ed953c0d 46
y_notsu 0:97f8ed953c0d 47 /* Reset all EMAC internal modules. */
y_notsu 0:97f8ed953c0d 48 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
y_notsu 0:97f8ed953c0d 49 MAC1_SIM_RES | MAC1_SOFT_RES;
y_notsu 0:97f8ed953c0d 50 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
y_notsu 0:97f8ed953c0d 51
y_notsu 0:97f8ed953c0d 52 /* A short delay after reset. */
y_notsu 0:97f8ed953c0d 53 for (tout = 100; tout; tout--);
y_notsu 0:97f8ed953c0d 54
y_notsu 0:97f8ed953c0d 55 /* Initialize MAC control registers. */
y_notsu 0:97f8ed953c0d 56 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
y_notsu 0:97f8ed953c0d 57 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
y_notsu 0:97f8ed953c0d 58 LPC_EMAC->MAXF = ETH_MAX_FLEN;
y_notsu 0:97f8ed953c0d 59 LPC_EMAC->CLRT = CLRT_DEF;
y_notsu 0:97f8ed953c0d 60 LPC_EMAC->IPGR = IPGR_DEF;
y_notsu 0:97f8ed953c0d 61
y_notsu 0:97f8ed953c0d 62 /* Enable Reduced MII interface. */
y_notsu 0:97f8ed953c0d 63 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
y_notsu 0:97f8ed953c0d 64
y_notsu 0:97f8ed953c0d 65 /* Reset Reduced MII Logic. */
y_notsu 0:97f8ed953c0d 66 LPC_EMAC->SUPP = SUPP_RES_RMII;
y_notsu 0:97f8ed953c0d 67 for (tout = 100; tout; tout--);
y_notsu 0:97f8ed953c0d 68 LPC_EMAC->SUPP = 0;
y_notsu 0:97f8ed953c0d 69
y_notsu 0:97f8ed953c0d 70 /* Put the DP83848C in reset mode */
y_notsu 0:97f8ed953c0d 71 write_PHY (PHY_REG_BMCR, 0x8000);
y_notsu 0:97f8ed953c0d 72
y_notsu 0:97f8ed953c0d 73 /* Wait for hardware reset to end. */
y_notsu 0:97f8ed953c0d 74 for (tout = 0; tout < 0x100000; tout++) {
y_notsu 0:97f8ed953c0d 75 regv = read_PHY (PHY_REG_BMCR);
y_notsu 0:97f8ed953c0d 76 if (!(regv & 0x8000)) {
y_notsu 0:97f8ed953c0d 77 /* Reset complete */
y_notsu 0:97f8ed953c0d 78 break;
y_notsu 0:97f8ed953c0d 79 }
y_notsu 0:97f8ed953c0d 80 }
y_notsu 0:97f8ed953c0d 81 }
y_notsu 0:97f8ed953c0d 82
y_notsu 0:97f8ed953c0d 83
y_notsu 0:97f8ed953c0d 84 void PHY_PowerDown()
y_notsu 0:97f8ed953c0d 85 {
y_notsu 0:97f8ed953c0d 86 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
y_notsu 0:97f8ed953c0d 87 EMAC_Init(); //init EMAC if it is not already init'd
y_notsu 0:97f8ed953c0d 88
y_notsu 0:97f8ed953c0d 89 unsigned int regv;
y_notsu 0:97f8ed953c0d 90 regv = read_PHY(PHY_REG_BMCR);
y_notsu 0:97f8ed953c0d 91 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN));
y_notsu 0:97f8ed953c0d 92 regv = read_PHY(PHY_REG_BMCR);
y_notsu 0:97f8ed953c0d 93
y_notsu 0:97f8ed953c0d 94 //shouldn't need the EMAC now.
y_notsu 0:97f8ed953c0d 95 Peripheral_PowerDown(LPC1768_PCONP_PCENET);
y_notsu 0:97f8ed953c0d 96
y_notsu 0:97f8ed953c0d 97 //and turn off the PHY OSC
y_notsu 0:97f8ed953c0d 98 LPC_GPIO1->FIODIR |= 0x8000000;
y_notsu 0:97f8ed953c0d 99 LPC_GPIO1->FIOCLR = 0x8000000;
y_notsu 0:97f8ed953c0d 100 }
y_notsu 0:97f8ed953c0d 101
y_notsu 0:97f8ed953c0d 102 void PHY_PowerUp()
y_notsu 0:97f8ed953c0d 103 {
y_notsu 0:97f8ed953c0d 104 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
y_notsu 0:97f8ed953c0d 105 EMAC_Init(); //init EMAC if it is not already init'd
y_notsu 0:97f8ed953c0d 106
y_notsu 0:97f8ed953c0d 107 LPC_GPIO1->FIODIR |= 0x8000000;
y_notsu 0:97f8ed953c0d 108 LPC_GPIO1->FIOSET = 0x8000000;
y_notsu 0:97f8ed953c0d 109
y_notsu 0:97f8ed953c0d 110 //wait for osc to be stable
y_notsu 0:97f8ed953c0d 111 wait_ms(200);
y_notsu 0:97f8ed953c0d 112
y_notsu 0:97f8ed953c0d 113 unsigned int regv;
y_notsu 0:97f8ed953c0d 114 regv = read_PHY(PHY_REG_BMCR);
y_notsu 0:97f8ed953c0d 115 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
y_notsu 0:97f8ed953c0d 116 regv = read_PHY(PHY_REG_BMCR);
y_notsu 0:97f8ed953c0d 117 }
y_notsu 0:97f8ed953c0d 118
y_notsu 0:97f8ed953c0d 119 void PHY_EnergyDetect_Enable()
y_notsu 0:97f8ed953c0d 120 {
y_notsu 0:97f8ed953c0d 121 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
y_notsu 0:97f8ed953c0d 122 EMAC_Init(); //init EMAC if it is not already init'd
y_notsu 0:97f8ed953c0d 123
y_notsu 0:97f8ed953c0d 124 unsigned int regv;
y_notsu 0:97f8ed953c0d 125 regv = read_PHY(PHY_REG_EDCR);
y_notsu 0:97f8ed953c0d 126 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE));
y_notsu 0:97f8ed953c0d 127 regv = read_PHY(PHY_REG_EDCR);
y_notsu 0:97f8ed953c0d 128 }
y_notsu 0:97f8ed953c0d 129
y_notsu 0:97f8ed953c0d 130 void PHY_EnergyDetect_Disable()
y_notsu 0:97f8ed953c0d 131 {
y_notsu 0:97f8ed953c0d 132 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
y_notsu 0:97f8ed953c0d 133 EMAC_Init(); //init EMAC if it is not already init'd
y_notsu 0:97f8ed953c0d 134 unsigned int regv;
y_notsu 0:97f8ed953c0d 135 regv = read_PHY(PHY_REG_EDCR);
y_notsu 0:97f8ed953c0d 136 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
y_notsu 0:97f8ed953c0d 137 regv = read_PHY(PHY_REG_EDCR);
y_notsu 0:97f8ed953c0d 138 }