Yuji Notsu / Mbed 2 deprecated MARMEX_Oled_GPS_3

This program is for mbed-Geiger counter system. It use OLED module, GPS module (with RTC), TextLCD, SD FileSystem and some Interrupt pin.

Dependencies:   TextLCD mbed

PowerControl/PowerControl.h@0:97f8ed953c0d, 2011-07-02 (annotated)

Committer:
y_notsu
Date:
Sat Jul 02 22:05:27 2011 +0000
Revision:
0:97f8ed953c0d
rev.0.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
y_notsu 0:97f8ed953c0d 1 /* mbed PowerControl Library
y_notsu 0:97f8ed953c0d 2 * Copyright (c) 2010 Michael Wei
y_notsu 0:97f8ed953c0d 3 */
y_notsu 0:97f8ed953c0d 4
y_notsu 0:97f8ed953c0d 5 #ifndef MBED_POWERCONTROL_H
y_notsu 0:97f8ed953c0d 6 #define MBED_POWERCONTROL_H
y_notsu 0:97f8ed953c0d 7
y_notsu 0:97f8ed953c0d 8 //shouldn't have to include, but fixes weird problems with defines
y_notsu 0:97f8ed953c0d 9 #include "LPC1768/LPC17xx.h"
y_notsu 0:97f8ed953c0d 10
y_notsu 0:97f8ed953c0d 11 //System Control Register
y_notsu 0:97f8ed953c0d 12 // bit 0: Reserved
y_notsu 0:97f8ed953c0d 13 // bit 1: Sleep on Exit
y_notsu 0:97f8ed953c0d 14 #define LPC1768_SCR_SLEEPONEXIT 0x2
y_notsu 0:97f8ed953c0d 15 // bit 2: Deep Sleep
y_notsu 0:97f8ed953c0d 16 #define LPC1768_SCR_SLEEPDEEP 0x4
y_notsu 0:97f8ed953c0d 17 // bit 3: Resereved
y_notsu 0:97f8ed953c0d 18 // bit 4: Send on Pending
y_notsu 0:97f8ed953c0d 19 #define LPC1768_SCR_SEVONPEND 0x10
y_notsu 0:97f8ed953c0d 20 // bit 5-31: Reserved
y_notsu 0:97f8ed953c0d 21
y_notsu 0:97f8ed953c0d 22 //Power Control Register
y_notsu 0:97f8ed953c0d 23 // bit 0: Power mode control bit 0 (power-down mode)
y_notsu 0:97f8ed953c0d 24 #define LPC1768_PCON_PM0 0x1
y_notsu 0:97f8ed953c0d 25 // bit 1: Power mode control bit 1 (deep power-down mode)
y_notsu 0:97f8ed953c0d 26 #define LPC1768_PCON_PM1 0x2
y_notsu 0:97f8ed953c0d 27 // bit 2: Brown-out reduced power mode
y_notsu 0:97f8ed953c0d 28 #define LPC1768_PCON_BODRPM 0x4
y_notsu 0:97f8ed953c0d 29 // bit 3: Brown-out global disable
y_notsu 0:97f8ed953c0d 30 #define LPC1768_PCON_BOGD 0x8
y_notsu 0:97f8ed953c0d 31 // bit 4: Brown-out reset disable
y_notsu 0:97f8ed953c0d 32 #define LPC1768_PCON_BORD 0x10
y_notsu 0:97f8ed953c0d 33 // bit 5-7 : Reserved
y_notsu 0:97f8ed953c0d 34 // bit 8: Sleep Mode Entry Flag
y_notsu 0:97f8ed953c0d 35 #define LPC1768_PCON_SMFLAG 0x100
y_notsu 0:97f8ed953c0d 36 // bit 9: Deep Sleep Entry Flag
y_notsu 0:97f8ed953c0d 37 #define LPC1768_PCON_DSFLAG 0x200
y_notsu 0:97f8ed953c0d 38 // bit 10: Power Down Entry Flag
y_notsu 0:97f8ed953c0d 39 #define LPC1768_PCON_PDFLAG 0x400
y_notsu 0:97f8ed953c0d 40 // bit 11: Deep Power Down Entry Flag
y_notsu 0:97f8ed953c0d 41 #define LPC1768_PCON_DPDFLAG 0x800
y_notsu 0:97f8ed953c0d 42 // bit 12-31: Reserved
y_notsu 0:97f8ed953c0d 43
y_notsu 0:97f8ed953c0d 44 //"Sleep Mode" (WFI).
y_notsu 0:97f8ed953c0d 45 inline void Sleep(void)
y_notsu 0:97f8ed953c0d 46 {
y_notsu 0:97f8ed953c0d 47 __WFI();
y_notsu 0:97f8ed953c0d 48 }
y_notsu 0:97f8ed953c0d 49
y_notsu 0:97f8ed953c0d 50 //"Deep Sleep" Mode
y_notsu 0:97f8ed953c0d 51 inline void DeepSleep(void)
y_notsu 0:97f8ed953c0d 52 {
y_notsu 0:97f8ed953c0d 53 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
y_notsu 0:97f8ed953c0d 54 __WFI();
y_notsu 0:97f8ed953c0d 55 }
y_notsu 0:97f8ed953c0d 56
y_notsu 0:97f8ed953c0d 57 //"Power-Down" Mode
y_notsu 0:97f8ed953c0d 58 inline void PowerDown(void)
y_notsu 0:97f8ed953c0d 59 {
y_notsu 0:97f8ed953c0d 60 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
y_notsu 0:97f8ed953c0d 61 LPC_SC->PCON &= ~LPC1768_PCON_PM1;
y_notsu 0:97f8ed953c0d 62 LPC_SC->PCON |= LPC1768_PCON_PM0;
y_notsu 0:97f8ed953c0d 63 __WFI();
y_notsu 0:97f8ed953c0d 64 //reset back to normal
y_notsu 0:97f8ed953c0d 65 LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
y_notsu 0:97f8ed953c0d 66 }
y_notsu 0:97f8ed953c0d 67
y_notsu 0:97f8ed953c0d 68 //"Deep Power-Down" Mode
y_notsu 0:97f8ed953c0d 69 inline void DeepPowerDown(void)
y_notsu 0:97f8ed953c0d 70 {
y_notsu 0:97f8ed953c0d 71 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
y_notsu 0:97f8ed953c0d 72 LPC_SC->PCON |= LPC1768_PCON_PM1 | LPC1768_PCON_PM0;
y_notsu 0:97f8ed953c0d 73 __WFI();
y_notsu 0:97f8ed953c0d 74 //reset back to normal
y_notsu 0:97f8ed953c0d 75 LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
y_notsu 0:97f8ed953c0d 76 }
y_notsu 0:97f8ed953c0d 77
y_notsu 0:97f8ed953c0d 78 //shut down BOD during power-down/deep sleep
y_notsu 0:97f8ed953c0d 79 inline void BrownOut_ReducedPowerMode_Enable(void)
y_notsu 0:97f8ed953c0d 80 {
y_notsu 0:97f8ed953c0d 81 LPC_SC->PCON |= LPC1768_PCON_BODRPM;
y_notsu 0:97f8ed953c0d 82 }
y_notsu 0:97f8ed953c0d 83
y_notsu 0:97f8ed953c0d 84 //turn on BOD during power-down/deep sleep
y_notsu 0:97f8ed953c0d 85 inline void BrownOut_ReducedPowerMode_Disable(void)
y_notsu 0:97f8ed953c0d 86 {
y_notsu 0:97f8ed953c0d 87 LPC_SC->PCON &= ~LPC1768_PCON_BODRPM;
y_notsu 0:97f8ed953c0d 88 }
y_notsu 0:97f8ed953c0d 89
y_notsu 0:97f8ed953c0d 90 //turn off brown out circutry
y_notsu 0:97f8ed953c0d 91 inline void BrownOut_Global_Disable(void)
y_notsu 0:97f8ed953c0d 92 {
y_notsu 0:97f8ed953c0d 93 LPC_SC->PCON |= LPC1768_PCON_BOGD;
y_notsu 0:97f8ed953c0d 94 }
y_notsu 0:97f8ed953c0d 95
y_notsu 0:97f8ed953c0d 96 //turn on brown out circutry
y_notsu 0:97f8ed953c0d 97 inline void BrownOut_Global_Enable(void)
y_notsu 0:97f8ed953c0d 98 {
y_notsu 0:97f8ed953c0d 99 LPC_SC->PCON &= !LPC1768_PCON_BOGD;
y_notsu 0:97f8ed953c0d 100 }
y_notsu 0:97f8ed953c0d 101
y_notsu 0:97f8ed953c0d 102 //turn off brown out reset circutry
y_notsu 0:97f8ed953c0d 103 inline void BrownOut_Reset_Disable(void)
y_notsu 0:97f8ed953c0d 104 {
y_notsu 0:97f8ed953c0d 105 LPC_SC->PCON |= LPC1768_PCON_BORD;
y_notsu 0:97f8ed953c0d 106 }
y_notsu 0:97f8ed953c0d 107
y_notsu 0:97f8ed953c0d 108 //turn on brown outreset circutry
y_notsu 0:97f8ed953c0d 109 inline void BrownOut_Reset_Enable(void)
y_notsu 0:97f8ed953c0d 110 {
y_notsu 0:97f8ed953c0d 111 LPC_SC->PCON &= ~LPC1768_PCON_BORD;
y_notsu 0:97f8ed953c0d 112 }
y_notsu 0:97f8ed953c0d 113 //Peripheral Control Register
y_notsu 0:97f8ed953c0d 114 // bit 0: Reserved
y_notsu 0:97f8ed953c0d 115 // bit 1: PCTIM0: Timer/Counter 0 power/clock enable
y_notsu 0:97f8ed953c0d 116 #define LPC1768_PCONP_PCTIM0 0x2
y_notsu 0:97f8ed953c0d 117 // bit 2: PCTIM1: Timer/Counter 1 power/clock enable
y_notsu 0:97f8ed953c0d 118 #define LPC1768_PCONP_PCTIM1 0x4
y_notsu 0:97f8ed953c0d 119 // bit 3: PCUART0: UART 0 power/clock enable
y_notsu 0:97f8ed953c0d 120 #define LPC1768_PCONP_PCUART0 0x8
y_notsu 0:97f8ed953c0d 121 // bit 4: PCUART1: UART 1 power/clock enable
y_notsu 0:97f8ed953c0d 122 #define LPC1768_PCONP_PCUART1 0x10
y_notsu 0:97f8ed953c0d 123 // bit 5: Reserved
y_notsu 0:97f8ed953c0d 124 // bit 6: PCPWM1: PWM 1 power/clock enable
y_notsu 0:97f8ed953c0d 125 #define LPC1768_PCONP_PCPWM1 0x40
y_notsu 0:97f8ed953c0d 126 // bit 7: PCI2C0: I2C interface 0 power/clock enable
y_notsu 0:97f8ed953c0d 127 #define LPC1768_PCONP_PCI2C0 0x80
y_notsu 0:97f8ed953c0d 128 // bit 8: PCSPI: SPI interface power/clock enable
y_notsu 0:97f8ed953c0d 129 #define LPC1768_PCONP_PCSPI 0x100
y_notsu 0:97f8ed953c0d 130 // bit 9: PCRTC: RTC power/clock enable
y_notsu 0:97f8ed953c0d 131 #define LPC1768_PCONP_PCRTC 0x200
y_notsu 0:97f8ed953c0d 132 // bit 10: PCSSP1: SSP interface 1 power/clock enable
y_notsu 0:97f8ed953c0d 133 #define LPC1768_PCONP_PCSSP1 0x400
y_notsu 0:97f8ed953c0d 134 // bit 11: Reserved
y_notsu 0:97f8ed953c0d 135 // bit 12: PCADC: A/D converter power/clock enable
y_notsu 0:97f8ed953c0d 136 #define LPC1768_PCONP_PCADC 0x1000
y_notsu 0:97f8ed953c0d 137 // bit 13: PCCAN1: CAN controller 1 power/clock enable
y_notsu 0:97f8ed953c0d 138 #define LPC1768_PCONP_PCCAN1 0x2000
y_notsu 0:97f8ed953c0d 139 // bit 14: PCCAN2: CAN controller 2 power/clock enable
y_notsu 0:97f8ed953c0d 140 #define LPC1768_PCONP_PCCAN2 0x4000
y_notsu 0:97f8ed953c0d 141 // bit 15: PCGPIO: GPIOs power/clock enable
y_notsu 0:97f8ed953c0d 142 #define LPC1768_PCONP_PCGPIO 0x8000
y_notsu 0:97f8ed953c0d 143 // bit 16: PCRIT: Repetitive interrupt timer power/clock enable
y_notsu 0:97f8ed953c0d 144 #define LPC1768_PCONP_PCRIT 0x10000
y_notsu 0:97f8ed953c0d 145 // bit 17: PCMCPWM: Motor control PWM power/clock enable
y_notsu 0:97f8ed953c0d 146 #define LPC1768_PCONP_PCMCPWM 0x20000
y_notsu 0:97f8ed953c0d 147 // bit 18: PCQEI: Quadrature encoder interface power/clock enable
y_notsu 0:97f8ed953c0d 148 #define LPC1768_PCONP_PCQEI 0x40000
y_notsu 0:97f8ed953c0d 149 // bit 19: PCI2C1: I2C interface 1 power/clock enable
y_notsu 0:97f8ed953c0d 150 #define LPC1768_PCONP_PCI2C1 0x80000
y_notsu 0:97f8ed953c0d 151 // bit 20: Reserved
y_notsu 0:97f8ed953c0d 152 // bit 21: PCSSP0: SSP interface 0 power/clock enable
y_notsu 0:97f8ed953c0d 153 #define LPC1768_PCONP_PCSSP0 0x200000
y_notsu 0:97f8ed953c0d 154 // bit 22: PCTIM2: Timer 2 power/clock enable
y_notsu 0:97f8ed953c0d 155 #define LPC1768_PCONP_PCTIM2 0x400000
y_notsu 0:97f8ed953c0d 156 // bit 23: PCTIM3: Timer 3 power/clock enable
y_notsu 0:97f8ed953c0d 157 #define LPC1768_PCONP_PCQTIM3 0x800000
y_notsu 0:97f8ed953c0d 158 // bit 24: PCUART2: UART 2 power/clock enable
y_notsu 0:97f8ed953c0d 159 #define LPC1768_PCONP_PCUART2 0x1000000
y_notsu 0:97f8ed953c0d 160 // bit 25: PCUART3: UART 3 power/clock enable
y_notsu 0:97f8ed953c0d 161 #define LPC1768_PCONP_PCUART3 0x2000000
y_notsu 0:97f8ed953c0d 162 // bit 26: PCI2C2: I2C interface 2 power/clock enable
y_notsu 0:97f8ed953c0d 163 #define LPC1768_PCONP_PCI2C2 0x4000000
y_notsu 0:97f8ed953c0d 164 // bit 27: PCI2S: I2S interface power/clock enable
y_notsu 0:97f8ed953c0d 165 #define LPC1768_PCONP_PCI2S 0x8000000
y_notsu 0:97f8ed953c0d 166 // bit 28: Reserved
y_notsu 0:97f8ed953c0d 167 // bit 29: PCGPDMA: GP DMA function power/clock enable
y_notsu 0:97f8ed953c0d 168 #define LPC1768_PCONP_PCGPDMA 0x20000000
y_notsu 0:97f8ed953c0d 169 // bit 30: PCENET: Ethernet block power/clock enable
y_notsu 0:97f8ed953c0d 170 #define LPC1768_PCONP_PCENET 0x40000000
y_notsu 0:97f8ed953c0d 171 // bit 31: PCUSB: USB interface power/clock enable
y_notsu 0:97f8ed953c0d 172 #define LPC1768_PCONP_PCUSB 0x80000000
y_notsu 0:97f8ed953c0d 173
y_notsu 0:97f8ed953c0d 174 //Powers Up specified Peripheral(s)
y_notsu 0:97f8ed953c0d 175 inline unsigned int Peripheral_PowerUp(unsigned int bitMask)
y_notsu 0:97f8ed953c0d 176 {
y_notsu 0:97f8ed953c0d 177 return LPC_SC->PCONP |= bitMask;
y_notsu 0:97f8ed953c0d 178 }
y_notsu 0:97f8ed953c0d 179
y_notsu 0:97f8ed953c0d 180 //Powers Down specified Peripheral(s)
y_notsu 0:97f8ed953c0d 181 inline unsigned int Peripheral_PowerDown(unsigned int bitMask)
y_notsu 0:97f8ed953c0d 182 {
y_notsu 0:97f8ed953c0d 183 return LPC_SC->PCONP &= ~bitMask;
y_notsu 0:97f8ed953c0d 184 }
y_notsu 0:97f8ed953c0d 185
y_notsu 0:97f8ed953c0d 186 //returns if the peripheral is on or off
y_notsu 0:97f8ed953c0d 187 inline bool Peripheral_GetStatus(unsigned int peripheral)
y_notsu 0:97f8ed953c0d 188 {
y_notsu 0:97f8ed953c0d 189 return (LPC_SC->PCONP & peripheral) ? true : false;
y_notsu 0:97f8ed953c0d 190 }
y_notsu 0:97f8ed953c0d 191
y_notsu 0:97f8ed953c0d 192 #endif