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mbed-os

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targets/TARGET_ONSEMI/TARGET_NCS36510/objects.h@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

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elessair 0:f269e3021894 1 /**
elessair 0:f269e3021894 2 ******************************************************************************
elessair 0:f269e3021894 3 * @file Objects.h
elessair 0:f269e3021894 4 * @brief Implements an assertion.
elessair 0:f269e3021894 5 * @internal
elessair 0:f269e3021894 6 * @author ON Semiconductor
elessair 0:f269e3021894 7 * $Rev: 0.1 $
elessair 0:f269e3021894 8 * $Date: 2015-11-06 $
elessair 0:f269e3021894 9 ******************************************************************************
elessair 0:f269e3021894 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
elessair 0:f269e3021894 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
elessair 0:f269e3021894 12 * under limited terms and conditions. The terms and conditions pertaining to the software
elessair 0:f269e3021894 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
elessair 0:f269e3021894 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
elessair 0:f269e3021894 15 * if applicable the software license agreement. Do not use this software and/or
elessair 0:f269e3021894 16 * documentation unless you have carefully read and you agree to the limited terms and
elessair 0:f269e3021894 17 * conditions. By using this software and/or documentation, you agree to the limited
elessair 0:f269e3021894 18 * terms and conditions.
elessair 0:f269e3021894 19 *
elessair 0:f269e3021894 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
elessair 0:f269e3021894 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
elessair 0:f269e3021894 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
elessair 0:f269e3021894 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
elessair 0:f269e3021894 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
elessair 0:f269e3021894 25 * @endinternal
elessair 0:f269e3021894 26 *
elessair 0:f269e3021894 27 * @ingroup debug
elessair 0:f269e3021894 28 */
elessair 0:f269e3021894 29 #ifndef OBJECTS_H_
elessair 0:f269e3021894 30 #define OBJECTS_H_
elessair 0:f269e3021894 31
elessair 0:f269e3021894 32
elessair 0:f269e3021894 33 #ifdef __cplusplus
elessair 0:f269e3021894 34 extern "C" {
elessair 0:f269e3021894 35 #endif
elessair 0:f269e3021894 36
elessair 0:f269e3021894 37 #include "gpio_map.h"
elessair 0:f269e3021894 38 #include "uart_16c550_map.h"
elessair 0:f269e3021894 39 #include "PinNames.h"
elessair 0:f269e3021894 40 #include "PortNames.h"
elessair 0:f269e3021894 41 #include "PeripheralNames.h"
elessair 0:f269e3021894 42 #include "target_config.h"
elessair 0:f269e3021894 43 #include "spi.h"
elessair 0:f269e3021894 44
elessair 0:f269e3021894 45 typedef enum {
elessair 0:f269e3021894 46 FlowControlNone_1,
elessair 0:f269e3021894 47 FlowControlRTS_1,
elessair 0:f269e3021894 48 FlowControlCTS_1,
elessair 0:f269e3021894 49 FlowControlRTSCTS_1
elessair 0:f269e3021894 50 } FlowControl_1;
elessair 0:f269e3021894 51
elessair 0:f269e3021894 52 struct serial_s {
elessair 0:f269e3021894 53 Uart16C550Reg_pt UARTREG;
elessair 0:f269e3021894 54 FlowControl_1 FlowCtrl;
elessair 0:f269e3021894 55 IRQn_Type IRQType;
elessair 0:f269e3021894 56 int index;
elessair 0:f269e3021894 57 };
elessair 0:f269e3021894 58
elessair 0:f269e3021894 59 typedef struct _gpio_t {
elessair 0:f269e3021894 60 GpioReg_pt GPIOMEMBASE;
elessair 0:f269e3021894 61 PinName gpioPin;
elessair 0:f269e3021894 62 uint32_t gpioMask;
elessair 0:f269e3021894 63
elessair 0:f269e3021894 64 } gpio_t;
elessair 0:f269e3021894 65
elessair 0:f269e3021894 66
elessair 0:f269e3021894 67 /* TODO: This is currently a dummy structure; implementation will be done along
elessair 0:f269e3021894 68 * with the sleep API implementation
elessair 0:f269e3021894 69 */
elessair 0:f269e3021894 70 typedef struct sleep_s {
elessair 0:f269e3021894 71 uint32_t timeToSleep; /* 0: Use sleep type variable to select low power mode; Noz-zero: Selects sleep type based on timeToSleep duration using table 1. sleep below */
elessair 0:f269e3021894 72 uint8_t SleepType; /* 0: Sleep; 1: DeepSleep; 2: Coma */
elessair 0:f269e3021894 73 } sleep_t;
elessair 0:f269e3021894 74
elessair 0:f269e3021894 75 /* Table 1. Sleep
elessair 0:f269e3021894 76 ___________________________________________________________________________________
elessair 0:f269e3021894 77 | Sleep duration | Sleep Type |
elessair 0:f269e3021894 78 |-------------------------------------------------------------------|---------------|
elessair 0:f269e3021894 79 | > Zero AND <= SLEEP_DURATION_SLEEP_MAX | sleep |
elessair 0:f269e3021894 80 | > SLEEP_DURATION_SLEEP_MAX AND <= SLEEP_DURATION_DEEPSLEEP_MAX | deepsleep |
elessair 0:f269e3021894 81 | > SLEEP_DURATION_DEEPSLEEP_MAX | coma |
elessair 0:f269e3021894 82 |___________________________________________________________________|_______________|
elessair 0:f269e3021894 83
elessair 0:f269e3021894 84 */
elessair 0:f269e3021894 85
elessair 0:f269e3021894 86 struct gpio_irq_s {
elessair 0:f269e3021894 87 uint32_t pin;
elessair 0:f269e3021894 88 uint32_t pinMask;
elessair 0:f269e3021894 89 GpioReg_pt GPIOMEMBASE;
elessair 0:f269e3021894 90 };
elessair 0:f269e3021894 91
elessair 0:f269e3021894 92 typedef struct {
elessair 0:f269e3021894 93
elessair 0:f269e3021894 94 /* options to configure the ADC */
elessair 0:f269e3021894 95 uint8_t interruptConfig; /**< 1= interrupt Enable 0=Interrupt Disable */
elessair 0:f269e3021894 96 uint8_t PrescaleVal; /**< Prescaler: Sets the converter clock frequency. Fclk = 32 MHz/(prescaler + 1) where prescaler is the value of this register segment. The minimum tested value is 07 (4 MHz clock) */
elessair 0:f269e3021894 97 uint8_t measurementType; /**< 1= Absolute 0= Differential */
elessair 0:f269e3021894 98 uint8_t mode; /**< 1= Continuous Conversion 0= Single Shot */
elessair 0:f269e3021894 99 uint8_t referenceCh; /**< Selects 1 to 8 channels for reference channel */
elessair 0:f269e3021894 100 uint8_t convCh; /**< Selects 1 or 8 channels to do a conversion on.*/
elessair 0:f269e3021894 101 uint8_t inputScale; /**< Sets the input scale, 000 ? 1.0, 001 ? 0.6923, 010 ? 0.5294, 011 ? 0.4286, 100 ? 0.3600, 101 ? 0.3103, 110 ? 0.2728, 111 ? 0.2432 */
elessair 0:f269e3021894 102 uint8_t samplingTime; /**< Sample Time. Sets the measure time in units of PCLKperiod * (Prescale + 1).*/
elessair 0:f269e3021894 103 uint8_t WarmUpTime; /**< The number of converter clock cycles that the state machine dwells in the warm or warm_meas state */
elessair 0:f269e3021894 104 uint16_t samplingRate; /**< Sets the sample rate in units of PCLKperiod * (Prescale + 1). */
elessair 0:f269e3021894 105
elessair 0:f269e3021894 106 } analog_config_s;
elessair 0:f269e3021894 107
elessair 0:f269e3021894 108 struct analogin_s {
elessair 0:f269e3021894 109
elessair 0:f269e3021894 110 analog_config_s *adcConf;
elessair 0:f269e3021894 111 AdcReg_pt adcReg;
elessair 0:f269e3021894 112 PinName pin;
elessair 0:f269e3021894 113 uint8_t pinFlag;
elessair 0:f269e3021894 114 };
elessair 0:f269e3021894 115
elessair 0:f269e3021894 116 struct pwmout_s {
elessair 0:f269e3021894 117
elessair 0:f269e3021894 118 PwmReg_pt pwmReg;
elessair 0:f269e3021894 119 };
elessair 0:f269e3021894 120
elessair 0:f269e3021894 121 struct port_s {
elessair 0:f269e3021894 122 GpioReg_pt GPIOMEMBASE;
elessair 0:f269e3021894 123 PortName port;
elessair 0:f269e3021894 124 uint32_t mask;
elessair 0:f269e3021894 125 };
elessair 0:f269e3021894 126
elessair 0:f269e3021894 127 typedef enum {
elessair 0:f269e3021894 128 littleEndian = 0,
elessair 0:f269e3021894 129 bigEndian
elessair 0:f269e3021894 130 } spi_ipc7207_endian_t, *spi_ipc7207_endian_pt;
elessair 0:f269e3021894 131
elessair 0:f269e3021894 132 /** Type for the clock polarity. */
elessair 0:f269e3021894 133 typedef enum {
elessair 0:f269e3021894 134 activeLow = 0,
elessair 0:f269e3021894 135 activeHigh
elessair 0:f269e3021894 136 } spi_clockPolarity_t, *spi_clockPolarity_pt;
elessair 0:f269e3021894 137
elessair 0:f269e3021894 138 /** Type for the clock phase. */
elessair 0:f269e3021894 139 typedef enum {
elessair 0:f269e3021894 140 risingEdge = 0,
elessair 0:f269e3021894 141 fallingEdge
elessair 0:f269e3021894 142 } spi_clockPhase_t, *spi_clockPhase_pt;
elessair 0:f269e3021894 143
elessair 0:f269e3021894 144 struct spi_s {
elessair 0:f269e3021894 145 SpiIpc7207Reg_pt membase; /* Register address */
elessair 0:f269e3021894 146 IRQn_Type irq; /* IRQ number of the IRQ associated to the device. */
elessair 0:f269e3021894 147 uint8_t irqEnable; /* IRQ enables for 8 IRQ sources:
elessair 0:f269e3021894 148 * - bit 7 = Receive FIFO Full
elessair 0:f269e3021894 149 * - bit 6 = Receive FIFO 'Half' Full (watermark level)
elessair 0:f269e3021894 150 * - bit 5 = Receive FIFO Not Empty
elessair 0:f269e3021894 151 * - bit 4 = Transmit FIFO Not Full
elessair 0:f269e3021894 152 * - bit 3 = Transmit FIFO 'Half' Empty (watermark level)
elessair 0:f269e3021894 153 * - bit 2 = Transmit FIFO Empty
elessair 0:f269e3021894 154 * - bit 1 = Transfer Error
elessair 0:f269e3021894 155 * - bit 0 = ssIn (conditionally inverted and synchronized to PCLK)
elessair 0:f269e3021894 156 * (unused option in current implementation / irq 6 and 7 used) */
elessair 0:f269e3021894 157 uint8_t slaveSelectEnable; /* Slave Select enables (x4):
elessair 0:f269e3021894 158 * - 0 (x4) = Slave select enable
elessair 0:f269e3021894 159 * - 1 (x4) = Slave select disable */
elessair 0:f269e3021894 160 uint8_t slaveSelectBurst; /* Slave Select burst mode:
elessair 0:f269e3021894 161 * - NO_BURST_MODE = Burst mode disable
elessair 0:f269e3021894 162 * - BURST_MODE = Burst mode enable */
elessair 0:f269e3021894 163 uint8_t slaveSelectPolarity; /* Slave Select polarity (x4) for up to 4 slaves:
elessair 0:f269e3021894 164 * - 0 (x4) = Slave select is active low
elessair 0:f269e3021894 165 * - 1 (x4) = Slave select is active high */
elessair 0:f269e3021894 166 uint8_t txWatermark; /* Transmit FIFO Watermark: Defines level of RX Half Full Flag
elessair 0:f269e3021894 167 * - Value between 1 and 15
elessair 0:f269e3021894 168 * (unused option in current implementation / not txWatermark irq used) */
elessair 0:f269e3021894 169 uint8_t rxWatermark; /* Receive FIFO Watermark: Defines level of TX Half Full Flag:
elessair 0:f269e3021894 170 * - Value between 1 and 15
elessair 0:f269e3021894 171 * * (unused option in current implementation / rxWatermark fixed to 1) */
elessair 0:f269e3021894 172 spi_ipc7207_endian_t endian; /* Bits endianness:
elessair 0:f269e3021894 173 * - LITTLE_ENDIAN = LSB first
elessair 0:f269e3021894 174 * - BIG_ENDIAN = MSB first */
elessair 0:f269e3021894 175 uint8_t samplingEdge; /* SDI sampling edge (relative to SDO sampling edge):
elessair 0:f269e3021894 176 * - 0 = opposite to SDO sampling edge
elessair 0:f269e3021894 177 * - 1 = same as SDO sampling edge */
elessair 0:f269e3021894 178 uint32_t baudrate; /* The expected baud rate. */
elessair 0:f269e3021894 179 spi_clockPolarity_t clockPolarity; /* The clock polarity (active high or low). */
elessair 0:f269e3021894 180 spi_clockPhase_t clockPhase; /* The clock phase (sample on rising or falling edge). */
elessair 0:f269e3021894 181 uint8_t wordSize; /* The size word size in number of bits. */
elessair 0:f269e3021894 182 uint8_t Mode;
elessair 0:f269e3021894 183 uint32_t event;
elessair 0:f269e3021894 184 };
elessair 0:f269e3021894 185
elessair 0:f269e3021894 186 struct i2c_s {
elessair 0:f269e3021894 187 uint32_t baudrate; /**< The expected baud rate. */
elessair 0:f269e3021894 188 uint32_t I2cStatusFromInt;
elessair 0:f269e3021894 189 uint8_t ClockSource; /**< I2C clock source, 0 – clkI2C pin, 1 – PCLK */
elessair 0:f269e3021894 190 uint8_t irqEnable; /**< IRQs to be enabled */
elessair 0:f269e3021894 191 I2cIpc7208Reg_pt membase; /**< The memory base for the device's registers. */
elessair 0:f269e3021894 192 IRQn_Type irq; /**< The IRQ number of the IRQ associated to the device. */
elessair 0:f269e3021894 193 //queue_pt rxQueue; /**< The receive queue for the device instance. */
elessair 0:f269e3021894 194 };
elessair 0:f269e3021894 195
elessair 0:f269e3021894 196 #ifdef __cplusplus
elessair 0:f269e3021894 197 }
elessair 0:f269e3021894 198 #endif
elessair 0:f269e3021894 199
elessair 0:f269e3021894 200 #endif //OBJECTS_H_