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targets/TARGET_ONSEMI/TARGET_NCS36510/dma_map.h@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

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elessair 0:f269e3021894 1 /**
elessair 0:f269e3021894 2 ******************************************************************************
elessair 0:f269e3021894 3 * @file dma_map.h
elessair 0:f269e3021894 4 * @brief DMA hw module register map
elessair 0:f269e3021894 5 * @internal
elessair 0:f269e3021894 6 * @author ON Semiconductor
elessair 0:f269e3021894 7 * $Rev: 3415 $
elessair 0:f269e3021894 8 * $Date: 2015-06-05 13:29:52 +0530 (Fri, 05 Jun 2015) $
elessair 0:f269e3021894 9 ******************************************************************************
elessair 0:f269e3021894 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
elessair 0:f269e3021894 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
elessair 0:f269e3021894 12 * under limited terms and conditions. The terms and conditions pertaining to the software
elessair 0:f269e3021894 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
elessair 0:f269e3021894 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
elessair 0:f269e3021894 15 * if applicable the software license agreement. Do not use this software and/or
elessair 0:f269e3021894 16 * documentation unless you have carefully read and you agree to the limited terms and
elessair 0:f269e3021894 17 * conditions. By using this software and/or documentation, you agree to the limited
elessair 0:f269e3021894 18 * terms and conditions.
elessair 0:f269e3021894 19 *
elessair 0:f269e3021894 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
elessair 0:f269e3021894 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
elessair 0:f269e3021894 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
elessair 0:f269e3021894 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
elessair 0:f269e3021894 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
elessair 0:f269e3021894 25 * @endinternal
elessair 0:f269e3021894 26 *
elessair 0:f269e3021894 27 * @ingroup dma
elessair 0:f269e3021894 28 *
elessair 0:f269e3021894 29 * @details
elessair 0:f269e3021894 30 */
elessair 0:f269e3021894 31
elessair 0:f269e3021894 32 #ifndef DMA_MAP_H_
elessair 0:f269e3021894 33 #define DMA_MAP_H_
elessair 0:f269e3021894 34
elessair 0:f269e3021894 35 /*************************************************************************************************
elessair 0:f269e3021894 36 * *
elessair 0:f269e3021894 37 * Header files *
elessair 0:f269e3021894 38 * *
elessair 0:f269e3021894 39 *************************************************************************************************/
elessair 0:f269e3021894 40
elessair 0:f269e3021894 41 #include "architecture.h"
elessair 0:f269e3021894 42
elessair 0:f269e3021894 43 /**************************************************************************************************
elessair 0:f269e3021894 44 * *
elessair 0:f269e3021894 45 * Type definitions *
elessair 0:f269e3021894 46 * *
elessair 0:f269e3021894 47 **************************************************************************************************/
elessair 0:f269e3021894 48
elessair 0:f269e3021894 49 /** DMA control HW registers structure overlay */
elessair 0:f269e3021894 50 #ifdef REVB
elessair 0:f269e3021894 51 typedef struct {
elessair 0:f269e3021894 52 __IO uint32_t CONTROL; /**< Write 1 to enable DMA, write 0 to disable */
elessair 0:f269e3021894 53 __IO uint32_t SOURCE; /**< Address of source, read to get the number of bytes written */
elessair 0:f269e3021894 54 __IO uint32_t DESTINATION; /**< Address of destination, read to get the number of bytes written */
elessair 0:f269e3021894 55 __IO uint32_t SIZE; /**< Lenght of the entire transfer */
elessair 0:f269e3021894 56 __IO uint32_t STATUS; /**< To be debined */
elessair 0:f269e3021894 57 __IO uint32_t INT_ENABLE; /**< Enable interrupt source by writing 1. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
elessair 0:f269e3021894 58 __IO uint32_t INT_CLEAR_ENABLE; /**< Clear Interrupt source by writing 1. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
elessair 0:f269e3021894 59 __I uint32_t INT_STATUS; /**< Current interrupt status. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
elessair 0:f269e3021894 60 } DmaReg_t, *DmaReg_pt;
elessair 0:f269e3021894 61 #endif /* REVB */
elessair 0:f269e3021894 62 #ifdef REVD
elessair 0:f269e3021894 63 typedef struct {
elessair 0:f269e3021894 64 union {
elessair 0:f269e3021894 65 struct {
elessair 0:f269e3021894 66 __IO uint32_t ENABLE:1; /**< DMA enable: 1 to enable; 0 to disable */
elessair 0:f269e3021894 67 __IO uint32_t MODE :2; /**< DMA mode: 00 – Memory to memory; 01 – Memory to peripheral; 10 – Peripheral to memory; 11 – Peripheral to peripheral */
elessair 0:f269e3021894 68 } BITS;
elessair 0:f269e3021894 69 __IO uint32_t WORD;
elessair 0:f269e3021894 70 } CONTROL; /**< Control register */
elessair 0:f269e3021894 71 __IO uint32_t SOURCE; /**< Address of source, read to get the number of bytes written */
elessair 0:f269e3021894 72 __IO uint32_t DESTINATION; /**< Address of destination, read to get the number of bytes written */
elessair 0:f269e3021894 73 __IO uint32_t SIZE; /**< Lenght of the entire transfer */
elessair 0:f269e3021894 74 union {
elessair 0:f269e3021894 75 struct {
elessair 0:f269e3021894 76 __I uint32_t COMPLETED:1; /**< Done: 0 – Not complete, 1 – Complete */
elessair 0:f269e3021894 77 __I uint32_t SOURCE_ERROR:1; /**< Source Error: 0 – No Error, 1 – Error */
elessair 0:f269e3021894 78 __I uint32_t DESTINATION_ERROR:1; /**< Destination Error: 0 – No Error, 1 – Source Error */
elessair 0:f269e3021894 79 } BITS;
elessair 0:f269e3021894 80 __I uint32_t WORD;
elessair 0:f269e3021894 81 } STATUS; /**< Status register */
elessair 0:f269e3021894 82 union {
elessair 0:f269e3021894 83 struct {
elessair 0:f269e3021894 84 __IO uint32_t COMPLETED:1; /**< A write of ‘1’ enables the interrupt generated by a DMA transfer complete */
elessair 0:f269e3021894 85 __IO uint32_t SOURCE_ERROR:1; /**< A write of ‘1’ enables the interrupt generated by an error on the source side of the DMA transfer */
elessair 0:f269e3021894 86 __IO uint32_t DESTINATION_ERROR:1; /**< A write of ‘1’ enables the interrupt generated by an error on the destination side of the DMA transfer */
elessair 0:f269e3021894 87 } BITS;
elessair 0:f269e3021894 88 __IO uint32_t WORD;
elessair 0:f269e3021894 89 } INT_ENABLE; /**< Interrupt enable */
elessair 0:f269e3021894 90 union {
elessair 0:f269e3021894 91 struct {
elessair 0:f269e3021894 92 __IO uint32_t COMPLETED:1; /**< A write clears the interrupt generated by a DMA transfer complete */
elessair 0:f269e3021894 93 __IO uint32_t SOURCE_ERROR:1; /**< A write clears the interrupt generated by an error on the source side of the DMA transfer */
elessair 0:f269e3021894 94 __IO uint32_t DESTINATION_ERROR:1; /**< A write clears the interrupt generated by an error on the destination side of the DMA transfer */
elessair 0:f269e3021894 95 } BITS;
elessair 0:f269e3021894 96 __IO uint32_t WORD;
elessair 0:f269e3021894 97 } INT_CLEAR; /**< Interrupt clear */
elessair 0:f269e3021894 98 union {
elessair 0:f269e3021894 99 struct {
elessair 0:f269e3021894 100 __I uint32_t COMPLETED:1; /**< Transfer complete interrupt */
elessair 0:f269e3021894 101 __I uint32_t SOURCE_ERROR:1; /**< Source error interrupt */
elessair 0:f269e3021894 102 __I uint32_t DESTINATION_ERROR:1; /**< Destination error interrupt */
elessair 0:f269e3021894 103 } BITS;
elessair 0:f269e3021894 104 __I uint32_t WORD;
elessair 0:f269e3021894 105 } INT_STATUS; /**< Interrupt status */
elessair 0:f269e3021894 106 } DmaReg_t, *DmaReg_pt;
elessair 0:f269e3021894 107 #endif /* REVD */
elessair 0:f269e3021894 108 #endif /* DMA_MAP_H_ */