Wilson Tang
Port to LPC1549. Partially tested, not all features ported
Fork of
QEI_hw
by 
Hexley Ball
qeihw.h@0:20a27391f6dc, 2010-12-11 (annotated)
- Committer:
- hexley
- Date:
- Sat Dec 11 01:34:35 2010 +0000
- Revision:
- 0:20a27391f6dc
- Child:
- 1:018226f83d80
Initial release
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| hexley | 0:20a27391f6dc | 1 | /* mbed Library - QEIhw |
| hexley | 0:20a27391f6dc | 2 | * Copyright (c) 2010, hball |
| hexley | 0:20a27391f6dc | 3 | * released under MIT license http://mbed.org/licence/mit |
| hexley | 0:20a27391f6dc | 4 | */ |
| hexley | 0:20a27391f6dc | 5 | |
| hexley | 0:20a27391f6dc | 6 | /***********************************************************************//** |
| hexley | 0:20a27391f6dc | 7 | * @file qeihw.h |
| hexley | 0:20a27391f6dc | 8 | * @brief Header file for the qeihw driver. Adapted from the CMSIS |
| hexley | 0:20a27391f6dc | 9 | * header, lpc17xx_qei.h, v 2.0 |
| hexley | 0:20a27391f6dc | 10 | * @version 0.0 |
| hexley | 0:20a27391f6dc | 11 | * @date 10 Dec 2010 |
| hexley | 0:20a27391f6dc | 12 | * @author hb |
| hexley | 0:20a27391f6dc | 13 | **************************************************************************/ |
| hexley | 0:20a27391f6dc | 14 | |
| hexley | 0:20a27391f6dc | 15 | |
| hexley | 0:20a27391f6dc | 16 | #ifndef MBED_QEIHW_H |
| hexley | 0:20a27391f6dc | 17 | #define MBED_QEIHW_H |
| hexley | 0:20a27391f6dc | 18 | |
| hexley | 0:20a27391f6dc | 19 | /* Includes ------------------------------------------------------------------- */ |
| hexley | 0:20a27391f6dc | 20 | #include "mbed.h" |
| hexley | 0:20a27391f6dc | 21 | |
| hexley | 0:20a27391f6dc | 22 | |
| hexley | 0:20a27391f6dc | 23 | /* Public Types --------------------------------------------------------------- */ |
| hexley | 0:20a27391f6dc | 24 | |
| hexley | 0:20a27391f6dc | 25 | /* Flag Status type definition */ |
| hexley | 0:20a27391f6dc | 26 | typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState; |
| hexley | 0:20a27391f6dc | 27 | |
| hexley | 0:20a27391f6dc | 28 | /* Functional State Definition */ |
| hexley | 0:20a27391f6dc | 29 | typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; |
| hexley | 0:20a27391f6dc | 30 | |
| hexley | 0:20a27391f6dc | 31 | |
| hexley | 0:20a27391f6dc | 32 | /* Other definitions */ |
| hexley | 0:20a27391f6dc | 33 | #define XTAL_FREQ 12000000 |
| hexley | 0:20a27391f6dc | 34 | |
| hexley | 0:20a27391f6dc | 35 | /* Public Functions ----------------------------------------------------------- */ |
| hexley | 0:20a27391f6dc | 36 | /** @defgroup QEI_Public_Functions QEI Public Functions |
| hexley | 0:20a27391f6dc | 37 | */ |
| hexley | 0:20a27391f6dc | 38 | class QEIHW { |
| hexley | 0:20a27391f6dc | 39 | public: |
| hexley | 0:20a27391f6dc | 40 | |
| hexley | 0:20a27391f6dc | 41 | /** Create a QEI object and configure it |
| hexley | 0:20a27391f6dc | 42 | * |
| hexley | 0:20a27391f6dc | 43 | * @param _dirinv Direction invert. When = 1, complements the QEICONF register DIR bit |
| hexley | 0:20a27391f6dc | 44 | * @param _sigmode Signal mode. When = 0, PhA and PhB are quadrature inputs. When = 1, PhA is direction and PhB is clock |
| hexley | 0:20a27391f6dc | 45 | * @param _capmode Capture mode. When = 0, count PhA edges only (2X mode). Whe = 1, count PhB edges also (4X mode). |
| hexley | 0:20a27391f6dc | 46 | * @param _invinx Invert index. When = 1, inverts the sense of the index signal |
| hexley | 0:20a27391f6dc | 47 | */ |
| hexley | 0:20a27391f6dc | 48 | QEIHW( uint32_t _dirinv, uint32_t _sigmode, uint32_t _capmode, uint32_t _invinx); |
| hexley | 0:20a27391f6dc | 49 | |
| hexley | 0:20a27391f6dc | 50 | /** Resets value for each type of QEI value, such as velocity, position, etc. |
| hexley | 0:20a27391f6dc | 51 | * |
| hexley | 0:20a27391f6dc | 52 | * @param[in] ulResetType QEI Reset Type, should be one of the following: |
| hexley | 0:20a27391f6dc | 53 | * - QEI_RESET_POS: Reset Position Counter |
| hexley | 0:20a27391f6dc | 54 | * - QEI_RESET_POSOnIDX: Reset Position Counter on Index signal |
| hexley | 0:20a27391f6dc | 55 | * - QEI_RESET_VEL: Reset Velocity |
| hexley | 0:20a27391f6dc | 56 | * - QEI_RESET_IDX: Reset Index Counter |
| hexley | 0:20a27391f6dc | 57 | */ |
| hexley | 0:20a27391f6dc | 58 | void Reset(uint32_t ulResetType); |
| hexley | 0:20a27391f6dc | 59 | |
| hexley | 0:20a27391f6dc | 60 | /** Powers down the QEI block, returns pins to GPIO mode |
| hexley | 0:20a27391f6dc | 61 | * |
| hexley | 0:20a27391f6dc | 62 | */ |
| hexley | 0:20a27391f6dc | 63 | void DeInit(); |
| hexley | 0:20a27391f6dc | 64 | |
| hexley | 0:20a27391f6dc | 65 | /** Report direction (QEISTAT bit DIR) |
| hexley | 0:20a27391f6dc | 66 | * |
| hexley | 0:20a27391f6dc | 67 | * @return State of the DIR bit (SET or RESET) |
| hexley | 0:20a27391f6dc | 68 | */ |
| hexley | 0:20a27391f6dc | 69 | FlagStatus Direction(); |
| hexley | 0:20a27391f6dc | 70 | |
| hexley | 0:20a27391f6dc | 71 | /** |
| hexley | 0:20a27391f6dc | 72 | * @brief Get current position value in QEI peripheral |
| hexley | 0:20a27391f6dc | 73 | * |
| hexley | 0:20a27391f6dc | 74 | * @return Current position value of QEI peripheral |
| hexley | 0:20a27391f6dc | 75 | */ |
| hexley | 0:20a27391f6dc | 76 | uint32_t GetPosition(); |
| hexley | 0:20a27391f6dc | 77 | |
| hexley | 0:20a27391f6dc | 78 | /** Set max position value for QEI peripheral |
| hexley | 0:20a27391f6dc | 79 | * |
| hexley | 0:20a27391f6dc | 80 | * @param[in] ulMaxPos Max position value to set |
| hexley | 0:20a27391f6dc | 81 | * @return None |
| hexley | 0:20a27391f6dc | 82 | */ |
| hexley | 0:20a27391f6dc | 83 | void SetMaxPosition(uint32_t ulMaxPos); |
| hexley | 0:20a27391f6dc | 84 | |
| hexley | 0:20a27391f6dc | 85 | /** Set position compare value for QEI peripheral |
| hexley | 0:20a27391f6dc | 86 | * @param[in] bPosCompCh Compare Position channel, should be: |
| hexley | 0:20a27391f6dc | 87 | * - QEI_COMPPOS_CH_0: QEI compare position channel 0 |
| hexley | 0:20a27391f6dc | 88 | * - QEI_COMPPOS_CH_1: QEI compare position channel 1 |
| hexley | 0:20a27391f6dc | 89 | * - QEI_COMPPOS_CH_2: QEI compare position channel 2 |
| hexley | 0:20a27391f6dc | 90 | * @param[in] ulPosComp Compare Position value to set |
| hexley | 0:20a27391f6dc | 91 | * @return None |
| hexley | 0:20a27391f6dc | 92 | */ |
| hexley | 0:20a27391f6dc | 93 | void SetPositionComp( uint8_t bPosCompCh, uint32_t ulPosComp); |
| hexley | 0:20a27391f6dc | 94 | |
| hexley | 0:20a27391f6dc | 95 | /** Get current index counter of QEI peripheral |
| hexley | 0:20a27391f6dc | 96 | * |
| hexley | 0:20a27391f6dc | 97 | * @return Current value of QEI index counter |
| hexley | 0:20a27391f6dc | 98 | */ |
| hexley | 0:20a27391f6dc | 99 | uint32_t GetIndex(); |
| hexley | 0:20a27391f6dc | 100 | |
| hexley | 0:20a27391f6dc | 101 | /** Set value for index compare in QEI peripheral |
| hexley | 0:20a27391f6dc | 102 | * @param[in] ulIndexComp Compare Index Value to set |
| hexley | 0:20a27391f6dc | 103 | * @return None |
| hexley | 0:20a27391f6dc | 104 | */ |
| hexley | 0:20a27391f6dc | 105 | void SetIndexComp( uint32_t ulIndexComp); |
| hexley | 0:20a27391f6dc | 106 | |
| hexley | 0:20a27391f6dc | 107 | /** Set Velocity timer reload value |
| hexley | 0:20a27391f6dc | 108 | * |
| hexley | 0:20a27391f6dc | 109 | * @param[in] ulReloadValue Velocity timer reload count |
| hexley | 0:20a27391f6dc | 110 | * @return None |
| hexley | 0:20a27391f6dc | 111 | */ |
| hexley | 0:20a27391f6dc | 112 | void SetVelocityTimerReload( uint32_t ulReloadValue); |
| hexley | 0:20a27391f6dc | 113 | |
| hexley | 0:20a27391f6dc | 114 | /** Set Velocity timer reload value in microseconds |
| hexley | 0:20a27391f6dc | 115 | * |
| hexley | 0:20a27391f6dc | 116 | * @param[in] ulReloadValue Velocity timer reload count |
| hexley | 0:20a27391f6dc | 117 | * @return None |
| hexley | 0:20a27391f6dc | 118 | */ |
| hexley | 0:20a27391f6dc | 119 | void SetVelocityTimerReload_us( uint32_t ulReloadValue); |
| hexley | 0:20a27391f6dc | 120 | |
| hexley | 0:20a27391f6dc | 121 | /** Get current timer counter in QEI peripheral |
| hexley | 0:20a27391f6dc | 122 | * |
| hexley | 0:20a27391f6dc | 123 | * @return Current timer counter in QEI peripheral |
| hexley | 0:20a27391f6dc | 124 | */ |
| hexley | 0:20a27391f6dc | 125 | uint32_t GetTimer(); |
| hexley | 0:20a27391f6dc | 126 | |
| hexley | 0:20a27391f6dc | 127 | /** Get current velocity pulse counter in current time period |
| hexley | 0:20a27391f6dc | 128 | * |
| hexley | 0:20a27391f6dc | 129 | * @return Current velocity pulse counter value |
| hexley | 0:20a27391f6dc | 130 | */ |
| hexley | 0:20a27391f6dc | 131 | uint32_t GetVelocity(); |
| hexley | 0:20a27391f6dc | 132 | |
| hexley | 0:20a27391f6dc | 133 | /** Get the most recently measured velocity of the QEI. When |
| hexley | 0:20a27391f6dc | 134 | * the Velocity timer in QEI is over-flow, the current velocity |
| hexley | 0:20a27391f6dc | 135 | * value will be loaded into Velocity Capture register. |
| hexley | 0:20a27391f6dc | 136 | * |
| hexley | 0:20a27391f6dc | 137 | * @return The most recently measured velocity value |
| hexley | 0:20a27391f6dc | 138 | */ |
| hexley | 0:20a27391f6dc | 139 | uint32_t GetVelocityCap(); |
| hexley | 0:20a27391f6dc | 140 | |
| hexley | 0:20a27391f6dc | 141 | /** Set Velocity Compare value for QEI peripheral |
| hexley | 0:20a27391f6dc | 142 | * |
| hexley | 0:20a27391f6dc | 143 | * @param[in] ulVelComp Compare Velocity value to set |
| hexley | 0:20a27391f6dc | 144 | * @return None |
| hexley | 0:20a27391f6dc | 145 | */ |
| hexley | 0:20a27391f6dc | 146 | void SetVelocityComp( uint32_t ulVelComp); |
| hexley | 0:20a27391f6dc | 147 | |
| hexley | 0:20a27391f6dc | 148 | /** Set value of sampling count for the digital filter in |
| hexley | 0:20a27391f6dc | 149 | * QEI peripheral |
| hexley | 0:20a27391f6dc | 150 | * |
| hexley | 0:20a27391f6dc | 151 | * @param[in] ulSamplingPulse Value of sampling count to set |
| hexley | 0:20a27391f6dc | 152 | * @return None |
| hexley | 0:20a27391f6dc | 153 | */ |
| hexley | 0:20a27391f6dc | 154 | void SetDigiFilter( uint32_t ulSamplingPulse); |
| hexley | 0:20a27391f6dc | 155 | |
| hexley | 0:20a27391f6dc | 156 | /** Check whether if specified interrupt flag status in QEI |
| hexley | 0:20a27391f6dc | 157 | * peripheral is set or not |
| hexley | 0:20a27391f6dc | 158 | * |
| hexley | 0:20a27391f6dc | 159 | * @param[in] ulIntType Interrupt Flag Status type, should be: |
| hexley | 0:20a27391f6dc | 160 | - QEI_INTFLAG_INX_Int: index pulse was detected interrupt |
| hexley | 0:20a27391f6dc | 161 | - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt |
| hexley | 0:20a27391f6dc | 162 | - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt |
| hexley | 0:20a27391f6dc | 163 | - QEI_INTFLAG_DIR_Int: Change of direction interrupt |
| hexley | 0:20a27391f6dc | 164 | - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt |
| hexley | 0:20a27391f6dc | 165 | - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt |
| hexley | 0:20a27391f6dc | 166 | - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 167 | current position interrupt |
| hexley | 0:20a27391f6dc | 168 | - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the |
| hexley | 0:20a27391f6dc | 169 | current position interrupt |
| hexley | 0:20a27391f6dc | 170 | - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 171 | current position interrupt |
| hexley | 0:20a27391f6dc | 172 | - QEI_INTFLAG_REV_Int: Index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 173 | index count interrupt |
| hexley | 0:20a27391f6dc | 174 | - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 175 | - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 176 | - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 177 | * @return New State of specified interrupt flag status (SET or RESET) |
| hexley | 0:20a27391f6dc | 178 | */ |
| hexley | 0:20a27391f6dc | 179 | FlagStatus GetIntStatus( uint32_t ulIntType); |
| hexley | 0:20a27391f6dc | 180 | |
| hexley | 0:20a27391f6dc | 181 | /** Enable/Disable specified interrupt in QEI peripheral |
| hexley | 0:20a27391f6dc | 182 | * |
| hexley | 0:20a27391f6dc | 183 | * @param[in] ulIntType Interrupt Flag Status type, should be: |
| hexley | 0:20a27391f6dc | 184 | * - QEI_INTFLAG_INX_Int: index pulse was detected interrupt |
| hexley | 0:20a27391f6dc | 185 | * - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt |
| hexley | 0:20a27391f6dc | 186 | * - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt |
| hexley | 0:20a27391f6dc | 187 | * - QEI_INTFLAG_DIR_Int: Change of direction interrupt |
| hexley | 0:20a27391f6dc | 188 | * - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt |
| hexley | 0:20a27391f6dc | 189 | * - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt |
| hexley | 0:20a27391f6dc | 190 | * - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 191 | * current position interrupt |
| hexley | 0:20a27391f6dc | 192 | * - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the |
| hexley | 0:20a27391f6dc | 193 | * current position interrupt |
| hexley | 0:20a27391f6dc | 194 | * - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 195 | * current position interrupt |
| hexley | 0:20a27391f6dc | 196 | * - QEI_INTFLAG_REV_Int: Index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 197 | * index count interrupt |
| hexley | 0:20a27391f6dc | 198 | * - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 199 | * - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 200 | * - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 201 | * @param[in] NewState New function state, should be: |
| hexley | 0:20a27391f6dc | 202 | * - DISABLE |
| hexley | 0:20a27391f6dc | 203 | * - ENABLE |
| hexley | 0:20a27391f6dc | 204 | * @return None |
| hexley | 0:20a27391f6dc | 205 | */ |
| hexley | 0:20a27391f6dc | 206 | void IntCmd( uint32_t ulIntType, FunctionalState NewState); |
| hexley | 0:20a27391f6dc | 207 | |
| hexley | 0:20a27391f6dc | 208 | /** Asserts specified interrupt in QEI peripheral |
| hexley | 0:20a27391f6dc | 209 | * |
| hexley | 0:20a27391f6dc | 210 | * @param[in] ulIntType Interrupt Flag Status type, should be: |
| hexley | 0:20a27391f6dc | 211 | - QEI_INTFLAG_INX_Int: index pulse was detected interrupt |
| hexley | 0:20a27391f6dc | 212 | - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt |
| hexley | 0:20a27391f6dc | 213 | - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt |
| hexley | 0:20a27391f6dc | 214 | - QEI_INTFLAG_DIR_Int: Change of direction interrupt |
| hexley | 0:20a27391f6dc | 215 | - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt |
| hexley | 0:20a27391f6dc | 216 | - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt |
| hexley | 0:20a27391f6dc | 217 | - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 218 | current position interrupt |
| hexley | 0:20a27391f6dc | 219 | - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the |
| hexley | 0:20a27391f6dc | 220 | current position interrupt |
| hexley | 0:20a27391f6dc | 221 | - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 222 | current position interrupt |
| hexley | 0:20a27391f6dc | 223 | - QEI_INTFLAG_REV_Int: Index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 224 | index count interrupt |
| hexley | 0:20a27391f6dc | 225 | - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 226 | - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 227 | - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 228 | * @return None |
| hexley | 0:20a27391f6dc | 229 | */ |
| hexley | 0:20a27391f6dc | 230 | void IntSet( uint32_t ulIntType); |
| hexley | 0:20a27391f6dc | 231 | |
| hexley | 0:20a27391f6dc | 232 | /** De-asserts specified interrupt (pending) in QEI peripheral |
| hexley | 0:20a27391f6dc | 233 | * |
| hexley | 0:20a27391f6dc | 234 | * @param[in] ulIntType Interrupt Flag Status type, should be: |
| hexley | 0:20a27391f6dc | 235 | - QEI_INTFLAG_INX_Int: index pulse was detected interrupt |
| hexley | 0:20a27391f6dc | 236 | - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt |
| hexley | 0:20a27391f6dc | 237 | - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt |
| hexley | 0:20a27391f6dc | 238 | - QEI_INTFLAG_DIR_Int: Change of direction interrupt |
| hexley | 0:20a27391f6dc | 239 | - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt |
| hexley | 0:20a27391f6dc | 240 | - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt |
| hexley | 0:20a27391f6dc | 241 | - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 242 | current position interrupt |
| hexley | 0:20a27391f6dc | 243 | - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the |
| hexley | 0:20a27391f6dc | 244 | current position interrupt |
| hexley | 0:20a27391f6dc | 245 | - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 246 | current position interrupt |
| hexley | 0:20a27391f6dc | 247 | - QEI_INTFLAG_REV_Int: Index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 248 | index count interrupt |
| hexley | 0:20a27391f6dc | 249 | - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 250 | - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 251 | - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 252 | * @return None |
| hexley | 0:20a27391f6dc | 253 | */ |
| hexley | 0:20a27391f6dc | 254 | void IntClear( uint32_t ulIntType); |
| hexley | 0:20a27391f6dc | 255 | |
| hexley | 0:20a27391f6dc | 256 | /** Append interrupt handler for specific QEI interrupt source |
| hexley | 0:20a27391f6dc | 257 | * |
| hexley | 0:20a27391f6dc | 258 | * @param[in] ulISRType Interrupt Flag Status type, should be: |
| hexley | 0:20a27391f6dc | 259 | * - QEI_INTFLAG_INX_Int: index pulse was detected interrupt |
| hexley | 0:20a27391f6dc | 260 | * - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt |
| hexley | 0:20a27391f6dc | 261 | * - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt |
| hexley | 0:20a27391f6dc | 262 | * - QEI_INTFLAG_DIR_Int: Change of direction interrupt |
| hexley | 0:20a27391f6dc | 263 | * - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt |
| hexley | 0:20a27391f6dc | 264 | * - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt |
| hexley | 0:20a27391f6dc | 265 | * - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 266 | * current position interrupt |
| hexley | 0:20a27391f6dc | 267 | * - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the |
| hexley | 0:20a27391f6dc | 268 | * current position interrupt |
| hexley | 0:20a27391f6dc | 269 | * - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 270 | * current position interrupt |
| hexley | 0:20a27391f6dc | 271 | * - QEI_INTFLAG_REV_Int: Index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 272 | * index count interrupt |
| hexley | 0:20a27391f6dc | 273 | * - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 274 | * - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 275 | * - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 276 | * |
| hexley | 0:20a27391f6dc | 277 | * @return none |
| hexley | 0:20a27391f6dc | 278 | */ |
| hexley | 0:20a27391f6dc | 279 | void AppendISR(uint32_t ulISRType, void(*fptr)(void)); |
| hexley | 0:20a27391f6dc | 280 | |
| hexley | 0:20a27391f6dc | 281 | /** Unappend interrupt handler for specific QEI interrupt source |
| hexley | 0:20a27391f6dc | 282 | * |
| hexley | 0:20a27391f6dc | 283 | * @param[in] ulISRType Interrupt Flag Status type, should be: |
| hexley | 0:20a27391f6dc | 284 | * - QEI_INTFLAG_INX_Int: index pulse was detected interrupt |
| hexley | 0:20a27391f6dc | 285 | * - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt |
| hexley | 0:20a27391f6dc | 286 | * - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt |
| hexley | 0:20a27391f6dc | 287 | * - QEI_INTFLAG_DIR_Int: Change of direction interrupt |
| hexley | 0:20a27391f6dc | 288 | * - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt |
| hexley | 0:20a27391f6dc | 289 | * - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt |
| hexley | 0:20a27391f6dc | 290 | * - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 291 | * current position interrupt |
| hexley | 0:20a27391f6dc | 292 | * - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the |
| hexley | 0:20a27391f6dc | 293 | * current position interrupt |
| hexley | 0:20a27391f6dc | 294 | * - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 295 | * current position interrupt |
| hexley | 0:20a27391f6dc | 296 | * - QEI_INTFLAG_REV_Int: Index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 297 | * index count interrupt |
| hexley | 0:20a27391f6dc | 298 | * - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 299 | * - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 300 | * - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 301 | * |
| hexley | 0:20a27391f6dc | 302 | * @return none |
| hexley | 0:20a27391f6dc | 303 | */ |
| hexley | 0:20a27391f6dc | 304 | void UnAppendISR(uint32_t ulISRType); |
| hexley | 0:20a27391f6dc | 305 | |
| hexley | 0:20a27391f6dc | 306 | |
| hexley | 0:20a27391f6dc | 307 | /** |
| hexley | 0:20a27391f6dc | 308 | * @brief Calculates the actual velocity in RPM passed via velocity |
| hexley | 0:20a27391f6dc | 309 | * capture value and Pulse Per Revolution (of the encoder) value |
| hexley | 0:20a27391f6dc | 310 | * parameter input. |
| hexley | 0:20a27391f6dc | 311 | * |
| hexley | 0:20a27391f6dc | 312 | * @param[in] ulVelCapValue Velocity capture input value that can |
| hexley | 0:20a27391f6dc | 313 | * be got from QEI_GetVelocityCap() function |
| hexley | 0:20a27391f6dc | 314 | * @param[in] ulPPR Pulse per round of encoder |
| hexley | 0:20a27391f6dc | 315 | * @return The actual value of velocity in RPM (Revolutions per minute) |
| hexley | 0:20a27391f6dc | 316 | */ |
| hexley | 0:20a27391f6dc | 317 | uint32_t CalculateRPM( uint32_t ulVelCapValue, uint32_t ulPPR); |
| hexley | 0:20a27391f6dc | 318 | |
| hexley | 0:20a27391f6dc | 319 | |
| hexley | 0:20a27391f6dc | 320 | /* Public Macros -------------------------------------------------------------- */ |
| hexley | 0:20a27391f6dc | 321 | /* QEI Reset types */ |
| hexley | 0:20a27391f6dc | 322 | #define QEI_RESET_POS QEI_CON_RESP /**< Reset position counter */ |
| hexley | 0:20a27391f6dc | 323 | #define QEI_RESET_POSOnIDX QEI_CON_RESPI /**< Reset Posistion Counter on Index */ |
| hexley | 0:20a27391f6dc | 324 | #define QEI_RESET_VEL QEI_CON_RESV /**< Reset Velocity */ |
| hexley | 0:20a27391f6dc | 325 | #define QEI_RESET_IDX QEI_CON_RESI /**< Reset Index Counter */ |
| hexley | 0:20a27391f6dc | 326 | |
| hexley | 0:20a27391f6dc | 327 | /* QEI Direction Invert Type Option */ |
| hexley | 0:20a27391f6dc | 328 | #define QEI_DIRINV_NONE ((uint32_t)(0)) /**< Direction is not inverted */ |
| hexley | 0:20a27391f6dc | 329 | #define QEI_DIRINV_CMPL ((uint32_t)(1)) /**< Direction is complemented */ |
| hexley | 0:20a27391f6dc | 330 | |
| hexley | 0:20a27391f6dc | 331 | /* QEI Signal Mode Option */ |
| hexley | 0:20a27391f6dc | 332 | #define QEI_SIGNALMODE_QUAD ((uint32_t)(0)) /**< Signal operation: Quadrature phase mode */ |
| hexley | 0:20a27391f6dc | 333 | #define QEI_SIGNALMODE_CLKDIR ((uint32_t)(1)) /**< Signal operation: Clock/Direction mode */ |
| hexley | 0:20a27391f6dc | 334 | |
| hexley | 0:20a27391f6dc | 335 | /* QEI Capture Mode Option */ |
| hexley | 0:20a27391f6dc | 336 | #define QEI_CAPMODE_2X ((uint32_t)(0)) /**< Capture mode: Only Phase-A edges are counted (2X) */ |
| hexley | 0:20a27391f6dc | 337 | #define QEI_CAPMODE_4X ((uint32_t)(1)) /**< Capture mode: BOTH PhA and PhB edges are counted (4X)*/ |
| hexley | 0:20a27391f6dc | 338 | |
| hexley | 0:20a27391f6dc | 339 | /* QEI Invert Index Signal Option */ |
| hexley | 0:20a27391f6dc | 340 | #define QEI_INVINX_NONE ((uint32_t)(0)) /**< Invert Index signal option: None */ |
| hexley | 0:20a27391f6dc | 341 | #define QEI_INVINX_EN ((uint32_t)(1)) /**< Invert Index signal option: Enable */ |
| hexley | 0:20a27391f6dc | 342 | |
| hexley | 0:20a27391f6dc | 343 | /* QEI timer reload option */ |
| hexley | 0:20a27391f6dc | 344 | #define QEI_TIMERRELOAD_TICKVAL ((uint8_t)(0)) /**< Reload value in absolute value */ |
| hexley | 0:20a27391f6dc | 345 | #define QEI_TIMERRELOAD_USVAL ((uint8_t)(1)) /**< Reload value in microsecond value */ |
| hexley | 0:20a27391f6dc | 346 | |
| hexley | 0:20a27391f6dc | 347 | /* QEI Flag Status type */ |
| hexley | 0:20a27391f6dc | 348 | #define QEI_STATUS_DIR ((uint32_t)(1<<0)) /**< Direction status */ |
| hexley | 0:20a27391f6dc | 349 | |
| hexley | 0:20a27391f6dc | 350 | /* QEI Compare Position channel option */ |
| hexley | 0:20a27391f6dc | 351 | #define QEI_COMPPOS_CH_0 ((uint8_t)(0)) /**< QEI compare position channel 0 */ |
| hexley | 0:20a27391f6dc | 352 | #define QEI_COMPPOS_CH_1 ((uint8_t)(1)) /**< QEI compare position channel 1 */ |
| hexley | 0:20a27391f6dc | 353 | #define QEI_COMPPOS_CH_2 ((uint8_t)(2)) /**< QEI compare position channel 2 */ |
| hexley | 0:20a27391f6dc | 354 | |
| hexley | 0:20a27391f6dc | 355 | /* QEI interrupt flag type */ |
| hexley | 0:20a27391f6dc | 356 | #define QEI_INTFLAG_INX_Int ((uint32_t)(1<<0)) /**< index pulse was detected interrupt */ |
| hexley | 0:20a27391f6dc | 357 | #define QEI_INTFLAG_TIM_Int ((uint32_t)(1<<1)) /**< Velocity timer over flow interrupt */ |
| hexley | 0:20a27391f6dc | 358 | #define QEI_INTFLAG_VELC_Int ((uint32_t)(1<<2)) /**< Capture velocity is less than compare interrupt */ |
| hexley | 0:20a27391f6dc | 359 | #define QEI_INTFLAG_DIR_Int ((uint32_t)(1<<3)) /**< Change of direction interrupt */ |
| hexley | 0:20a27391f6dc | 360 | #define QEI_INTFLAG_ERR_Int ((uint32_t)(1<<4)) /**< An encoder phase error interrupt */ |
| hexley | 0:20a27391f6dc | 361 | #define QEI_INTFLAG_ENCLK_Int ((uint32_t)(1<<5)) /**< An encoder clock pulse was detected interrupt */ |
| hexley | 0:20a27391f6dc | 362 | #define QEI_INTFLAG_POS0_Int ((uint32_t)(1<<6)) /**< position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 363 | current position interrupt */ |
| hexley | 0:20a27391f6dc | 364 | #define QEI_INTFLAG_POS1_Int ((uint32_t)(1<<7)) /**< position 1 compare value is equal to the |
| hexley | 0:20a27391f6dc | 365 | current position interrupt */ |
| hexley | 0:20a27391f6dc | 366 | #define QEI_INTFLAG_POS2_Int ((uint32_t)(1<<8)) /**< position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 367 | current position interrupt */ |
| hexley | 0:20a27391f6dc | 368 | #define QEI_INTFLAG_REV_Int ((uint32_t)(1<<9)) /**< Index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 369 | index count interrupt */ |
| hexley | 0:20a27391f6dc | 370 | #define QEI_INTFLAG_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 371 | #define QEI_INTFLAG_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 372 | #define QEI_INTFLAG_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 373 | |
| hexley | 0:20a27391f6dc | 374 | /* QEI Process position reporting options */ |
| hexley | 0:20a27391f6dc | 375 | #define QEI_PROCESS_OPERATE 0; |
| hexley | 0:20a27391f6dc | 376 | #define QEI_PROCESS_RESET 1; |
| hexley | 0:20a27391f6dc | 377 | #define QEI_PROCESS_INCREMENTAL 0; |
| hexley | 0:20a27391f6dc | 378 | #define QEI_PROCESS_ACCUMULATE 1; |
| hexley | 0:20a27391f6dc | 379 | #define QEI_PROCESS_LINEAR 0; |
| hexley | 0:20a27391f6dc | 380 | #define QEI_PROCESS_WEIGHTED 1; |
| hexley | 0:20a27391f6dc | 381 | |
| hexley | 0:20a27391f6dc | 382 | private: |
| hexley | 0:20a27391f6dc | 383 | static void _Qeiisr(void); |
| hexley | 0:20a27391f6dc | 384 | void Qeiisr(void); |
| hexley | 0:20a27391f6dc | 385 | static QEIHW *instance; |
| hexley | 0:20a27391f6dc | 386 | |
| hexley | 0:20a27391f6dc | 387 | void(*_qei_isr[13])(); |
| hexley | 0:20a27391f6dc | 388 | |
| hexley | 0:20a27391f6dc | 389 | |
| hexley | 0:20a27391f6dc | 390 | /* Private Macros ------------------------------------------------------------- */ |
| hexley | 0:20a27391f6dc | 391 | /* --------------------- BIT DEFINITIONS -------------------------------------- */ |
| hexley | 0:20a27391f6dc | 392 | /* Quadrature Encoder Interface Control Register Definition --------------------- */ |
| hexley | 0:20a27391f6dc | 393 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 394 | * Macro defines for QEI Control register |
| hexley | 0:20a27391f6dc | 395 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 396 | #define QEI_CON_RESP ((uint32_t)(1<<0)) /**< Reset position counter */ |
| hexley | 0:20a27391f6dc | 397 | #define QEI_CON_RESPI ((uint32_t)(1<<1)) /**< Reset Posistion Counter on Index */ |
| hexley | 0:20a27391f6dc | 398 | #define QEI_CON_RESV ((uint32_t)(1<<2)) /**< Reset Velocity */ |
| hexley | 0:20a27391f6dc | 399 | #define QEI_CON_RESI ((uint32_t)(1<<3)) /**< Reset Index Counter */ |
| hexley | 0:20a27391f6dc | 400 | #define QEI_CON_BITMASK ((uint32_t)(0x0F)) /**< QEI Control register bit-mask */ |
| hexley | 0:20a27391f6dc | 401 | |
| hexley | 0:20a27391f6dc | 402 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 403 | * Macro defines for QEI Configuration register |
| hexley | 0:20a27391f6dc | 404 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 405 | #define QEI_CONF_DIRINV ((uint32_t)(1<<0)) /**< Direction Invert */ |
| hexley | 0:20a27391f6dc | 406 | #define QEI_CONF_SIGMODE ((uint32_t)(1<<1)) /**< Signal mode */ |
| hexley | 0:20a27391f6dc | 407 | #define QEI_CONF_CAPMODE ((uint32_t)(1<<2)) /**< Capture mode */ |
| hexley | 0:20a27391f6dc | 408 | #define QEI_CONF_INVINX ((uint32_t)(1<<3)) /**< Invert index */ |
| hexley | 0:20a27391f6dc | 409 | #define QEI_CONF_BITMASK ((uint32_t)(0x0F)) /**< QEI Configuration register bit-mask */ |
| hexley | 0:20a27391f6dc | 410 | |
| hexley | 0:20a27391f6dc | 411 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 412 | * Macro defines for QEI Status register |
| hexley | 0:20a27391f6dc | 413 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 414 | #define QEI_STAT_DIR ((uint32_t)(1<<0)) /**< Direction bit */ |
| hexley | 0:20a27391f6dc | 415 | #define QEI_STAT_BITMASK ((uint32_t)(1<<0)) /**< QEI status register bit-mask */ |
| hexley | 0:20a27391f6dc | 416 | |
| hexley | 0:20a27391f6dc | 417 | /* Quadrature Encoder Interface Interrupt registers definitions --------------------- */ |
| hexley | 0:20a27391f6dc | 418 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 419 | * Macro defines for QEI Interrupt Status register |
| hexley | 0:20a27391f6dc | 420 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 421 | #define QEI_INTSTAT_INX_Int ((uint32_t)(1<<0)) /**< Indicates that an index pulse was detected */ |
| hexley | 0:20a27391f6dc | 422 | #define QEI_INTSTAT_TIM_Int ((uint32_t)(1<<1)) /**< Indicates that a velocity timer overflow occurred */ |
| hexley | 0:20a27391f6dc | 423 | #define QEI_INTSTAT_VELC_Int ((uint32_t)(1<<2)) /**< Indicates that capture velocity is less than compare velocity */ |
| hexley | 0:20a27391f6dc | 424 | #define QEI_INTSTAT_DIR_Int ((uint32_t)(1<<3)) /**< Indicates that a change of direction was detected */ |
| hexley | 0:20a27391f6dc | 425 | #define QEI_INTSTAT_ERR_Int ((uint32_t)(1<<4)) /**< Indicates that an encoder phase error was detected */ |
| hexley | 0:20a27391f6dc | 426 | #define QEI_INTSTAT_ENCLK_Int ((uint32_t)(1<<5)) /**< Indicates that and encoder clock pulse was detected */ |
| hexley | 0:20a27391f6dc | 427 | #define QEI_INTSTAT_POS0_Int ((uint32_t)(1<<6)) /**< Indicates that the position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 428 | current position */ |
| hexley | 0:20a27391f6dc | 429 | #define QEI_INTSTAT_POS1_Int ((uint32_t)(1<<7)) /**< Indicates that the position 1compare value is equal to the |
| hexley | 0:20a27391f6dc | 430 | current position */ |
| hexley | 0:20a27391f6dc | 431 | #define QEI_INTSTAT_POS2_Int ((uint32_t)(1<<8)) /**< Indicates that the position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 432 | current position */ |
| hexley | 0:20a27391f6dc | 433 | #define QEI_INTSTAT_REV_Int ((uint32_t)(1<<9)) /**< Indicates that the index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 434 | index count */ |
| hexley | 0:20a27391f6dc | 435 | #define QEI_INTSTAT_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt. Set when |
| hexley | 0:20a27391f6dc | 436 | both the POS0_Int bit is set and the REV_Int is set */ |
| hexley | 0:20a27391f6dc | 437 | #define QEI_INTSTAT_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt. Set when |
| hexley | 0:20a27391f6dc | 438 | both the POS1_Int bit is set and the REV_Int is set */ |
| hexley | 0:20a27391f6dc | 439 | #define QEI_INTSTAT_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt. Set when |
| hexley | 0:20a27391f6dc | 440 | both the POS2_Int bit is set and the REV_Int is set */ |
| hexley | 0:20a27391f6dc | 441 | #define QEI_INTSTAT_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */ |
| hexley | 0:20a27391f6dc | 442 | |
| hexley | 0:20a27391f6dc | 443 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 444 | * Macro defines for QEI Interrupt Set register |
| hexley | 0:20a27391f6dc | 445 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 446 | #define QEI_INTSET_INX_Int ((uint32_t)(1<<0)) /**< Set Bit Indicates that an index pulse was detected */ |
| hexley | 0:20a27391f6dc | 447 | #define QEI_INTSET_TIM_Int ((uint32_t)(1<<1)) /**< Set Bit Indicates that a velocity timer overflow occurred */ |
| hexley | 0:20a27391f6dc | 448 | #define QEI_INTSET_VELC_Int ((uint32_t)(1<<2)) /**< Set Bit Indicates that capture velocity is less than compare velocity */ |
| hexley | 0:20a27391f6dc | 449 | #define QEI_INTSET_DIR_Int ((uint32_t)(1<<3)) /**< Set Bit Indicates that a change of direction was detected */ |
| hexley | 0:20a27391f6dc | 450 | #define QEI_INTSET_ERR_Int ((uint32_t)(1<<4)) /**< Set Bit Indicates that an encoder phase error was detected */ |
| hexley | 0:20a27391f6dc | 451 | #define QEI_INTSET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Bit Indicates that and encoder clock pulse was detected */ |
| hexley | 0:20a27391f6dc | 452 | #define QEI_INTSET_POS0_Int ((uint32_t)(1<<6)) /**< Set Bit Indicates that the position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 453 | current position */ |
| hexley | 0:20a27391f6dc | 454 | #define QEI_INTSET_POS1_Int ((uint32_t)(1<<7)) /**< Set Bit Indicates that the position 1compare value is equal to the |
| hexley | 0:20a27391f6dc | 455 | current position */ |
| hexley | 0:20a27391f6dc | 456 | #define QEI_INTSET_POS2_Int ((uint32_t)(1<<8)) /**< Set Bit Indicates that the position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 457 | current position */ |
| hexley | 0:20a27391f6dc | 458 | #define QEI_INTSET_REV_Int ((uint32_t)(1<<9)) /**< Set Bit Indicates that the index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 459 | index count */ |
| hexley | 0:20a27391f6dc | 460 | #define QEI_INTSET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Bit that combined position 0 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 461 | #define QEI_INTSET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Bit that Combined position 1 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 462 | #define QEI_INTSET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Bit that Combined position 2 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 463 | #define QEI_INTSET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Set register bit-mask */ |
| hexley | 0:20a27391f6dc | 464 | |
| hexley | 0:20a27391f6dc | 465 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 466 | * Macro defines for QEI Interrupt Clear register |
| hexley | 0:20a27391f6dc | 467 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 468 | #define QEI_INTCLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Bit Indicates that an index pulse was detected */ |
| hexley | 0:20a27391f6dc | 469 | #define QEI_INTCLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Bit Indicates that a velocity timer overflow occurred */ |
| hexley | 0:20a27391f6dc | 470 | #define QEI_INTCLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Bit Indicates that capture velocity is less than compare velocity */ |
| hexley | 0:20a27391f6dc | 471 | #define QEI_INTCLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Bit Indicates that a change of direction was detected */ |
| hexley | 0:20a27391f6dc | 472 | #define QEI_INTCLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Bit Indicates that an encoder phase error was detected */ |
| hexley | 0:20a27391f6dc | 473 | #define QEI_INTCLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Bit Indicates that and encoder clock pulse was detected */ |
| hexley | 0:20a27391f6dc | 474 | #define QEI_INTCLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Bit Indicates that the position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 475 | current position */ |
| hexley | 0:20a27391f6dc | 476 | #define QEI_INTCLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Bit Indicates that the position 1compare value is equal to the |
| hexley | 0:20a27391f6dc | 477 | current position */ |
| hexley | 0:20a27391f6dc | 478 | #define QEI_INTCLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Bit Indicates that the position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 479 | current position */ |
| hexley | 0:20a27391f6dc | 480 | #define QEI_INTCLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Bit Indicates that the index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 481 | index count */ |
| hexley | 0:20a27391f6dc | 482 | #define QEI_INTCLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Bit that combined position 0 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 483 | #define QEI_INTCLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Bit that Combined position 1 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 484 | #define QEI_INTCLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Bit that Combined position 2 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 485 | #define QEI_INTCLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Clear register bit-mask */ |
| hexley | 0:20a27391f6dc | 486 | |
| hexley | 0:20a27391f6dc | 487 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 488 | * Macro defines for QEI Interrupt Enable register |
| hexley | 0:20a27391f6dc | 489 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 490 | #define QEI_INTEN_INX_Int ((uint32_t)(1<<0)) /**< Enabled Interrupt Bit Indicates that an index pulse was detected */ |
| hexley | 0:20a27391f6dc | 491 | #define QEI_INTEN_TIM_Int ((uint32_t)(1<<1)) /**< Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */ |
| hexley | 0:20a27391f6dc | 492 | #define QEI_INTEN_VELC_Int ((uint32_t)(1<<2)) /**< Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */ |
| hexley | 0:20a27391f6dc | 493 | #define QEI_INTEN_DIR_Int ((uint32_t)(1<<3)) /**< Enabled Interrupt Bit Indicates that a change of direction was detected */ |
| hexley | 0:20a27391f6dc | 494 | #define QEI_INTEN_ERR_Int ((uint32_t)(1<<4)) /**< Enabled Interrupt Bit Indicates that an encoder phase error was detected */ |
| hexley | 0:20a27391f6dc | 495 | #define QEI_INTEN_ENCLK_Int ((uint32_t)(1<<5)) /**< Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */ |
| hexley | 0:20a27391f6dc | 496 | #define QEI_INTEN_POS0_Int ((uint32_t)(1<<6)) /**< Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 497 | current position */ |
| hexley | 0:20a27391f6dc | 498 | #define QEI_INTEN_POS1_Int ((uint32_t)(1<<7)) /**< Enabled Interrupt Bit Indicates that the position 1compare value is equal to the |
| hexley | 0:20a27391f6dc | 499 | current position */ |
| hexley | 0:20a27391f6dc | 500 | #define QEI_INTEN_POS2_Int ((uint32_t)(1<<8)) /**< Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 501 | current position */ |
| hexley | 0:20a27391f6dc | 502 | #define QEI_INTEN_REV_Int ((uint32_t)(1<<9)) /**< Enabled Interrupt Bit Indicates that the index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 503 | index count */ |
| hexley | 0:20a27391f6dc | 504 | #define QEI_INTEN_POS0REV_Int ((uint32_t)(1<<10)) /**< Enabled Interrupt Bit that combined position 0 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 505 | #define QEI_INTEN_POS1REV_Int ((uint32_t)(1<<11)) /**< Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 506 | #define QEI_INTEN_POS2REV_Int ((uint32_t)(1<<12)) /**< Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 507 | #define QEI_INTEN_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable register bit-mask */ |
| hexley | 0:20a27391f6dc | 508 | |
| hexley | 0:20a27391f6dc | 509 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 510 | * Macro defines for QEI Interrupt Enable Set register |
| hexley | 0:20a27391f6dc | 511 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 512 | #define QEI_IESET_INX_Int ((uint32_t)(1<<0)) /**< Set Enable Interrupt Bit Indicates that an index pulse was detected */ |
| hexley | 0:20a27391f6dc | 513 | #define QEI_IESET_TIM_Int ((uint32_t)(1<<1)) /**< Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */ |
| hexley | 0:20a27391f6dc | 514 | #define QEI_IESET_VELC_Int ((uint32_t)(1<<2)) /**< Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */ |
| hexley | 0:20a27391f6dc | 515 | #define QEI_IESET_DIR_Int ((uint32_t)(1<<3)) /**< Set Enable Interrupt Bit Indicates that a change of direction was detected */ |
| hexley | 0:20a27391f6dc | 516 | #define QEI_IESET_ERR_Int ((uint32_t)(1<<4)) /**< Set Enable Interrupt Bit Indicates that an encoder phase error was detected */ |
| hexley | 0:20a27391f6dc | 517 | #define QEI_IESET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */ |
| hexley | 0:20a27391f6dc | 518 | #define QEI_IESET_POS0_Int ((uint32_t)(1<<6)) /**< Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 519 | current position */ |
| hexley | 0:20a27391f6dc | 520 | #define QEI_IESET_POS1_Int ((uint32_t)(1<<7)) /**< Set Enable Interrupt Bit Indicates that the position 1compare value is equal to the |
| hexley | 0:20a27391f6dc | 521 | current position */ |
| hexley | 0:20a27391f6dc | 522 | #define QEI_IESET_POS2_Int ((uint32_t)(1<<8)) /**< Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 523 | current position */ |
| hexley | 0:20a27391f6dc | 524 | #define QEI_IESET_REV_Int ((uint32_t)(1<<9)) /**< Set Enable Interrupt Bit Indicates that the index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 525 | index count */ |
| hexley | 0:20a27391f6dc | 526 | #define QEI_IESET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 527 | #define QEI_IESET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 528 | #define QEI_IESET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 529 | #define QEI_IESET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Set register bit-mask */ |
| hexley | 0:20a27391f6dc | 530 | |
| hexley | 0:20a27391f6dc | 531 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 532 | * Macro defines for QEI Interrupt Enable Clear register |
| hexley | 0:20a27391f6dc | 533 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 534 | #define QEI_IECLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Enabled Interrupt Bit Indicates that an index pulse was detected */ |
| hexley | 0:20a27391f6dc | 535 | #define QEI_IECLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */ |
| hexley | 0:20a27391f6dc | 536 | #define QEI_IECLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */ |
| hexley | 0:20a27391f6dc | 537 | #define QEI_IECLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Enabled Interrupt Bit Indicates that a change of direction was detected */ |
| hexley | 0:20a27391f6dc | 538 | #define QEI_IECLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */ |
| hexley | 0:20a27391f6dc | 539 | #define QEI_IECLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */ |
| hexley | 0:20a27391f6dc | 540 | #define QEI_IECLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 541 | current position */ |
| hexley | 0:20a27391f6dc | 542 | #define QEI_IECLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the |
| hexley | 0:20a27391f6dc | 543 | current position */ |
| hexley | 0:20a27391f6dc | 544 | #define QEI_IECLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 545 | current position */ |
| hexley | 0:20a27391f6dc | 546 | #define QEI_IECLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 547 | index count */ |
| hexley | 0:20a27391f6dc | 548 | #define QEI_IECLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 549 | #define QEI_IECLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 550 | #define QEI_IECLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 551 | #define QEI_IECLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Clear register bit-mask */ |
| hexley | 0:20a27391f6dc | 552 | |
| hexley | 0:20a27391f6dc | 553 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 554 | * Macro defines for PCONP register QEI-related bits |
| hexley | 0:20a27391f6dc | 555 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 556 | #define PCONP_QEI_ENABLE ((uint32_t)(1<<18)) /**< QEI peripheral power enable bit */ |
| hexley | 0:20a27391f6dc | 557 | #define PCONP_QEI_DISABLE ~((uint32_t)(1<<18)) /**< QEI peripheral power disable bit-mask */ |
| hexley | 0:20a27391f6dc | 558 | |
| hexley | 0:20a27391f6dc | 559 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 560 | * Macro defines for PCLKSELx register QEI-related bits |
| hexley | 0:20a27391f6dc | 561 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 562 | #define PCLKSEL_CCLK_DIV_1 1UL /**< Set PCLK to CCLK/1 */ |
| hexley | 0:20a27391f6dc | 563 | #define PCLKSEL_CCLK_DIV_2 2UL /**< Set PCLK to CCLK/2 */ |
| hexley | 0:20a27391f6dc | 564 | #define PCLKSEL_CCLK_DIV_4 0UL /**< Set PCLK to CCLK/4 */ |
| hexley | 0:20a27391f6dc | 565 | #define PCLKSEL_CCLK_DIV_8 3UL /**< Set PCLK to CCLK/8 */ |
| hexley | 0:20a27391f6dc | 566 | #define PCLKSEL1_PCLK_QEI_MASK ((uint32_t)(3<<0)) /**< PCLK_QEI PCLK_QEI bit field mask */ |
| hexley | 0:20a27391f6dc | 567 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 568 | * Macro defines for PINSEL3 register QEI-related bits |
| hexley | 0:20a27391f6dc | 569 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 570 | #define PINSEL3_MCI0 ((uint32_t)(1<<8)) /**< MCIO (PhA) pin select */ |
| hexley | 0:20a27391f6dc | 571 | #define PINSEL3_MCI0_MASK ~((uint32_t)(3<<8)) /**< MCIO (PhA) pin mask */ |
| hexley | 0:20a27391f6dc | 572 | #define PINSEL3_MCI1 ((uint32_t)(1<<14)) /**< MCI1 (PhB) pin select */ |
| hexley | 0:20a27391f6dc | 573 | #define PINSEL3_MCI1_MASK ~((uint32_t)(3<<14)) /**< MCI2 (PhB) pin mask */ |
| hexley | 0:20a27391f6dc | 574 | #define PINSEL3_MCI2 ((uint32_t)(1<<16)) /**< MCI2 (Index) pin select */ |
| hexley | 0:20a27391f6dc | 575 | #define PINSEL3_MCI2_MASK ~((uint32_t)(3<<16)) /**< MCI2 (Index) pin mask */ |
| hexley | 0:20a27391f6dc | 576 | |
| hexley | 0:20a27391f6dc | 577 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 578 | * Macro defines for PINMODE3 register QEI-related bits |
| hexley | 0:20a27391f6dc | 579 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 580 | #define PIN_PULL_UP 0UL |
| hexley | 0:20a27391f6dc | 581 | #define PIN_REPEATER 1UL |
| hexley | 0:20a27391f6dc | 582 | #define PIN_NORESISTOR 2UL |
| hexley | 0:20a27391f6dc | 583 | #define PIN_PULL_DOWN 3UL |
| hexley | 0:20a27391f6dc | 584 | |
| hexley | 0:20a27391f6dc | 585 | #define PINMODE3_MCI0 ((uint32_t)(PIN_NORESISTOR<<8)) /**< MCIO (PhA) resistor selection */ |
| hexley | 0:20a27391f6dc | 586 | #define PINMODE3_GPIO1p20 ((uint32_t)(PIN_PULL_DOWN<<8)) /**< GPIO 1.20) resistor selection */ |
| hexley | 0:20a27391f6dc | 587 | #define PINMODE3_MCI0_MASK ~((uint32_t)(3<<8)) /**< MCIO (PhA) resistor mask */ |
| hexley | 0:20a27391f6dc | 588 | |
| hexley | 0:20a27391f6dc | 589 | #define PINMODE3_MCI1 ((uint32_t)(PIN_NORESISTOR<<14)) /**< MCI1 (PhB) resistor selection */ |
| hexley | 0:20a27391f6dc | 590 | #define PINMODE3_GPIO1p23 ((uint32_t)(PIN_PULL_DOWN<<14)) /**< GPIO 1.23) resistor selection */ |
| hexley | 0:20a27391f6dc | 591 | #define PINMODE3_MCI1_MASK ~((uint32_t)(3<<14)) /**< MCI1 (PhB) resistor mask */ |
| hexley | 0:20a27391f6dc | 592 | |
| hexley | 0:20a27391f6dc | 593 | #define PINMODE3_MCI2 ((uint32_t)(PIN_PULL_UP<<16)) /**< MCI2 (Index) resistor selection */ |
| hexley | 0:20a27391f6dc | 594 | #define PINMODE3_GPIO1p24 ((uint32_t)(PIN_PULL_DOWN<<16)) /**< GPIO 1.24) resistor selection */ |
| hexley | 0:20a27391f6dc | 595 | #define PINMODE3_MCI2_MASK ~((uint32_t)(3<<16)) /**< MCI2 (Index) resistor mask */ |
| hexley | 0:20a27391f6dc | 596 | |
| hexley | 0:20a27391f6dc | 597 | }; |
| hexley | 0:20a27391f6dc | 598 | |
| hexley | 0:20a27391f6dc | 599 | |
| hexley | 0:20a27391f6dc | 600 | #endif /* MBED_QEI_H */ |
| hexley | 0:20a27391f6dc | 601 | /* --------------------------------- End Of File ------------------------------ */ |