Wilson Tang
Port to LPC1549. Partially tested, not all features ported
Fork of
QEI_hw
by 
Hexley Ball
qeihw.h@1:018226f83d80, 2010-12-11 (annotated)
- Committer:
- hexley
- Date:
- Sat Dec 11 01:51:58 2010 +0000
- Revision:
- 1:018226f83d80
- Parent:
- 0:20a27391f6dc
- Child:
- 3:68844cd35e64
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| hexley | 0:20a27391f6dc | 1 | /* mbed Library - QEIhw |
| hexley | 0:20a27391f6dc | 2 | * Copyright (c) 2010, hball |
| hexley | 0:20a27391f6dc | 3 | * released under MIT license http://mbed.org/licence/mit |
| hexley | 0:20a27391f6dc | 4 | */ |
| hexley | 0:20a27391f6dc | 5 | |
| hexley | 0:20a27391f6dc | 6 | /***********************************************************************//** |
| hexley | 0:20a27391f6dc | 7 | * @file qeihw.h |
| hexley | 0:20a27391f6dc | 8 | * @brief Header file for the qeihw driver. Adapted from the CMSIS |
| hexley | 0:20a27391f6dc | 9 | * header, lpc17xx_qei.h, v 2.0 |
| hexley | 0:20a27391f6dc | 10 | * @version 0.0 |
| hexley | 0:20a27391f6dc | 11 | * @date 10 Dec 2010 |
| hexley | 0:20a27391f6dc | 12 | * @author hb |
| hexley | 0:20a27391f6dc | 13 | **************************************************************************/ |
| hexley | 0:20a27391f6dc | 14 | |
| hexley | 0:20a27391f6dc | 15 | |
| hexley | 0:20a27391f6dc | 16 | #ifndef MBED_QEIHW_H |
| hexley | 0:20a27391f6dc | 17 | #define MBED_QEIHW_H |
| hexley | 0:20a27391f6dc | 18 | |
| hexley | 0:20a27391f6dc | 19 | /* Includes ------------------------------------------------------------------- */ |
| hexley | 0:20a27391f6dc | 20 | #include "mbed.h" |
| hexley | 0:20a27391f6dc | 21 | |
| hexley | 0:20a27391f6dc | 22 | |
| hexley | 0:20a27391f6dc | 23 | /* Public Types --------------------------------------------------------------- */ |
| hexley | 0:20a27391f6dc | 24 | |
| hexley | 0:20a27391f6dc | 25 | /* Flag Status type definition */ |
| hexley | 0:20a27391f6dc | 26 | typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState; |
| hexley | 0:20a27391f6dc | 27 | |
| hexley | 0:20a27391f6dc | 28 | /* Functional State Definition */ |
| hexley | 0:20a27391f6dc | 29 | typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; |
| hexley | 0:20a27391f6dc | 30 | |
| hexley | 0:20a27391f6dc | 31 | |
| hexley | 0:20a27391f6dc | 32 | /* Other definitions */ |
| hexley | 0:20a27391f6dc | 33 | #define XTAL_FREQ 12000000 |
| hexley | 0:20a27391f6dc | 34 | |
| hexley | 0:20a27391f6dc | 35 | /* Public Functions ----------------------------------------------------------- */ |
| hexley | 0:20a27391f6dc | 36 | /** @defgroup QEI_Public_Functions QEI Public Functions |
| hexley | 0:20a27391f6dc | 37 | */ |
| hexley | 1:018226f83d80 | 38 | |
| hexley | 1:018226f83d80 | 39 | /** QEI hardware interface class |
| hexley | 1:018226f83d80 | 40 | * Requires mbed hardware modification: connect |
| hexley | 1:018226f83d80 | 41 | * encoder PhA to p1.20, and PhB to p1.23. |
| hexley | 1:018226f83d80 | 42 | * |
| hexley | 1:018226f83d80 | 43 | * Example: |
| hexley | 1:018226f83d80 | 44 | * @code |
| hexley | 1:018226f83d80 | 45 | * // Display changes in encoder position and direction |
| hexley | 1:018226f83d80 | 46 | #include "mbed.h" |
| hexley | 1:018226f83d80 | 47 | * #include "qeihw.h" |
| hexley | 1:018226f83d80 | 48 | * |
| hexley | 1:018226f83d80 | 49 | * DigitalOut led1(LED1); |
| hexley | 1:018226f83d80 | 50 | * DigitalOut led3(LED3); |
| hexley | 1:018226f83d80 | 51 | * QEIHW qei(QEI_DIRINV_NONE, QEI_SIGNALMODE_QUAD, QEI_CAPMODE_2X, QEI_INVINX_NONE ); |
| hexley | 1:018226f83d80 | 52 | * |
| hexley | 1:018226f83d80 | 53 | * int main() { |
| hexley | 1:018226f83d80 | 54 | * int32_t temp, position = 0; |
| hexley | 1:018226f83d80 | 55 | * qei.SetDigiFilter(480UL); |
| hexley | 1:018226f83d80 | 56 | * qei.SetMaxPosition(0xFFFFFFFF); |
| hexley | 1:018226f83d80 | 57 | * |
| hexley | 1:018226f83d80 | 58 | * while(1) { |
| hexley | 1:018226f83d80 | 59 | * while(position == (temp = qei.GetPosition()) ); |
| hexley | 1:018226f83d80 | 60 | * position = temp; |
| hexley | 1:018226f83d80 | 61 | * printf("New position = %d.\r\n", temp); |
| hexley | 1:018226f83d80 | 62 | * led1 = qei.Direction() == SET ? 1 : 0; |
| hexley | 1:018226f83d80 | 63 | * led3 = !led1; |
| hexley | 1:018226f83d80 | 64 | * wait(0.1); |
| hexley | 1:018226f83d80 | 65 | * } |
| hexley | 1:018226f83d80 | 66 | * } |
| hexley | 1:018226f83d80 | 67 | * @endcode |
| hexley | 1:018226f83d80 | 68 | */ |
| hexley | 1:018226f83d80 | 69 | |
| hexley | 0:20a27391f6dc | 70 | class QEIHW { |
| hexley | 0:20a27391f6dc | 71 | public: |
| hexley | 0:20a27391f6dc | 72 | |
| hexley | 0:20a27391f6dc | 73 | /** Create a QEI object and configure it |
| hexley | 0:20a27391f6dc | 74 | * |
| hexley | 0:20a27391f6dc | 75 | * @param _dirinv Direction invert. When = 1, complements the QEICONF register DIR bit |
| hexley | 0:20a27391f6dc | 76 | * @param _sigmode Signal mode. When = 0, PhA and PhB are quadrature inputs. When = 1, PhA is direction and PhB is clock |
| hexley | 0:20a27391f6dc | 77 | * @param _capmode Capture mode. When = 0, count PhA edges only (2X mode). Whe = 1, count PhB edges also (4X mode). |
| hexley | 0:20a27391f6dc | 78 | * @param _invinx Invert index. When = 1, inverts the sense of the index signal |
| hexley | 0:20a27391f6dc | 79 | */ |
| hexley | 0:20a27391f6dc | 80 | QEIHW( uint32_t _dirinv, uint32_t _sigmode, uint32_t _capmode, uint32_t _invinx); |
| hexley | 0:20a27391f6dc | 81 | |
| hexley | 0:20a27391f6dc | 82 | /** Resets value for each type of QEI value, such as velocity, position, etc. |
| hexley | 0:20a27391f6dc | 83 | * |
| hexley | 0:20a27391f6dc | 84 | * @param[in] ulResetType QEI Reset Type, should be one of the following: |
| hexley | 0:20a27391f6dc | 85 | * - QEI_RESET_POS: Reset Position Counter |
| hexley | 0:20a27391f6dc | 86 | * - QEI_RESET_POSOnIDX: Reset Position Counter on Index signal |
| hexley | 0:20a27391f6dc | 87 | * - QEI_RESET_VEL: Reset Velocity |
| hexley | 0:20a27391f6dc | 88 | * - QEI_RESET_IDX: Reset Index Counter |
| hexley | 0:20a27391f6dc | 89 | */ |
| hexley | 0:20a27391f6dc | 90 | void Reset(uint32_t ulResetType); |
| hexley | 0:20a27391f6dc | 91 | |
| hexley | 0:20a27391f6dc | 92 | /** Powers down the QEI block, returns pins to GPIO mode |
| hexley | 0:20a27391f6dc | 93 | * |
| hexley | 0:20a27391f6dc | 94 | */ |
| hexley | 0:20a27391f6dc | 95 | void DeInit(); |
| hexley | 0:20a27391f6dc | 96 | |
| hexley | 0:20a27391f6dc | 97 | /** Report direction (QEISTAT bit DIR) |
| hexley | 0:20a27391f6dc | 98 | * |
| hexley | 0:20a27391f6dc | 99 | * @return State of the DIR bit (SET or RESET) |
| hexley | 0:20a27391f6dc | 100 | */ |
| hexley | 0:20a27391f6dc | 101 | FlagStatus Direction(); |
| hexley | 0:20a27391f6dc | 102 | |
| hexley | 0:20a27391f6dc | 103 | /** |
| hexley | 0:20a27391f6dc | 104 | * @brief Get current position value in QEI peripheral |
| hexley | 0:20a27391f6dc | 105 | * |
| hexley | 0:20a27391f6dc | 106 | * @return Current position value of QEI peripheral |
| hexley | 0:20a27391f6dc | 107 | */ |
| hexley | 0:20a27391f6dc | 108 | uint32_t GetPosition(); |
| hexley | 0:20a27391f6dc | 109 | |
| hexley | 0:20a27391f6dc | 110 | /** Set max position value for QEI peripheral |
| hexley | 0:20a27391f6dc | 111 | * |
| hexley | 0:20a27391f6dc | 112 | * @param[in] ulMaxPos Max position value to set |
| hexley | 0:20a27391f6dc | 113 | * @return None |
| hexley | 0:20a27391f6dc | 114 | */ |
| hexley | 0:20a27391f6dc | 115 | void SetMaxPosition(uint32_t ulMaxPos); |
| hexley | 0:20a27391f6dc | 116 | |
| hexley | 0:20a27391f6dc | 117 | /** Set position compare value for QEI peripheral |
| hexley | 0:20a27391f6dc | 118 | * @param[in] bPosCompCh Compare Position channel, should be: |
| hexley | 0:20a27391f6dc | 119 | * - QEI_COMPPOS_CH_0: QEI compare position channel 0 |
| hexley | 0:20a27391f6dc | 120 | * - QEI_COMPPOS_CH_1: QEI compare position channel 1 |
| hexley | 0:20a27391f6dc | 121 | * - QEI_COMPPOS_CH_2: QEI compare position channel 2 |
| hexley | 0:20a27391f6dc | 122 | * @param[in] ulPosComp Compare Position value to set |
| hexley | 0:20a27391f6dc | 123 | * @return None |
| hexley | 0:20a27391f6dc | 124 | */ |
| hexley | 0:20a27391f6dc | 125 | void SetPositionComp( uint8_t bPosCompCh, uint32_t ulPosComp); |
| hexley | 0:20a27391f6dc | 126 | |
| hexley | 0:20a27391f6dc | 127 | /** Get current index counter of QEI peripheral |
| hexley | 0:20a27391f6dc | 128 | * |
| hexley | 0:20a27391f6dc | 129 | * @return Current value of QEI index counter |
| hexley | 0:20a27391f6dc | 130 | */ |
| hexley | 0:20a27391f6dc | 131 | uint32_t GetIndex(); |
| hexley | 0:20a27391f6dc | 132 | |
| hexley | 0:20a27391f6dc | 133 | /** Set value for index compare in QEI peripheral |
| hexley | 0:20a27391f6dc | 134 | * @param[in] ulIndexComp Compare Index Value to set |
| hexley | 0:20a27391f6dc | 135 | * @return None |
| hexley | 0:20a27391f6dc | 136 | */ |
| hexley | 0:20a27391f6dc | 137 | void SetIndexComp( uint32_t ulIndexComp); |
| hexley | 0:20a27391f6dc | 138 | |
| hexley | 0:20a27391f6dc | 139 | /** Set Velocity timer reload value |
| hexley | 0:20a27391f6dc | 140 | * |
| hexley | 0:20a27391f6dc | 141 | * @param[in] ulReloadValue Velocity timer reload count |
| hexley | 0:20a27391f6dc | 142 | * @return None |
| hexley | 0:20a27391f6dc | 143 | */ |
| hexley | 0:20a27391f6dc | 144 | void SetVelocityTimerReload( uint32_t ulReloadValue); |
| hexley | 0:20a27391f6dc | 145 | |
| hexley | 0:20a27391f6dc | 146 | /** Set Velocity timer reload value in microseconds |
| hexley | 0:20a27391f6dc | 147 | * |
| hexley | 0:20a27391f6dc | 148 | * @param[in] ulReloadValue Velocity timer reload count |
| hexley | 0:20a27391f6dc | 149 | * @return None |
| hexley | 0:20a27391f6dc | 150 | */ |
| hexley | 0:20a27391f6dc | 151 | void SetVelocityTimerReload_us( uint32_t ulReloadValue); |
| hexley | 0:20a27391f6dc | 152 | |
| hexley | 0:20a27391f6dc | 153 | /** Get current timer counter in QEI peripheral |
| hexley | 0:20a27391f6dc | 154 | * |
| hexley | 0:20a27391f6dc | 155 | * @return Current timer counter in QEI peripheral |
| hexley | 0:20a27391f6dc | 156 | */ |
| hexley | 0:20a27391f6dc | 157 | uint32_t GetTimer(); |
| hexley | 0:20a27391f6dc | 158 | |
| hexley | 0:20a27391f6dc | 159 | /** Get current velocity pulse counter in current time period |
| hexley | 0:20a27391f6dc | 160 | * |
| hexley | 0:20a27391f6dc | 161 | * @return Current velocity pulse counter value |
| hexley | 0:20a27391f6dc | 162 | */ |
| hexley | 0:20a27391f6dc | 163 | uint32_t GetVelocity(); |
| hexley | 0:20a27391f6dc | 164 | |
| hexley | 0:20a27391f6dc | 165 | /** Get the most recently measured velocity of the QEI. When |
| hexley | 0:20a27391f6dc | 166 | * the Velocity timer in QEI is over-flow, the current velocity |
| hexley | 0:20a27391f6dc | 167 | * value will be loaded into Velocity Capture register. |
| hexley | 0:20a27391f6dc | 168 | * |
| hexley | 0:20a27391f6dc | 169 | * @return The most recently measured velocity value |
| hexley | 0:20a27391f6dc | 170 | */ |
| hexley | 0:20a27391f6dc | 171 | uint32_t GetVelocityCap(); |
| hexley | 0:20a27391f6dc | 172 | |
| hexley | 0:20a27391f6dc | 173 | /** Set Velocity Compare value for QEI peripheral |
| hexley | 0:20a27391f6dc | 174 | * |
| hexley | 0:20a27391f6dc | 175 | * @param[in] ulVelComp Compare Velocity value to set |
| hexley | 0:20a27391f6dc | 176 | * @return None |
| hexley | 0:20a27391f6dc | 177 | */ |
| hexley | 0:20a27391f6dc | 178 | void SetVelocityComp( uint32_t ulVelComp); |
| hexley | 0:20a27391f6dc | 179 | |
| hexley | 0:20a27391f6dc | 180 | /** Set value of sampling count for the digital filter in |
| hexley | 0:20a27391f6dc | 181 | * QEI peripheral |
| hexley | 0:20a27391f6dc | 182 | * |
| hexley | 0:20a27391f6dc | 183 | * @param[in] ulSamplingPulse Value of sampling count to set |
| hexley | 0:20a27391f6dc | 184 | * @return None |
| hexley | 0:20a27391f6dc | 185 | */ |
| hexley | 0:20a27391f6dc | 186 | void SetDigiFilter( uint32_t ulSamplingPulse); |
| hexley | 0:20a27391f6dc | 187 | |
| hexley | 0:20a27391f6dc | 188 | /** Check whether if specified interrupt flag status in QEI |
| hexley | 0:20a27391f6dc | 189 | * peripheral is set or not |
| hexley | 0:20a27391f6dc | 190 | * |
| hexley | 0:20a27391f6dc | 191 | * @param[in] ulIntType Interrupt Flag Status type, should be: |
| hexley | 0:20a27391f6dc | 192 | - QEI_INTFLAG_INX_Int: index pulse was detected interrupt |
| hexley | 0:20a27391f6dc | 193 | - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt |
| hexley | 0:20a27391f6dc | 194 | - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt |
| hexley | 0:20a27391f6dc | 195 | - QEI_INTFLAG_DIR_Int: Change of direction interrupt |
| hexley | 0:20a27391f6dc | 196 | - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt |
| hexley | 0:20a27391f6dc | 197 | - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt |
| hexley | 0:20a27391f6dc | 198 | - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 199 | current position interrupt |
| hexley | 0:20a27391f6dc | 200 | - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the |
| hexley | 0:20a27391f6dc | 201 | current position interrupt |
| hexley | 0:20a27391f6dc | 202 | - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 203 | current position interrupt |
| hexley | 0:20a27391f6dc | 204 | - QEI_INTFLAG_REV_Int: Index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 205 | index count interrupt |
| hexley | 0:20a27391f6dc | 206 | - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 207 | - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 208 | - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 209 | * @return New State of specified interrupt flag status (SET or RESET) |
| hexley | 0:20a27391f6dc | 210 | */ |
| hexley | 0:20a27391f6dc | 211 | FlagStatus GetIntStatus( uint32_t ulIntType); |
| hexley | 0:20a27391f6dc | 212 | |
| hexley | 0:20a27391f6dc | 213 | /** Enable/Disable specified interrupt in QEI peripheral |
| hexley | 0:20a27391f6dc | 214 | * |
| hexley | 0:20a27391f6dc | 215 | * @param[in] ulIntType Interrupt Flag Status type, should be: |
| hexley | 0:20a27391f6dc | 216 | * - QEI_INTFLAG_INX_Int: index pulse was detected interrupt |
| hexley | 0:20a27391f6dc | 217 | * - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt |
| hexley | 0:20a27391f6dc | 218 | * - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt |
| hexley | 0:20a27391f6dc | 219 | * - QEI_INTFLAG_DIR_Int: Change of direction interrupt |
| hexley | 0:20a27391f6dc | 220 | * - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt |
| hexley | 0:20a27391f6dc | 221 | * - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt |
| hexley | 0:20a27391f6dc | 222 | * - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 223 | * current position interrupt |
| hexley | 0:20a27391f6dc | 224 | * - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the |
| hexley | 0:20a27391f6dc | 225 | * current position interrupt |
| hexley | 0:20a27391f6dc | 226 | * - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 227 | * current position interrupt |
| hexley | 0:20a27391f6dc | 228 | * - QEI_INTFLAG_REV_Int: Index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 229 | * index count interrupt |
| hexley | 0:20a27391f6dc | 230 | * - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 231 | * - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 232 | * - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 233 | * @param[in] NewState New function state, should be: |
| hexley | 0:20a27391f6dc | 234 | * - DISABLE |
| hexley | 0:20a27391f6dc | 235 | * - ENABLE |
| hexley | 0:20a27391f6dc | 236 | * @return None |
| hexley | 0:20a27391f6dc | 237 | */ |
| hexley | 0:20a27391f6dc | 238 | void IntCmd( uint32_t ulIntType, FunctionalState NewState); |
| hexley | 0:20a27391f6dc | 239 | |
| hexley | 0:20a27391f6dc | 240 | /** Asserts specified interrupt in QEI peripheral |
| hexley | 0:20a27391f6dc | 241 | * |
| hexley | 0:20a27391f6dc | 242 | * @param[in] ulIntType Interrupt Flag Status type, should be: |
| hexley | 0:20a27391f6dc | 243 | - QEI_INTFLAG_INX_Int: index pulse was detected interrupt |
| hexley | 0:20a27391f6dc | 244 | - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt |
| hexley | 0:20a27391f6dc | 245 | - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt |
| hexley | 0:20a27391f6dc | 246 | - QEI_INTFLAG_DIR_Int: Change of direction interrupt |
| hexley | 0:20a27391f6dc | 247 | - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt |
| hexley | 0:20a27391f6dc | 248 | - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt |
| hexley | 0:20a27391f6dc | 249 | - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 250 | current position interrupt |
| hexley | 0:20a27391f6dc | 251 | - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the |
| hexley | 0:20a27391f6dc | 252 | current position interrupt |
| hexley | 0:20a27391f6dc | 253 | - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 254 | current position interrupt |
| hexley | 0:20a27391f6dc | 255 | - QEI_INTFLAG_REV_Int: Index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 256 | index count interrupt |
| hexley | 0:20a27391f6dc | 257 | - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 258 | - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 259 | - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 260 | * @return None |
| hexley | 0:20a27391f6dc | 261 | */ |
| hexley | 0:20a27391f6dc | 262 | void IntSet( uint32_t ulIntType); |
| hexley | 0:20a27391f6dc | 263 | |
| hexley | 0:20a27391f6dc | 264 | /** De-asserts specified interrupt (pending) in QEI peripheral |
| hexley | 0:20a27391f6dc | 265 | * |
| hexley | 0:20a27391f6dc | 266 | * @param[in] ulIntType Interrupt Flag Status type, should be: |
| hexley | 0:20a27391f6dc | 267 | - QEI_INTFLAG_INX_Int: index pulse was detected interrupt |
| hexley | 0:20a27391f6dc | 268 | - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt |
| hexley | 0:20a27391f6dc | 269 | - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt |
| hexley | 0:20a27391f6dc | 270 | - QEI_INTFLAG_DIR_Int: Change of direction interrupt |
| hexley | 0:20a27391f6dc | 271 | - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt |
| hexley | 0:20a27391f6dc | 272 | - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt |
| hexley | 0:20a27391f6dc | 273 | - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 274 | current position interrupt |
| hexley | 0:20a27391f6dc | 275 | - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the |
| hexley | 0:20a27391f6dc | 276 | current position interrupt |
| hexley | 0:20a27391f6dc | 277 | - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 278 | current position interrupt |
| hexley | 0:20a27391f6dc | 279 | - QEI_INTFLAG_REV_Int: Index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 280 | index count interrupt |
| hexley | 0:20a27391f6dc | 281 | - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 282 | - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 283 | - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 284 | * @return None |
| hexley | 0:20a27391f6dc | 285 | */ |
| hexley | 0:20a27391f6dc | 286 | void IntClear( uint32_t ulIntType); |
| hexley | 0:20a27391f6dc | 287 | |
| hexley | 0:20a27391f6dc | 288 | /** Append interrupt handler for specific QEI interrupt source |
| hexley | 0:20a27391f6dc | 289 | * |
| hexley | 0:20a27391f6dc | 290 | * @param[in] ulISRType Interrupt Flag Status type, should be: |
| hexley | 0:20a27391f6dc | 291 | * - QEI_INTFLAG_INX_Int: index pulse was detected interrupt |
| hexley | 0:20a27391f6dc | 292 | * - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt |
| hexley | 0:20a27391f6dc | 293 | * - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt |
| hexley | 0:20a27391f6dc | 294 | * - QEI_INTFLAG_DIR_Int: Change of direction interrupt |
| hexley | 0:20a27391f6dc | 295 | * - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt |
| hexley | 0:20a27391f6dc | 296 | * - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt |
| hexley | 0:20a27391f6dc | 297 | * - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 298 | * current position interrupt |
| hexley | 0:20a27391f6dc | 299 | * - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the |
| hexley | 0:20a27391f6dc | 300 | * current position interrupt |
| hexley | 0:20a27391f6dc | 301 | * - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 302 | * current position interrupt |
| hexley | 0:20a27391f6dc | 303 | * - QEI_INTFLAG_REV_Int: Index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 304 | * index count interrupt |
| hexley | 0:20a27391f6dc | 305 | * - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 306 | * - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 307 | * - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 308 | * |
| hexley | 0:20a27391f6dc | 309 | * @return none |
| hexley | 0:20a27391f6dc | 310 | */ |
| hexley | 0:20a27391f6dc | 311 | void AppendISR(uint32_t ulISRType, void(*fptr)(void)); |
| hexley | 0:20a27391f6dc | 312 | |
| hexley | 0:20a27391f6dc | 313 | /** Unappend interrupt handler for specific QEI interrupt source |
| hexley | 0:20a27391f6dc | 314 | * |
| hexley | 0:20a27391f6dc | 315 | * @param[in] ulISRType Interrupt Flag Status type, should be: |
| hexley | 0:20a27391f6dc | 316 | * - QEI_INTFLAG_INX_Int: index pulse was detected interrupt |
| hexley | 0:20a27391f6dc | 317 | * - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt |
| hexley | 0:20a27391f6dc | 318 | * - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt |
| hexley | 0:20a27391f6dc | 319 | * - QEI_INTFLAG_DIR_Int: Change of direction interrupt |
| hexley | 0:20a27391f6dc | 320 | * - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt |
| hexley | 0:20a27391f6dc | 321 | * - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt |
| hexley | 0:20a27391f6dc | 322 | * - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 323 | * current position interrupt |
| hexley | 0:20a27391f6dc | 324 | * - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the |
| hexley | 0:20a27391f6dc | 325 | * current position interrupt |
| hexley | 0:20a27391f6dc | 326 | * - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 327 | * current position interrupt |
| hexley | 0:20a27391f6dc | 328 | * - QEI_INTFLAG_REV_Int: Index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 329 | * index count interrupt |
| hexley | 0:20a27391f6dc | 330 | * - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 331 | * - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 332 | * - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt |
| hexley | 0:20a27391f6dc | 333 | * |
| hexley | 0:20a27391f6dc | 334 | * @return none |
| hexley | 0:20a27391f6dc | 335 | */ |
| hexley | 0:20a27391f6dc | 336 | void UnAppendISR(uint32_t ulISRType); |
| hexley | 0:20a27391f6dc | 337 | |
| hexley | 0:20a27391f6dc | 338 | |
| hexley | 0:20a27391f6dc | 339 | /** |
| hexley | 0:20a27391f6dc | 340 | * @brief Calculates the actual velocity in RPM passed via velocity |
| hexley | 0:20a27391f6dc | 341 | * capture value and Pulse Per Revolution (of the encoder) value |
| hexley | 0:20a27391f6dc | 342 | * parameter input. |
| hexley | 0:20a27391f6dc | 343 | * |
| hexley | 0:20a27391f6dc | 344 | * @param[in] ulVelCapValue Velocity capture input value that can |
| hexley | 0:20a27391f6dc | 345 | * be got from QEI_GetVelocityCap() function |
| hexley | 0:20a27391f6dc | 346 | * @param[in] ulPPR Pulse per round of encoder |
| hexley | 0:20a27391f6dc | 347 | * @return The actual value of velocity in RPM (Revolutions per minute) |
| hexley | 0:20a27391f6dc | 348 | */ |
| hexley | 0:20a27391f6dc | 349 | uint32_t CalculateRPM( uint32_t ulVelCapValue, uint32_t ulPPR); |
| hexley | 0:20a27391f6dc | 350 | |
| hexley | 0:20a27391f6dc | 351 | |
| hexley | 0:20a27391f6dc | 352 | /* Public Macros -------------------------------------------------------------- */ |
| hexley | 0:20a27391f6dc | 353 | /* QEI Reset types */ |
| hexley | 0:20a27391f6dc | 354 | #define QEI_RESET_POS QEI_CON_RESP /**< Reset position counter */ |
| hexley | 0:20a27391f6dc | 355 | #define QEI_RESET_POSOnIDX QEI_CON_RESPI /**< Reset Posistion Counter on Index */ |
| hexley | 0:20a27391f6dc | 356 | #define QEI_RESET_VEL QEI_CON_RESV /**< Reset Velocity */ |
| hexley | 0:20a27391f6dc | 357 | #define QEI_RESET_IDX QEI_CON_RESI /**< Reset Index Counter */ |
| hexley | 0:20a27391f6dc | 358 | |
| hexley | 0:20a27391f6dc | 359 | /* QEI Direction Invert Type Option */ |
| hexley | 0:20a27391f6dc | 360 | #define QEI_DIRINV_NONE ((uint32_t)(0)) /**< Direction is not inverted */ |
| hexley | 0:20a27391f6dc | 361 | #define QEI_DIRINV_CMPL ((uint32_t)(1)) /**< Direction is complemented */ |
| hexley | 0:20a27391f6dc | 362 | |
| hexley | 0:20a27391f6dc | 363 | /* QEI Signal Mode Option */ |
| hexley | 0:20a27391f6dc | 364 | #define QEI_SIGNALMODE_QUAD ((uint32_t)(0)) /**< Signal operation: Quadrature phase mode */ |
| hexley | 0:20a27391f6dc | 365 | #define QEI_SIGNALMODE_CLKDIR ((uint32_t)(1)) /**< Signal operation: Clock/Direction mode */ |
| hexley | 0:20a27391f6dc | 366 | |
| hexley | 0:20a27391f6dc | 367 | /* QEI Capture Mode Option */ |
| hexley | 0:20a27391f6dc | 368 | #define QEI_CAPMODE_2X ((uint32_t)(0)) /**< Capture mode: Only Phase-A edges are counted (2X) */ |
| hexley | 0:20a27391f6dc | 369 | #define QEI_CAPMODE_4X ((uint32_t)(1)) /**< Capture mode: BOTH PhA and PhB edges are counted (4X)*/ |
| hexley | 0:20a27391f6dc | 370 | |
| hexley | 0:20a27391f6dc | 371 | /* QEI Invert Index Signal Option */ |
| hexley | 0:20a27391f6dc | 372 | #define QEI_INVINX_NONE ((uint32_t)(0)) /**< Invert Index signal option: None */ |
| hexley | 0:20a27391f6dc | 373 | #define QEI_INVINX_EN ((uint32_t)(1)) /**< Invert Index signal option: Enable */ |
| hexley | 0:20a27391f6dc | 374 | |
| hexley | 0:20a27391f6dc | 375 | /* QEI timer reload option */ |
| hexley | 0:20a27391f6dc | 376 | #define QEI_TIMERRELOAD_TICKVAL ((uint8_t)(0)) /**< Reload value in absolute value */ |
| hexley | 0:20a27391f6dc | 377 | #define QEI_TIMERRELOAD_USVAL ((uint8_t)(1)) /**< Reload value in microsecond value */ |
| hexley | 0:20a27391f6dc | 378 | |
| hexley | 0:20a27391f6dc | 379 | /* QEI Flag Status type */ |
| hexley | 0:20a27391f6dc | 380 | #define QEI_STATUS_DIR ((uint32_t)(1<<0)) /**< Direction status */ |
| hexley | 0:20a27391f6dc | 381 | |
| hexley | 0:20a27391f6dc | 382 | /* QEI Compare Position channel option */ |
| hexley | 0:20a27391f6dc | 383 | #define QEI_COMPPOS_CH_0 ((uint8_t)(0)) /**< QEI compare position channel 0 */ |
| hexley | 0:20a27391f6dc | 384 | #define QEI_COMPPOS_CH_1 ((uint8_t)(1)) /**< QEI compare position channel 1 */ |
| hexley | 0:20a27391f6dc | 385 | #define QEI_COMPPOS_CH_2 ((uint8_t)(2)) /**< QEI compare position channel 2 */ |
| hexley | 0:20a27391f6dc | 386 | |
| hexley | 0:20a27391f6dc | 387 | /* QEI interrupt flag type */ |
| hexley | 0:20a27391f6dc | 388 | #define QEI_INTFLAG_INX_Int ((uint32_t)(1<<0)) /**< index pulse was detected interrupt */ |
| hexley | 0:20a27391f6dc | 389 | #define QEI_INTFLAG_TIM_Int ((uint32_t)(1<<1)) /**< Velocity timer over flow interrupt */ |
| hexley | 0:20a27391f6dc | 390 | #define QEI_INTFLAG_VELC_Int ((uint32_t)(1<<2)) /**< Capture velocity is less than compare interrupt */ |
| hexley | 0:20a27391f6dc | 391 | #define QEI_INTFLAG_DIR_Int ((uint32_t)(1<<3)) /**< Change of direction interrupt */ |
| hexley | 0:20a27391f6dc | 392 | #define QEI_INTFLAG_ERR_Int ((uint32_t)(1<<4)) /**< An encoder phase error interrupt */ |
| hexley | 0:20a27391f6dc | 393 | #define QEI_INTFLAG_ENCLK_Int ((uint32_t)(1<<5)) /**< An encoder clock pulse was detected interrupt */ |
| hexley | 0:20a27391f6dc | 394 | #define QEI_INTFLAG_POS0_Int ((uint32_t)(1<<6)) /**< position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 395 | current position interrupt */ |
| hexley | 0:20a27391f6dc | 396 | #define QEI_INTFLAG_POS1_Int ((uint32_t)(1<<7)) /**< position 1 compare value is equal to the |
| hexley | 0:20a27391f6dc | 397 | current position interrupt */ |
| hexley | 0:20a27391f6dc | 398 | #define QEI_INTFLAG_POS2_Int ((uint32_t)(1<<8)) /**< position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 399 | current position interrupt */ |
| hexley | 0:20a27391f6dc | 400 | #define QEI_INTFLAG_REV_Int ((uint32_t)(1<<9)) /**< Index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 401 | index count interrupt */ |
| hexley | 0:20a27391f6dc | 402 | #define QEI_INTFLAG_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 403 | #define QEI_INTFLAG_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 404 | #define QEI_INTFLAG_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 405 | |
| hexley | 0:20a27391f6dc | 406 | /* QEI Process position reporting options */ |
| hexley | 0:20a27391f6dc | 407 | #define QEI_PROCESS_OPERATE 0; |
| hexley | 0:20a27391f6dc | 408 | #define QEI_PROCESS_RESET 1; |
| hexley | 0:20a27391f6dc | 409 | #define QEI_PROCESS_INCREMENTAL 0; |
| hexley | 0:20a27391f6dc | 410 | #define QEI_PROCESS_ACCUMULATE 1; |
| hexley | 0:20a27391f6dc | 411 | #define QEI_PROCESS_LINEAR 0; |
| hexley | 0:20a27391f6dc | 412 | #define QEI_PROCESS_WEIGHTED 1; |
| hexley | 0:20a27391f6dc | 413 | |
| hexley | 0:20a27391f6dc | 414 | private: |
| hexley | 0:20a27391f6dc | 415 | static void _Qeiisr(void); |
| hexley | 0:20a27391f6dc | 416 | void Qeiisr(void); |
| hexley | 0:20a27391f6dc | 417 | static QEIHW *instance; |
| hexley | 0:20a27391f6dc | 418 | |
| hexley | 0:20a27391f6dc | 419 | void(*_qei_isr[13])(); |
| hexley | 0:20a27391f6dc | 420 | |
| hexley | 0:20a27391f6dc | 421 | |
| hexley | 0:20a27391f6dc | 422 | /* Private Macros ------------------------------------------------------------- */ |
| hexley | 0:20a27391f6dc | 423 | /* --------------------- BIT DEFINITIONS -------------------------------------- */ |
| hexley | 0:20a27391f6dc | 424 | /* Quadrature Encoder Interface Control Register Definition --------------------- */ |
| hexley | 0:20a27391f6dc | 425 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 426 | * Macro defines for QEI Control register |
| hexley | 0:20a27391f6dc | 427 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 428 | #define QEI_CON_RESP ((uint32_t)(1<<0)) /**< Reset position counter */ |
| hexley | 0:20a27391f6dc | 429 | #define QEI_CON_RESPI ((uint32_t)(1<<1)) /**< Reset Posistion Counter on Index */ |
| hexley | 0:20a27391f6dc | 430 | #define QEI_CON_RESV ((uint32_t)(1<<2)) /**< Reset Velocity */ |
| hexley | 0:20a27391f6dc | 431 | #define QEI_CON_RESI ((uint32_t)(1<<3)) /**< Reset Index Counter */ |
| hexley | 0:20a27391f6dc | 432 | #define QEI_CON_BITMASK ((uint32_t)(0x0F)) /**< QEI Control register bit-mask */ |
| hexley | 0:20a27391f6dc | 433 | |
| hexley | 0:20a27391f6dc | 434 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 435 | * Macro defines for QEI Configuration register |
| hexley | 0:20a27391f6dc | 436 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 437 | #define QEI_CONF_DIRINV ((uint32_t)(1<<0)) /**< Direction Invert */ |
| hexley | 0:20a27391f6dc | 438 | #define QEI_CONF_SIGMODE ((uint32_t)(1<<1)) /**< Signal mode */ |
| hexley | 0:20a27391f6dc | 439 | #define QEI_CONF_CAPMODE ((uint32_t)(1<<2)) /**< Capture mode */ |
| hexley | 0:20a27391f6dc | 440 | #define QEI_CONF_INVINX ((uint32_t)(1<<3)) /**< Invert index */ |
| hexley | 0:20a27391f6dc | 441 | #define QEI_CONF_BITMASK ((uint32_t)(0x0F)) /**< QEI Configuration register bit-mask */ |
| hexley | 0:20a27391f6dc | 442 | |
| hexley | 0:20a27391f6dc | 443 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 444 | * Macro defines for QEI Status register |
| hexley | 0:20a27391f6dc | 445 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 446 | #define QEI_STAT_DIR ((uint32_t)(1<<0)) /**< Direction bit */ |
| hexley | 0:20a27391f6dc | 447 | #define QEI_STAT_BITMASK ((uint32_t)(1<<0)) /**< QEI status register bit-mask */ |
| hexley | 0:20a27391f6dc | 448 | |
| hexley | 0:20a27391f6dc | 449 | /* Quadrature Encoder Interface Interrupt registers definitions --------------------- */ |
| hexley | 0:20a27391f6dc | 450 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 451 | * Macro defines for QEI Interrupt Status register |
| hexley | 0:20a27391f6dc | 452 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 453 | #define QEI_INTSTAT_INX_Int ((uint32_t)(1<<0)) /**< Indicates that an index pulse was detected */ |
| hexley | 0:20a27391f6dc | 454 | #define QEI_INTSTAT_TIM_Int ((uint32_t)(1<<1)) /**< Indicates that a velocity timer overflow occurred */ |
| hexley | 0:20a27391f6dc | 455 | #define QEI_INTSTAT_VELC_Int ((uint32_t)(1<<2)) /**< Indicates that capture velocity is less than compare velocity */ |
| hexley | 0:20a27391f6dc | 456 | #define QEI_INTSTAT_DIR_Int ((uint32_t)(1<<3)) /**< Indicates that a change of direction was detected */ |
| hexley | 0:20a27391f6dc | 457 | #define QEI_INTSTAT_ERR_Int ((uint32_t)(1<<4)) /**< Indicates that an encoder phase error was detected */ |
| hexley | 0:20a27391f6dc | 458 | #define QEI_INTSTAT_ENCLK_Int ((uint32_t)(1<<5)) /**< Indicates that and encoder clock pulse was detected */ |
| hexley | 0:20a27391f6dc | 459 | #define QEI_INTSTAT_POS0_Int ((uint32_t)(1<<6)) /**< Indicates that the position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 460 | current position */ |
| hexley | 0:20a27391f6dc | 461 | #define QEI_INTSTAT_POS1_Int ((uint32_t)(1<<7)) /**< Indicates that the position 1compare value is equal to the |
| hexley | 0:20a27391f6dc | 462 | current position */ |
| hexley | 0:20a27391f6dc | 463 | #define QEI_INTSTAT_POS2_Int ((uint32_t)(1<<8)) /**< Indicates that the position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 464 | current position */ |
| hexley | 0:20a27391f6dc | 465 | #define QEI_INTSTAT_REV_Int ((uint32_t)(1<<9)) /**< Indicates that the index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 466 | index count */ |
| hexley | 0:20a27391f6dc | 467 | #define QEI_INTSTAT_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt. Set when |
| hexley | 0:20a27391f6dc | 468 | both the POS0_Int bit is set and the REV_Int is set */ |
| hexley | 0:20a27391f6dc | 469 | #define QEI_INTSTAT_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt. Set when |
| hexley | 0:20a27391f6dc | 470 | both the POS1_Int bit is set and the REV_Int is set */ |
| hexley | 0:20a27391f6dc | 471 | #define QEI_INTSTAT_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt. Set when |
| hexley | 0:20a27391f6dc | 472 | both the POS2_Int bit is set and the REV_Int is set */ |
| hexley | 0:20a27391f6dc | 473 | #define QEI_INTSTAT_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */ |
| hexley | 0:20a27391f6dc | 474 | |
| hexley | 0:20a27391f6dc | 475 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 476 | * Macro defines for QEI Interrupt Set register |
| hexley | 0:20a27391f6dc | 477 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 478 | #define QEI_INTSET_INX_Int ((uint32_t)(1<<0)) /**< Set Bit Indicates that an index pulse was detected */ |
| hexley | 0:20a27391f6dc | 479 | #define QEI_INTSET_TIM_Int ((uint32_t)(1<<1)) /**< Set Bit Indicates that a velocity timer overflow occurred */ |
| hexley | 0:20a27391f6dc | 480 | #define QEI_INTSET_VELC_Int ((uint32_t)(1<<2)) /**< Set Bit Indicates that capture velocity is less than compare velocity */ |
| hexley | 0:20a27391f6dc | 481 | #define QEI_INTSET_DIR_Int ((uint32_t)(1<<3)) /**< Set Bit Indicates that a change of direction was detected */ |
| hexley | 0:20a27391f6dc | 482 | #define QEI_INTSET_ERR_Int ((uint32_t)(1<<4)) /**< Set Bit Indicates that an encoder phase error was detected */ |
| hexley | 0:20a27391f6dc | 483 | #define QEI_INTSET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Bit Indicates that and encoder clock pulse was detected */ |
| hexley | 0:20a27391f6dc | 484 | #define QEI_INTSET_POS0_Int ((uint32_t)(1<<6)) /**< Set Bit Indicates that the position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 485 | current position */ |
| hexley | 0:20a27391f6dc | 486 | #define QEI_INTSET_POS1_Int ((uint32_t)(1<<7)) /**< Set Bit Indicates that the position 1compare value is equal to the |
| hexley | 0:20a27391f6dc | 487 | current position */ |
| hexley | 0:20a27391f6dc | 488 | #define QEI_INTSET_POS2_Int ((uint32_t)(1<<8)) /**< Set Bit Indicates that the position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 489 | current position */ |
| hexley | 0:20a27391f6dc | 490 | #define QEI_INTSET_REV_Int ((uint32_t)(1<<9)) /**< Set Bit Indicates that the index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 491 | index count */ |
| hexley | 0:20a27391f6dc | 492 | #define QEI_INTSET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Bit that combined position 0 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 493 | #define QEI_INTSET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Bit that Combined position 1 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 494 | #define QEI_INTSET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Bit that Combined position 2 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 495 | #define QEI_INTSET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Set register bit-mask */ |
| hexley | 0:20a27391f6dc | 496 | |
| hexley | 0:20a27391f6dc | 497 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 498 | * Macro defines for QEI Interrupt Clear register |
| hexley | 0:20a27391f6dc | 499 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 500 | #define QEI_INTCLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Bit Indicates that an index pulse was detected */ |
| hexley | 0:20a27391f6dc | 501 | #define QEI_INTCLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Bit Indicates that a velocity timer overflow occurred */ |
| hexley | 0:20a27391f6dc | 502 | #define QEI_INTCLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Bit Indicates that capture velocity is less than compare velocity */ |
| hexley | 0:20a27391f6dc | 503 | #define QEI_INTCLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Bit Indicates that a change of direction was detected */ |
| hexley | 0:20a27391f6dc | 504 | #define QEI_INTCLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Bit Indicates that an encoder phase error was detected */ |
| hexley | 0:20a27391f6dc | 505 | #define QEI_INTCLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Bit Indicates that and encoder clock pulse was detected */ |
| hexley | 0:20a27391f6dc | 506 | #define QEI_INTCLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Bit Indicates that the position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 507 | current position */ |
| hexley | 0:20a27391f6dc | 508 | #define QEI_INTCLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Bit Indicates that the position 1compare value is equal to the |
| hexley | 0:20a27391f6dc | 509 | current position */ |
| hexley | 0:20a27391f6dc | 510 | #define QEI_INTCLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Bit Indicates that the position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 511 | current position */ |
| hexley | 0:20a27391f6dc | 512 | #define QEI_INTCLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Bit Indicates that the index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 513 | index count */ |
| hexley | 0:20a27391f6dc | 514 | #define QEI_INTCLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Bit that combined position 0 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 515 | #define QEI_INTCLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Bit that Combined position 1 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 516 | #define QEI_INTCLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Bit that Combined position 2 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 517 | #define QEI_INTCLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Clear register bit-mask */ |
| hexley | 0:20a27391f6dc | 518 | |
| hexley | 0:20a27391f6dc | 519 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 520 | * Macro defines for QEI Interrupt Enable register |
| hexley | 0:20a27391f6dc | 521 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 522 | #define QEI_INTEN_INX_Int ((uint32_t)(1<<0)) /**< Enabled Interrupt Bit Indicates that an index pulse was detected */ |
| hexley | 0:20a27391f6dc | 523 | #define QEI_INTEN_TIM_Int ((uint32_t)(1<<1)) /**< Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */ |
| hexley | 0:20a27391f6dc | 524 | #define QEI_INTEN_VELC_Int ((uint32_t)(1<<2)) /**< Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */ |
| hexley | 0:20a27391f6dc | 525 | #define QEI_INTEN_DIR_Int ((uint32_t)(1<<3)) /**< Enabled Interrupt Bit Indicates that a change of direction was detected */ |
| hexley | 0:20a27391f6dc | 526 | #define QEI_INTEN_ERR_Int ((uint32_t)(1<<4)) /**< Enabled Interrupt Bit Indicates that an encoder phase error was detected */ |
| hexley | 0:20a27391f6dc | 527 | #define QEI_INTEN_ENCLK_Int ((uint32_t)(1<<5)) /**< Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */ |
| hexley | 0:20a27391f6dc | 528 | #define QEI_INTEN_POS0_Int ((uint32_t)(1<<6)) /**< Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 529 | current position */ |
| hexley | 0:20a27391f6dc | 530 | #define QEI_INTEN_POS1_Int ((uint32_t)(1<<7)) /**< Enabled Interrupt Bit Indicates that the position 1compare value is equal to the |
| hexley | 0:20a27391f6dc | 531 | current position */ |
| hexley | 0:20a27391f6dc | 532 | #define QEI_INTEN_POS2_Int ((uint32_t)(1<<8)) /**< Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 533 | current position */ |
| hexley | 0:20a27391f6dc | 534 | #define QEI_INTEN_REV_Int ((uint32_t)(1<<9)) /**< Enabled Interrupt Bit Indicates that the index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 535 | index count */ |
| hexley | 0:20a27391f6dc | 536 | #define QEI_INTEN_POS0REV_Int ((uint32_t)(1<<10)) /**< Enabled Interrupt Bit that combined position 0 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 537 | #define QEI_INTEN_POS1REV_Int ((uint32_t)(1<<11)) /**< Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 538 | #define QEI_INTEN_POS2REV_Int ((uint32_t)(1<<12)) /**< Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 539 | #define QEI_INTEN_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable register bit-mask */ |
| hexley | 0:20a27391f6dc | 540 | |
| hexley | 0:20a27391f6dc | 541 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 542 | * Macro defines for QEI Interrupt Enable Set register |
| hexley | 0:20a27391f6dc | 543 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 544 | #define QEI_IESET_INX_Int ((uint32_t)(1<<0)) /**< Set Enable Interrupt Bit Indicates that an index pulse was detected */ |
| hexley | 0:20a27391f6dc | 545 | #define QEI_IESET_TIM_Int ((uint32_t)(1<<1)) /**< Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */ |
| hexley | 0:20a27391f6dc | 546 | #define QEI_IESET_VELC_Int ((uint32_t)(1<<2)) /**< Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */ |
| hexley | 0:20a27391f6dc | 547 | #define QEI_IESET_DIR_Int ((uint32_t)(1<<3)) /**< Set Enable Interrupt Bit Indicates that a change of direction was detected */ |
| hexley | 0:20a27391f6dc | 548 | #define QEI_IESET_ERR_Int ((uint32_t)(1<<4)) /**< Set Enable Interrupt Bit Indicates that an encoder phase error was detected */ |
| hexley | 0:20a27391f6dc | 549 | #define QEI_IESET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */ |
| hexley | 0:20a27391f6dc | 550 | #define QEI_IESET_POS0_Int ((uint32_t)(1<<6)) /**< Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 551 | current position */ |
| hexley | 0:20a27391f6dc | 552 | #define QEI_IESET_POS1_Int ((uint32_t)(1<<7)) /**< Set Enable Interrupt Bit Indicates that the position 1compare value is equal to the |
| hexley | 0:20a27391f6dc | 553 | current position */ |
| hexley | 0:20a27391f6dc | 554 | #define QEI_IESET_POS2_Int ((uint32_t)(1<<8)) /**< Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 555 | current position */ |
| hexley | 0:20a27391f6dc | 556 | #define QEI_IESET_REV_Int ((uint32_t)(1<<9)) /**< Set Enable Interrupt Bit Indicates that the index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 557 | index count */ |
| hexley | 0:20a27391f6dc | 558 | #define QEI_IESET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 559 | #define QEI_IESET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 560 | #define QEI_IESET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 561 | #define QEI_IESET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Set register bit-mask */ |
| hexley | 0:20a27391f6dc | 562 | |
| hexley | 0:20a27391f6dc | 563 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 564 | * Macro defines for QEI Interrupt Enable Clear register |
| hexley | 0:20a27391f6dc | 565 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 566 | #define QEI_IECLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Enabled Interrupt Bit Indicates that an index pulse was detected */ |
| hexley | 0:20a27391f6dc | 567 | #define QEI_IECLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */ |
| hexley | 0:20a27391f6dc | 568 | #define QEI_IECLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */ |
| hexley | 0:20a27391f6dc | 569 | #define QEI_IECLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Enabled Interrupt Bit Indicates that a change of direction was detected */ |
| hexley | 0:20a27391f6dc | 570 | #define QEI_IECLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */ |
| hexley | 0:20a27391f6dc | 571 | #define QEI_IECLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */ |
| hexley | 0:20a27391f6dc | 572 | #define QEI_IECLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the |
| hexley | 0:20a27391f6dc | 573 | current position */ |
| hexley | 0:20a27391f6dc | 574 | #define QEI_IECLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the |
| hexley | 0:20a27391f6dc | 575 | current position */ |
| hexley | 0:20a27391f6dc | 576 | #define QEI_IECLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the |
| hexley | 0:20a27391f6dc | 577 | current position */ |
| hexley | 0:20a27391f6dc | 578 | #define QEI_IECLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current |
| hexley | 0:20a27391f6dc | 579 | index count */ |
| hexley | 0:20a27391f6dc | 580 | #define QEI_IECLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 581 | #define QEI_IECLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 582 | #define QEI_IECLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */ |
| hexley | 0:20a27391f6dc | 583 | #define QEI_IECLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Clear register bit-mask */ |
| hexley | 0:20a27391f6dc | 584 | |
| hexley | 0:20a27391f6dc | 585 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 586 | * Macro defines for PCONP register QEI-related bits |
| hexley | 0:20a27391f6dc | 587 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 588 | #define PCONP_QEI_ENABLE ((uint32_t)(1<<18)) /**< QEI peripheral power enable bit */ |
| hexley | 0:20a27391f6dc | 589 | #define PCONP_QEI_DISABLE ~((uint32_t)(1<<18)) /**< QEI peripheral power disable bit-mask */ |
| hexley | 0:20a27391f6dc | 590 | |
| hexley | 0:20a27391f6dc | 591 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 592 | * Macro defines for PCLKSELx register QEI-related bits |
| hexley | 0:20a27391f6dc | 593 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 594 | #define PCLKSEL_CCLK_DIV_1 1UL /**< Set PCLK to CCLK/1 */ |
| hexley | 0:20a27391f6dc | 595 | #define PCLKSEL_CCLK_DIV_2 2UL /**< Set PCLK to CCLK/2 */ |
| hexley | 0:20a27391f6dc | 596 | #define PCLKSEL_CCLK_DIV_4 0UL /**< Set PCLK to CCLK/4 */ |
| hexley | 0:20a27391f6dc | 597 | #define PCLKSEL_CCLK_DIV_8 3UL /**< Set PCLK to CCLK/8 */ |
| hexley | 0:20a27391f6dc | 598 | #define PCLKSEL1_PCLK_QEI_MASK ((uint32_t)(3<<0)) /**< PCLK_QEI PCLK_QEI bit field mask */ |
| hexley | 0:20a27391f6dc | 599 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 600 | * Macro defines for PINSEL3 register QEI-related bits |
| hexley | 0:20a27391f6dc | 601 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 602 | #define PINSEL3_MCI0 ((uint32_t)(1<<8)) /**< MCIO (PhA) pin select */ |
| hexley | 0:20a27391f6dc | 603 | #define PINSEL3_MCI0_MASK ~((uint32_t)(3<<8)) /**< MCIO (PhA) pin mask */ |
| hexley | 0:20a27391f6dc | 604 | #define PINSEL3_MCI1 ((uint32_t)(1<<14)) /**< MCI1 (PhB) pin select */ |
| hexley | 0:20a27391f6dc | 605 | #define PINSEL3_MCI1_MASK ~((uint32_t)(3<<14)) /**< MCI2 (PhB) pin mask */ |
| hexley | 0:20a27391f6dc | 606 | #define PINSEL3_MCI2 ((uint32_t)(1<<16)) /**< MCI2 (Index) pin select */ |
| hexley | 0:20a27391f6dc | 607 | #define PINSEL3_MCI2_MASK ~((uint32_t)(3<<16)) /**< MCI2 (Index) pin mask */ |
| hexley | 0:20a27391f6dc | 608 | |
| hexley | 0:20a27391f6dc | 609 | /*********************************************************************//** |
| hexley | 0:20a27391f6dc | 610 | * Macro defines for PINMODE3 register QEI-related bits |
| hexley | 0:20a27391f6dc | 611 | **********************************************************************/ |
| hexley | 0:20a27391f6dc | 612 | #define PIN_PULL_UP 0UL |
| hexley | 0:20a27391f6dc | 613 | #define PIN_REPEATER 1UL |
| hexley | 0:20a27391f6dc | 614 | #define PIN_NORESISTOR 2UL |
| hexley | 0:20a27391f6dc | 615 | #define PIN_PULL_DOWN 3UL |
| hexley | 0:20a27391f6dc | 616 | |
| hexley | 0:20a27391f6dc | 617 | #define PINMODE3_MCI0 ((uint32_t)(PIN_NORESISTOR<<8)) /**< MCIO (PhA) resistor selection */ |
| hexley | 0:20a27391f6dc | 618 | #define PINMODE3_GPIO1p20 ((uint32_t)(PIN_PULL_DOWN<<8)) /**< GPIO 1.20) resistor selection */ |
| hexley | 0:20a27391f6dc | 619 | #define PINMODE3_MCI0_MASK ~((uint32_t)(3<<8)) /**< MCIO (PhA) resistor mask */ |
| hexley | 0:20a27391f6dc | 620 | |
| hexley | 0:20a27391f6dc | 621 | #define PINMODE3_MCI1 ((uint32_t)(PIN_NORESISTOR<<14)) /**< MCI1 (PhB) resistor selection */ |
| hexley | 0:20a27391f6dc | 622 | #define PINMODE3_GPIO1p23 ((uint32_t)(PIN_PULL_DOWN<<14)) /**< GPIO 1.23) resistor selection */ |
| hexley | 0:20a27391f6dc | 623 | #define PINMODE3_MCI1_MASK ~((uint32_t)(3<<14)) /**< MCI1 (PhB) resistor mask */ |
| hexley | 0:20a27391f6dc | 624 | |
| hexley | 0:20a27391f6dc | 625 | #define PINMODE3_MCI2 ((uint32_t)(PIN_PULL_UP<<16)) /**< MCI2 (Index) resistor selection */ |
| hexley | 0:20a27391f6dc | 626 | #define PINMODE3_GPIO1p24 ((uint32_t)(PIN_PULL_DOWN<<16)) /**< GPIO 1.24) resistor selection */ |
| hexley | 0:20a27391f6dc | 627 | #define PINMODE3_MCI2_MASK ~((uint32_t)(3<<16)) /**< MCI2 (Index) resistor mask */ |
| hexley | 0:20a27391f6dc | 628 | |
| hexley | 0:20a27391f6dc | 629 | }; |
| hexley | 0:20a27391f6dc | 630 | |
| hexley | 0:20a27391f6dc | 631 | |
| hexley | 0:20a27391f6dc | 632 | #endif /* MBED_QEI_H */ |
| hexley | 0:20a27391f6dc | 633 | /* --------------------------------- End Of File ------------------------------ */ |