SPI or I2C to UART Bridge
Dependents: SC16IS750_Test mbed_SC16IS750 Xadow_SC16IS750_Test Xadow_MPU9150AHRS
SC16IS750.h@1:0440152c5387, 2014-02-09 (annotated)
- Committer:
- wim
- Date:
- Sun Feb 09 14:58:06 2014 +0000
- Revision:
- 1:0440152c5387
- Parent:
- 0:d64854a60f95
- Child:
- 2:76cb93b511f2
working proto, tested on BOB
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
wim | 0:d64854a60f95 | 1 | /* SC16IS750 interface |
wim | 1:0440152c5387 | 2 | * v0.1 WH, Nov 2013, Ported to mbed, Sparkfun Libs used as example. Added I2C and SPI I/F and more methods |
wim | 0:d64854a60f95 | 3 | * |
wim | 0:d64854a60f95 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a copy of this software |
wim | 0:d64854a60f95 | 5 | * and associated documentation files (the "Software"), to deal in the Software without restriction, |
wim | 0:d64854a60f95 | 6 | * including without limitation the rights to use, copy, modify, merge, publish, distribute, |
wim | 0:d64854a60f95 | 7 | * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is |
wim | 0:d64854a60f95 | 8 | * furnished to do so, subject to the following conditions: |
wim | 0:d64854a60f95 | 9 | * |
wim | 0:d64854a60f95 | 10 | * The above copyright notice and this permission notice shall be included in all copies or |
wim | 0:d64854a60f95 | 11 | * substantial portions of the Software. |
wim | 0:d64854a60f95 | 12 | * |
wim | 0:d64854a60f95 | 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING |
wim | 0:d64854a60f95 | 14 | * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
wim | 0:d64854a60f95 | 15 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, |
wim | 0:d64854a60f95 | 16 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
wim | 0:d64854a60f95 | 17 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
wim | 0:d64854a60f95 | 18 | */ |
wim | 0:d64854a60f95 | 19 | #ifndef _SC16IS750_H |
wim | 0:d64854a60f95 | 20 | #define _SC16IS750_H |
wim | 0:d64854a60f95 | 21 | |
wim | 1:0440152c5387 | 22 | //I2C Slaveaddresses A1 A0 |
wim | 1:0440152c5387 | 23 | #define SC16IS750_SA0 0x90 /* VDD VDD */ |
wim | 1:0440152c5387 | 24 | #define SC16IS750_SA1 0x92 /* VDD VSS */ |
wim | 1:0440152c5387 | 25 | #define SC16IS750_SA2 0x94 /* VDD SCL */ |
wim | 1:0440152c5387 | 26 | #define SC16IS750_SA3 0x95 /* VDD SDA */ |
wim | 1:0440152c5387 | 27 | #define SC16IS750_SA4 0x98 /* VSS VDD */ |
wim | 1:0440152c5387 | 28 | #define SC16IS750_SA5 0x9A /* VSS VSS */ |
wim | 1:0440152c5387 | 29 | #define SC16IS750_SA6 0x9C /* VSS SCL */ |
wim | 1:0440152c5387 | 30 | #define SC16IS750_SA7 0x9E /* VSS SDA */ |
wim | 1:0440152c5387 | 31 | #define SC16IS750_SA8 0xA0 /* SCL VDD */ |
wim | 1:0440152c5387 | 32 | #define SC16IS750_SA9 0xA2 /* SCL VSS */ |
wim | 1:0440152c5387 | 33 | #define SC16IS750_SA10 0xA4 /* SCL SCL */ |
wim | 1:0440152c5387 | 34 | #define SC16IS750_SA11 0xA6 /* SCL SDA */ |
wim | 1:0440152c5387 | 35 | #define SC16IS750_SA12 0xA8 /* SDA VDD */ |
wim | 1:0440152c5387 | 36 | #define SC16IS750_SA13 0xAA /* SDA VSS */ |
wim | 1:0440152c5387 | 37 | #define SC16IS750_SA14 0xAC /* SDA SCL */ |
wim | 1:0440152c5387 | 38 | #define SC16IS750_SA15 0xAE /* SDA SDA */ |
wim | 1:0440152c5387 | 39 | |
wim | 0:d64854a60f95 | 40 | //Default I2C Slaveaddress |
wim | 1:0440152c5387 | 41 | #define DEFAULT_SC16IS750_ADDR SC16IS750_SA0 |
wim | 0:d64854a60f95 | 42 | |
wim | 0:d64854a60f95 | 43 | //Default baudrate |
wim | 0:d64854a60f95 | 44 | #define DEFAULT_BAUD_RATE 9600 |
wim | 0:d64854a60f95 | 45 | |
wim | 0:d64854a60f95 | 46 | #define ENABLE_BULK_TRANSFERS 0x01 |
wim | 0:d64854a60f95 | 47 | |
wim | 0:d64854a60f95 | 48 | #define XTAL_FREQUENCY 14745600UL // On-board crystal (New mid-2010 Version) |
wim | 0:d64854a60f95 | 49 | |
wim | 0:d64854a60f95 | 50 | // See datasheet section 7.8 for configuring the |
wim | 0:d64854a60f95 | 51 | // "Programmable baud rate generator" |
wim | 0:d64854a60f95 | 52 | #define PRESCALER 1 // Default prescaler after reset |
wim | 0:d64854a60f95 | 53 | #define BAUD_RATE_DIVISOR(baud) ((XTAL_FREQUENCY/PRESCALER)/(baud*16UL)) |
wim | 0:d64854a60f95 | 54 | |
wim | 0:d64854a60f95 | 55 | // See section 8.4 of the datasheet for definitions |
wim | 0:d64854a60f95 | 56 | // of bits in the Line Control Register (LCR) |
wim | 0:d64854a60f95 | 57 | #define LCR_BITS5 0x00 |
wim | 0:d64854a60f95 | 58 | #define LCR_BITS6 0x01 |
wim | 0:d64854a60f95 | 59 | #define LCR_BITS7 0x02 |
wim | 0:d64854a60f95 | 60 | #define LCR_BITS8 0x03 |
wim | 0:d64854a60f95 | 61 | |
wim | 0:d64854a60f95 | 62 | #define LCR_BITS1 0x00 |
wim | 0:d64854a60f95 | 63 | #define LCR_BITS2 0x04 |
wim | 0:d64854a60f95 | 64 | |
wim | 0:d64854a60f95 | 65 | #define LCR_NONE 0x00 |
wim | 0:d64854a60f95 | 66 | #define LCR_ODD 0x08 |
wim | 0:d64854a60f95 | 67 | #define LCR_EVEN 0x18 |
wim | 0:d64854a60f95 | 68 | #define LCR_FORCED1 0x28 |
wim | 0:d64854a60f95 | 69 | #define LCR_FORCED0 0x38 |
wim | 0:d64854a60f95 | 70 | |
wim | 0:d64854a60f95 | 71 | #define LCR_BRK_ENA 0x40 |
wim | 0:d64854a60f95 | 72 | #define LCR_BRK_DIS 0x00 |
wim | 0:d64854a60f95 | 73 | |
wim | 1:0440152c5387 | 74 | #define LCR_ENABLE_DIV 0x80 |
wim | 1:0440152c5387 | 75 | #define LCR_DISABLE_DIV 0x00 |
wim | 0:d64854a60f95 | 76 | |
wim | 1:0440152c5387 | 77 | #define LCR_ENABLE_ENHANCED_FUNCTIONS (0xBF) |
wim | 0:d64854a60f95 | 78 | |
wim | 0:d64854a60f95 | 79 | // See section 8.10 of the datasheet for definitions |
wim | 0:d64854a60f95 | 80 | // of bits in the Enhanced Features Register (EFR) |
wim | 0:d64854a60f95 | 81 | #define EFR_ENABLE_CTS (1 << 7) |
wim | 0:d64854a60f95 | 82 | #define EFR_ENABLE_RTS (1 << 6) |
wim | 0:d64854a60f95 | 83 | #define EFR_ENABLE_ENHANCED_FUNCTIONS (1 << 4) |
wim | 0:d64854a60f95 | 84 | |
wim | 1:0440152c5387 | 85 | |
wim | 1:0440152c5387 | 86 | // See section 8.xx of the datasheet for definitions |
wim | 1:0440152c5387 | 87 | // of bits in the Flow Control Register (FCR) |
wim | 1:0440152c5387 | 88 | #define FCR_RX_IRQ_14 (3 << 6) |
wim | 1:0440152c5387 | 89 | #define FCR_RX_IRQ_8 (2 << 6) |
wim | 1:0440152c5387 | 90 | #define FCR_RX_IRQ_4 (1 << 6) |
wim | 1:0440152c5387 | 91 | #define FCR_RX_IRQ_1 (0 << 6) |
wim | 1:0440152c5387 | 92 | #define FCR_RX_IRQ_NONE (0 << 6) |
wim | 1:0440152c5387 | 93 | #define FCR_ENA_FIFO_64 (1 << 5) |
wim | 1:0440152c5387 | 94 | #define FCR_TXFIFO_RST (1 << 2) |
wim | 1:0440152c5387 | 95 | #define FCR_RXFIFO_RST (1 << 1) |
wim | 1:0440152c5387 | 96 | #define FCR_ENABLE_FIFO (1 << 0) |
wim | 1:0440152c5387 | 97 | |
wim | 1:0440152c5387 | 98 | |
wim | 1:0440152c5387 | 99 | |
wim | 1:0440152c5387 | 100 | /* |
wim | 1:0440152c5387 | 101 | * Interrupt enable register. |
wim | 1:0440152c5387 | 102 | */ |
wim | 1:0440152c5387 | 103 | |
wim | 1:0440152c5387 | 104 | #define IER_ERBI (0x01) /* Enable received data available interrupt */ |
wim | 1:0440152c5387 | 105 | #define IER_ETBEI (0x02) /* Enable transmitter holding register empty interrupt */ |
wim | 1:0440152c5387 | 106 | #define IER_ELSI (0x04) /* Enable receiver line status interrupt */ |
wim | 1:0440152c5387 | 107 | #define IER_EDSSI (0x08) /* Enable modem status interrupt */ |
wim | 1:0440152c5387 | 108 | #define IER_SLEEP (0x10) /* Enable sleep mode */ |
wim | 1:0440152c5387 | 109 | |
wim | 1:0440152c5387 | 110 | /* |
wim | 1:0440152c5387 | 111 | * Modem control register. |
wim | 1:0440152c5387 | 112 | */ |
wim | 1:0440152c5387 | 113 | |
wim | 1:0440152c5387 | 114 | #define MCR_MDTR (0x01) /* Data terminal ready. */ |
wim | 1:0440152c5387 | 115 | #define MCR_MRTS (0x02) /* Request to send. */ |
wim | 1:0440152c5387 | 116 | //#define MCR_TCR_TLR_BIT (6) |
wim | 1:0440152c5387 | 117 | #define MCR_ENABLE_TCR_TLR (1 << 2) |
wim | 1:0440152c5387 | 118 | |
wim | 1:0440152c5387 | 119 | /* |
wim | 1:0440152c5387 | 120 | * Line status register. |
wim | 1:0440152c5387 | 121 | */ |
wim | 1:0440152c5387 | 122 | |
wim | 1:0440152c5387 | 123 | #define LSR_DR (0x01) /* Data ready */ |
wim | 1:0440152c5387 | 124 | #define LSR_OE (0x02) /* Overrun error */ |
wim | 1:0440152c5387 | 125 | #define LSR_PE (0x04) /* Parity error */ |
wim | 1:0440152c5387 | 126 | #define LSR_FE (0x08) /* Framing error */ |
wim | 1:0440152c5387 | 127 | #define LSR_BI (0x10) /* Break interrupt */ |
wim | 1:0440152c5387 | 128 | #define LSR_THRE (0x20) /* Transmitter holding register (FIFO empty) */ |
wim | 1:0440152c5387 | 129 | #define LSR_TEMT (0x40) /* Transmitter empty (FIFO and TSR both empty) */ |
wim | 1:0440152c5387 | 130 | |
wim | 1:0440152c5387 | 131 | /* |
wim | 1:0440152c5387 | 132 | * Interrupt identification register. |
wim | 1:0440152c5387 | 133 | * Bit 0 is set to 0 if an IT is pending. |
wim | 1:0440152c5387 | 134 | * Bits 1 and 2 are used to identify the IT. |
wim | 1:0440152c5387 | 135 | */ |
wim | 1:0440152c5387 | 136 | |
wim | 1:0440152c5387 | 137 | #define IIR_BITS_USED (0x07) |
wim | 1:0440152c5387 | 138 | #define IIR_IT_NOT_PENDING (0x01) |
wim | 1:0440152c5387 | 139 | #define IIR_RX_DATA (0x04) |
wim | 1:0440152c5387 | 140 | #define IIR_TX_EMPTY (0x02) |
wim | 1:0440152c5387 | 141 | #define IIR_MODEM_STATUS (0x00) |
wim | 1:0440152c5387 | 142 | |
wim | 1:0440152c5387 | 143 | |
wim | 1:0440152c5387 | 144 | /* |
wim | 1:0440152c5387 | 145 | * IO Control register. |
wim | 1:0440152c5387 | 146 | * Bit 0 is set to 0 to enable latch of IO inputs. |
wim | 1:0440152c5387 | 147 | * Bit 1 is set to enable GPIO[7-4] as /RI, /CD, /DTR, /DST. |
wim | 1:0440152c5387 | 148 | * Bit 2 is set to enable software reset. |
wim | 1:0440152c5387 | 149 | */ |
wim | 1:0440152c5387 | 150 | #define IOC_ENA_LATCH (0x01) |
wim | 1:0440152c5387 | 151 | #define IOC_ENA_MODEM (0x02) |
wim | 1:0440152c5387 | 152 | #define IOC_SW_RST (0x04) |
wim | 1:0440152c5387 | 153 | |
wim | 1:0440152c5387 | 154 | |
wim | 1:0440152c5387 | 155 | |
wim | 0:d64854a60f95 | 156 | // See Chapter 11 of datasheet |
wim | 0:d64854a60f95 | 157 | #define SPI_READ_MODE_FLAG 0x80 |
wim | 0:d64854a60f95 | 158 | |
wim | 0:d64854a60f95 | 159 | |
wim | 0:d64854a60f95 | 160 | /** Abstract class SC16IS750 for a converter between either SPI or I2C and a Serial port |
wim | 0:d64854a60f95 | 161 | * |
wim | 0:d64854a60f95 | 162 | * Supports both SPI and I2C interfaces through derived classes |
wim | 0:d64854a60f95 | 163 | * |
wim | 0:d64854a60f95 | 164 | * @code |
wim | 0:d64854a60f95 | 165 | * |
wim | 0:d64854a60f95 | 166 | * @endcode |
wim | 0:d64854a60f95 | 167 | */ |
wim | 0:d64854a60f95 | 168 | //class SC16IS750 : public Serial { //Fout, geen Serial constr met Serial(NC, NC) toegestaan... |
wim | 0:d64854a60f95 | 169 | class SC16IS750 { |
wim | 0:d64854a60f95 | 170 | |
wim | 0:d64854a60f95 | 171 | public: |
wim | 0:d64854a60f95 | 172 | |
wim | 0:d64854a60f95 | 173 | // SC16IS750 Register definitions (shifted to align) |
wim | 0:d64854a60f95 | 174 | enum RegisterName { |
wim | 1:0440152c5387 | 175 | /* |
wim | 1:0440152c5387 | 176 | * 16750 addresses. Registers accessed when LCR[7] = 0. |
wim | 1:0440152c5387 | 177 | */ |
wim | 1:0440152c5387 | 178 | RHR = 0x00 << 3, /* Rx buffer register - Read access */ |
wim | 1:0440152c5387 | 179 | THR = 0x00 << 3, /* Tx holding register - Write access */ |
wim | 1:0440152c5387 | 180 | IER = 0x01 << 3, /* Interrupt enable reg - RD/WR access */ |
wim | 1:0440152c5387 | 181 | |
wim | 1:0440152c5387 | 182 | /* |
wim | 1:0440152c5387 | 183 | * 16750 addresses. Registers accessed when LCR[7] = 1. |
wim | 1:0440152c5387 | 184 | */ |
wim | 1:0440152c5387 | 185 | DLL = 0x00 << 3, /* Divisor latch (LSB) - RD/WR access */ |
wim | 1:0440152c5387 | 186 | DLH = 0x01 << 3, /* Divisor latch (MSB) - RD/WR access */ |
wim | 1:0440152c5387 | 187 | |
wim | 1:0440152c5387 | 188 | /* |
wim | 1:0440152c5387 | 189 | * 16750 addresses. IIR/FCR is accessed when LCR[7:0] <> 0xBF. |
wim | 1:0440152c5387 | 190 | * Bit 5 of the FCR register is accessed when LCR[7] = 1. |
wim | 1:0440152c5387 | 191 | */ |
wim | 1:0440152c5387 | 192 | IIR = 0x02 << 3, /* Interrupt id. register - Read only */ |
wim | 1:0440152c5387 | 193 | FCR = 0x02 << 3, /* FIFO control register - Write only */ |
wim | 1:0440152c5387 | 194 | /* |
wim | 1:0440152c5387 | 195 | * 16750 addresses. EFR is accessed when LCR[7:0] = 0xBF. |
wim | 1:0440152c5387 | 196 | */ |
wim | 1:0440152c5387 | 197 | EFR = 0x02 << 3, /* Enhanced features reg - RD/WR access */ |
wim | 1:0440152c5387 | 198 | |
wim | 1:0440152c5387 | 199 | /* |
wim | 1:0440152c5387 | 200 | * 16750 addresses. |
wim | 1:0440152c5387 | 201 | */ |
wim | 1:0440152c5387 | 202 | LCR = 0x03 << 3, /* Line control register - RD/WR access */ |
wim | 1:0440152c5387 | 203 | /* |
wim | 1:0440152c5387 | 204 | * 16750 addresses. MCR/LSR is accessed when LCR[7:0] <> 0xBF. |
wim | 1:0440152c5387 | 205 | * Bit 7 of the MCR register is accessed when EFR[4] = 1. |
wim | 1:0440152c5387 | 206 | */ |
wim | 1:0440152c5387 | 207 | MCR = 0x04 << 3, /* Modem control register - RD/WR access */ |
wim | 1:0440152c5387 | 208 | LSR = 0x05 << 3, /* Line status register - Read only */ |
wim | 1:0440152c5387 | 209 | |
wim | 1:0440152c5387 | 210 | /* |
wim | 1:0440152c5387 | 211 | * 16750 addresses. MSR/SPR is accessed when LCR[7:0] <> 0xBF. |
wim | 1:0440152c5387 | 212 | * MSR, SPR register is accessed when EFR[1]=0 and MCR[2]=0. |
wim | 1:0440152c5387 | 213 | */ |
wim | 1:0440152c5387 | 214 | MSR = 0x06 << 3, /* Modem status register - Read only */ |
wim | 1:0440152c5387 | 215 | SPR = 0x07 << 3, /* Scratchpad register - RD/WR access */ |
wim | 1:0440152c5387 | 216 | /* |
wim | 1:0440152c5387 | 217 | * 16750 addresses. TCR/TLR is accessed when LCR[7:0] <> 0xBF. |
wim | 1:0440152c5387 | 218 | * TCR, TLR register is accessed when EFR[1]=1 and MCR[2]=1. |
wim | 1:0440152c5387 | 219 | */ |
wim | 1:0440152c5387 | 220 | TCR = 0x06 << 3, /* Transmission control register - RD/WR access */ |
wim | 1:0440152c5387 | 221 | TLR = 0x07 << 3, /* Trigger level register - RD/WR access */ |
wim | 1:0440152c5387 | 222 | |
wim | 1:0440152c5387 | 223 | /* |
wim | 1:0440152c5387 | 224 | * 16750 addresses. XON, XOFF is accessed when LCR[7:0] = 0xBF. |
wim | 1:0440152c5387 | 225 | */ |
wim | 1:0440152c5387 | 226 | XON1 = 0x04 << 3, /* XON1 register - RD/WR access */ |
wim | 1:0440152c5387 | 227 | XON2 = 0x05 << 3, /* XON2 register - RD/WR access */ |
wim | 1:0440152c5387 | 228 | XOFF1 = 0x06 << 3, /* XOFF1 register - RD/WR access */ |
wim | 1:0440152c5387 | 229 | XOFF2 = 0x07 << 3, /* XOFF2 register - RD/WR access */ |
wim | 1:0440152c5387 | 230 | |
wim | 1:0440152c5387 | 231 | /* |
wim | 1:0440152c5387 | 232 | * 16750 addresses. |
wim | 1:0440152c5387 | 233 | */ |
wim | 1:0440152c5387 | 234 | TXLVL = 0x08 << 3, /* TX FIFO Level register - Read only */ |
wim | 1:0440152c5387 | 235 | RXLVL = 0x09 << 3, /* RX FIFO Level register - Read only */ |
wim | 1:0440152c5387 | 236 | IODIR = 0x0A << 3, /* IO Pin Direction reg - RD/WR access */ |
wim | 1:0440152c5387 | 237 | IOSTATE = 0x0B << 3, /* IO Pin State reg - Read only */ |
wim | 1:0440152c5387 | 238 | IOINTENA = 0x0C << 3, /* IO Interrupt Enable - RD/WR access */ |
wim | 1:0440152c5387 | 239 | // reserved = 0x0D << 3, |
wim | 1:0440152c5387 | 240 | IOCTRL = 0x0E << 3, /* IO Control register - RD/WR access */ |
wim | 1:0440152c5387 | 241 | EFCR = 0x0F << 3, /* Extra features reg - RD/WR access */ |
wim | 1:0440152c5387 | 242 | |
wim | 0:d64854a60f95 | 243 | } ; |
wim | 0:d64854a60f95 | 244 | |
wim | 0:d64854a60f95 | 245 | |
wim | 1:0440152c5387 | 246 | // This enum used to be part of SerialBase class (access via SerialBase.h). |
wim | 1:0440152c5387 | 247 | // It seems not be supported anymore. The enums for Parity have moved to Serial now.. |
wim | 1:0440152c5387 | 248 | enum Flow { |
wim | 1:0440152c5387 | 249 | Disabled = 0, |
wim | 1:0440152c5387 | 250 | RTS, |
wim | 1:0440152c5387 | 251 | CTS, |
wim | 1:0440152c5387 | 252 | RTSCTS |
wim | 1:0440152c5387 | 253 | }; |
wim | 1:0440152c5387 | 254 | |
wim | 1:0440152c5387 | 255 | |
wim | 0:d64854a60f95 | 256 | // SC16IS750 configuration register values |
wim | 1:0440152c5387 | 257 | // Several configuration registers are write-only. Need to save values to allow restoring. |
wim | 0:d64854a60f95 | 258 | struct SC16IS750_cfg { |
wim | 0:d64854a60f95 | 259 | char baudrate; |
wim | 0:d64854a60f95 | 260 | char dataformat; |
wim | 0:d64854a60f95 | 261 | char flowctrl; |
wim | 1:0440152c5387 | 262 | char fifoformat; |
wim | 1:0440152c5387 | 263 | bool fifoenable; |
wim | 0:d64854a60f95 | 264 | }; |
wim | 0:d64854a60f95 | 265 | |
wim | 0:d64854a60f95 | 266 | |
wim | 0:d64854a60f95 | 267 | /** Determine if there is a character available to read. |
wim | 0:d64854a60f95 | 268 | * @return 1 if there is a character available to read, 0 otherwise |
wim | 0:d64854a60f95 | 269 | */ |
wim | 1:0440152c5387 | 270 | int readable(); |
wim | 0:d64854a60f95 | 271 | |
wim | 1:0440152c5387 | 272 | /** Determine how many characters available for reading. |
wim | 0:d64854a60f95 | 273 | * @return int Characters available to read |
wim | 0:d64854a60f95 | 274 | */ |
wim | 1:0440152c5387 | 275 | int readableCount(); |
wim | 0:d64854a60f95 | 276 | |
wim | 0:d64854a60f95 | 277 | /** Determine if there is space available to write a character. |
wim | 0:d64854a60f95 | 278 | * @return 1 if there is a space for a character to write, 0 otherwise |
wim | 0:d64854a60f95 | 279 | */ |
wim | 1:0440152c5387 | 280 | int writable(); |
wim | 0:d64854a60f95 | 281 | |
wim | 1:0440152c5387 | 282 | /** Determine how much space available for writing characters. |
wim | 1:0440152c5387 | 283 | * @return int character space available to write |
wim | 0:d64854a60f95 | 284 | */ |
wim | 1:0440152c5387 | 285 | int writableCount(); |
wim | 1:0440152c5387 | 286 | |
wim | 0:d64854a60f95 | 287 | |
wim | 1:0440152c5387 | 288 | /** |
wim | 1:0440152c5387 | 289 | * Read char from UART Bridge. |
wim | 1:0440152c5387 | 290 | * Acts in the same manner as 'Serial.read()'. |
wim | 1:0440152c5387 | 291 | * @param none |
wim | 1:0440152c5387 | 292 | * @return char read or -1 if no data available. |
wim | 1:0440152c5387 | 293 | */ |
wim | 1:0440152c5387 | 294 | int getc(); |
wim | 1:0440152c5387 | 295 | |
wim | 1:0440152c5387 | 296 | /** |
wim | 1:0440152c5387 | 297 | * Write char to UART Bridge. Blocking when no free space in FIFO |
wim | 1:0440152c5387 | 298 | * @param value char to be written |
wim | 1:0440152c5387 | 299 | * @return value written |
wim | 1:0440152c5387 | 300 | */ |
wim | 1:0440152c5387 | 301 | int putc(int value); |
wim | 1:0440152c5387 | 302 | |
wim | 1:0440152c5387 | 303 | void write(const char *str); |
wim | 0:d64854a60f95 | 304 | |
wim | 0:d64854a60f95 | 305 | /** Set baudrate of the serial port. |
wim | 0:d64854a60f95 | 306 | * @param baud integer baudrate (4800, 9600 etc) |
wim | 0:d64854a60f95 | 307 | * @return none |
wim | 0:d64854a60f95 | 308 | */ |
wim | 1:0440152c5387 | 309 | void baud(int baudrate = DEFAULT_BAUD_RATE); |
wim | 0:d64854a60f95 | 310 | |
wim | 0:d64854a60f95 | 311 | /** Set the transmission format used by the serial port. |
wim | 0:d64854a60f95 | 312 | * @param bits The number of bits in a word (5-8; default = 8) |
wim | 0:d64854a60f95 | 313 | * @param parity The parity used (Serial::None, Serial::Odd, Serial::Even, Serial::Forced1, Serial::Forced0; default = Serial::None) |
wim | 0:d64854a60f95 | 314 | * @param stop_bits The number of stop bits (1 or 2; default = 1) |
wim | 0:d64854a60f95 | 315 | */ |
wim | 1:0440152c5387 | 316 | void format(int bits=8, Serial::Parity parity=Serial::None, int stop_bits=1); |
wim | 1:0440152c5387 | 317 | #if(0) |
wim | 1:0440152c5387 | 318 | /** Attach a function to call whenever a serial interrupt is generated |
wim | 1:0440152c5387 | 319 | * |
wim | 1:0440152c5387 | 320 | * @param fptr A pointer to a void function, or 0 to set as none |
wim | 1:0440152c5387 | 321 | * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty) |
wim | 1:0440152c5387 | 322 | */ |
wim | 1:0440152c5387 | 323 | void attach(void (*fptr)(void), IrqType type=RxIrq); |
wim | 1:0440152c5387 | 324 | |
wim | 1:0440152c5387 | 325 | /** Attach a member function to call whenever a serial interrupt is generated |
wim | 1:0440152c5387 | 326 | * |
wim | 1:0440152c5387 | 327 | * @param tptr pointer to the object to call the member function on |
wim | 1:0440152c5387 | 328 | * @param mptr pointer to the member function to be called |
wim | 1:0440152c5387 | 329 | * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty) |
wim | 1:0440152c5387 | 330 | */ |
wim | 1:0440152c5387 | 331 | template<typename T> |
wim | 1:0440152c5387 | 332 | void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) { |
wim | 1:0440152c5387 | 333 | if((mptr != NULL) && (tptr != NULL)) { |
wim | 1:0440152c5387 | 334 | _irq[type].attach(tptr, mptr); |
wim | 1:0440152c5387 | 335 | serial_irq_set(&_serial, (SerialIrq)type, 1); |
wim | 1:0440152c5387 | 336 | } |
wim | 1:0440152c5387 | 337 | } |
wim | 1:0440152c5387 | 338 | #endif |
wim | 1:0440152c5387 | 339 | |
wim | 1:0440152c5387 | 340 | /** Generate a break condition on the serial line |
wim | 1:0440152c5387 | 341 | */ |
wim | 1:0440152c5387 | 342 | void send_break(); |
wim | 0:d64854a60f95 | 343 | |
wim | 1:0440152c5387 | 344 | |
wim | 1:0440152c5387 | 345 | /** Set a break condition on the serial line |
wim | 1:0440152c5387 | 346 | * @param enable break condition |
wim | 1:0440152c5387 | 347 | */ |
wim | 1:0440152c5387 | 348 | void set_break(bool enable=false); |
wim | 1:0440152c5387 | 349 | |
wim | 1:0440152c5387 | 350 | |
wim | 1:0440152c5387 | 351 | /** Set the flow control type on the serial port |
wim | 1:0440152c5387 | 352 | * Added for compatibility with Serial Class. |
wim | 1:0440152c5387 | 353 | * SC16IS750 supports only Flow, Pins can not be selected. |
wim | 1:0440152c5387 | 354 | * |
wim | 1:0440152c5387 | 355 | * @param type the flow control type (Disabled, RTS, CTS, RTSCTS) |
wim | 1:0440152c5387 | 356 | * @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS) |
wim | 1:0440152c5387 | 357 | * @param flow2 the second flow control pin (CTS for RTSCTS) |
wim | 1:0440152c5387 | 358 | */ |
wim | 1:0440152c5387 | 359 | void set_flow_control(Flow type=Disabled, PinName flow1=NC, PinName flow2=NC); |
wim | 1:0440152c5387 | 360 | |
wim | 0:d64854a60f95 | 361 | /** |
wim | 0:d64854a60f95 | 362 | * Check that UART is connected and operational. |
wim | 0:d64854a60f95 | 363 | * @param none |
wim | 0:d64854a60f95 | 364 | * @return bool true when connected, false otherwise |
wim | 0:d64854a60f95 | 365 | */ |
wim | 0:d64854a60f95 | 366 | bool connected(); |
wim | 0:d64854a60f95 | 367 | |
wim | 0:d64854a60f95 | 368 | |
wim | 0:d64854a60f95 | 369 | #if ENABLE_BULK_TRANSFERS |
wim | 0:d64854a60f95 | 370 | void write(const uint8_t *buffer, size_t size); |
wim | 0:d64854a60f95 | 371 | #else |
wim | 0:d64854a60f95 | 372 | // using Print::write; |
wim | 0:d64854a60f95 | 373 | #endif |
wim | 1:0440152c5387 | 374 | |
wim | 1:0440152c5387 | 375 | /** Flush the UART FIFOs while maintaining current FIFO mode. |
wim | 1:0440152c5387 | 376 | * @param none |
wim | 1:0440152c5387 | 377 | * @return none |
wim | 1:0440152c5387 | 378 | */ |
wim | 1:0440152c5387 | 379 | void flush(); |
wim | 0:d64854a60f95 | 380 | |
wim | 0:d64854a60f95 | 381 | //required for Stream |
wim | 1:0440152c5387 | 382 | int peek() {return 0;}; |
wim | 1:0440152c5387 | 383 | |
wim | 1:0440152c5387 | 384 | |
wim | 1:0440152c5387 | 385 | /** Set direction of I/O port pins. |
wim | 1:0440152c5387 | 386 | * This method is specific to the SPI-I2C UART and not found on the 16750 |
wim | 1:0440152c5387 | 387 | * @param bits Bitpattern for I/O (1=output, 0=input) |
wim | 1:0440152c5387 | 388 | * @return none |
wim | 1:0440152c5387 | 389 | */ |
wim | 1:0440152c5387 | 390 | void ioSetDirection(unsigned char bits); |
wim | 0:d64854a60f95 | 391 | |
wim | 1:0440152c5387 | 392 | /** Set bits of I/O port pins. |
wim | 1:0440152c5387 | 393 | * This method is specific to the SPI-I2C UART and not found on the 16750 |
wim | 1:0440152c5387 | 394 | * @param bits Bitpattern for I/O (1= set output bit, 0 = clear output bit) |
wim | 1:0440152c5387 | 395 | * @return none |
wim | 1:0440152c5387 | 396 | */ |
wim | 1:0440152c5387 | 397 | void ioSetState(unsigned char bits); |
wim | 1:0440152c5387 | 398 | |
wim | 1:0440152c5387 | 399 | /** Get bits of I/O port pins. |
wim | 1:0440152c5387 | 400 | * This method is specific to the SPI-I2C UART and not found on the 16750 |
wim | 1:0440152c5387 | 401 | * @param none |
wim | 1:0440152c5387 | 402 | * @return bits Bitpattern for I/O (1= bit set, 0 = bit cleared) |
wim | 1:0440152c5387 | 403 | */ |
wim | 1:0440152c5387 | 404 | unsigned char ioGetState(); |
wim | 1:0440152c5387 | 405 | |
wim | 1:0440152c5387 | 406 | |
wim | 1:0440152c5387 | 407 | /** Software Reset SC16IS750 device. |
wim | 1:0440152c5387 | 408 | * This method is specific to the SPI-I2C UART and not found on the 16750 |
wim | 1:0440152c5387 | 409 | * @param none |
wim | 1:0440152c5387 | 410 | * @return none |
wim | 1:0440152c5387 | 411 | */ |
wim | 1:0440152c5387 | 412 | void swReset(); |
wim | 1:0440152c5387 | 413 | |
wim | 0:d64854a60f95 | 414 | |
wim | 0:d64854a60f95 | 415 | /** Write value to internal register. |
wim | 0:d64854a60f95 | 416 | * Pure virtual, must be declared in derived class. |
wim | 1:0440152c5387 | 417 | * @param registerAddress The address of the Register (enum RegisterName) |
wim | 0:d64854a60f95 | 418 | * @param data The 8bit value to write |
wim | 0:d64854a60f95 | 419 | * @return none |
wim | 0:d64854a60f95 | 420 | */ |
wim | 1:0440152c5387 | 421 | virtual void writeRegister (RegisterName register_address, char data ) =0; |
wim | 0:d64854a60f95 | 422 | |
wim | 0:d64854a60f95 | 423 | /** Read value from internal register. |
wim | 0:d64854a60f95 | 424 | * Pure virtual, must be declared in derived class. |
wim | 1:0440152c5387 | 425 | * @param registerAddress The address of the Register (enum RegisterName) |
wim | 0:d64854a60f95 | 426 | * @return char The 8bit value read from the register |
wim | 0:d64854a60f95 | 427 | */ |
wim | 1:0440152c5387 | 428 | virtual char readRegister (RegisterName register_address ) =0; |
wim | 1:0440152c5387 | 429 | |
wim | 0:d64854a60f95 | 430 | |
wim | 1:0440152c5387 | 431 | /** Initialise internal registers |
wim | 1:0440152c5387 | 432 | * Should be in protection section. Public for testing purposes |
wim | 1:0440152c5387 | 433 | * If initialisation fails this method does not return. |
wim | 1:0440152c5387 | 434 | * @param none |
wim | 1:0440152c5387 | 435 | * @return none |
wim | 1:0440152c5387 | 436 | */ |
wim | 1:0440152c5387 | 437 | void _init(); |
wim | 1:0440152c5387 | 438 | |
wim | 0:d64854a60f95 | 439 | protected: |
wim | 0:d64854a60f95 | 440 | //protected is accessible to derived classes, but not to external users |
wim | 0:d64854a60f95 | 441 | |
wim | 1:0440152c5387 | 442 | /** Constructor for this Abstract Class is protected |
wim | 1:0440152c5387 | 443 | * |
wim | 1:0440152c5387 | 444 | */ |
wim | 1:0440152c5387 | 445 | SC16IS750(); |
wim | 1:0440152c5387 | 446 | |
wim | 1:0440152c5387 | 447 | |
wim | 0:d64854a60f95 | 448 | SC16IS750_cfg _config; |
wim | 0:d64854a60f95 | 449 | |
wim | 0:d64854a60f95 | 450 | private: |
wim | 0:d64854a60f95 | 451 | //private is not accessible to derived classes, nor external users |
wim | 1:0440152c5387 | 452 | |
wim | 0:d64854a60f95 | 453 | }; |
wim | 0:d64854a60f95 | 454 | |
wim | 0:d64854a60f95 | 455 | |
wim | 0:d64854a60f95 | 456 | |
wim | 0:d64854a60f95 | 457 | /** Class SC16IS750_SPI for a converter between SPI and a Serial port |
wim | 0:d64854a60f95 | 458 | * |
wim | 0:d64854a60f95 | 459 | * @code |
wim | 0:d64854a60f95 | 460 | * #include "mbed.h" |
wim | 0:d64854a60f95 | 461 | * #include "SC16IS750.h" |
wim | 0:d64854a60f95 | 462 | * |
wim | 0:d64854a60f95 | 463 | * SPI spi(PTD2, PTD3, PTD1); //MOSI, MISO, SCK |
wim | 0:d64854a60f95 | 464 | * SC16IS750_SPI serial_spi(&spi, PTD0); |
wim | 0:d64854a60f95 | 465 | * |
wim | 0:d64854a60f95 | 466 | * Serial pc(USBTX,USBRX); |
wim | 0:d64854a60f95 | 467 | * |
wim | 0:d64854a60f95 | 468 | * int main() { |
wim | 0:d64854a60f95 | 469 | * pc.printf("\nHello World!\n"); |
wim | 0:d64854a60f95 | 470 | * |
wim | 0:d64854a60f95 | 471 | * while(1) { |
wim | 0:d64854a60f95 | 472 | * serial_spi.ioSetState(0x00); |
wim | 0:d64854a60f95 | 473 | * wait(0.5); |
wim | 0:d64854a60f95 | 474 | * pc.putc('*'); |
wim | 0:d64854a60f95 | 475 | * } |
wim | 0:d64854a60f95 | 476 | * } |
wim | 0:d64854a60f95 | 477 | * |
wim | 0:d64854a60f95 | 478 | * @endcode |
wim | 0:d64854a60f95 | 479 | */ |
wim | 0:d64854a60f95 | 480 | class SC16IS750_SPI : public SC16IS750 { |
wim | 0:d64854a60f95 | 481 | public: |
wim | 0:d64854a60f95 | 482 | |
wim | 0:d64854a60f95 | 483 | /** Create a SC16IS750_SPI object using a specified SPI bus and CS |
wim | 0:d64854a60f95 | 484 | * |
wim | 0:d64854a60f95 | 485 | * @param SPI &spi the SPI port to connect to |
wim | 0:d64854a60f95 | 486 | * @param cs the Pin of the CS |
wim | 0:d64854a60f95 | 487 | */ |
wim | 0:d64854a60f95 | 488 | SC16IS750_SPI(SPI *spi, PinName cs); |
wim | 0:d64854a60f95 | 489 | |
wim | 0:d64854a60f95 | 490 | /** Write value to internal register. |
wim | 1:0440152c5387 | 491 | * @param registerAddress The address of the Register (enum RegisterName) |
wim | 0:d64854a60f95 | 492 | * @param data The 8bit value to write |
wim | 0:d64854a60f95 | 493 | * @return none |
wim | 0:d64854a60f95 | 494 | */ |
wim | 0:d64854a60f95 | 495 | virtual void writeRegister(SC16IS750::RegisterName registerAddress, char data); |
wim | 0:d64854a60f95 | 496 | |
wim | 0:d64854a60f95 | 497 | /** Read value from internal register. |
wim | 1:0440152c5387 | 498 | * @param registerAddress The address of the Register (enum RegisterName) |
wim | 0:d64854a60f95 | 499 | * @return char The 8bit value read from the register |
wim | 0:d64854a60f95 | 500 | */ |
wim | 0:d64854a60f95 | 501 | virtual char readRegister(SC16IS750::RegisterName registerAddress); |
wim | 0:d64854a60f95 | 502 | |
wim | 0:d64854a60f95 | 503 | protected: |
wim | 0:d64854a60f95 | 504 | //protected is accessible to derived classes, but not to external users |
wim | 0:d64854a60f95 | 505 | |
wim | 0:d64854a60f95 | 506 | |
wim | 0:d64854a60f95 | 507 | private: |
wim | 0:d64854a60f95 | 508 | SPI *_spi; //SPI bus reference |
wim | 0:d64854a60f95 | 509 | DigitalOut _cs; //CS of SPI device |
wim | 0:d64854a60f95 | 510 | |
wim | 0:d64854a60f95 | 511 | }; |
wim | 0:d64854a60f95 | 512 | |
wim | 0:d64854a60f95 | 513 | |
wim | 0:d64854a60f95 | 514 | |
wim | 0:d64854a60f95 | 515 | /** Class SC16IS750_I2C for a converter between I2C and a Serial port |
wim | 0:d64854a60f95 | 516 | * |
wim | 0:d64854a60f95 | 517 | * @code |
wim | 0:d64854a60f95 | 518 | * #include "mbed.h" |
wim | 0:d64854a60f95 | 519 | * #include "SC16IS750.h" |
wim | 0:d64854a60f95 | 520 | * |
wim | 0:d64854a60f95 | 521 | * I2C i2c(PTE0, PTE1); //SDA, SCL |
wim | 0:d64854a60f95 | 522 | * SC16IS750_I2C serial_i2c(&i2c, DEFAULT_SC16IS750_ADDR); |
wim | 0:d64854a60f95 | 523 | * |
wim | 0:d64854a60f95 | 524 | * Serial pc(USBTX,USBRX); |
wim | 0:d64854a60f95 | 525 | * |
wim | 0:d64854a60f95 | 526 | * int main() { |
wim | 0:d64854a60f95 | 527 | * pc.printf("\nHello World!\n"); |
wim | 0:d64854a60f95 | 528 | * |
wim | 0:d64854a60f95 | 529 | * while(1) { |
wim | 0:d64854a60f95 | 530 | * serial_i2c.ioSetState(0x00); |
wim | 0:d64854a60f95 | 531 | * wait(0.5); |
wim | 0:d64854a60f95 | 532 | * pc.putc('*'); |
wim | 0:d64854a60f95 | 533 | * } |
wim | 0:d64854a60f95 | 534 | * } |
wim | 0:d64854a60f95 | 535 | * |
wim | 0:d64854a60f95 | 536 | * @endcode |
wim | 0:d64854a60f95 | 537 | */ |
wim | 0:d64854a60f95 | 538 | class SC16IS750_I2C : public SC16IS750 { |
wim | 0:d64854a60f95 | 539 | public: |
wim | 0:d64854a60f95 | 540 | |
wim | 0:d64854a60f95 | 541 | /** Create a SC16IS750_I2C object using a specified I2C bus and slaveaddress |
wim | 0:d64854a60f95 | 542 | * |
wim | 0:d64854a60f95 | 543 | * @param I2C &i2c the I2C port to connect to |
wim | 0:d64854a60f95 | 544 | * @param char deviceAddress the address of the SC16IS750 |
wim | 0:d64854a60f95 | 545 | */ |
wim | 0:d64854a60f95 | 546 | SC16IS750_I2C(I2C *i2c, uint8_t deviceAddress = DEFAULT_SC16IS750_ADDR); |
wim | 0:d64854a60f95 | 547 | |
wim | 0:d64854a60f95 | 548 | /** Write value to internal register. |
wim | 1:0440152c5387 | 549 | * @param registerAddress The address of the Register (enum RegisterName) |
wim | 0:d64854a60f95 | 550 | * @param data The 8bit value to write |
wim | 0:d64854a60f95 | 551 | * @return none |
wim | 0:d64854a60f95 | 552 | */ |
wim | 0:d64854a60f95 | 553 | virtual void writeRegister(SC16IS750::RegisterName register_address, char data ); |
wim | 0:d64854a60f95 | 554 | |
wim | 0:d64854a60f95 | 555 | /** Read value from internal register. |
wim | 1:0440152c5387 | 556 | * @param registerAddress The address of the Register (enum RegisterName) |
wim | 0:d64854a60f95 | 557 | * @return char The 8bit value read from the register |
wim | 0:d64854a60f95 | 558 | */ |
wim | 0:d64854a60f95 | 559 | virtual char readRegister(SC16IS750::RegisterName register_address ); |
wim | 0:d64854a60f95 | 560 | |
wim | 0:d64854a60f95 | 561 | protected: |
wim | 0:d64854a60f95 | 562 | //protected is accessible to derived classes, but not to external users |
wim | 0:d64854a60f95 | 563 | |
wim | 0:d64854a60f95 | 564 | |
wim | 0:d64854a60f95 | 565 | private: |
wim | 0:d64854a60f95 | 566 | I2C *_i2c; //I2C bus reference |
wim | 0:d64854a60f95 | 567 | uint8_t _slaveAddress; //I2C Slave address of device |
wim | 0:d64854a60f95 | 568 | |
wim | 0:d64854a60f95 | 569 | }; |
wim | 0:d64854a60f95 | 570 | |
wim | 0:d64854a60f95 | 571 | |
wim | 0:d64854a60f95 | 572 | #endif // _SC16IS750_H |