valeria toffoli / Mbed OS COG4050_adxrs290_adxrs453

driver for gyro

Dependencies:   COG4050_ADT7420

Fork of COG4050_adxl355_adxl357-ver2 by ADI_CAC

ADXRS290/ADXRS290.cpp@9:1afd906c5ed2, 2018-09-07 (annotated)

Committer:
vtoffoli
Date:
Fri Sep 07 15:49:25 2018 +0000
Revision:
9:1afd906c5ed2
Parent:
7:5aaa09c40283 
basic driver;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vtoffoli 6:45d2393ef468 1 #include <stdint.h>
vtoffoli 6:45d2393ef468 2 #include "mbed.h"
vtoffoli 6:45d2393ef468 3 #include "ADXRS290.h"
vtoffoli 6:45d2393ef468 4
vtoffoli 7:5aaa09c40283 5 /** ----------------------------------- */
vtoffoli 7:5aaa09c40283 6 /** SPI - MAX 5MHZ */
vtoffoli 7:5aaa09c40283 7 /** ----------------------------------- */
vtoffoli 6:45d2393ef468 8 ADXRS290::ADXRS290(PinName cs_pin, PinName MOSI, PinName MISO, PinName SCK): adxrs290(MOSI, MISO, SCK), cs(cs_pin)
vtoffoli 6:45d2393ef468 9 {
vtoffoli 6:45d2393ef468 10 cs = 1;
vtoffoli 6:45d2393ef468 11 adxrs290.format(8,_SPI_MODE);
vtoffoli 6:45d2393ef468 12 adxrs290.lock();
vtoffoli 6:45d2393ef468 13 }
vtoffoli 6:45d2393ef468 14 void ADXRS290::frequency(int hz)
vtoffoli 6:45d2393ef468 15 {
vtoffoli 6:45d2393ef468 16 adxrs290.frequency(hz);
vtoffoli 6:45d2393ef468 17 }
vtoffoli 6:45d2393ef468 18
vtoffoli 6:45d2393ef468 19 /** ----------------------------------- */
vtoffoli 6:45d2393ef468 20 /** Writes the reg register with data */
vtoffoli 6:45d2393ef468 21 /** ----------------------------------- */
vtoffoli 7:5aaa09c40283 22 void ADXRS290::write_reg(ADXRS290_register_t reg, uint8_t data){
vtoffoli 7:5aaa09c40283 23 adxrs290.format(8, _SPI_MODE);
vtoffoli 7:5aaa09c40283 24 cs = false;
vtoffoli 7:5aaa09c40283 25 adxrs290.write(static_cast<uint8_t>(reg) | _WRITE_REG_CMD);
vtoffoli 7:5aaa09c40283 26 adxrs290.write(data);
vtoffoli 7:5aaa09c40283 27 cs = true;
vtoffoli 7:5aaa09c40283 28 }
vtoffoli 7:5aaa09c40283 29 /** ----------------------------------- */
vtoffoli 7:5aaa09c40283 30 /** Reads the reg register */
vtoffoli 7:5aaa09c40283 31 /** ----------------------------------- */
vtoffoli 7:5aaa09c40283 32 uint8_t ADXRS290::read_reg(ADXRS290_register_t reg){
vtoffoli 7:5aaa09c40283 33 uint8_t ret_val;
vtoffoli 7:5aaa09c40283 34 adxrs290.format(8, _SPI_MODE);
vtoffoli 7:5aaa09c40283 35 cs = false;
vtoffoli 7:5aaa09c40283 36 adxrs290.write(static_cast<uint8_t>(reg) | _READ_REG_CMD);
vtoffoli 7:5aaa09c40283 37 ret_val = adxrs290.write(_DUMMY_BYTE);
vtoffoli 7:5aaa09c40283 38 cs = true;
vtoffoli 7:5aaa09c40283 39 return ret_val;
vtoffoli 7:5aaa09c40283 40 }
vtoffoli 7:5aaa09c40283 41 uint16_t ADXRS290::read_reg_u16(ADXRS290_register_t reg){
vtoffoli 7:5aaa09c40283 42 uint16_t ret_val = 0;
vtoffoli 7:5aaa09c40283 43 adxrs290.format(8, _SPI_MODE);
vtoffoli 7:5aaa09c40283 44 cs = false;
vtoffoli 7:5aaa09c40283 45 adxrs290.write(static_cast<uint8_t>(reg) | _READ_REG_CMD);
vtoffoli 7:5aaa09c40283 46 ret_val = adxrs290.write(_DUMMY_BYTE);
vtoffoli 7:5aaa09c40283 47 ret_val = (ret_val) | (adxrs290.write(_DUMMY_BYTE)<<8);
vtoffoli 7:5aaa09c40283 48 cs = true;
vtoffoli 7:5aaa09c40283 49 return ret_val;
vtoffoli 7:5aaa09c40283 50 }
vtoffoli 7:5aaa09c40283 51 /** ----------------------------------- */
vtoffoli 7:5aaa09c40283 52 /** Sets the CTL registers */
vtoffoli 7:5aaa09c40283 53 /** ----------------------------------- */
vtoffoli 7:5aaa09c40283 54 void ADXRS290::set_power_ctl_reg(uint8_t data){
vtoffoli 7:5aaa09c40283 55 write_reg(POWER_CTL, data);
vtoffoli 7:5aaa09c40283 56 wait(0.1);
vtoffoli 7:5aaa09c40283 57 }
vtoffoli 7:5aaa09c40283 58 void ADXRS290::set_filter_ctl_reg(ADXRS290_filter_ctl_t hpf, ADXRS290_filter_ctl_t lpf){
vtoffoli 7:5aaa09c40283 59 write_reg(FILTER, hpf|lpf);
vtoffoli 7:5aaa09c40283 60 }
vtoffoli 9:1afd906c5ed2 61 void ADXRS290::set_sync(ADXRS290_dataready_ctl_t data){
vtoffoli 9:1afd906c5ed2 62 }
vtoffoli 9:1afd906c5ed2 63 /** ----------------------------------- */
vtoffoli 9:1afd906c5ed2 64 /** READ data registers */
vtoffoli 9:1afd906c5ed2 65 /** ----------------------------------- */
vtoffoli 7:5aaa09c40283 66 uint16_t ADXRS290::scanx(){
vtoffoli 7:5aaa09c40283 67 return read_reg_u16(DATAX0);
vtoffoli 7:5aaa09c40283 68 }
vtoffoli 7:5aaa09c40283 69 uint16_t ADXRS290::scany(){
vtoffoli 7:5aaa09c40283 70 return read_reg_u16(DATAY0);
vtoffoli 7:5aaa09c40283 71 }
vtoffoli 7:5aaa09c40283 72 uint16_t ADXRS290::scant(){
vtoffoli 7:5aaa09c40283 73 return read_reg_u16(TEMP0);
vtoffoli 9:1afd906c5ed2 74 }
vtoffoli 9:1afd906c5ed2 75 ADXRS290::ADXRS290_rate_t ADXRS290::scan(){
vtoffoli 9:1afd906c5ed2 76 uint16_t datax, datay, dataz;
vtoffoli 9:1afd906c5ed2 77 ADXRS290_rate_t res;
vtoffoli 9:1afd906c5ed2 78 // multiple byte read procedure
vtoffoli 9:1afd906c5ed2 79 adxrs290.format(8, _SPI_MODE);
vtoffoli 9:1afd906c5ed2 80 cs = false;
vtoffoli 9:1afd906c5ed2 81 adxrs290.write(static_cast<uint8_t>(DATAX0) | _READ_REG_CMD);
vtoffoli 9:1afd906c5ed2 82 datax = adxrs290.write(_DUMMY_BYTE);
vtoffoli 9:1afd906c5ed2 83 datax = (datax) | (adxrs290.write(_DUMMY_BYTE)<<8);
vtoffoli 9:1afd906c5ed2 84 datay = adxrs290.write(_DUMMY_BYTE);
vtoffoli 9:1afd906c5ed2 85 datay = (datay) | (adxrs290.write(_DUMMY_BYTE)<<8);
vtoffoli 9:1afd906c5ed2 86 dataz = adxrs290.write(_DUMMY_BYTE);
vtoffoli 9:1afd906c5ed2 87 dataz = (dataz) | (adxrs290.write(_DUMMY_BYTE)<<8);
vtoffoli 9:1afd906c5ed2 88 cs = true;
vtoffoli 9:1afd906c5ed2 89 // 2s compl conversion
vtoffoli 9:1afd906c5ed2 90 if ((datax & 0x8000) == 0) {res.rt_x=float(datax);}
vtoffoli 9:1afd906c5ed2 91 else{res.rt_x=float((~(datax - 0x01)) & 0xffff) * -1;}
vtoffoli 9:1afd906c5ed2 92 if ((datay & 0x8000) == 0) {res.rt_y=float(datay);}
vtoffoli 9:1afd906c5ed2 93 else{res.rt_y=float((~(datay - 0x01)) & 0xffff) * -1;}
vtoffoli 9:1afd906c5ed2 94 if ((dataz & 0x8000) == 0) {res.rt_z=float(dataz);}
vtoffoli 9:1afd906c5ed2 95 else{res.rt_z=float((~(dataz - 0x01)) & 0xffff) * -1;}
vtoffoli 9:1afd906c5ed2 96 return res;
vtoffoli 9:1afd906c5ed2 97 }