Diff: Target2.h

Revision:

0:27d35fa263b5

Child:

1:eb30547ba84d

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/Target2.h	Sun Sep 01 08:25:28 2013 +0000
@@ -0,0 +1,70 @@
+// Target2.h 2013/9/1
+#pragma once
+#include "mbed.h"
+#include "SWD.h"
+
+#define TARGET_RUNNING  (1<<0)
+#define TARGET_HALTED   (1<<1)
+
+class Target2;
+class CoreReg {
+public:
+    void setup(Target2* target, uint8_t reg);
+    uint32_t read();
+    void write(uint32_t value);
+    
+    CoreReg& operator= (int value) {
+        write(value);
+        return *this;
+    }
+
+    CoreReg& operator= (CoreReg& rhs) {
+        write(rhs.read());
+        return *this;
+    }
+
+    operator uint32_t() {
+        return read();
+    }
+protected:
+    Target2* _target;
+    uint8_t _reg;    
+};
+
+class Target2 {
+public:
+    Target2(PinName swdio, PinName swclk, PinName reset, Serial* usbpc);
+    bool setup();
+    uint32_t readMemory(uint32_t addr);
+    void readMemory(uint32_t addr, uint32_t* data, int count);
+    void writeMemory(uint32_t addr, uint32_t data);
+    void writeMemory(uint32_t addr, uint32_t* data, int count);
+    void halt();
+    void resume();
+    void Abort();
+    void Reset();
+    int getStatus();
+    bool wait_status(int status, int timeout_ms = 500);
+    CoreReg r0;
+    CoreReg r1; 
+    CoreReg r2; 
+    CoreReg r3; 
+    CoreReg r4; 
+    CoreReg r5; 
+    CoreReg r6; 
+    CoreReg r7; 
+    CoreReg r8; 
+    CoreReg r9; 
+    CoreReg r10; 
+    CoreReg r11; 
+    CoreReg r12; 
+    CoreReg sp; 
+    CoreReg lr; 
+    CoreReg pc;
+    CoreReg xpsr;
+private:
+    void _setaddr(uint32_t addr); 
+protected:
+    SWD _swd;
+    Serial* _pc;
+};