Norimasa Okamoto / Mbed 2 deprecated lpcterm2

semihost server example program

Dependencies:   SWD mbed USBLocalFileSystem BaseDAP USBDAP

/media/uploads/va009039/kl46z-lpc800-360x480.jpg

LPCXpresso
LPC11U68		LPCXpresso
LPC1549		FRDM-KL46ZEA LPC4088 QSB
app-board		LPC1768
app-board		LPC810LPC1114FN28
serverserverserverserverserverclientclient
SWDIOD12D12D12p25p21p4(P0_2)p12
SWCLKD10D10D10p26p22p3(P0_3)p3
nRESET
*option		D6D6D6p34p30p1(P0_5)p23
GNDGNDGNDGNDp1p1p7p22
3.3VP3V3P3V3P3V3p44p40p6p21
flash writeSW2(P0_1)SW3(P1_9)SW1p14
joystick
center		p14
joystick
center

client example:

Import programlpc810-semihost_helloworld

semihost client example program

Last commit 20 Feb 2014 by Norimasa Okamoto

Target2.h@0:27d35fa263b5, 2013-09-01 (annotated)

Committer:
va009039
Date:
Sun Sep 01 08:25:28 2013 +0000
Revision:
0:27d35fa263b5
Child:
1:eb30547ba84d
first commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
va009039 0:27d35fa263b5 1 // Target2.h 2013/9/1
va009039 0:27d35fa263b5 2 #pragma once
va009039 0:27d35fa263b5 3 #include "mbed.h"
va009039 0:27d35fa263b5 4 #include "SWD.h"
va009039 0:27d35fa263b5 5
va009039 0:27d35fa263b5 6 #define TARGET_RUNNING (1<<0)
va009039 0:27d35fa263b5 7 #define TARGET_HALTED (1<<1)
va009039 0:27d35fa263b5 8
va009039 0:27d35fa263b5 9 class Target2;
va009039 0:27d35fa263b5 10 class CoreReg {
va009039 0:27d35fa263b5 11 public:
va009039 0:27d35fa263b5 12 void setup(Target2* target, uint8_t reg);
va009039 0:27d35fa263b5 13 uint32_t read();
va009039 0:27d35fa263b5 14 void write(uint32_t value);
va009039 0:27d35fa263b5 15
va009039 0:27d35fa263b5 16 CoreReg& operator= (int value) {
va009039 0:27d35fa263b5 17 write(value);
va009039 0:27d35fa263b5 18 return *this;
va009039 0:27d35fa263b5 19 }
va009039 0:27d35fa263b5 20
va009039 0:27d35fa263b5 21 CoreReg& operator= (CoreReg& rhs) {
va009039 0:27d35fa263b5 22 write(rhs.read());
va009039 0:27d35fa263b5 23 return *this;
va009039 0:27d35fa263b5 24 }
va009039 0:27d35fa263b5 25
va009039 0:27d35fa263b5 26 operator uint32_t() {
va009039 0:27d35fa263b5 27 return read();
va009039 0:27d35fa263b5 28 }
va009039 0:27d35fa263b5 29 protected:
va009039 0:27d35fa263b5 30 Target2* _target;
va009039 0:27d35fa263b5 31 uint8_t _reg;
va009039 0:27d35fa263b5 32 };
va009039 0:27d35fa263b5 33
va009039 0:27d35fa263b5 34 class Target2 {
va009039 0:27d35fa263b5 35 public:
va009039 0:27d35fa263b5 36 Target2(PinName swdio, PinName swclk, PinName reset, Serial* usbpc);
va009039 0:27d35fa263b5 37 bool setup();
va009039 0:27d35fa263b5 38 uint32_t readMemory(uint32_t addr);
va009039 0:27d35fa263b5 39 void readMemory(uint32_t addr, uint32_t* data, int count);
va009039 0:27d35fa263b5 40 void writeMemory(uint32_t addr, uint32_t data);
va009039 0:27d35fa263b5 41 void writeMemory(uint32_t addr, uint32_t* data, int count);
va009039 0:27d35fa263b5 42 void halt();
va009039 0:27d35fa263b5 43 void resume();
va009039 0:27d35fa263b5 44 void Abort();
va009039 0:27d35fa263b5 45 void Reset();
va009039 0:27d35fa263b5 46 int getStatus();
va009039 0:27d35fa263b5 47 bool wait_status(int status, int timeout_ms = 500);
va009039 0:27d35fa263b5 48 CoreReg r0;
va009039 0:27d35fa263b5 49 CoreReg r1;
va009039 0:27d35fa263b5 50 CoreReg r2;
va009039 0:27d35fa263b5 51 CoreReg r3;
va009039 0:27d35fa263b5 52 CoreReg r4;
va009039 0:27d35fa263b5 53 CoreReg r5;
va009039 0:27d35fa263b5 54 CoreReg r6;
va009039 0:27d35fa263b5 55 CoreReg r7;
va009039 0:27d35fa263b5 56 CoreReg r8;
va009039 0:27d35fa263b5 57 CoreReg r9;
va009039 0:27d35fa263b5 58 CoreReg r10;
va009039 0:27d35fa263b5 59 CoreReg r11;
va009039 0:27d35fa263b5 60 CoreReg r12;
va009039 0:27d35fa263b5 61 CoreReg sp;
va009039 0:27d35fa263b5 62 CoreReg lr;
va009039 0:27d35fa263b5 63 CoreReg pc;
va009039 0:27d35fa263b5 64 CoreReg xpsr;
va009039 0:27d35fa263b5 65 private:
va009039 0:27d35fa263b5 66 void _setaddr(uint32_t addr);
va009039 0:27d35fa263b5 67 protected:
va009039 0:27d35fa263b5 68 SWD _swd;
va009039 0:27d35fa263b5 69 Serial* _pc;
va009039 0:27d35fa263b5 70 };