semihost server example program
Dependencies: SWD mbed USBLocalFileSystem BaseDAP USBDAP
LPCXpresso LPC11U68 | LPCXpresso LPC1549 | FRDM-KL46Z | EA LPC4088 QSB app-board | LPC1768 app-board | LPC810 | LPC1114FN28 | |
---|---|---|---|---|---|---|---|
server | server | server | server | server | client | client | |
SWDIO | D12 | D12 | D12 | p25 | p21 | p4(P0_2) | p12 |
SWCLK | D10 | D10 | D10 | p26 | p22 | p3(P0_3) | p3 |
nRESET *option | D6 | D6 | D6 | p34 | p30 | p1(P0_5) | p23 |
GND | GND | GND | GND | p1 | p1 | p7 | p22 |
3.3V | P3V3 | P3V3 | P3V3 | p44 | p40 | p6 | p21 |
flash write | SW2(P0_1) | SW3(P1_9) | SW1 | p14 joystick center | p14 joystick center |
client example:
Import programlpc810-semihost_helloworld
semihost client example program
Target2.h@6:5da6ad51a18f, 2013-09-23 (annotated)
- Committer:
- va009039
- Date:
- Mon Sep 23 00:31:45 2013 +0000
- Revision:
- 6:5da6ad51a18f
- Parent:
- 5:2774358f5e4f
- Child:
- 7:acfd2dbff157
validate the address of the breakpoint.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
va009039 | 6:5da6ad51a18f | 1 | // Target2.h 2013/9/17 |
va009039 | 0:27d35fa263b5 | 2 | #pragma once |
va009039 | 0:27d35fa263b5 | 3 | #include "mbed.h" |
va009039 | 0:27d35fa263b5 | 4 | #include "SWD.h" |
va009039 | 0:27d35fa263b5 | 5 | |
va009039 | 0:27d35fa263b5 | 6 | #define TARGET_RUNNING (1<<0) |
va009039 | 0:27d35fa263b5 | 7 | #define TARGET_HALTED (1<<1) |
va009039 | 0:27d35fa263b5 | 8 | |
va009039 | 0:27d35fa263b5 | 9 | class Target2; |
va009039 | 0:27d35fa263b5 | 10 | class CoreReg { |
va009039 | 0:27d35fa263b5 | 11 | public: |
va009039 | 0:27d35fa263b5 | 12 | void setup(Target2* target, uint8_t reg); |
va009039 | 0:27d35fa263b5 | 13 | uint32_t read(); |
va009039 | 0:27d35fa263b5 | 14 | void write(uint32_t value); |
va009039 | 0:27d35fa263b5 | 15 | |
va009039 | 0:27d35fa263b5 | 16 | CoreReg& operator= (int value) { |
va009039 | 0:27d35fa263b5 | 17 | write(value); |
va009039 | 0:27d35fa263b5 | 18 | return *this; |
va009039 | 0:27d35fa263b5 | 19 | } |
va009039 | 0:27d35fa263b5 | 20 | |
va009039 | 0:27d35fa263b5 | 21 | CoreReg& operator= (CoreReg& rhs) { |
va009039 | 0:27d35fa263b5 | 22 | write(rhs.read()); |
va009039 | 0:27d35fa263b5 | 23 | return *this; |
va009039 | 0:27d35fa263b5 | 24 | } |
va009039 | 0:27d35fa263b5 | 25 | |
va009039 | 0:27d35fa263b5 | 26 | operator uint32_t() { |
va009039 | 0:27d35fa263b5 | 27 | return read(); |
va009039 | 0:27d35fa263b5 | 28 | } |
va009039 | 0:27d35fa263b5 | 29 | protected: |
va009039 | 0:27d35fa263b5 | 30 | Target2* _target; |
va009039 | 0:27d35fa263b5 | 31 | uint8_t _reg; |
va009039 | 0:27d35fa263b5 | 32 | }; |
va009039 | 0:27d35fa263b5 | 33 | |
va009039 | 5:2774358f5e4f | 34 | /** Target MCU interface |
va009039 | 5:2774358f5e4f | 35 | */ |
va009039 | 0:27d35fa263b5 | 36 | class Target2 { |
va009039 | 0:27d35fa263b5 | 37 | public: |
va009039 | 5:2774358f5e4f | 38 | /** create target MCU interface |
va009039 | 5:2774358f5e4f | 39 | * @param swdio SWD(swdio) pin |
va009039 | 5:2774358f5e4f | 40 | * @param swclk SWD(swclk) pin |
va009039 | 5:2774358f5e4f | 41 | * @param reset reset pin |
va009039 | 5:2774358f5e4f | 42 | */ |
va009039 | 5:2774358f5e4f | 43 | Target2(PinName swdio, PinName swclk, PinName reset); |
va009039 | 0:27d35fa263b5 | 44 | bool setup(); |
va009039 | 6:5da6ad51a18f | 45 | void SWJClock(uint32_t clock_hz); |
va009039 | 0:27d35fa263b5 | 46 | uint32_t readMemory(uint32_t addr); |
va009039 | 0:27d35fa263b5 | 47 | void readMemory(uint32_t addr, uint32_t* data, int count); |
va009039 | 0:27d35fa263b5 | 48 | void writeMemory(uint32_t addr, uint32_t data); |
va009039 | 0:27d35fa263b5 | 49 | void writeMemory(uint32_t addr, uint32_t* data, int count); |
va009039 | 1:eb30547ba84d | 50 | uint8_t readMemory8(uint32_t addr); |
va009039 | 1:eb30547ba84d | 51 | void writeMemory8(uint32_t addr, uint8_t data); |
va009039 | 0:27d35fa263b5 | 52 | void halt(); |
va009039 | 0:27d35fa263b5 | 53 | void resume(); |
va009039 | 1:eb30547ba84d | 54 | void step(); |
va009039 | 0:27d35fa263b5 | 55 | void Abort(); |
va009039 | 3:d7a7cde0bfb8 | 56 | void HardwareReset(); |
va009039 | 2:32e9437348ad | 57 | void SoftwareReset(); |
va009039 | 0:27d35fa263b5 | 58 | int getStatus(); |
va009039 | 0:27d35fa263b5 | 59 | bool wait_status(int status, int timeout_ms = 500); |
va009039 | 4:5e4107edcbdb | 60 | bool prog_status(); |
va009039 | 6:5da6ad51a18f | 61 | bool setBreakpoint0(uint32_t addr); |
va009039 | 6:5da6ad51a18f | 62 | void removeBreakpoint0(uint32_t addr); |
va009039 | 4:5e4107edcbdb | 63 | |
va009039 | 0:27d35fa263b5 | 64 | CoreReg r0; |
va009039 | 0:27d35fa263b5 | 65 | CoreReg r1; |
va009039 | 0:27d35fa263b5 | 66 | CoreReg r2; |
va009039 | 0:27d35fa263b5 | 67 | CoreReg r3; |
va009039 | 0:27d35fa263b5 | 68 | CoreReg r4; |
va009039 | 0:27d35fa263b5 | 69 | CoreReg r5; |
va009039 | 0:27d35fa263b5 | 70 | CoreReg r6; |
va009039 | 0:27d35fa263b5 | 71 | CoreReg r7; |
va009039 | 0:27d35fa263b5 | 72 | CoreReg r8; |
va009039 | 0:27d35fa263b5 | 73 | CoreReg r9; |
va009039 | 0:27d35fa263b5 | 74 | CoreReg r10; |
va009039 | 0:27d35fa263b5 | 75 | CoreReg r11; |
va009039 | 0:27d35fa263b5 | 76 | CoreReg r12; |
va009039 | 0:27d35fa263b5 | 77 | CoreReg sp; |
va009039 | 0:27d35fa263b5 | 78 | CoreReg lr; |
va009039 | 0:27d35fa263b5 | 79 | CoreReg pc; |
va009039 | 0:27d35fa263b5 | 80 | CoreReg xpsr; |
va009039 | 3:d7a7cde0bfb8 | 81 | |
va009039 | 3:d7a7cde0bfb8 | 82 | uint32_t idcode; |
va009039 | 5:2774358f5e4f | 83 | protected: |
va009039 | 0:27d35fa263b5 | 84 | void _setaddr(uint32_t addr); |
va009039 | 1:eb30547ba84d | 85 | void _setaddr8(uint32_t addr); |
va009039 | 5:2774358f5e4f | 86 | void JTAG2SWD(); |
va009039 | 5:2774358f5e4f | 87 | |
va009039 | 0:27d35fa263b5 | 88 | SWD _swd; |
va009039 | 0:27d35fa263b5 | 89 | }; |