Norimasa Okamoto / STM32_IAP

IAP compatible.

Fork of IAP by Tedd OKANO

Import programSTM32_IAP_internal_flash_write

STM32_IAP demo.

Last commit 30 Apr 2016 by Norimasa Okamoto

Import programSTM32_IAP_test

STM32_IAP test

Last commit 01 May 2016 by Norimasa Okamoto

IAP_STM32F0.cpp@12:fd6a08b46228, 2016-04-30 (annotated)

Committer:
va009039
Date:
Sat Apr 30 03:32:33 2016 +0000
Revision:
12:fd6a08b46228
Parent:
9:7e19f12b81b4 
add STM32L0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
va009039 9:7e19f12b81b4 1 #if defined(TARGET_STM32F0)||defined(TARGET_STM32F1)
va009039 9:7e19f12b81b4 2 /** IAP : internal Flash memory access library
va009039 9:7e19f12b81b4 3 *
va009039 9:7e19f12b81b4 4 * The internal Flash memory access is described in the LPC1768 and LPC11U24 usermanual.
va009039 9:7e19f12b81b4 5 * http://www.nxp.com/documents/user_manual/UM10360.pdf
va009039 9:7e19f12b81b4 6 * http://www.nxp.com/documents/user_manual/UM10462.pdf
va009039 9:7e19f12b81b4 7 *
va009039 9:7e19f12b81b4 8 * LPC1768 --
va009039 9:7e19f12b81b4 9 * Chapter 2: "LPC17xx Memory map"
va009039 9:7e19f12b81b4 10 * Chapter 32: "LPC17xx Flash memory interface and programming"
va009039 9:7e19f12b81b4 11 * refering Rev. 01 - 4 January 2010
va009039 9:7e19f12b81b4 12 *
va009039 9:7e19f12b81b4 13 * LPC11U24 --
va009039 9:7e19f12b81b4 14 * Chapter 2: "LPC11Uxx Memory mapping"
va009039 9:7e19f12b81b4 15 * Chapter 20: "LPC11Uxx Flash programming firmware"
va009039 9:7e19f12b81b4 16 * refering Rev. 03 - 16 July 2012
va009039 9:7e19f12b81b4 17 *
va009039 9:7e19f12b81b4 18 * Released under the MIT License: http://mbed.org/license/mit
va009039 9:7e19f12b81b4 19 *
va009039 9:7e19f12b81b4 20 * revision 1.0 09-Mar-2010 1st release
va009039 9:7e19f12b81b4 21 * revision 1.1 12-Mar-2010 chaged: to make possible to reserve flash area for user
va009039 9:7e19f12b81b4 22 * it can be set by USER_FLASH_AREA_START and USER_FLASH_AREA_SIZE in IAP.h
va009039 9:7e19f12b81b4 23 * revision 2.0 26-Nov-2012 LPC11U24 code added
va009039 9:7e19f12b81b4 24 * revision 2.1 26-Nov-2012 EEPROM access code imported from Suga koubou san's (http://mbed.org/users/okini3939/) library
va009039 9:7e19f12b81b4 25 * http://mbed.org/users/okini3939/code/M0_EEPROM_test/
va009039 9:7e19f12b81b4 26 * revision 3.0 09-Jan-2015 LPC812 and LPC824 support added
va009039 9:7e19f12b81b4 27 * revision 3.1 13-Jan-2015 LPC1114 support added
va009039 9:7e19f12b81b4 28 * revision 3.1.1 16-Jan-2015 Target MCU name changed for better compatibility across the platforms
va009039 9:7e19f12b81b4 29 */
va009039 9:7e19f12b81b4 30
va009039 9:7e19f12b81b4 31 #include "mbed.h"
va009039 9:7e19f12b81b4 32 #include "IAP.h"
va009039 9:7e19f12b81b4 33
va009039 9:7e19f12b81b4 34 #define USER_FLASH_AREA_START_STR( x ) STR( x )
va009039 9:7e19f12b81b4 35 #define STR( x ) #x
va009039 9:7e19f12b81b4 36
va009039 9:7e19f12b81b4 37 //unsigned char user_area[ USER_FLASH_AREA_SIZE ] __attribute__((section( ".ARM.__at_" USER_FLASH_AREA_START_STR( USER_FLASH_AREA_START ) ), zero_init));
va009039 9:7e19f12b81b4 38
va009039 9:7e19f12b81b4 39 /*
va009039 9:7e19f12b81b4 40 * Reserve of flash area is explained by Igor. Please refer next URL
va009039 9:7e19f12b81b4 41 * http://mbed.org/users/okano/notebook/iap-in-application-programming-internal-flash-eras/?page=1#comment-271
va009039 9:7e19f12b81b4 42 */
va009039 9:7e19f12b81b4 43
va009039 9:7e19f12b81b4 44 //unsigned char user_area[ size ] __attribute__((section(".ARM.__at_0x78000"), zero_init));
va009039 9:7e19f12b81b4 45
va009039 9:7e19f12b81b4 46 /*
va009039 9:7e19f12b81b4 47 * IAP command codes
va009039 9:7e19f12b81b4 48 * Table 589. "IAP Command Summary", Chapter 8. "IAP commands", usermanual
va009039 9:7e19f12b81b4 49 */
va009039 9:7e19f12b81b4 50
va009039 9:7e19f12b81b4 51 enum command_code {
va009039 9:7e19f12b81b4 52 IAPCommand_Prepare_sector_for_write_operation = 50,
va009039 9:7e19f12b81b4 53 IAPCommand_Copy_RAM_to_Flash,
va009039 9:7e19f12b81b4 54 IAPCommand_Erase_sector,
va009039 9:7e19f12b81b4 55 IAPCommand_Blank_check_sector,
va009039 9:7e19f12b81b4 56 IAPCommand_Read_part_ID,
va009039 9:7e19f12b81b4 57 IAPCommand_Read_Boot_Code_version,
va009039 9:7e19f12b81b4 58 IAPCommand_Compare,
va009039 9:7e19f12b81b4 59 IAPCommand_Reinvoke_ISP,
va009039 9:7e19f12b81b4 60 IAPCommand_Read_device_serial_number,
va009039 9:7e19f12b81b4 61 #if defined(TARGET_LPC11UXX)
va009039 9:7e19f12b81b4 62 IAPCommand_EEPROM_Write = 61,
va009039 9:7e19f12b81b4 63 IAPCommand_EEPROM_Read,
va009039 9:7e19f12b81b4 64 #elif defined(TARGET_LPC81X) || defined(TARGET_LPC82X)
va009039 9:7e19f12b81b4 65 IAPCommand_Erase_page = 59,
va009039 9:7e19f12b81b4 66 #endif
va009039 9:7e19f12b81b4 67 };
va009039 9:7e19f12b81b4 68
va009039 9:7e19f12b81b4 69 int IAP::reinvoke_isp( void ) {
va009039 9:7e19f12b81b4 70 return INVALID_COMMAND;
va009039 9:7e19f12b81b4 71 }
va009039 9:7e19f12b81b4 72
va009039 9:7e19f12b81b4 73 /** Read part identification number
va009039 9:7e19f12b81b4 74 *
va009039 9:7e19f12b81b4 75 * @return device ID
va009039 9:7e19f12b81b4 76 * @see read_serial()
va009039 9:7e19f12b81b4 77 */
va009039 9:7e19f12b81b4 78 int IAP::read_ID( void )
va009039 9:7e19f12b81b4 79 {
va009039 9:7e19f12b81b4 80 IAP_result[1] = HAL_GetDEVID();
va009039 9:7e19f12b81b4 81 return ( (int)IAP_result[ 1 ] ); // to return the number itself (this command always returns CMD_SUCCESS)
va009039 9:7e19f12b81b4 82 }
va009039 9:7e19f12b81b4 83
va009039 9:7e19f12b81b4 84 #if defined(TARGET_STM32F0)
va009039 9:7e19f12b81b4 85 int *IAP::read_serial( void ) {
va009039 9:7e19f12b81b4 86 memcpy(&IAP_result[1], (void*)0x1ffff7ac, sizeof(uint32_t) * 3);
va009039 9:7e19f12b81b4 87 IAP_result[4] = 0;
va009039 9:7e19f12b81b4 88 return ( (int *)&IAP_result[ 1 ] ); // to return the number itself (this command always returns CMD_SUCCESS)
va009039 9:7e19f12b81b4 89 }
va009039 9:7e19f12b81b4 90
va009039 9:7e19f12b81b4 91 #elif defined(TARGET_STM32F1)
va009039 9:7e19f12b81b4 92 int *IAP::read_serial( void ) {
va009039 9:7e19f12b81b4 93 memset(&IAP_result[1], 0x00, sizeof(uint32_t) * 4);
va009039 9:7e19f12b81b4 94 return ( (int *)&IAP_result[ 1 ] ); // to return the number itself (this command always returns CMD_SUCCESS)
va009039 9:7e19f12b81b4 95 }
va009039 9:7e19f12b81b4 96
va009039 9:7e19f12b81b4 97 #endif
va009039 9:7e19f12b81b4 98
va009039 9:7e19f12b81b4 99 int IAP::blank_check( int start, int end )
va009039 9:7e19f12b81b4 100 {
va009039 9:7e19f12b81b4 101 if (!IS_FLASH_NB_PAGES(FLASH_BASE, start) || !IS_FLASH_NB_PAGES(FLASH_BASE, end)) {
va009039 9:7e19f12b81b4 102 return INVALID_SECTOR;
va009039 9:7e19f12b81b4 103 }
va009039 9:7e19f12b81b4 104 uint8_t* p = reinterpret_cast<uint8_t*>(FLASH_BASE + start * FLASH_PAGE_SIZE);
va009039 9:7e19f12b81b4 105 uint8_t* e = p + (end - start + 1) * FLASH_PAGE_SIZE;
va009039 9:7e19f12b81b4 106 while(p < e) {
va009039 9:7e19f12b81b4 107 if (*p++ != 0x00) {
va009039 9:7e19f12b81b4 108 return SECTOR_NOT_BLANK;
va009039 9:7e19f12b81b4 109 }
va009039 9:7e19f12b81b4 110 }
va009039 9:7e19f12b81b4 111 return CMD_SUCCESS;
va009039 9:7e19f12b81b4 112 }
va009039 9:7e19f12b81b4 113
va009039 9:7e19f12b81b4 114 struct FLASH_Unlock {
va009039 9:7e19f12b81b4 115 FLASH_Unlock() { HAL_FLASH_Unlock(); }
va009039 9:7e19f12b81b4 116 ~FLASH_Unlock() { HAL_FLASH_Lock(); }
va009039 9:7e19f12b81b4 117 };
va009039 9:7e19f12b81b4 118
va009039 9:7e19f12b81b4 119 int IAP::erase( int start, int end )
va009039 9:7e19f12b81b4 120 {
va009039 9:7e19f12b81b4 121 if (!IS_FLASH_NB_PAGES(FLASH_BASE, start) || !IS_FLASH_NB_PAGES(FLASH_BASE, end)) {
va009039 9:7e19f12b81b4 122 return INVALID_SECTOR;
va009039 9:7e19f12b81b4 123 }
va009039 9:7e19f12b81b4 124 FLASH_EraseInitTypeDef Erase;
va009039 9:7e19f12b81b4 125 Erase.TypeErase = FLASH_TYPEERASE_PAGES;
va009039 9:7e19f12b81b4 126 Erase.PageAddress = start * FLASH_PAGE_SIZE;
va009039 9:7e19f12b81b4 127 Erase.NbPages = end - start + 1;
va009039 9:7e19f12b81b4 128 uint32_t PageError = 0;
va009039 9:7e19f12b81b4 129 FLASH_Unlock unlock;
va009039 9:7e19f12b81b4 130 HAL_StatusTypeDef status = HAL_FLASHEx_Erase(&Erase, &PageError);
va009039 9:7e19f12b81b4 131 return status == HAL_OK ? CMD_SUCCESS : INVALID_COMMAND;
va009039 9:7e19f12b81b4 132 }
va009039 9:7e19f12b81b4 133
va009039 9:7e19f12b81b4 134 int IAP::prepare( int start, int end )
va009039 9:7e19f12b81b4 135 {
va009039 9:7e19f12b81b4 136 if (!IS_FLASH_NB_PAGES(FLASH_BASE, start) || !IS_FLASH_NB_PAGES(FLASH_BASE, end)) {
va009039 9:7e19f12b81b4 137 return INVALID_SECTOR;
va009039 9:7e19f12b81b4 138 }
va009039 9:7e19f12b81b4 139 return CMD_SUCCESS;
va009039 9:7e19f12b81b4 140 }
va009039 9:7e19f12b81b4 141
va009039 9:7e19f12b81b4 142 int IAP::write( char *source_addr, char *target_addr, int size )
va009039 9:7e19f12b81b4 143 {
va009039 12:fd6a08b46228 144 if (!IS_FLASH_PROGRAM_ADDRESS((uint32_t)target_addr) || !IS_FLASH_PROGRAM_ADDRESS((uint32_t)target_addr + size - 1)) {
va009039 9:7e19f12b81b4 145 return DST_ADDR_NOT_MAPPED;
va009039 9:7e19f12b81b4 146 }
va009039 9:7e19f12b81b4 147 uint32_t data;
va009039 9:7e19f12b81b4 148 FLASH_Unlock unlock;
va009039 9:7e19f12b81b4 149 for(int n = 0; n < size; n += sizeof(data)) {
va009039 9:7e19f12b81b4 150 memcpy(&data, source_addr + n, sizeof(data));
va009039 9:7e19f12b81b4 151 if (HAL_OK != HAL_FLASH_Program(TYPEPROGRAM_WORD, (uint32_t)target_addr + n, data)) {
va009039 9:7e19f12b81b4 152 return INVALID_COMMAND;
va009039 9:7e19f12b81b4 153 }
va009039 9:7e19f12b81b4 154 }
va009039 9:7e19f12b81b4 155 return CMD_SUCCESS;
va009039 9:7e19f12b81b4 156 }
va009039 9:7e19f12b81b4 157
va009039 9:7e19f12b81b4 158 int IAP::compare( char *source_addr, char *target_addr, int size )
va009039 9:7e19f12b81b4 159 {
va009039 9:7e19f12b81b4 160 return memcmp(source_addr, target_addr, size) == 0 ? CMD_SUCCESS : COMPARE_ERROR;
va009039 9:7e19f12b81b4 161 }
va009039 9:7e19f12b81b4 162
va009039 9:7e19f12b81b4 163 int IAP::read_BootVer(void)
va009039 9:7e19f12b81b4 164 {
va009039 9:7e19f12b81b4 165 // TODO
va009039 9:7e19f12b81b4 166 return 0;
va009039 9:7e19f12b81b4 167 }
va009039 9:7e19f12b81b4 168
va009039 9:7e19f12b81b4 169 char * IAP::reserved_flash_area_start( void )
va009039 9:7e19f12b81b4 170 {
va009039 9:7e19f12b81b4 171 // TODO
va009039 9:7e19f12b81b4 172 return NULL;
va009039 9:7e19f12b81b4 173 }
va009039 9:7e19f12b81b4 174
va009039 9:7e19f12b81b4 175 int IAP::reserved_flash_area_size( void )
va009039 9:7e19f12b81b4 176 {
va009039 9:7e19f12b81b4 177 // TODO
va009039 9:7e19f12b81b4 178 return 0;
va009039 9:7e19f12b81b4 179 }
va009039 9:7e19f12b81b4 180
va009039 9:7e19f12b81b4 181 #if defined(TARGET_LPC11UXX)
va009039 9:7e19f12b81b4 182
va009039 9:7e19f12b81b4 183 int IAP::write_eeprom( char *source_addr, char *target_addr, int size )
va009039 9:7e19f12b81b4 184 {
va009039 9:7e19f12b81b4 185 IAP_command[ 0 ] = IAPCommand_EEPROM_Write;
va009039 9:7e19f12b81b4 186 IAP_command[ 1 ] = (unsigned int)target_addr; // Destination EEPROM address where data bytes are to be written. This address should be a 256 byte boundary.
va009039 9:7e19f12b81b4 187 IAP_command[ 2 ] = (unsigned int)source_addr; // Source RAM address from which data bytes are to be read. This address should be a word boundary.
va009039 9:7e19f12b81b4 188 IAP_command[ 3 ] = size; // Number of bytes to be written. Should be 256 | 512 | 1024 | 4096.
va009039 9:7e19f12b81b4 189 IAP_command[ 4 ] = cclk_kHz; // CPU Clock Frequency (CCLK) in kHz.
va009039 9:7e19f12b81b4 190
va009039 9:7e19f12b81b4 191 iap_entry( IAP_command, IAP_result );
va009039 9:7e19f12b81b4 192
va009039 9:7e19f12b81b4 193 return ( (int)IAP_result[ 0 ] );
va009039 9:7e19f12b81b4 194 }
va009039 9:7e19f12b81b4 195
va009039 9:7e19f12b81b4 196 int IAP::read_eeprom( char *source_addr, char *target_addr, int size )
va009039 9:7e19f12b81b4 197 {
va009039 9:7e19f12b81b4 198 IAP_command[ 0 ] = IAPCommand_EEPROM_Read;
va009039 9:7e19f12b81b4 199 IAP_command[ 1 ] = (unsigned int)source_addr; // Source EEPROM address from which data bytes are to be read. This address should be a word boundary.
va009039 9:7e19f12b81b4 200 IAP_command[ 2 ] = (unsigned int)target_addr; // Destination RAM address where data bytes are to be written. This address should be a 256 byte boundary.
va009039 9:7e19f12b81b4 201 IAP_command[ 3 ] = size; // Number of bytes to be written. Should be 256 | 512 | 1024 | 4096.
va009039 9:7e19f12b81b4 202 IAP_command[ 4 ] = cclk_kHz; // CPU Clock Frequency (CCLK) in kHz.
va009039 9:7e19f12b81b4 203
va009039 9:7e19f12b81b4 204 iap_entry( IAP_command, IAP_result );
va009039 9:7e19f12b81b4 205
va009039 9:7e19f12b81b4 206 return ( (int)IAP_result[ 0 ] );
va009039 9:7e19f12b81b4 207 }
va009039 9:7e19f12b81b4 208
va009039 9:7e19f12b81b4 209 #elif defined(TARGET_LPC81X) || defined(TARGET_LPC82X)
va009039 9:7e19f12b81b4 210
va009039 9:7e19f12b81b4 211 int IAP::erase_page( int start, int end )
va009039 9:7e19f12b81b4 212 {
va009039 9:7e19f12b81b4 213 IAP_command[ 0 ] = IAPCommand_Erase_page;
va009039 9:7e19f12b81b4 214 IAP_command[ 1 ] = (unsigned int)start; // Start Sector Number
va009039 9:7e19f12b81b4 215 IAP_command[ 2 ] = (unsigned int)end; // End Sector Number (should be greater than or equal to start sector number)
va009039 9:7e19f12b81b4 216 IAP_command[ 3 ] = cclk_kHz; // CPU Clock Frequency (CCLK) in kHz
va009039 9:7e19f12b81b4 217
va009039 9:7e19f12b81b4 218 iap_entry( IAP_command, IAP_result );
va009039 9:7e19f12b81b4 219
va009039 9:7e19f12b81b4 220 return ( (int)IAP_result[ 0 ] );
va009039 9:7e19f12b81b4 221 }
va009039 9:7e19f12b81b4 222
va009039 9:7e19f12b81b4 223 #endif
va009039 9:7e19f12b81b4 224
va009039 9:7e19f12b81b4 225 #endif // TARGET_STM32F0, TARGET_STM32F1