Genadi Zawidowski / mbed-dev

mbed library sources. Supersedes mbed-src. Edited target satm32f446 for user USART3 pins

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Fork of mbed-dev by mbed official

targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c@179:b0033dcd6934, 2017-12-07 (annotated)

Committer:
AnnaBridge
Date:
Thu Dec 07 14:01:42 2017 +0000
Revision:
179:b0033dcd6934
Parent:
172:7d866c31b3c5
Child:
182:a56a73fd2a6f
mbed-dev library. Release version 157

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:7d866c31b3c5 1 /* mbed Microcontroller Library
AnnaBridge 172:7d866c31b3c5 2 * Copyright (c) 2015-2016 Nuvoton
AnnaBridge 172:7d866c31b3c5 3 *
AnnaBridge 172:7d866c31b3c5 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 172:7d866c31b3c5 5 * you may not use this file except in compliance with the License.
AnnaBridge 172:7d866c31b3c5 6 * You may obtain a copy of the License at
AnnaBridge 172:7d866c31b3c5 7 *
AnnaBridge 172:7d866c31b3c5 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 172:7d866c31b3c5 9 *
AnnaBridge 172:7d866c31b3c5 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 172:7d866c31b3c5 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 172:7d866c31b3c5 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 172:7d866c31b3c5 13 * See the License for the specific language governing permissions and
AnnaBridge 172:7d866c31b3c5 14 * limitations under the License.
AnnaBridge 172:7d866c31b3c5 15 */
AnnaBridge 172:7d866c31b3c5 16
AnnaBridge 172:7d866c31b3c5 17 #include "lp_ticker_api.h"
AnnaBridge 172:7d866c31b3c5 18
AnnaBridge 172:7d866c31b3c5 19 #if DEVICE_LOWPOWERTIMER
AnnaBridge 172:7d866c31b3c5 20
AnnaBridge 172:7d866c31b3c5 21 #include "sleep_api.h"
AnnaBridge 172:7d866c31b3c5 22 #include "nu_modutil.h"
AnnaBridge 172:7d866c31b3c5 23 #include "nu_miscutil.h"
AnnaBridge 172:7d866c31b3c5 24 #include "mbed_critical.h"
AnnaBridge 172:7d866c31b3c5 25
AnnaBridge 172:7d866c31b3c5 26 // lp_ticker tick = us = timestamp
AnnaBridge 172:7d866c31b3c5 27 #define US_PER_TICK (1)
AnnaBridge 172:7d866c31b3c5 28 #define US_PER_SEC (1000 * 1000)
AnnaBridge 172:7d866c31b3c5 29
AnnaBridge 172:7d866c31b3c5 30 #define US_PER_TMR2_INT (US_PER_SEC * 10)
AnnaBridge 172:7d866c31b3c5 31 #define TMR2_CLK_PER_SEC (__LXT)
AnnaBridge 172:7d866c31b3c5 32 #define TMR2_CLK_PER_TMR2_INT ((uint32_t) ((uint64_t) US_PER_TMR2_INT * TMR2_CLK_PER_SEC / US_PER_SEC))
AnnaBridge 172:7d866c31b3c5 33 #define TMR3_CLK_PER_SEC (__LXT)
AnnaBridge 172:7d866c31b3c5 34
AnnaBridge 172:7d866c31b3c5 35 static void tmr2_vec(void);
AnnaBridge 172:7d866c31b3c5 36 static void tmr3_vec(void);
AnnaBridge 172:7d866c31b3c5 37 static void lp_ticker_arm_cd(void);
AnnaBridge 172:7d866c31b3c5 38
AnnaBridge 172:7d866c31b3c5 39 static int lp_ticker_inited = 0;
AnnaBridge 172:7d866c31b3c5 40 static volatile uint32_t counter_major = 0;
AnnaBridge 172:7d866c31b3c5 41 static volatile uint32_t cd_major_minor_clks = 0;
AnnaBridge 172:7d866c31b3c5 42 static volatile uint32_t cd_minor_clks = 0;
AnnaBridge 172:7d866c31b3c5 43 static volatile uint32_t wakeup_tick = (uint32_t) -1;
AnnaBridge 172:7d866c31b3c5 44
AnnaBridge 172:7d866c31b3c5 45 // NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC.
AnnaBridge 172:7d866c31b3c5 46 // NOTE: TIMER_2 for normal counting and TIMER_3 for scheduled wakeup
AnnaBridge 172:7d866c31b3c5 47 static const struct nu_modinit_s timer2_modinit = {TIMER_2, TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_LXT, 0, TMR2_RST, TMR2_IRQn, (void *) tmr2_vec};
AnnaBridge 172:7d866c31b3c5 48 static const struct nu_modinit_s timer3_modinit = {TIMER_3, TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_LXT, 0, TMR3_RST, TMR3_IRQn, (void *) tmr3_vec};
AnnaBridge 172:7d866c31b3c5 49
AnnaBridge 172:7d866c31b3c5 50 #define TMR_CMP_MIN 2
AnnaBridge 172:7d866c31b3c5 51 #define TMR_CMP_MAX 0xFFFFFFu
AnnaBridge 172:7d866c31b3c5 52
AnnaBridge 172:7d866c31b3c5 53 void lp_ticker_init(void)
AnnaBridge 172:7d866c31b3c5 54 {
AnnaBridge 172:7d866c31b3c5 55 if (lp_ticker_inited) {
AnnaBridge 172:7d866c31b3c5 56 return;
AnnaBridge 172:7d866c31b3c5 57 }
AnnaBridge 172:7d866c31b3c5 58 lp_ticker_inited = 1;
AnnaBridge 172:7d866c31b3c5 59
AnnaBridge 172:7d866c31b3c5 60 counter_major = 0;
AnnaBridge 172:7d866c31b3c5 61 cd_major_minor_clks = 0;
AnnaBridge 172:7d866c31b3c5 62 cd_minor_clks = 0;
AnnaBridge 172:7d866c31b3c5 63 wakeup_tick = (uint32_t) -1;
AnnaBridge 172:7d866c31b3c5 64
AnnaBridge 172:7d866c31b3c5 65 // Reset module
AnnaBridge 172:7d866c31b3c5 66 SYS_ResetModule(timer2_modinit.rsetidx);
AnnaBridge 172:7d866c31b3c5 67 SYS_ResetModule(timer3_modinit.rsetidx);
AnnaBridge 172:7d866c31b3c5 68
AnnaBridge 172:7d866c31b3c5 69 // Select IP clock source
AnnaBridge 172:7d866c31b3c5 70 CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv);
AnnaBridge 172:7d866c31b3c5 71 CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv);
AnnaBridge 172:7d866c31b3c5 72 // Enable IP clock
AnnaBridge 172:7d866c31b3c5 73 CLK_EnableModuleClock(timer2_modinit.clkidx);
AnnaBridge 172:7d866c31b3c5 74 CLK_EnableModuleClock(timer3_modinit.clkidx);
AnnaBridge 172:7d866c31b3c5 75
AnnaBridge 172:7d866c31b3c5 76 // Configure clock
AnnaBridge 172:7d866c31b3c5 77 uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
AnnaBridge 172:7d866c31b3c5 78 uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_PER_SEC - 1;
AnnaBridge 172:7d866c31b3c5 79 MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127);
AnnaBridge 172:7d866c31b3c5 80 MBED_ASSERT((clk_timer2 % TMR2_CLK_PER_SEC) == 0);
AnnaBridge 172:7d866c31b3c5 81 uint32_t cmp_timer2 = TMR2_CLK_PER_TMR2_INT;
AnnaBridge 172:7d866c31b3c5 82 MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX);
AnnaBridge 172:7d866c31b3c5 83 // Continuous mode
AnnaBridge 172:7d866c31b3c5 84 // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default.
AnnaBridge 172:7d866c31b3c5 85 ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer2/* | TIMER_CTL_CNTDATEN_Msk*/;
AnnaBridge 172:7d866c31b3c5 86 ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMP = cmp_timer2;
AnnaBridge 172:7d866c31b3c5 87
AnnaBridge 172:7d866c31b3c5 88 // Set vector
AnnaBridge 172:7d866c31b3c5 89 NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var);
AnnaBridge 172:7d866c31b3c5 90 NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var);
AnnaBridge 172:7d866c31b3c5 91
AnnaBridge 172:7d866c31b3c5 92 NVIC_EnableIRQ(timer2_modinit.irq_n);
AnnaBridge 172:7d866c31b3c5 93 NVIC_EnableIRQ(timer3_modinit.irq_n);
AnnaBridge 172:7d866c31b3c5 94
AnnaBridge 172:7d866c31b3c5 95 TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
AnnaBridge 172:7d866c31b3c5 96 TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
AnnaBridge 172:7d866c31b3c5 97
AnnaBridge 172:7d866c31b3c5 98 // NOTE: TIMER_Start() first and then lp_ticker_set_interrupt(); otherwise, we may get stuck in lp_ticker_read() because
AnnaBridge 172:7d866c31b3c5 99 // timer is not running.
AnnaBridge 172:7d866c31b3c5 100
AnnaBridge 172:7d866c31b3c5 101 // Start timer
AnnaBridge 172:7d866c31b3c5 102 TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
AnnaBridge 172:7d866c31b3c5 103
AnnaBridge 172:7d866c31b3c5 104 // Schedule wakeup to match semantics of lp_ticker_get_compare_match()
AnnaBridge 172:7d866c31b3c5 105 lp_ticker_set_interrupt(wakeup_tick);
AnnaBridge 172:7d866c31b3c5 106 }
AnnaBridge 172:7d866c31b3c5 107
AnnaBridge 172:7d866c31b3c5 108 timestamp_t lp_ticker_read()
AnnaBridge 172:7d866c31b3c5 109 {
AnnaBridge 172:7d866c31b3c5 110 if (! lp_ticker_inited) {
AnnaBridge 172:7d866c31b3c5 111 lp_ticker_init();
AnnaBridge 172:7d866c31b3c5 112 }
AnnaBridge 172:7d866c31b3c5 113
AnnaBridge 172:7d866c31b3c5 114 TIMER_T * timer2_base = (TIMER_T *) NU_MODBASE(timer2_modinit.modname);
AnnaBridge 172:7d866c31b3c5 115
AnnaBridge 172:7d866c31b3c5 116 do {
AnnaBridge 172:7d866c31b3c5 117 uint64_t major_minor_clks;
AnnaBridge 172:7d866c31b3c5 118 uint32_t minor_clks;
AnnaBridge 172:7d866c31b3c5 119
AnnaBridge 172:7d866c31b3c5 120 // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
AnnaBridge 172:7d866c31b3c5 121 // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
AnnaBridge 172:7d866c31b3c5 122 do {
AnnaBridge 172:7d866c31b3c5 123 core_util_critical_section_enter();
AnnaBridge 172:7d866c31b3c5 124
AnnaBridge 172:7d866c31b3c5 125 // NOTE: Order of reading minor_us/carry here is significant.
AnnaBridge 172:7d866c31b3c5 126 minor_clks = TIMER_GetCounter(timer2_base);
AnnaBridge 172:7d866c31b3c5 127 uint32_t carry = (timer2_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
AnnaBridge 172:7d866c31b3c5 128 // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Handle carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
AnnaBridge 172:7d866c31b3c5 129 if (carry && minor_clks > (TMR2_CLK_PER_TMR2_INT / 2)) {
AnnaBridge 172:7d866c31b3c5 130 major_minor_clks = (counter_major + 1) * TMR2_CLK_PER_TMR2_INT;
AnnaBridge 172:7d866c31b3c5 131 } else {
AnnaBridge 172:7d866c31b3c5 132 major_minor_clks = (counter_major + carry) * TMR2_CLK_PER_TMR2_INT + minor_clks;
AnnaBridge 172:7d866c31b3c5 133 }
AnnaBridge 172:7d866c31b3c5 134
AnnaBridge 172:7d866c31b3c5 135 core_util_critical_section_exit();
AnnaBridge 172:7d866c31b3c5 136 } while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
AnnaBridge 172:7d866c31b3c5 137
AnnaBridge 172:7d866c31b3c5 138 // Add power-down compensation
AnnaBridge 172:7d866c31b3c5 139 return ((uint64_t) major_minor_clks * US_PER_SEC / TMR2_CLK_PER_SEC / US_PER_TICK);
AnnaBridge 172:7d866c31b3c5 140 } while (0);
AnnaBridge 172:7d866c31b3c5 141 }
AnnaBridge 172:7d866c31b3c5 142
AnnaBridge 172:7d866c31b3c5 143 void lp_ticker_set_interrupt(timestamp_t timestamp)
AnnaBridge 172:7d866c31b3c5 144 {
AnnaBridge 179:b0033dcd6934 145 uint32_t delta = timestamp - lp_ticker_read();
AnnaBridge 172:7d866c31b3c5 146 wakeup_tick = timestamp;
AnnaBridge 172:7d866c31b3c5 147
AnnaBridge 172:7d866c31b3c5 148 TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
AnnaBridge 172:7d866c31b3c5 149
AnnaBridge 179:b0033dcd6934 150 cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
AnnaBridge 179:b0033dcd6934 151 lp_ticker_arm_cd();
AnnaBridge 172:7d866c31b3c5 152 }
AnnaBridge 172:7d866c31b3c5 153
AnnaBridge 172:7d866c31b3c5 154 void lp_ticker_fire_interrupt(void)
AnnaBridge 172:7d866c31b3c5 155 {
AnnaBridge 172:7d866c31b3c5 156 // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here.
AnnaBridge 172:7d866c31b3c5 157 // This prevents a recursive loop under heavy load which can lead to a stack overflow.
AnnaBridge 172:7d866c31b3c5 158 cd_major_minor_clks = cd_minor_clks = 0;
AnnaBridge 172:7d866c31b3c5 159 NVIC_SetPendingIRQ(timer3_modinit.irq_n);
AnnaBridge 172:7d866c31b3c5 160 }
AnnaBridge 172:7d866c31b3c5 161
AnnaBridge 172:7d866c31b3c5 162 void lp_ticker_disable_interrupt(void)
AnnaBridge 172:7d866c31b3c5 163 {
AnnaBridge 172:7d866c31b3c5 164 TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
AnnaBridge 172:7d866c31b3c5 165 }
AnnaBridge 172:7d866c31b3c5 166
AnnaBridge 172:7d866c31b3c5 167 void lp_ticker_clear_interrupt(void)
AnnaBridge 172:7d866c31b3c5 168 {
AnnaBridge 172:7d866c31b3c5 169 TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
AnnaBridge 172:7d866c31b3c5 170 }
AnnaBridge 172:7d866c31b3c5 171
AnnaBridge 172:7d866c31b3c5 172 static void tmr2_vec(void)
AnnaBridge 172:7d866c31b3c5 173 {
AnnaBridge 172:7d866c31b3c5 174 TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
AnnaBridge 172:7d866c31b3c5 175 TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
AnnaBridge 172:7d866c31b3c5 176 counter_major ++;
AnnaBridge 172:7d866c31b3c5 177 }
AnnaBridge 172:7d866c31b3c5 178
AnnaBridge 172:7d866c31b3c5 179 static void tmr3_vec(void)
AnnaBridge 172:7d866c31b3c5 180 {
AnnaBridge 172:7d866c31b3c5 181 TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
AnnaBridge 172:7d866c31b3c5 182 TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
AnnaBridge 172:7d866c31b3c5 183 cd_major_minor_clks = (cd_major_minor_clks > cd_minor_clks) ? (cd_major_minor_clks - cd_minor_clks) : 0;
AnnaBridge 172:7d866c31b3c5 184 if (cd_major_minor_clks == 0) {
AnnaBridge 172:7d866c31b3c5 185 // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
AnnaBridge 172:7d866c31b3c5 186 lp_ticker_irq_handler();
AnnaBridge 172:7d866c31b3c5 187 } else {
AnnaBridge 172:7d866c31b3c5 188 lp_ticker_arm_cd();
AnnaBridge 172:7d866c31b3c5 189 }
AnnaBridge 172:7d866c31b3c5 190 }
AnnaBridge 172:7d866c31b3c5 191
AnnaBridge 172:7d866c31b3c5 192 static void lp_ticker_arm_cd(void)
AnnaBridge 172:7d866c31b3c5 193 {
AnnaBridge 172:7d866c31b3c5 194 TIMER_T * timer3_base = (TIMER_T *) NU_MODBASE(timer3_modinit.modname);
AnnaBridge 172:7d866c31b3c5 195
AnnaBridge 172:7d866c31b3c5 196 // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
AnnaBridge 172:7d866c31b3c5 197 // NUC472/M451: See TIMER_CTL_RSTCNT_Msk
AnnaBridge 172:7d866c31b3c5 198 // M480
AnnaBridge 172:7d866c31b3c5 199 timer3_base->CNT = 0;
AnnaBridge 172:7d866c31b3c5 200 while (timer3_base->CNT & TIMER_CNT_RSTACT_Msk);
AnnaBridge 172:7d866c31b3c5 201 // One-shot mode, Clock = 1 KHz
AnnaBridge 172:7d866c31b3c5 202 uint32_t clk_timer3 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
AnnaBridge 172:7d866c31b3c5 203 uint32_t prescale_timer3 = clk_timer3 / TMR3_CLK_PER_SEC - 1;
AnnaBridge 172:7d866c31b3c5 204 MBED_ASSERT((prescale_timer3 != (uint32_t) -1) && prescale_timer3 <= 127);
AnnaBridge 172:7d866c31b3c5 205 MBED_ASSERT((clk_timer3 % TMR3_CLK_PER_SEC) == 0);
AnnaBridge 172:7d866c31b3c5 206 // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default.
AnnaBridge 172:7d866c31b3c5 207 timer3_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/);
AnnaBridge 172:7d866c31b3c5 208 timer3_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer3/* | TIMER_CTL_CNTDATEN_Msk*/;
AnnaBridge 172:7d866c31b3c5 209
AnnaBridge 172:7d866c31b3c5 210 cd_minor_clks = cd_major_minor_clks;
AnnaBridge 172:7d866c31b3c5 211 cd_minor_clks = NU_CLAMP(cd_minor_clks, TMR_CMP_MIN, TMR_CMP_MAX);
AnnaBridge 172:7d866c31b3c5 212 timer3_base->CMP = cd_minor_clks;
AnnaBridge 172:7d866c31b3c5 213
AnnaBridge 172:7d866c31b3c5 214 TIMER_EnableInt(timer3_base);
AnnaBridge 172:7d866c31b3c5 215 TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
AnnaBridge 172:7d866c31b3c5 216 TIMER_Start(timer3_base);
AnnaBridge 172:7d866c31b3c5 217 }
AnnaBridge 172:7d866c31b3c5 218 #endif