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targets/TARGET_Maxim/TARGET_MAX32620C/mxc/lp.c@188:3f10722804f9, 2018-07-30 (annotated)

Committer:
ua1arn
Date:
Mon Jul 30 12:31:10 2018 +0000
Revision:
188:3f10722804f9
Parent:
186:707f6e361f3e 
before add multi-configuration USB descriptors

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 186:707f6e361f3e 1 /*******************************************************************************
Anna Bridge 186:707f6e361f3e 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
Anna Bridge 186:707f6e361f3e 3 *
Anna Bridge 186:707f6e361f3e 4 * Permission is hereby granted, free of charge, to any person obtaining a
Anna Bridge 186:707f6e361f3e 5 * copy of this software and associated documentation files (the "Software"),
Anna Bridge 186:707f6e361f3e 6 * to deal in the Software without restriction, including without limitation
Anna Bridge 186:707f6e361f3e 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
Anna Bridge 186:707f6e361f3e 8 * and/or sell copies of the Software, and to permit persons to whom the
Anna Bridge 186:707f6e361f3e 9 * Software is furnished to do so, subject to the following conditions:
Anna Bridge 186:707f6e361f3e 10 *
Anna Bridge 186:707f6e361f3e 11 * The above copyright notice and this permission notice shall be included
Anna Bridge 186:707f6e361f3e 12 * in all copies or substantial portions of the Software.
Anna Bridge 186:707f6e361f3e 13 *
Anna Bridge 186:707f6e361f3e 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Anna Bridge 186:707f6e361f3e 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Anna Bridge 186:707f6e361f3e 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Anna Bridge 186:707f6e361f3e 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Anna Bridge 186:707f6e361f3e 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Anna Bridge 186:707f6e361f3e 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Anna Bridge 186:707f6e361f3e 20 * OTHER DEALINGS IN THE SOFTWARE.
Anna Bridge 186:707f6e361f3e 21 *
Anna Bridge 186:707f6e361f3e 22 * Except as contained in this notice, the name of Maxim Integrated
Anna Bridge 186:707f6e361f3e 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
Anna Bridge 186:707f6e361f3e 24 * Products, Inc. Branding Policy.
Anna Bridge 186:707f6e361f3e 25 *
Anna Bridge 186:707f6e361f3e 26 * The mere transfer of this software does not imply any licenses
Anna Bridge 186:707f6e361f3e 27 * of trade secrets, proprietary technology, copyrights, patents,
Anna Bridge 186:707f6e361f3e 28 * trademarks, maskwork rights, or any other form of intellectual
Anna Bridge 186:707f6e361f3e 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
Anna Bridge 186:707f6e361f3e 30 * ownership rights.
Anna Bridge 186:707f6e361f3e 31 *
Anna Bridge 186:707f6e361f3e 32 * $Date: 2016-06-03 13:37:31 -0500 (Fri, 03 Jun 2016) $
Anna Bridge 186:707f6e361f3e 33 * $Revision: 23186 $
Anna Bridge 186:707f6e361f3e 34 * ******************************************************************************/
Anna Bridge 186:707f6e361f3e 35
Anna Bridge 186:707f6e361f3e 36 /***** Includes *****/
Anna Bridge 186:707f6e361f3e 37 #include "mxc_config.h"
Anna Bridge 186:707f6e361f3e 38 #include "mxc_assert.h"
Anna Bridge 186:707f6e361f3e 39 #include "lp.h"
Anna Bridge 186:707f6e361f3e 40 #include "ioman_regs.h"
Anna Bridge 186:707f6e361f3e 41 #include "uart_regs.h"
Anna Bridge 186:707f6e361f3e 42
Anna Bridge 186:707f6e361f3e 43 /***** Definitions *****/
Anna Bridge 186:707f6e361f3e 44
Anna Bridge 186:707f6e361f3e 45 #ifndef LP0_PRE_HOOK
Anna Bridge 186:707f6e361f3e 46 #define LP0_PRE_HOOK
Anna Bridge 186:707f6e361f3e 47 #endif
Anna Bridge 186:707f6e361f3e 48 #ifndef LP1_PRE_HOOK
Anna Bridge 186:707f6e361f3e 49 #define LP1_PRE_HOOK
Anna Bridge 186:707f6e361f3e 50 #endif
Anna Bridge 186:707f6e361f3e 51 #ifndef LP1_POST_HOOK
Anna Bridge 186:707f6e361f3e 52 #define LP1_POST_HOOK
Anna Bridge 186:707f6e361f3e 53 #endif
Anna Bridge 186:707f6e361f3e 54
Anna Bridge 186:707f6e361f3e 55 /***** Globals *****/
Anna Bridge 186:707f6e361f3e 56
Anna Bridge 186:707f6e361f3e 57 /***** Functions *****/
Anna Bridge 186:707f6e361f3e 58
Anna Bridge 186:707f6e361f3e 59 /* Clear all wake-up configuration */
Anna Bridge 186:707f6e361f3e 60 void LP_ClearWakeUpConfig(void)
Anna Bridge 186:707f6e361f3e 61 {
Anna Bridge 186:707f6e361f3e 62 /* Clear GPIO WUD event and configuration registers, globally */
Anna Bridge 186:707f6e361f3e 63 MXC_PWRSEQ->reg1 |= (MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH |
Anna Bridge 186:707f6e361f3e 64 MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
Anna Bridge 186:707f6e361f3e 65 MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH |
Anna Bridge 186:707f6e361f3e 66 MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
Anna Bridge 186:707f6e361f3e 67
Anna Bridge 186:707f6e361f3e 68 /* Mask off all wake-up sources */
Anna Bridge 186:707f6e361f3e 69 MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP |
Anna Bridge 186:707f6e361f3e 70 MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP |
Anna Bridge 186:707f6e361f3e 71 MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP |
Anna Bridge 186:707f6e361f3e 72 MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 |
Anna Bridge 186:707f6e361f3e 73 MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 |
Anna Bridge 186:707f6e361f3e 74 MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP |
Anna Bridge 186:707f6e361f3e 75 MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER);
Anna Bridge 186:707f6e361f3e 76 }
Anna Bridge 186:707f6e361f3e 77
Anna Bridge 186:707f6e361f3e 78 /* Clear wake-up flags */
Anna Bridge 186:707f6e361f3e 79 unsigned int LP_ClearWakeUpFlags(void)
Anna Bridge 186:707f6e361f3e 80 {
Anna Bridge 186:707f6e361f3e 81 unsigned int flags_tmp;
Anna Bridge 186:707f6e361f3e 82
Anna Bridge 186:707f6e361f3e 83 /* Get flags */
Anna Bridge 186:707f6e361f3e 84 flags_tmp = MXC_PWRSEQ->flags;
Anna Bridge 186:707f6e361f3e 85
Anna Bridge 186:707f6e361f3e 86 /* Clear GPIO WUD event registers, globally */
Anna Bridge 186:707f6e361f3e 87 MXC_PWRSEQ->reg1 |= (MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH);
Anna Bridge 186:707f6e361f3e 88 MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH);
Anna Bridge 186:707f6e361f3e 89
Anna Bridge 186:707f6e361f3e 90 /* Clear power sequencer event flags (write-1-to-clear) */
Anna Bridge 186:707f6e361f3e 91 MXC_PWRSEQ->flags = flags_tmp;
Anna Bridge 186:707f6e361f3e 92
Anna Bridge 186:707f6e361f3e 93 return flags_tmp;
Anna Bridge 186:707f6e361f3e 94 }
Anna Bridge 186:707f6e361f3e 95
Anna Bridge 186:707f6e361f3e 96 /* Configure the selected pin for wake-up detect */
Anna Bridge 186:707f6e361f3e 97 int LP_ConfigGPIOWakeUpDetect(const gpio_cfg_t *gpio, unsigned int act_high, lp_pu_pd_select_t wk_pu_pd)
Anna Bridge 186:707f6e361f3e 98 {
Anna Bridge 186:707f6e361f3e 99 int result = E_NO_ERROR;
Anna Bridge 186:707f6e361f3e 100 unsigned int pin;
Anna Bridge 186:707f6e361f3e 101
Anna Bridge 186:707f6e361f3e 102 /* Check that port and pin are within range */
Anna Bridge 186:707f6e361f3e 103 MXC_ASSERT(gpio->port < MXC_GPIO_NUM_PORTS);
Anna Bridge 186:707f6e361f3e 104 MXC_ASSERT(gpio->mask > 0);
Anna Bridge 186:707f6e361f3e 105
Anna Bridge 186:707f6e361f3e 106 /* Ports 0-3 are controlled by wud_req0, while 4-7 are controlled by wud_req1 */
Anna Bridge 186:707f6e361f3e 107 if (gpio->port < 4) {
Anna Bridge 186:707f6e361f3e 108 MXC_IOMAN->wud_req0 |= (gpio->mask << (gpio->port << 3));
Anna Bridge 186:707f6e361f3e 109 if (MXC_IOMAN->wud_ack0 != MXC_IOMAN->wud_req0) { /* Order of volatile access does not matter here */
Anna Bridge 186:707f6e361f3e 110 result = E_BUSY;
Anna Bridge 186:707f6e361f3e 111 }
Anna Bridge 186:707f6e361f3e 112 } else if (gpio->port < 8) {
Anna Bridge 186:707f6e361f3e 113 MXC_IOMAN->wud_req1 |= (gpio->mask << ((gpio->port - 4) << 3));
Anna Bridge 186:707f6e361f3e 114 if (MXC_IOMAN->wud_ack1 != MXC_IOMAN->wud_req1) { /* Order of volatile access does not matter here */
Anna Bridge 186:707f6e361f3e 115 result = E_BUSY;
Anna Bridge 186:707f6e361f3e 116 }
Anna Bridge 186:707f6e361f3e 117 } else {
Anna Bridge 186:707f6e361f3e 118 return E_NOT_SUPPORTED;
Anna Bridge 186:707f6e361f3e 119 }
Anna Bridge 186:707f6e361f3e 120
Anna Bridge 186:707f6e361f3e 121 if (result == E_NO_ERROR) {
Anna Bridge 186:707f6e361f3e 122
Anna Bridge 186:707f6e361f3e 123 for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
Anna Bridge 186:707f6e361f3e 124
Anna Bridge 186:707f6e361f3e 125 if (gpio->mask & (1 << pin)) {
Anna Bridge 186:707f6e361f3e 126
Anna Bridge 186:707f6e361f3e 127 /* Enable modifications to WUD configuration */
Anna Bridge 186:707f6e361f3e 128 MXC_PWRMAN->wud_ctrl = MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE;
Anna Bridge 186:707f6e361f3e 129
Anna Bridge 186:707f6e361f3e 130 /* Select pad in WUD control */
Anna Bridge 186:707f6e361f3e 131 /* Note: Pads are numbered from 0-48; {0-7} => {P0.0-P0.7}, {8-15} => {P1.0-P1.7}, etc. */
Anna Bridge 186:707f6e361f3e 132 MXC_PWRMAN->wud_ctrl |= (gpio->port * 8) + pin;
Anna Bridge 186:707f6e361f3e 133
Anna Bridge 186:707f6e361f3e 134 /* Configure sense level on this pad */
Anna Bridge 186:707f6e361f3e 135 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
Anna Bridge 186:707f6e361f3e 136
Anna Bridge 186:707f6e361f3e 137 if (act_high) {
Anna Bridge 186:707f6e361f3e 138 /* Select active high with PULSE0 (backwards from what you'd expect) */
Anna Bridge 186:707f6e361f3e 139 MXC_PWRMAN->wud_pulse0 = 1;
Anna Bridge 186:707f6e361f3e 140 } else {
Anna Bridge 186:707f6e361f3e 141 /* Select active low with PULSE1 (backwards from what you'd expect) */
Anna Bridge 186:707f6e361f3e 142 MXC_PWRMAN->wud_pulse1 = 1;
Anna Bridge 186:707f6e361f3e 143 }
Anna Bridge 186:707f6e361f3e 144
Anna Bridge 186:707f6e361f3e 145 /* Clear out the pad mode */
Anna Bridge 186:707f6e361f3e 146 MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
Anna Bridge 186:707f6e361f3e 147
Anna Bridge 186:707f6e361f3e 148 /* Select this pad to have the wake-up function enabled */
Anna Bridge 186:707f6e361f3e 149 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
Anna Bridge 186:707f6e361f3e 150
Anna Bridge 186:707f6e361f3e 151 /* Activate with PULSE1 */
Anna Bridge 186:707f6e361f3e 152 MXC_PWRMAN->wud_pulse1 = 1;
Anna Bridge 186:707f6e361f3e 153
Anna Bridge 186:707f6e361f3e 154 if (wk_pu_pd != LP_NO_PULL) {
Anna Bridge 186:707f6e361f3e 155 /* Select weak pull-up/pull-down on this pad while in LP1 */
Anna Bridge 186:707f6e361f3e 156 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
Anna Bridge 186:707f6e361f3e 157
Anna Bridge 186:707f6e361f3e 158 /* Again, logic is opposite of what you'd expect */
Anna Bridge 186:707f6e361f3e 159 if (wk_pu_pd == LP_WEAK_PULL_UP) {
Anna Bridge 186:707f6e361f3e 160 MXC_PWRMAN->wud_pulse0 = 1;
Anna Bridge 186:707f6e361f3e 161 } else {
Anna Bridge 186:707f6e361f3e 162 MXC_PWRMAN->wud_pulse1 = 1;
Anna Bridge 186:707f6e361f3e 163 }
Anna Bridge 186:707f6e361f3e 164 }
Anna Bridge 186:707f6e361f3e 165
Anna Bridge 186:707f6e361f3e 166 /* Disable configuration each time, required by hardware */
Anna Bridge 186:707f6e361f3e 167 MXC_PWRMAN->wud_ctrl = 0;
Anna Bridge 186:707f6e361f3e 168 }
Anna Bridge 186:707f6e361f3e 169 }
Anna Bridge 186:707f6e361f3e 170 }
Anna Bridge 186:707f6e361f3e 171
Anna Bridge 186:707f6e361f3e 172 /* Disable configuration */
Anna Bridge 186:707f6e361f3e 173 MXC_IOMAN->wud_req0 = 0;
Anna Bridge 186:707f6e361f3e 174 MXC_IOMAN->wud_req1 = 0;
Anna Bridge 186:707f6e361f3e 175
Anna Bridge 186:707f6e361f3e 176 /* Enable IOWakeup, as there is at least 1 GPIO pin configured as a wake source */
Anna Bridge 186:707f6e361f3e 177 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP;
Anna Bridge 186:707f6e361f3e 178
Anna Bridge 186:707f6e361f3e 179 return result;
Anna Bridge 186:707f6e361f3e 180 }
Anna Bridge 186:707f6e361f3e 181
Anna Bridge 186:707f6e361f3e 182 int LP_IsGPIOWakeUpSource(const gpio_cfg_t *gpio)
Anna Bridge 186:707f6e361f3e 183 {
Anna Bridge 186:707f6e361f3e 184 uint8_t gpioWokeUp = 0;
Anna Bridge 186:707f6e361f3e 185
Anna Bridge 186:707f6e361f3e 186 /* Check that port and pin are within range */
Anna Bridge 186:707f6e361f3e 187 MXC_ASSERT(gpio->port < MXC_GPIO_NUM_PORTS);
Anna Bridge 186:707f6e361f3e 188 MXC_ASSERT(gpio->mask > 0);
Anna Bridge 186:707f6e361f3e 189
Anna Bridge 186:707f6e361f3e 190 /* Ports 0-3 are wud_seen0, while 4-7 are wud_seen1*/
Anna Bridge 186:707f6e361f3e 191 if (gpio->port < 4) {
Anna Bridge 186:707f6e361f3e 192 gpioWokeUp = (MXC_PWRMAN->wud_seen0 >> (gpio->port << 3)) & gpio->mask;
Anna Bridge 186:707f6e361f3e 193 } else if (gpio->port < 8) {
Anna Bridge 186:707f6e361f3e 194 gpioWokeUp = (MXC_PWRMAN->wud_seen1 >> ((gpio->port - 4) << 3)) & gpio->mask;
Anna Bridge 186:707f6e361f3e 195 } else {
Anna Bridge 186:707f6e361f3e 196 return E_NOT_SUPPORTED;
Anna Bridge 186:707f6e361f3e 197 }
Anna Bridge 186:707f6e361f3e 198
Anna Bridge 186:707f6e361f3e 199 return gpioWokeUp;
Anna Bridge 186:707f6e361f3e 200 }
Anna Bridge 186:707f6e361f3e 201
Anna Bridge 186:707f6e361f3e 202 int LP_ClearGPIOWakeUpDetect(const gpio_cfg_t *gpio)
Anna Bridge 186:707f6e361f3e 203 {
Anna Bridge 186:707f6e361f3e 204 int result = E_NO_ERROR;
Anna Bridge 186:707f6e361f3e 205 unsigned int pin;
Anna Bridge 186:707f6e361f3e 206
Anna Bridge 186:707f6e361f3e 207 /* Check that port and pin are within range */
Anna Bridge 186:707f6e361f3e 208 MXC_ASSERT(gpio->port < MXC_GPIO_NUM_PORTS);
Anna Bridge 186:707f6e361f3e 209 MXC_ASSERT(gpio->mask > 0);
Anna Bridge 186:707f6e361f3e 210
Anna Bridge 186:707f6e361f3e 211 /* Ports 0-3 are controlled by wud_req0, while 4-7 are controlled by wud_req1*/
Anna Bridge 186:707f6e361f3e 212 if (gpio->port < 4) {
Anna Bridge 186:707f6e361f3e 213 MXC_IOMAN->wud_req0 |= (gpio->mask << (gpio->port << 3));
Anna Bridge 186:707f6e361f3e 214 if (MXC_IOMAN->wud_ack0 != MXC_IOMAN->wud_req0) { /* Order of volatile access does not matter here */
Anna Bridge 186:707f6e361f3e 215 result = E_BUSY;
Anna Bridge 186:707f6e361f3e 216 }
Anna Bridge 186:707f6e361f3e 217 } else if (gpio->port < 8) {
Anna Bridge 186:707f6e361f3e 218 MXC_IOMAN->wud_req1 |= (gpio->mask << ((gpio->port - 4) << 3));
Anna Bridge 186:707f6e361f3e 219 if (MXC_IOMAN->wud_ack1 != MXC_IOMAN->wud_req1) { /* Order of volatile access does not matter here */
Anna Bridge 186:707f6e361f3e 220 result = E_BUSY;
Anna Bridge 186:707f6e361f3e 221 }
Anna Bridge 186:707f6e361f3e 222 } else {
Anna Bridge 186:707f6e361f3e 223 return E_NOT_SUPPORTED;
Anna Bridge 186:707f6e361f3e 224 }
Anna Bridge 186:707f6e361f3e 225
Anna Bridge 186:707f6e361f3e 226 if (result == E_NO_ERROR) {
Anna Bridge 186:707f6e361f3e 227 for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
Anna Bridge 186:707f6e361f3e 228 if (gpio->mask & (1 << pin)) {
Anna Bridge 186:707f6e361f3e 229
Anna Bridge 186:707f6e361f3e 230 /* Enable modifications to WUD configuration */
Anna Bridge 186:707f6e361f3e 231 MXC_PWRMAN->wud_ctrl = MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE;
Anna Bridge 186:707f6e361f3e 232
Anna Bridge 186:707f6e361f3e 233 /* Select pad in WUD control */
Anna Bridge 186:707f6e361f3e 234 /* Note: Pads are numbered from 0-48; {0-7} => {P0.0-P0.7}, {8-15} => {P1.0-P1.7}, etc. */
Anna Bridge 186:707f6e361f3e 235 MXC_PWRMAN->wud_ctrl |= (gpio->port * 8) + pin;
Anna Bridge 186:707f6e361f3e 236
Anna Bridge 186:707f6e361f3e 237 /* Clear out the pad mode */
Anna Bridge 186:707f6e361f3e 238 MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
Anna Bridge 186:707f6e361f3e 239
Anna Bridge 186:707f6e361f3e 240 /* Select the wake up function on this pad */
Anna Bridge 186:707f6e361f3e 241 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
Anna Bridge 186:707f6e361f3e 242
Anna Bridge 186:707f6e361f3e 243 /* disable wake up with PULSE0 */
Anna Bridge 186:707f6e361f3e 244 MXC_PWRMAN->wud_pulse0 = 1;
Anna Bridge 186:707f6e361f3e 245
Anna Bridge 186:707f6e361f3e 246 /* Disable configuration each time, required by hardware */
Anna Bridge 186:707f6e361f3e 247 MXC_PWRMAN->wud_ctrl = 0;
Anna Bridge 186:707f6e361f3e 248 }
Anna Bridge 186:707f6e361f3e 249 }
Anna Bridge 186:707f6e361f3e 250 }
Anna Bridge 186:707f6e361f3e 251
Anna Bridge 186:707f6e361f3e 252 /* Disable configuration */
Anna Bridge 186:707f6e361f3e 253 MXC_IOMAN->wud_req0 = 0;
Anna Bridge 186:707f6e361f3e 254 MXC_IOMAN->wud_req1 = 0;
Anna Bridge 186:707f6e361f3e 255
Anna Bridge 186:707f6e361f3e 256 return result;
Anna Bridge 186:707f6e361f3e 257 }
Anna Bridge 186:707f6e361f3e 258
Anna Bridge 186:707f6e361f3e 259 int LP_ConfigUSBWakeUp(unsigned int plug_en, unsigned int unplug_en)
Anna Bridge 186:707f6e361f3e 260 {
Anna Bridge 186:707f6e361f3e 261 /* Enable or disable wake on USB plug-in */
Anna Bridge 186:707f6e361f3e 262 if (plug_en) {
Anna Bridge 186:707f6e361f3e 263 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP;
Anna Bridge 186:707f6e361f3e 264 } else {
Anna Bridge 186:707f6e361f3e 265 MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP);
Anna Bridge 186:707f6e361f3e 266 }
Anna Bridge 186:707f6e361f3e 267
Anna Bridge 186:707f6e361f3e 268 /* Enable or disable wake on USB unplug */
Anna Bridge 186:707f6e361f3e 269 if (unplug_en) {
Anna Bridge 186:707f6e361f3e 270 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP;
Anna Bridge 186:707f6e361f3e 271 } else {
Anna Bridge 186:707f6e361f3e 272 MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP);
Anna Bridge 186:707f6e361f3e 273 }
Anna Bridge 186:707f6e361f3e 274
Anna Bridge 186:707f6e361f3e 275 return E_NO_ERROR;
Anna Bridge 186:707f6e361f3e 276 }
Anna Bridge 186:707f6e361f3e 277
Anna Bridge 186:707f6e361f3e 278 int LP_ConfigRTCWakeUp(unsigned int comp0_en, unsigned int comp1_en,
Anna Bridge 186:707f6e361f3e 279 unsigned int prescale_cmp_en, unsigned int rollover_en)
Anna Bridge 186:707f6e361f3e 280 {
Anna Bridge 186:707f6e361f3e 281 /* Note: MXC_PWRSEQ.pwr_misc[0] should be set to have the mask be active low */
Anna Bridge 186:707f6e361f3e 282
Anna Bridge 186:707f6e361f3e 283 /* Enable or disable wake on RTC Compare 0 */
Anna Bridge 186:707f6e361f3e 284 if (comp0_en) {
Anna Bridge 186:707f6e361f3e 285 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_FLAGS_RTC_CMPR0;
Anna Bridge 186:707f6e361f3e 286
Anna Bridge 186:707f6e361f3e 287 } else {
Anna Bridge 186:707f6e361f3e 288 MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_FLAGS_RTC_CMPR0);
Anna Bridge 186:707f6e361f3e 289 }
Anna Bridge 186:707f6e361f3e 290
Anna Bridge 186:707f6e361f3e 291 /* Enable or disable wake on RTC Compare 1 */
Anna Bridge 186:707f6e361f3e 292 if (comp1_en) {
Anna Bridge 186:707f6e361f3e 293 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_FLAGS_RTC_CMPR1;
Anna Bridge 186:707f6e361f3e 294
Anna Bridge 186:707f6e361f3e 295 } else {
Anna Bridge 186:707f6e361f3e 296 MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_FLAGS_RTC_CMPR1);
Anna Bridge 186:707f6e361f3e 297 }
Anna Bridge 186:707f6e361f3e 298
Anna Bridge 186:707f6e361f3e 299 /* Enable or disable wake on RTC Prescaler */
Anna Bridge 186:707f6e361f3e 300 if (prescale_cmp_en) {
Anna Bridge 186:707f6e361f3e 301 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP;
Anna Bridge 186:707f6e361f3e 302
Anna Bridge 186:707f6e361f3e 303 } else {
Anna Bridge 186:707f6e361f3e 304 MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP);
Anna Bridge 186:707f6e361f3e 305 }
Anna Bridge 186:707f6e361f3e 306
Anna Bridge 186:707f6e361f3e 307 /* Enable or disable wake on RTC Rollover */
Anna Bridge 186:707f6e361f3e 308 if (rollover_en) {
Anna Bridge 186:707f6e361f3e 309 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER;
Anna Bridge 186:707f6e361f3e 310
Anna Bridge 186:707f6e361f3e 311 } else {
Anna Bridge 186:707f6e361f3e 312 MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER);
Anna Bridge 186:707f6e361f3e 313 }
Anna Bridge 186:707f6e361f3e 314
Anna Bridge 186:707f6e361f3e 315 return E_NO_ERROR;
Anna Bridge 186:707f6e361f3e 316 }
Anna Bridge 186:707f6e361f3e 317
Anna Bridge 186:707f6e361f3e 318
Anna Bridge 186:707f6e361f3e 319 int LP_EnterLP2(void)
Anna Bridge 186:707f6e361f3e 320 {
Anna Bridge 186:707f6e361f3e 321 /* Clear SLEEPDEEP bit to avoid LP1/LP0 entry*/
Anna Bridge 186:707f6e361f3e 322 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
Anna Bridge 186:707f6e361f3e 323
Anna Bridge 186:707f6e361f3e 324 /* Go into LP2 mode and wait for an interrupt to wake the processor */
Anna Bridge 186:707f6e361f3e 325 __WFI();
Anna Bridge 186:707f6e361f3e 326
Anna Bridge 186:707f6e361f3e 327 return E_NO_ERROR;
Anna Bridge 186:707f6e361f3e 328 }
Anna Bridge 186:707f6e361f3e 329
Anna Bridge 186:707f6e361f3e 330 int LP_EnterLP1(void)
Anna Bridge 186:707f6e361f3e 331 {
Anna Bridge 186:707f6e361f3e 332 /* Turn on retention controller */
Anna Bridge 186:707f6e361f3e 333 MXC_PWRSEQ->retn_ctrl0 |= MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN;
Anna Bridge 186:707f6e361f3e 334
Anna Bridge 186:707f6e361f3e 335 /* Clear the firstboot bit, which is generated by a POR event and locks out LPx modes */
Anna Bridge 186:707f6e361f3e 336 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT);
Anna Bridge 186:707f6e361f3e 337
Anna Bridge 186:707f6e361f3e 338 /* Set the LP1 select bit so CPU goes to LP1 during SLEEPDEEP */
Anna Bridge 186:707f6e361f3e 339 MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_LP1;
Anna Bridge 186:707f6e361f3e 340
Anna Bridge 186:707f6e361f3e 341 /* The SLEEPDEEP bit will cause a WFE() to trigger LP0/LP1 (depending on ..._REG0_PWR_LP1 state) */
Anna Bridge 186:707f6e361f3e 342 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
Anna Bridge 186:707f6e361f3e 343
Anna Bridge 186:707f6e361f3e 344 /* Performance-measurement hook, may be defined as nothing */
Anna Bridge 186:707f6e361f3e 345 LP1_PRE_HOOK;
Anna Bridge 186:707f6e361f3e 346
Anna Bridge 186:707f6e361f3e 347 /* Dummy read to make sure SSB writes are complete */
Anna Bridge 186:707f6e361f3e 348 MXC_PWRSEQ->reg0;
Anna Bridge 186:707f6e361f3e 349
Anna Bridge 186:707f6e361f3e 350 /* Enter LP1 -- sequence is per instructions from ARM, Ltd. */
Anna Bridge 186:707f6e361f3e 351 __SEV();
Anna Bridge 186:707f6e361f3e 352 __WFE();
Anna Bridge 186:707f6e361f3e 353 __WFE();
Anna Bridge 186:707f6e361f3e 354
Anna Bridge 186:707f6e361f3e 355 /* Performance-measurement hook, may be defined as nothing */
Anna Bridge 186:707f6e361f3e 356 LP1_POST_HOOK;
Anna Bridge 186:707f6e361f3e 357
Anna Bridge 186:707f6e361f3e 358 /* Clear SLEEPDEEP bit */
Anna Bridge 186:707f6e361f3e 359 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
Anna Bridge 186:707f6e361f3e 360
Anna Bridge 186:707f6e361f3e 361 /* No error */
Anna Bridge 186:707f6e361f3e 362 return E_NO_ERROR;
Anna Bridge 186:707f6e361f3e 363 }
Anna Bridge 186:707f6e361f3e 364
Anna Bridge 186:707f6e361f3e 365 void LP_EnterLP0(void)
Anna Bridge 186:707f6e361f3e 366 {
Anna Bridge 186:707f6e361f3e 367 /* Turn off Auto GPIO Freeze/UnFreeze in sleep modes */
Anna Bridge 186:707f6e361f3e 368 MXC_PWRSEQ->reg1 &= ~MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE;
Anna Bridge 186:707f6e361f3e 369
Anna Bridge 186:707f6e361f3e 370 /* Disable interrupts, ok not to save state as exit LP0 is a reset */
Anna Bridge 186:707f6e361f3e 371 __disable_irq();
Anna Bridge 186:707f6e361f3e 372
Anna Bridge 186:707f6e361f3e 373 /* Clear the firstboot bit, which is generated by a POR event and locks out LPx modes */
Anna Bridge 186:707f6e361f3e 374 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT);
Anna Bridge 186:707f6e361f3e 375
Anna Bridge 186:707f6e361f3e 376 /* Turn off retention controller */
Anna Bridge 186:707f6e361f3e 377 MXC_PWRSEQ->retn_ctrl0 &= ~(MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN);
Anna Bridge 186:707f6e361f3e 378
Anna Bridge 186:707f6e361f3e 379 /* Turn off retention regulator */
Anna Bridge 186:707f6e361f3e 380 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP);
Anna Bridge 186:707f6e361f3e 381
Anna Bridge 186:707f6e361f3e 382 /* LP0 ONLY to eliminate ~50nA of leakage on VDD12 */
Anna Bridge 186:707f6e361f3e 383 MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW;
Anna Bridge 186:707f6e361f3e 384
Anna Bridge 186:707f6e361f3e 385 /* Clear the LP1 select bit so CPU goes to LP0 during SLEEPDEEP */
Anna Bridge 186:707f6e361f3e 386 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_LP1);
Anna Bridge 186:707f6e361f3e 387
Anna Bridge 186:707f6e361f3e 388 /* The SLEEPDEEP bit will cause a WFE() to trigger LP0/LP1 (depending on ..._REG0_PWR_LP1 state) */
Anna Bridge 186:707f6e361f3e 389 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
Anna Bridge 186:707f6e361f3e 390
Anna Bridge 186:707f6e361f3e 391 /* Performance-measurement hook, may be defined as nothing */
Anna Bridge 186:707f6e361f3e 392 LP0_PRE_HOOK;
Anna Bridge 186:707f6e361f3e 393
Anna Bridge 186:707f6e361f3e 394 /* Freeze GPIO using MBUS so that it doesn't change while digital core is alseep */
Anna Bridge 186:707f6e361f3e 395 MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE;
Anna Bridge 186:707f6e361f3e 396
Anna Bridge 186:707f6e361f3e 397 /* Dummy read to make sure SSB writes are complete */
Anna Bridge 186:707f6e361f3e 398 MXC_PWRSEQ->reg0;
Anna Bridge 186:707f6e361f3e 399
Anna Bridge 186:707f6e361f3e 400 /* Go into LP0 -- sequence is per instructions from ARM, Ltd. */
Anna Bridge 186:707f6e361f3e 401 __SEV();
Anna Bridge 186:707f6e361f3e 402 __WFE();
Anna Bridge 186:707f6e361f3e 403 __WFE();
Anna Bridge 186:707f6e361f3e 404
Anna Bridge 186:707f6e361f3e 405 /* Catch the case where this code does not properly sleep */
Anna Bridge 186:707f6e361f3e 406 /* Unfreeze the GPIO by clearing MBUS_GATE (always safe to do) */
Anna Bridge 186:707f6e361f3e 407 MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE);
Anna Bridge 186:707f6e361f3e 408 MXC_ASSERT_FAIL();
Anna Bridge 186:707f6e361f3e 409 while (1) {
Anna Bridge 186:707f6e361f3e 410 __NOP();
Anna Bridge 186:707f6e361f3e 411 }
Anna Bridge 186:707f6e361f3e 412
Anna Bridge 186:707f6e361f3e 413 /* Does not actually return */
Anna Bridge 186:707f6e361f3e 414 }