Diff: STM32_FMC.cpp

Revision:

20:4b2a3c310b61

Parent:

19:8b7595ced647

--- a/STM32_FMC.cpp	Tue Jul 24 23:24:53 2018 +0000
+++ b/STM32_FMC.cpp	Mon Jul 30 12:31:40 2018 +0000
@@ -5,9 +5,10 @@
 #include "platform/platform.h"
 #include "hal/pinmap.h"
 
+#define BLD446 1
 
 
-#define SDRAM_TIMEOUT     ((uint32_t)0xFFFF) 
+#define SDRAM_TIMEOUT     ((uint32_t)0xFFFF)
 
 #define SDRAM_MODEREG_BURST_LENGTH_1             ((uint16_t)0x0000)
 #define SDRAM_MODEREG_BURST_LENGTH_2             ((uint16_t)0x0001)
@@ -18,8 +19,8 @@
 #define SDRAM_MODEREG_CAS_LATENCY_2              ((uint16_t)0x0020)
 #define SDRAM_MODEREG_CAS_LATENCY_3              ((uint16_t)0x0030)
 #define SDRAM_MODEREG_OPERATING_MODE_STANDARD    ((uint16_t)0x0000)
-#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) 
-#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     ((uint16_t)0x0200) 
+#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     ((uint16_t)0x0200)
 
 #define REFRESH_COUNT       ((uint32_t)0x056A)   /* SDRAM refresh counter (90MHz SDRAM clock) */
 
@@ -29,38 +30,46 @@
   * @param  Command: Pointer to SDRAM command structure
   * @retval None
   */
-static void SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command)
+static void SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram)
 {
-    __IO uint32_t tmpmrd =0;
+    FMC_SDRAM_CommandTypeDef Command = { 0 };
+#if BLD446
+    unsigned CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1_2;
+#else
+    unsigned CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;  // 429
+#endif
+    uint32_t tmpmrd = 0;
     /* Step 3:  Configure a clock configuration enable command */
-    Command->CommandMode           = FMC_SDRAM_CMD_CLK_ENABLE;
-    Command->CommandTarget         = FMC_SDRAM_CMD_TARGET_BANK1_2;
-    Command->AutoRefreshNumber     = 1;
-    Command->ModeRegisterDefinition = 0;
+    Command.CommandMode           = FMC_SDRAM_CMD_CLK_ENABLE;
+    Command.CommandTarget         = CommandTarget;
+    Command.AutoRefreshNumber     = 1;
+    Command.ModeRegisterDefinition = 0;
 
     /* Send the command */
-    HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
+    HAL_SDRAM_SendCommand(hsdram, &Command, 0x1000);
 
     /* Step 4: Insert 100 ms delay */
     wait((float)0.1);
 
     /* Step 5: Configure a PALL (precharge all) command */
-    Command->CommandMode           = FMC_SDRAM_CMD_PALL;
-    Command->CommandTarget         = FMC_SDRAM_CMD_TARGET_BANK1_2;
-    Command->AutoRefreshNumber     = 1;
-    Command->ModeRegisterDefinition = 0;
+    Command.CommandMode           = FMC_SDRAM_CMD_PALL;
+    Command.CommandTarget         = CommandTarget;
+    Command.AutoRefreshNumber     = 1;
+    Command.ModeRegisterDefinition = 0;
 
     /* Send the command */
-    HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
+    HAL_SDRAM_SendCommand(hsdram, &Command, 0x1000);
+    wait((float)0.1);
 
     /* Step 6 : Configure a Auto-Refresh command */
-    Command->CommandMode           = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
-    Command->CommandTarget         = FMC_SDRAM_CMD_TARGET_BANK1_2;
-    Command->AutoRefreshNumber     = 4;
-    Command->ModeRegisterDefinition = 0;
+    Command.CommandMode           = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
+    Command.CommandTarget         = CommandTarget;
+    Command.AutoRefreshNumber     = 4;
+    Command.ModeRegisterDefinition = 0;
 
     /* Send the command */
-    HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
+    HAL_SDRAM_SendCommand(hsdram, &Command, 0x1000);
+    wait((float)0.1);
 
     /* Step 7: Program the external memory mode register */
     tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1          |
@@ -69,18 +78,20 @@
              SDRAM_MODEREG_OPERATING_MODE_STANDARD |
              SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
 
-    Command->CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
-    Command->CommandTarget         = FMC_SDRAM_CMD_TARGET_BANK1_2;
-    Command->AutoRefreshNumber     = 1;
-    Command->ModeRegisterDefinition = tmpmrd;
+    Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
+    Command.CommandTarget         = CommandTarget;
+    Command.AutoRefreshNumber     = 1;
+    Command.ModeRegisterDefinition = tmpmrd;
 
     /* Send the command */
-    HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
+    HAL_SDRAM_SendCommand(hsdram, &Command, 0x1000);
+    wait((float)0.1);
 
     /* Step 8: Set the refresh rate counter */
     /* (15.62 us x Freq) - 20 */
     /* Set the device refresh counter */
     HAL_SDRAM_ProgramRefreshRate(hsdram, REFRESH_COUNT);
+    wait((float)0.1);
 }
 
 typedef class fmc
@@ -97,6 +108,7 @@
         _deep_sleep_locked(false) {
         core_util_critical_section_enter();
 
+        __HAL_RCC_GPIOB_CLK_ENABLE();   // 429
         __HAL_RCC_GPIOC_CLK_ENABLE();
         __HAL_RCC_GPIOD_CLK_ENABLE();
         __HAL_RCC_GPIOE_CLK_ENABLE();
@@ -174,17 +186,23 @@
         pin_function(PD_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC));  // FMC_D14
         pin_function(PD_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC));  // FMC_D15
 
+#if BLD446
+        // STM32F446
+        pin_function(PC_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC));  // FMC_SDCKE0
+        pin_function(PC_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC));  // FMC_SDNE0
+#else
+        // STM32F429
+        pin_function(PB_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC));  // FMC_SDCKE1
+        pin_function(PB_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC));  // FMC_SDNE1
+#endif
+        pin_function(PC_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC));  // FMC_SDNWE
+        pin_function(PE_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC));  // FMC_NBL0
+        pin_function(PE_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC));  // FMC_NBL1
+        pin_function(PF_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC));  // FMC_SDNRAS
         pin_function(PG_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC));  // FMC_BA0
         pin_function(PG_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC));  // FMC_BA1
         pin_function(PG_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC));  // FMC_SDCLK
-
         pin_function(PG_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC));  // FMC_SDNCAS
-        pin_function(PC_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC));  // FMC_SDNWE
-        pin_function(PC_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC));  // FMC_SDNE0
-        pin_function(PC_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC));  // FMC_SDCKE0
-        pin_function(PF_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC));  // FMC_SDNRAS
-        pin_function(PE_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC));  // FMC_NBL0
-        pin_function(PE_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC));  // FMC_NBL1
 
         __HAL_RCC_FMC_CLK_ENABLE();
 
@@ -192,11 +210,15 @@
         /** Perform the SDRAM1 memory initialization sequence
         */
         SDRAM_HandleTypeDef hsdram1 = { 0 };
-        FMC_SDRAM_CommandTypeDef command = { 0 };
 
         hsdram1.Instance = FMC_Bank5_6;
+
         /* hsdram1.Init */
-        hsdram1.Init.SDBank = FMC_SDRAM_BANK1;
+#if BLD446
+        hsdram1.Init.SDBank = FMC_SDRAM_BANK1;      // 446
+#else
+        hsdram1.Init.SDBank = FMC_SDRAM_BANK2;      // 429
+#endif
         hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
         hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
         hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16;
@@ -219,7 +241,7 @@
             //_Error_Handler(__FILE__, __LINE__);
         }
         /* Program the SDRAM external device */
-        SDRAM_Initialization_Sequence(&hsdram1, &command);
+        SDRAM_Initialization_Sequence(&hsdram1);
 
         core_util_critical_section_exit();
     }
@@ -245,4 +267,4 @@
 
 } FMC;
 
-static FMC fmc;
+//static FMC fmc;