Genadi Zawidowski / IGLOO_board

boart test board

Dependencies:   USBDevice mbed-dev lwip

Fork of USBSerial_HelloWorld by Compass Yap

STM32_FMC.cpp@19:8b7595ced647, 2018-07-24 (annotated)

Committer:
ua1arn
Date:
Tue Jul 24 23:24:53 2018 +0000
Revision:
19:8b7595ced647
Parent:
18:c276f3d01630
Child:
20:4b2a3c310b61
added sdram init

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ua1arn 19:8b7595ced647 1 #include "mbed.h"
ua1arn 17:8279856460a8 2 #include "platform/mbed_critical.h"
ua1arn 17:8279856460a8 3 #include "platform/mbed_power_mgmt.h"
ua1arn 17:8279856460a8 4
ua1arn 17:8279856460a8 5 #include "platform/platform.h"
ua1arn 17:8279856460a8 6 #include "hal/pinmap.h"
ua1arn 17:8279856460a8 7
ua1arn 19:8b7595ced647 8
ua1arn 19:8b7595ced647 9
ua1arn 19:8b7595ced647 10 #define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
ua1arn 19:8b7595ced647 11
ua1arn 19:8b7595ced647 12 #define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
ua1arn 19:8b7595ced647 13 #define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
ua1arn 19:8b7595ced647 14 #define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
ua1arn 19:8b7595ced647 15 #define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
ua1arn 19:8b7595ced647 16 #define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
ua1arn 19:8b7595ced647 17 #define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
ua1arn 19:8b7595ced647 18 #define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
ua1arn 19:8b7595ced647 19 #define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
ua1arn 19:8b7595ced647 20 #define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
ua1arn 19:8b7595ced647 21 #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
ua1arn 19:8b7595ced647 22 #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
ua1arn 19:8b7595ced647 23
ua1arn 19:8b7595ced647 24 #define REFRESH_COUNT ((uint32_t)0x056A) /* SDRAM refresh counter (90MHz SDRAM clock) */
ua1arn 19:8b7595ced647 25
ua1arn 19:8b7595ced647 26 /**
ua1arn 19:8b7595ced647 27 * @brief Perform the SDRAM exernal memory inialization sequence
ua1arn 19:8b7595ced647 28 * @param hsdram: SDRAM handle
ua1arn 19:8b7595ced647 29 * @param Command: Pointer to SDRAM command structure
ua1arn 19:8b7595ced647 30 * @retval None
ua1arn 19:8b7595ced647 31 */
ua1arn 19:8b7595ced647 32 static void SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command)
ua1arn 19:8b7595ced647 33 {
ua1arn 19:8b7595ced647 34 __IO uint32_t tmpmrd =0;
ua1arn 19:8b7595ced647 35 /* Step 3: Configure a clock configuration enable command */
ua1arn 19:8b7595ced647 36 Command->CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
ua1arn 19:8b7595ced647 37 Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1_2;
ua1arn 19:8b7595ced647 38 Command->AutoRefreshNumber = 1;
ua1arn 19:8b7595ced647 39 Command->ModeRegisterDefinition = 0;
ua1arn 19:8b7595ced647 40
ua1arn 19:8b7595ced647 41 /* Send the command */
ua1arn 19:8b7595ced647 42 HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
ua1arn 19:8b7595ced647 43
ua1arn 19:8b7595ced647 44 /* Step 4: Insert 100 ms delay */
ua1arn 19:8b7595ced647 45 wait((float)0.1);
ua1arn 19:8b7595ced647 46
ua1arn 19:8b7595ced647 47 /* Step 5: Configure a PALL (precharge all) command */
ua1arn 19:8b7595ced647 48 Command->CommandMode = FMC_SDRAM_CMD_PALL;
ua1arn 19:8b7595ced647 49 Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1_2;
ua1arn 19:8b7595ced647 50 Command->AutoRefreshNumber = 1;
ua1arn 19:8b7595ced647 51 Command->ModeRegisterDefinition = 0;
ua1arn 19:8b7595ced647 52
ua1arn 19:8b7595ced647 53 /* Send the command */
ua1arn 19:8b7595ced647 54 HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
ua1arn 19:8b7595ced647 55
ua1arn 19:8b7595ced647 56 /* Step 6 : Configure a Auto-Refresh command */
ua1arn 19:8b7595ced647 57 Command->CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
ua1arn 19:8b7595ced647 58 Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1_2;
ua1arn 19:8b7595ced647 59 Command->AutoRefreshNumber = 4;
ua1arn 19:8b7595ced647 60 Command->ModeRegisterDefinition = 0;
ua1arn 19:8b7595ced647 61
ua1arn 19:8b7595ced647 62 /* Send the command */
ua1arn 19:8b7595ced647 63 HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
ua1arn 19:8b7595ced647 64
ua1arn 19:8b7595ced647 65 /* Step 7: Program the external memory mode register */
ua1arn 19:8b7595ced647 66 tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |
ua1arn 19:8b7595ced647 67 SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
ua1arn 19:8b7595ced647 68 SDRAM_MODEREG_CAS_LATENCY_2 |
ua1arn 19:8b7595ced647 69 SDRAM_MODEREG_OPERATING_MODE_STANDARD |
ua1arn 19:8b7595ced647 70 SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
ua1arn 19:8b7595ced647 71
ua1arn 19:8b7595ced647 72 Command->CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
ua1arn 19:8b7595ced647 73 Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1_2;
ua1arn 19:8b7595ced647 74 Command->AutoRefreshNumber = 1;
ua1arn 19:8b7595ced647 75 Command->ModeRegisterDefinition = tmpmrd;
ua1arn 19:8b7595ced647 76
ua1arn 19:8b7595ced647 77 /* Send the command */
ua1arn 19:8b7595ced647 78 HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
ua1arn 19:8b7595ced647 79
ua1arn 19:8b7595ced647 80 /* Step 8: Set the refresh rate counter */
ua1arn 19:8b7595ced647 81 /* (15.62 us x Freq) - 20 */
ua1arn 19:8b7595ced647 82 /* Set the device refresh counter */
ua1arn 19:8b7595ced647 83 HAL_SDRAM_ProgramRefreshRate(hsdram, REFRESH_COUNT);
ua1arn 19:8b7595ced647 84 }
ua1arn 19:8b7595ced647 85
ua1arn 18:c276f3d01630 86 typedef class fmc
ua1arn 17:8279856460a8 87 {
ua1arn 17:8279856460a8 88 public:
ua1arn 17:8279856460a8 89
ua1arn 18:c276f3d01630 90 ~fmc() {
ua1arn 17:8279856460a8 91 core_util_critical_section_enter();
ua1arn 17:8279856460a8 92 unlock_deep_sleep();
ua1arn 17:8279856460a8 93 core_util_critical_section_exit();
ua1arn 17:8279856460a8 94 }
ua1arn 17:8279856460a8 95
ua1arn 18:c276f3d01630 96 fmc() :
ua1arn 17:8279856460a8 97 _deep_sleep_locked(false) {
ua1arn 17:8279856460a8 98 core_util_critical_section_enter();
ua1arn 18:c276f3d01630 99
ua1arn 17:8279856460a8 100 __HAL_RCC_GPIOC_CLK_ENABLE();
ua1arn 17:8279856460a8 101 __HAL_RCC_GPIOD_CLK_ENABLE();
ua1arn 17:8279856460a8 102 __HAL_RCC_GPIOE_CLK_ENABLE();
ua1arn 17:8279856460a8 103 __HAL_RCC_GPIOF_CLK_ENABLE();
ua1arn 17:8279856460a8 104 __HAL_RCC_GPIOG_CLK_ENABLE();
ua1arn 17:8279856460a8 105
ua1arn 18:c276f3d01630 106
ua1arn 18:c276f3d01630 107 /** FMC GPIO Configuration
ua1arn 18:c276f3d01630 108 PF0 ------> FMC_A0
ua1arn 18:c276f3d01630 109 PF1 ------> FMC_A1
ua1arn 18:c276f3d01630 110 PF2 ------> FMC_A2
ua1arn 18:c276f3d01630 111 PF3 ------> FMC_A3
ua1arn 18:c276f3d01630 112 PF4 ------> FMC_A4
ua1arn 18:c276f3d01630 113 PF5 ------> FMC_A5
ua1arn 18:c276f3d01630 114 PC0 ------> FMC_SDNWE
ua1arn 18:c276f3d01630 115 PC2 ------> FMC_SDNE0
ua1arn 18:c276f3d01630 116 PC3 ------> FMC_SDCKE0
ua1arn 18:c276f3d01630 117 PF11 ------> FMC_SDNRAS
ua1arn 18:c276f3d01630 118 PF12 ------> FMC_A6
ua1arn 18:c276f3d01630 119 PF13 ------> FMC_A7
ua1arn 18:c276f3d01630 120 PF14 ------> FMC_A8
ua1arn 18:c276f3d01630 121 PF15 ------> FMC_A9
ua1arn 18:c276f3d01630 122 PG0 ------> FMC_A10
ua1arn 18:c276f3d01630 123 PG1 ------> FMC_A11
ua1arn 18:c276f3d01630 124 PE7 ------> FMC_D4
ua1arn 18:c276f3d01630 125 PE8 ------> FMC_D5
ua1arn 18:c276f3d01630 126 PE9 ------> FMC_D6
ua1arn 18:c276f3d01630 127 PE10 ------> FMC_D7
ua1arn 18:c276f3d01630 128 PE11 ------> FMC_D8
ua1arn 18:c276f3d01630 129 PE12 ------> FMC_D9
ua1arn 18:c276f3d01630 130 PE13 ------> FMC_D10
ua1arn 18:c276f3d01630 131 PE14 ------> FMC_D11
ua1arn 18:c276f3d01630 132 PE15 ------> FMC_D12
ua1arn 18:c276f3d01630 133 PD8 ------> FMC_D13
ua1arn 18:c276f3d01630 134 PD9 ------> FMC_D14
ua1arn 18:c276f3d01630 135 PD10 ------> FMC_D15
ua1arn 18:c276f3d01630 136 PD14 ------> FMC_D0
ua1arn 18:c276f3d01630 137 PD15 ------> FMC_D1
ua1arn 18:c276f3d01630 138 PG4 ------> FMC_BA0
ua1arn 18:c276f3d01630 139 PG5 ------> FMC_BA1
ua1arn 18:c276f3d01630 140 PG8 ------> FMC_SDCLK
ua1arn 18:c276f3d01630 141 PD0 ------> FMC_D2
ua1arn 18:c276f3d01630 142 PD1 ------> FMC_D3
ua1arn 18:c276f3d01630 143 PG15 ------> FMC_SDNCAS
ua1arn 18:c276f3d01630 144 PE0 ------> FMC_NBL0
ua1arn 18:c276f3d01630 145 PE1 ------> FMC_NBL1
ua1arn 18:c276f3d01630 146 */
ua1arn 18:c276f3d01630 147 pin_function(PF_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_A0
ua1arn 18:c276f3d01630 148 pin_function(PF_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_A1
ua1arn 18:c276f3d01630 149 pin_function(PF_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_A2
ua1arn 18:c276f3d01630 150 pin_function(PF_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_A3
ua1arn 18:c276f3d01630 151 pin_function(PF_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_A4
ua1arn 18:c276f3d01630 152 pin_function(PF_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_A5
ua1arn 18:c276f3d01630 153 pin_function(PF_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_A6
ua1arn 18:c276f3d01630 154 pin_function(PF_13, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_A7
ua1arn 18:c276f3d01630 155 pin_function(PF_14, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_A8
ua1arn 18:c276f3d01630 156 pin_function(PF_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_A9
ua1arn 18:c276f3d01630 157 pin_function(PG_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_A10
ua1arn 18:c276f3d01630 158 pin_function(PG_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_A11
ua1arn 19:8b7595ced647 159
ua1arn 19:8b7595ced647 160 pin_function(PD_14, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D0
ua1arn 19:8b7595ced647 161 pin_function(PD_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D1
ua1arn 19:8b7595ced647 162 pin_function(PD_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D2
ua1arn 19:8b7595ced647 163 pin_function(PD_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D3
ua1arn 18:c276f3d01630 164 pin_function(PE_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D4
ua1arn 18:c276f3d01630 165 pin_function(PE_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D5
ua1arn 18:c276f3d01630 166 pin_function(PE_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D6
ua1arn 18:c276f3d01630 167 pin_function(PE_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D7
ua1arn 18:c276f3d01630 168 pin_function(PE_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D8
ua1arn 18:c276f3d01630 169 pin_function(PE_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D9
ua1arn 18:c276f3d01630 170 pin_function(PE_13, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D10
ua1arn 18:c276f3d01630 171 pin_function(PE_14, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D11
ua1arn 18:c276f3d01630 172 pin_function(PE_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D12
ua1arn 18:c276f3d01630 173 pin_function(PD_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D13
ua1arn 18:c276f3d01630 174 pin_function(PD_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D14
ua1arn 18:c276f3d01630 175 pin_function(PD_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_D15
ua1arn 19:8b7595ced647 176
ua1arn 18:c276f3d01630 177 pin_function(PG_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_BA0
ua1arn 18:c276f3d01630 178 pin_function(PG_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_BA1
ua1arn 18:c276f3d01630 179 pin_function(PG_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_SDCLK
ua1arn 19:8b7595ced647 180
ua1arn 18:c276f3d01630 181 pin_function(PG_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_SDNCAS
ua1arn 19:8b7595ced647 182 pin_function(PC_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_SDNWE
ua1arn 19:8b7595ced647 183 pin_function(PC_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_SDNE0
ua1arn 19:8b7595ced647 184 pin_function(PC_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_SDCKE0
ua1arn 19:8b7595ced647 185 pin_function(PF_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_SDNRAS
ua1arn 18:c276f3d01630 186 pin_function(PE_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_NBL0
ua1arn 18:c276f3d01630 187 pin_function(PE_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)); // FMC_NBL1
ua1arn 17:8279856460a8 188
ua1arn 17:8279856460a8 189 __HAL_RCC_FMC_CLK_ENABLE();
ua1arn 18:c276f3d01630 190
ua1arn 19:8b7595ced647 191 FMC_SDRAM_TimingTypeDef SdramTiming = { 0 };
ua1arn 18:c276f3d01630 192 /** Perform the SDRAM1 memory initialization sequence
ua1arn 18:c276f3d01630 193 */
ua1arn 19:8b7595ced647 194 SDRAM_HandleTypeDef hsdram1 = { 0 };
ua1arn 19:8b7595ced647 195 FMC_SDRAM_CommandTypeDef command = { 0 };
ua1arn 18:c276f3d01630 196
ua1arn 19:8b7595ced647 197 hsdram1.Instance = FMC_Bank5_6;
ua1arn 18:c276f3d01630 198 /* hsdram1.Init */
ua1arn 18:c276f3d01630 199 hsdram1.Init.SDBank = FMC_SDRAM_BANK1;
ua1arn 18:c276f3d01630 200 hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
ua1arn 18:c276f3d01630 201 hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
ua1arn 18:c276f3d01630 202 hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16;
ua1arn 18:c276f3d01630 203 hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
ua1arn 18:c276f3d01630 204 hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
ua1arn 18:c276f3d01630 205 hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
ua1arn 18:c276f3d01630 206 hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_3;
ua1arn 18:c276f3d01630 207 hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
ua1arn 18:c276f3d01630 208 hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
ua1arn 18:c276f3d01630 209 /* SdramTiming */
ua1arn 18:c276f3d01630 210 SdramTiming.LoadToActiveDelay = 2;
ua1arn 18:c276f3d01630 211 SdramTiming.ExitSelfRefreshDelay = 7;
ua1arn 18:c276f3d01630 212 SdramTiming.SelfRefreshTime = 4;
ua1arn 18:c276f3d01630 213 SdramTiming.RowCycleDelay = 2;
ua1arn 18:c276f3d01630 214 SdramTiming.WriteRecoveryTime = 2;
ua1arn 18:c276f3d01630 215 SdramTiming.RPDelay = 2;
ua1arn 18:c276f3d01630 216 SdramTiming.RCDDelay = 2;
ua1arn 18:c276f3d01630 217
ua1arn 18:c276f3d01630 218 if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK) {
ua1arn 18:c276f3d01630 219 //_Error_Handler(__FILE__, __LINE__);
ua1arn 18:c276f3d01630 220 }
ua1arn 19:8b7595ced647 221 /* Program the SDRAM external device */
ua1arn 19:8b7595ced647 222 SDRAM_Initialization_Sequence(&hsdram1, &command);
ua1arn 18:c276f3d01630 223
ua1arn 17:8279856460a8 224 core_util_critical_section_exit();
ua1arn 18:c276f3d01630 225 }
ua1arn 17:8279856460a8 226
ua1arn 17:8279856460a8 227 protected:
ua1arn 17:8279856460a8 228 /** Lock deep sleep only if it is not yet locked */
ua1arn 17:8279856460a8 229 void lock_deep_sleep() {
ua1arn 17:8279856460a8 230 if (_deep_sleep_locked == false) {
ua1arn 17:8279856460a8 231 sleep_manager_lock_deep_sleep();
ua1arn 17:8279856460a8 232 _deep_sleep_locked = true;
ua1arn 17:8279856460a8 233 }
ua1arn 17:8279856460a8 234 }
ua1arn 17:8279856460a8 235
ua1arn 17:8279856460a8 236 /** Unlock deep sleep in case it is locked */
ua1arn 17:8279856460a8 237 void unlock_deep_sleep() {
ua1arn 17:8279856460a8 238 if (_deep_sleep_locked == true) {
ua1arn 17:8279856460a8 239 sleep_manager_unlock_deep_sleep();
ua1arn 17:8279856460a8 240 _deep_sleep_locked = false;
ua1arn 17:8279856460a8 241 }
ua1arn 17:8279856460a8 242 }
ua1arn 17:8279856460a8 243
ua1arn 17:8279856460a8 244 bool _deep_sleep_locked;
ua1arn 17:8279856460a8 245
ua1arn 17:8279856460a8 246 } FMC;
ua1arn 17:8279856460a8 247
ua1arn 17:8279856460a8 248 static FMC fmc;