Timothy Mulrooney / SX1272Liby

first draft

Dependents:   LoRaWAN-demo-72_tjm frdm_LoRa_Connect_Woodstream_Demo_tjm frdm_LoRa_Connect_Woodstream_Demo_jlc

Fork of SX1272Lib by Semtech

sx1272/sx1272-hal.cpp@5:e6a3f05e4743, 2016-08-09 (annotated)

Committer:
tmulrooney
Date:
Tue Aug 09 14:37:25 2016 +0000
Revision:
5:e6a3f05e4743
Parent:
4:352d0947f887
Child:
6:af0463c03b8b
production board

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mluis 0:45c4f0364ca4 1 /*
mluis 0:45c4f0364ca4 2 / _____) _ | |
mluis 0:45c4f0364ca4 3 ( (____ _____ ____ _| |_ _____ ____| |__
mluis 0:45c4f0364ca4 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
mluis 0:45c4f0364ca4 5 _____) ) ____| | | || |_| ____( (___| | | |
mluis 0:45c4f0364ca4 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 0:45c4f0364ca4 7 (C) 2015 Semtech
mluis 0:45c4f0364ca4 8
mluis 0:45c4f0364ca4 9 Description: -
mluis 0:45c4f0364ca4 10
mluis 0:45c4f0364ca4 11 License: Revised BSD License, see LICENSE.TXT file include in the project
mluis 0:45c4f0364ca4 12
mluis 0:45c4f0364ca4 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
mluis 0:45c4f0364ca4 14 */
mluis 0:45c4f0364ca4 15 #include "sx1272-hal.h"
mluis 0:45c4f0364ca4 16
GregCr 2:cd1093b6676f 17 const RadioRegisters_t SX1272MB2xAS::RadioRegsInit[] = RADIO_INIT_REGISTERS_VALUE;
mluis 0:45c4f0364ca4 18
GregCr 2:cd1093b6676f 19 SX1272MB2xAS::SX1272MB2xAS( RadioEvents_t *events,
mluis 0:45c4f0364ca4 20 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
mluis 0:45c4f0364ca4 21 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5,
mluis 0:45c4f0364ca4 22 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 23 PinName rfSwitchCntr1, PinName rfSwitchCntr2 )
dudmuck 1:b0372ef620d0 24 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 25 PinName txctl, PinName rxctl )
mluis 0:45c4f0364ca4 26 #else
mluis 0:45c4f0364ca4 27 PinName antSwitch )
mluis 0:45c4f0364ca4 28 #endif
tmulrooney 3:73a1f904eaa5 29 // : SX1272( events, mosi, miso, sclk, nss, reset, dio0, dio1, dio2, dio3, dio4, dio5 ),
tmulrooney 5:e6a3f05e4743 30 // : SX1272( events, PTD6, PTD7, PTD5, PTD4, reset, PTC2, PTB1, PTC3, PTB0, PTC4, PTC1 ),
tmulrooney 5:e6a3f05e4743 31 : SX1272( events, PTC6, PTC7, PTC5, PTC4, reset, PTC8, PTC9, PTC10, PTC11, PTD0, PTD1 ),
mluis 0:45c4f0364ca4 32 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 33 RfSwitchCntr1( rfSwitchCntr1 ),
mluis 0:45c4f0364ca4 34 RfSwitchCntr2( rfSwitchCntr2 ),
dudmuck 1:b0372ef620d0 35 PwrAmpCntr( PD_2 )
dudmuck 1:b0372ef620d0 36 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 37 TxCtl ( txctl ),
dudmuck 1:b0372ef620d0 38 RxCtl ( rxctl )
mluis 0:45c4f0364ca4 39 #else
tmulrooney 3:73a1f904eaa5 40 // AntSwitch( antSwitch ),
tmulrooney 5:e6a3f05e4743 41 // AntSwitch( PTC6 ),
tmulrooney 5:e6a3f05e4743 42 AntSwitch( PTC0 ),
mluis 0:45c4f0364ca4 43 #if( defined ( TARGET_NUCLEO_L152RE ) )
dudmuck 1:b0372ef620d0 44 Fake( D8 )
mluis 0:45c4f0364ca4 45 #else
mluis 0:45c4f0364ca4 46 Fake( A3 )
mluis 0:45c4f0364ca4 47 #endif
mluis 0:45c4f0364ca4 48 #endif
mluis 0:45c4f0364ca4 49 {
mluis 0:45c4f0364ca4 50 this->RadioEvents = events;
mluis 0:45c4f0364ca4 51
mluis 0:45c4f0364ca4 52 Reset( );
mluis 0:45c4f0364ca4 53
mluis 0:45c4f0364ca4 54 IoInit( );
mluis 0:45c4f0364ca4 55
mluis 0:45c4f0364ca4 56 SetOpMode( RF_OPMODE_SLEEP );
mluis 0:45c4f0364ca4 57
mluis 0:45c4f0364ca4 58 IoIrqInit( dioIrq );
mluis 0:45c4f0364ca4 59
mluis 0:45c4f0364ca4 60 RadioRegistersInit( );
mluis 0:45c4f0364ca4 61
mluis 0:45c4f0364ca4 62 SetModem( MODEM_FSK );
mluis 0:45c4f0364ca4 63
mluis 0:45c4f0364ca4 64 this->settings.State = RF_IDLE ;
mluis 0:45c4f0364ca4 65 }
mluis 0:45c4f0364ca4 66
GregCr 2:cd1093b6676f 67 SX1272MB2xAS::SX1272MB2xAS( RadioEvents_t *events )
mluis 0:45c4f0364ca4 68 #if defined ( TARGET_NUCLEO_L152RE )
mluis 0:45c4f0364ca4 69 : SX1272( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, A3, D9 ), // For NUCLEO L152RE dio4 is on port A3
mluis 0:45c4f0364ca4 70 AntSwitch( A4 ),
mluis 0:45c4f0364ca4 71 Fake( D8 )
mluis 0:45c4f0364ca4 72 #elif defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 73 : SX1272( events, PB_15, PB_14, PB_13, PB_12, PC_2, PC_6, PC_10, PC_11, PC_8, PC_9, PC_12 ),
mluis 0:45c4f0364ca4 74 RfSwitchCntr1( PC_4 ),
mluis 0:45c4f0364ca4 75 RfSwitchCntr2( PC_13 ),
mluis 0:45c4f0364ca4 76 PwrAmpCntr( PD_2 )
dudmuck 1:b0372ef620d0 77 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 78 : SX1272( events, LORA_MOSI, LORA_MISO, LORA_SCK, LORA_NSS, LORA_RESET, LORA_DIO0, LORA_DIO1, LORA_DIO2, LORA_DIO3, LORA_DIO4, LORA_DIO5 ),
dudmuck 1:b0372ef620d0 79 TxCtl( LORA_TXCTL ),
dudmuck 1:b0372ef620d0 80 RxCtl( LORA_RXCTL )
mluis 0:45c4f0364ca4 81 #else
tmulrooney 3:73a1f904eaa5 82 // : SX1272( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
tmulrooney 3:73a1f904eaa5 83 // AntSwitch( A4 ),
tmulrooney 5:e6a3f05e4743 84 // : SX1272( events, PTD6, PTD7, PTD5, PTD4, A0, PTC2, PTB1, PTC3, PTB0, PTC4, PTC1 ),
tmulrooney 5:e6a3f05e4743 85 : SX1272( events, PTC6, PTC7, PTC5, PTC4, A0, PTC8, PTC9, PTC10, PTC11, PTD0, PTD1 ),
tmulrooney 3:73a1f904eaa5 86 AntSwitch( PTC6 ),
mluis 0:45c4f0364ca4 87 Fake( A3 )
mluis 0:45c4f0364ca4 88 #endif
mluis 0:45c4f0364ca4 89 {
mluis 0:45c4f0364ca4 90 this->RadioEvents = events;
mluis 0:45c4f0364ca4 91
mluis 0:45c4f0364ca4 92 Reset( );
mluis 0:45c4f0364ca4 93
mluis 0:45c4f0364ca4 94 boardConnected = UNKNOWN;
mluis 0:45c4f0364ca4 95
mluis 0:45c4f0364ca4 96 DetectBoardType( );
mluis 0:45c4f0364ca4 97
mluis 0:45c4f0364ca4 98 IoInit( );
mluis 0:45c4f0364ca4 99
mluis 0:45c4f0364ca4 100 SetOpMode( RF_OPMODE_SLEEP );
mluis 0:45c4f0364ca4 101 IoIrqInit( dioIrq );
mluis 0:45c4f0364ca4 102
mluis 0:45c4f0364ca4 103 RadioRegistersInit( );
mluis 0:45c4f0364ca4 104
mluis 0:45c4f0364ca4 105 SetModem( MODEM_FSK );
mluis 0:45c4f0364ca4 106
mluis 0:45c4f0364ca4 107 this->settings.State = RF_IDLE ;
mluis 0:45c4f0364ca4 108 }
mluis 0:45c4f0364ca4 109
mluis 0:45c4f0364ca4 110 //-------------------------------------------------------------------------
mluis 0:45c4f0364ca4 111 // Board relative functions
mluis 0:45c4f0364ca4 112 //-------------------------------------------------------------------------
GregCr 2:cd1093b6676f 113 uint8_t SX1272MB2xAS::DetectBoardType( void )
mluis 0:45c4f0364ca4 114 {
mluis 0:45c4f0364ca4 115 if( boardConnected == UNKNOWN )
mluis 0:45c4f0364ca4 116 {
mluis 0:45c4f0364ca4 117 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 118 boardConnected = NA_MOTE_72;
dudmuck 1:b0372ef620d0 119 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 120 boardConnected = MDOT_F411RE;
mluis 0:45c4f0364ca4 121 #else
mluis 0:45c4f0364ca4 122 this->AntSwitch.input( );
mluis 0:45c4f0364ca4 123 wait_ms( 1 );
mluis 0:45c4f0364ca4 124 if( this->AntSwitch == 1 )
mluis 0:45c4f0364ca4 125 {
mluis 0:45c4f0364ca4 126 boardConnected = SX1272MB1DCS;
mluis 0:45c4f0364ca4 127 }
mluis 0:45c4f0364ca4 128 else
mluis 0:45c4f0364ca4 129 {
GregCr 2:cd1093b6676f 130 boardConnected = SX1272MB2XAS;
mluis 0:45c4f0364ca4 131 }
mluis 0:45c4f0364ca4 132 this->AntSwitch.output( );
mluis 0:45c4f0364ca4 133 wait_ms( 1 );
mluis 0:45c4f0364ca4 134 #endif
mluis 0:45c4f0364ca4 135 }
mluis 0:45c4f0364ca4 136 return ( boardConnected );
mluis 0:45c4f0364ca4 137 }
mluis 0:45c4f0364ca4 138
GregCr 2:cd1093b6676f 139 void SX1272MB2xAS::IoInit( void )
mluis 0:45c4f0364ca4 140 {
mluis 0:45c4f0364ca4 141 AntSwInit( );
mluis 0:45c4f0364ca4 142 SpiInit( );
mluis 0:45c4f0364ca4 143 }
mluis 0:45c4f0364ca4 144
GregCr 2:cd1093b6676f 145 void SX1272MB2xAS::RadioRegistersInit( )
mluis 0:45c4f0364ca4 146 {
mluis 0:45c4f0364ca4 147 uint8_t i = 0;
mluis 0:45c4f0364ca4 148 for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ )
mluis 0:45c4f0364ca4 149 {
mluis 0:45c4f0364ca4 150 SetModem( RadioRegsInit[i].Modem );
mluis 0:45c4f0364ca4 151 Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
mluis 0:45c4f0364ca4 152 }
mluis 0:45c4f0364ca4 153 }
mluis 0:45c4f0364ca4 154
GregCr 2:cd1093b6676f 155 void SX1272MB2xAS::SpiInit( void )
mluis 0:45c4f0364ca4 156 {
mluis 0:45c4f0364ca4 157 nss = 1;
tmulrooney 4:352d0947f887 158 spi.format( 8,0 );
tmulrooney 5:e6a3f05e4743 159 // uint32_t frequencyToSet = 8000000;
tmulrooney 5:e6a3f05e4743 160 uint32_t frequencyToSet = (8000000 * 2)/3; /* 8 MHz/12 Mhz */
tmulrooney 4:352d0947f887 161 // #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_MOTE_L152RC ) || defined ( TARGET_LPC11U6X ) || defined ( TARGET_MTS_MDOT_F411RE ) )
mluis 0:45c4f0364ca4 162 spi.frequency( frequencyToSet );
tmulrooney 4:352d0947f887 163 // #elif( defined ( TARGET_KL25Z ) ) //busclock frequency is halved -> double the spi frequency to compensate
tmulrooney 4:352d0947f887 164 // spi.frequency( frequencyToSet * 2 );
tmulrooney 4:352d0947f887 165 // #else
tmulrooney 4:352d0947f887 166 // #warning "Check the board's SPI frequency"x
tmulrooney 4:352d0947f887 167 // #endif
mluis 0:45c4f0364ca4 168 wait(0.1);
mluis 0:45c4f0364ca4 169 }
mluis 0:45c4f0364ca4 170
GregCr 2:cd1093b6676f 171 void SX1272MB2xAS::IoIrqInit( DioIrqHandler *irqHandlers )
mluis 0:45c4f0364ca4 172 {
mluis 0:45c4f0364ca4 173 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_MOTE_L152RC ) || defined ( TARGET_LPC11U6X ) )
mluis 0:45c4f0364ca4 174 dio0.mode( PullDown );
mluis 0:45c4f0364ca4 175 dio1.mode( PullDown );
mluis 0:45c4f0364ca4 176 dio2.mode( PullDown );
mluis 0:45c4f0364ca4 177 dio3.mode( PullDown );
mluis 0:45c4f0364ca4 178 dio4.mode( PullDown );
mluis 0:45c4f0364ca4 179 #endif
GregCr 2:cd1093b6676f 180 dio0.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[0] ) );
GregCr 2:cd1093b6676f 181 dio1.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[1] ) );
GregCr 2:cd1093b6676f 182 dio2.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[2] ) );
GregCr 2:cd1093b6676f 183 dio3.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[3] ) );
GregCr 2:cd1093b6676f 184 dio4.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[4] ) );
mluis 0:45c4f0364ca4 185 }
mluis 0:45c4f0364ca4 186
GregCr 2:cd1093b6676f 187 void SX1272MB2xAS::IoDeInit( void )
mluis 0:45c4f0364ca4 188 {
mluis 0:45c4f0364ca4 189 //nothing
mluis 0:45c4f0364ca4 190 }
mluis 0:45c4f0364ca4 191
GregCr 2:cd1093b6676f 192 uint8_t SX1272MB2xAS::GetPaSelect( uint32_t channel )
mluis 0:45c4f0364ca4 193 {
dudmuck 1:b0372ef620d0 194 if( boardConnected == SX1272MB1DCS || boardConnected == MDOT_F411RE )
mluis 0:45c4f0364ca4 195 {
mluis 0:45c4f0364ca4 196 return RF_PACONFIG_PASELECT_PABOOST;
mluis 0:45c4f0364ca4 197 }
mluis 0:45c4f0364ca4 198 else
mluis 0:45c4f0364ca4 199 {
mluis 0:45c4f0364ca4 200 return RF_PACONFIG_PASELECT_RFO;
mluis 0:45c4f0364ca4 201 }
mluis 0:45c4f0364ca4 202 }
mluis 0:45c4f0364ca4 203
GregCr 2:cd1093b6676f 204 void SX1272MB2xAS::SetAntSwLowPower( bool status )
mluis 0:45c4f0364ca4 205 {
mluis 0:45c4f0364ca4 206 if( isRadioActive != status )
mluis 0:45c4f0364ca4 207 {
mluis 0:45c4f0364ca4 208 isRadioActive = status;
mluis 0:45c4f0364ca4 209
mluis 0:45c4f0364ca4 210 if( status == false )
mluis 0:45c4f0364ca4 211 {
mluis 0:45c4f0364ca4 212 AntSwInit( );
mluis 0:45c4f0364ca4 213 }
mluis 0:45c4f0364ca4 214 else
mluis 0:45c4f0364ca4 215 {
mluis 0:45c4f0364ca4 216 AntSwDeInit( );
mluis 0:45c4f0364ca4 217 }
mluis 0:45c4f0364ca4 218 }
mluis 0:45c4f0364ca4 219 }
mluis 0:45c4f0364ca4 220
GregCr 2:cd1093b6676f 221 void SX1272MB2xAS::AntSwInit( void )
mluis 0:45c4f0364ca4 222 {
mluis 0:45c4f0364ca4 223 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 224 this->RfSwitchCntr1 = 0;
mluis 0:45c4f0364ca4 225 this->RfSwitchCntr2 = 0;
mluis 0:45c4f0364ca4 226 this->PwrAmpCntr = 0;
dudmuck 1:b0372ef620d0 227 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 228 this->TxCtl = 0;
dudmuck 1:b0372ef620d0 229 this->RxCtl = 0;
mluis 0:45c4f0364ca4 230 #else
mluis 0:45c4f0364ca4 231 this->AntSwitch = 0;
mluis 0:45c4f0364ca4 232 #endif
mluis 0:45c4f0364ca4 233 }
mluis 0:45c4f0364ca4 234
GregCr 2:cd1093b6676f 235 void SX1272MB2xAS::AntSwDeInit( void )
mluis 0:45c4f0364ca4 236 {
mluis 0:45c4f0364ca4 237 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 238 this->RfSwitchCntr1 = 0;
mluis 0:45c4f0364ca4 239 this->RfSwitchCntr2 = 0;
mluis 0:45c4f0364ca4 240 this->PwrAmpCntr = 0;
dudmuck 1:b0372ef620d0 241 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 242 this->TxCtl = 0;
dudmuck 1:b0372ef620d0 243 this->RxCtl = 0;
mluis 0:45c4f0364ca4 244 #else
mluis 0:45c4f0364ca4 245 this->AntSwitch = 0;
mluis 0:45c4f0364ca4 246 #endif
mluis 0:45c4f0364ca4 247 }
mluis 0:45c4f0364ca4 248
GregCr 2:cd1093b6676f 249 void SX1272MB2xAS::SetAntSw( uint8_t rxTx )
mluis 0:45c4f0364ca4 250 {
mluis 0:45c4f0364ca4 251 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 252 switch( this->currentOpMode )
mluis 0:45c4f0364ca4 253 {
mluis 0:45c4f0364ca4 254 case RFLR_OPMODE_TRANSMITTER:
mluis 0:45c4f0364ca4 255 if( ( Read( REG_PACONFIG ) & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
mluis 0:45c4f0364ca4 256 {
mluis 0:45c4f0364ca4 257 this->RfSwitchCntr1 = 1;
mluis 0:45c4f0364ca4 258 this->RfSwitchCntr2 = 0;
mluis 0:45c4f0364ca4 259 }
mluis 0:45c4f0364ca4 260 else
mluis 0:45c4f0364ca4 261 {
mluis 0:45c4f0364ca4 262 this->RfSwitchCntr1 = 0;
mluis 0:45c4f0364ca4 263 this->RfSwitchCntr2 = 1;
mluis 0:45c4f0364ca4 264 }
mluis 0:45c4f0364ca4 265 break;
mluis 0:45c4f0364ca4 266 case RFLR_OPMODE_RECEIVER:
mluis 0:45c4f0364ca4 267 case RFLR_OPMODE_RECEIVER_SINGLE:
mluis 0:45c4f0364ca4 268 case RFLR_OPMODE_CAD:
mluis 0:45c4f0364ca4 269 this->RfSwitchCntr1 = 1;
mluis 0:45c4f0364ca4 270 this->RfSwitchCntr2 = 1;
mluis 0:45c4f0364ca4 271 break;
mluis 0:45c4f0364ca4 272 default:
mluis 0:45c4f0364ca4 273 this->RfSwitchCntr1 = 0;
mluis 0:45c4f0364ca4 274 this->RfSwitchCntr2 = 0;
mluis 0:45c4f0364ca4 275 this->PwrAmpCntr = 0;
mluis 0:45c4f0364ca4 276 break;
mluis 0:45c4f0364ca4 277 }
dudmuck 1:b0372ef620d0 278 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 279 if( this->rxTx == rxTx )
dudmuck 1:b0372ef620d0 280 {
dudmuck 1:b0372ef620d0 281 //no need to go further
dudmuck 1:b0372ef620d0 282 return;
dudmuck 1:b0372ef620d0 283 }
dudmuck 1:b0372ef620d0 284
dudmuck 1:b0372ef620d0 285 /* SKY13350 */
dudmuck 1:b0372ef620d0 286 this->rxTx = rxTx;
dudmuck 1:b0372ef620d0 287
dudmuck 1:b0372ef620d0 288 // 1: Tx, 0: Rx
dudmuck 1:b0372ef620d0 289 if( rxTx != 0 )
dudmuck 1:b0372ef620d0 290 {
dudmuck 1:b0372ef620d0 291 this->TxCtl = 1;
dudmuck 1:b0372ef620d0 292 this->RxCtl = 0;
dudmuck 1:b0372ef620d0 293 }
dudmuck 1:b0372ef620d0 294 else
dudmuck 1:b0372ef620d0 295 {
dudmuck 1:b0372ef620d0 296 this->TxCtl = 0;
dudmuck 1:b0372ef620d0 297 this->RxCtl = 1;
dudmuck 1:b0372ef620d0 298 }
mluis 0:45c4f0364ca4 299 #else
mluis 0:45c4f0364ca4 300 if( this->rxTx == rxTx )
mluis 0:45c4f0364ca4 301 {
mluis 0:45c4f0364ca4 302 //no need to go further
mluis 0:45c4f0364ca4 303 return;
mluis 0:45c4f0364ca4 304 }
mluis 0:45c4f0364ca4 305
mluis 0:45c4f0364ca4 306 this->rxTx = rxTx;
mluis 0:45c4f0364ca4 307
mluis 0:45c4f0364ca4 308 // 1: Tx, 0: Rx
mluis 0:45c4f0364ca4 309 if( rxTx != 0 )
mluis 0:45c4f0364ca4 310 {
mluis 0:45c4f0364ca4 311 this->AntSwitch = 1;
mluis 0:45c4f0364ca4 312 }
mluis 0:45c4f0364ca4 313 else
mluis 0:45c4f0364ca4 314 {
mluis 0:45c4f0364ca4 315 this->AntSwitch = 0;
mluis 0:45c4f0364ca4 316 }
mluis 0:45c4f0364ca4 317 #endif
mluis 0:45c4f0364ca4 318 }
mluis 0:45c4f0364ca4 319
GregCr 2:cd1093b6676f 320 bool SX1272MB2xAS::CheckRfFrequency( uint32_t frequency )
mluis 0:45c4f0364ca4 321 {
mluis 0:45c4f0364ca4 322 //TODO: Implement check, currently all frequencies are supported
mluis 0:45c4f0364ca4 323 return true;
mluis 0:45c4f0364ca4 324 }
mluis 0:45c4f0364ca4 325
mluis 0:45c4f0364ca4 326
GregCr 2:cd1093b6676f 327 void SX1272MB2xAS::Reset( void )
mluis 0:45c4f0364ca4 328 {
mluis 0:45c4f0364ca4 329 reset.output();
mluis 0:45c4f0364ca4 330 reset = 0;
mluis 0:45c4f0364ca4 331 wait_ms( 1 );
mluis 0:45c4f0364ca4 332 reset.input();
mluis 0:45c4f0364ca4 333 wait_ms( 6 );
mluis 0:45c4f0364ca4 334 }
mluis 0:45c4f0364ca4 335
GregCr 2:cd1093b6676f 336 void SX1272MB2xAS::Write( uint8_t addr, uint8_t data )
mluis 0:45c4f0364ca4 337 {
mluis 0:45c4f0364ca4 338 Write( addr, &data, 1 );
mluis 0:45c4f0364ca4 339 }
mluis 0:45c4f0364ca4 340
GregCr 2:cd1093b6676f 341 uint8_t SX1272MB2xAS::Read( uint8_t addr )
mluis 0:45c4f0364ca4 342 {
mluis 0:45c4f0364ca4 343 uint8_t data;
mluis 0:45c4f0364ca4 344 Read( addr, &data, 1 );
mluis 0:45c4f0364ca4 345 return data;
mluis 0:45c4f0364ca4 346 }
mluis 0:45c4f0364ca4 347
GregCr 2:cd1093b6676f 348 void SX1272MB2xAS::Write( uint8_t addr, uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 349 {
mluis 0:45c4f0364ca4 350 uint8_t i;
mluis 0:45c4f0364ca4 351
mluis 0:45c4f0364ca4 352 nss = 0;
mluis 0:45c4f0364ca4 353 spi.write( addr | 0x80 );
mluis 0:45c4f0364ca4 354 for( i = 0; i < size; i++ )
mluis 0:45c4f0364ca4 355 {
mluis 0:45c4f0364ca4 356 spi.write( buffer[i] );
mluis 0:45c4f0364ca4 357 }
mluis 0:45c4f0364ca4 358 nss = 1;
mluis 0:45c4f0364ca4 359 }
mluis 0:45c4f0364ca4 360
GregCr 2:cd1093b6676f 361 void SX1272MB2xAS::Read( uint8_t addr, uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 362 {
mluis 0:45c4f0364ca4 363 uint8_t i;
mluis 0:45c4f0364ca4 364
mluis 0:45c4f0364ca4 365 nss = 0;
mluis 0:45c4f0364ca4 366 spi.write( addr & 0x7F );
mluis 0:45c4f0364ca4 367 for( i = 0; i < size; i++ )
mluis 0:45c4f0364ca4 368 {
mluis 0:45c4f0364ca4 369 buffer[i] = spi.write( 0 );
mluis 0:45c4f0364ca4 370 }
mluis 0:45c4f0364ca4 371 nss = 1;
mluis 0:45c4f0364ca4 372 }
mluis 0:45c4f0364ca4 373
GregCr 2:cd1093b6676f 374 void SX1272MB2xAS::WriteFifo( uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 375 {
mluis 0:45c4f0364ca4 376 Write( 0, buffer, size );
mluis 0:45c4f0364ca4 377 }
mluis 0:45c4f0364ca4 378
GregCr 2:cd1093b6676f 379 void SX1272MB2xAS::ReadFifo( uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 380 {
mluis 0:45c4f0364ca4 381 Read( 0, buffer, size );
mluis 0:45c4f0364ca4 382 }