Timothy Mulrooney / SX1272Liby

first draft

Dependents:   LoRaWAN-demo-72_tjm frdm_LoRa_Connect_Woodstream_Demo_tjm frdm_LoRa_Connect_Woodstream_Demo_jlc

Fork of SX1272Lib by Semtech

sx1272/sx1272-hal.cpp@6:af0463c03b8b, 2016-08-09 (annotated)

Committer:
tmulrooney
Date:
Tue Aug 09 18:19:47 2016 +0000
Revision:
6:af0463c03b8b
Parent:
5:e6a3f05e4743 
update

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mluis 0:45c4f0364ca4 1 /*
mluis 0:45c4f0364ca4 2 / _____) _ | |
mluis 0:45c4f0364ca4 3 ( (____ _____ ____ _| |_ _____ ____| |__
mluis 0:45c4f0364ca4 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
mluis 0:45c4f0364ca4 5 _____) ) ____| | | || |_| ____( (___| | | |
mluis 0:45c4f0364ca4 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 0:45c4f0364ca4 7 (C) 2015 Semtech
mluis 0:45c4f0364ca4 8
mluis 0:45c4f0364ca4 9 Description: -
mluis 0:45c4f0364ca4 10
mluis 0:45c4f0364ca4 11 License: Revised BSD License, see LICENSE.TXT file include in the project
mluis 0:45c4f0364ca4 12
mluis 0:45c4f0364ca4 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
mluis 0:45c4f0364ca4 14 */
mluis 0:45c4f0364ca4 15 #include "sx1272-hal.h"
mluis 0:45c4f0364ca4 16
GregCr 2:cd1093b6676f 17 const RadioRegisters_t SX1272MB2xAS::RadioRegsInit[] = RADIO_INIT_REGISTERS_VALUE;
mluis 0:45c4f0364ca4 18
GregCr 2:cd1093b6676f 19 SX1272MB2xAS::SX1272MB2xAS( RadioEvents_t *events,
mluis 0:45c4f0364ca4 20 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
mluis 0:45c4f0364ca4 21 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5,
mluis 0:45c4f0364ca4 22 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 23 PinName rfSwitchCntr1, PinName rfSwitchCntr2 )
dudmuck 1:b0372ef620d0 24 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 25 PinName txctl, PinName rxctl )
mluis 0:45c4f0364ca4 26 #else
mluis 0:45c4f0364ca4 27 PinName antSwitch )
mluis 0:45c4f0364ca4 28 #endif
tmulrooney 3:73a1f904eaa5 29 // : SX1272( events, mosi, miso, sclk, nss, reset, dio0, dio1, dio2, dio3, dio4, dio5 ),
tmulrooney 5:e6a3f05e4743 30 // : SX1272( events, PTD6, PTD7, PTD5, PTD4, reset, PTC2, PTB1, PTC3, PTB0, PTC4, PTC1 ),
tmulrooney 5:e6a3f05e4743 31 : SX1272( events, PTC6, PTC7, PTC5, PTC4, reset, PTC8, PTC9, PTC10, PTC11, PTD0, PTD1 ),
mluis 0:45c4f0364ca4 32 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 33 RfSwitchCntr1( rfSwitchCntr1 ),
mluis 0:45c4f0364ca4 34 RfSwitchCntr2( rfSwitchCntr2 ),
dudmuck 1:b0372ef620d0 35 PwrAmpCntr( PD_2 )
dudmuck 1:b0372ef620d0 36 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 37 TxCtl ( txctl ),
dudmuck 1:b0372ef620d0 38 RxCtl ( rxctl )
mluis 0:45c4f0364ca4 39 #else
tmulrooney 3:73a1f904eaa5 40 // AntSwitch( antSwitch ),
tmulrooney 5:e6a3f05e4743 41 // AntSwitch( PTC6 ),
tmulrooney 6:af0463c03b8b 42 AntSwitch( PTC0),
mluis 0:45c4f0364ca4 43 #if( defined ( TARGET_NUCLEO_L152RE ) )
dudmuck 1:b0372ef620d0 44 Fake( D8 )
mluis 0:45c4f0364ca4 45 #else
mluis 0:45c4f0364ca4 46 Fake( A3 )
mluis 0:45c4f0364ca4 47 #endif
mluis 0:45c4f0364ca4 48 #endif
mluis 0:45c4f0364ca4 49 {
mluis 0:45c4f0364ca4 50 this->RadioEvents = events;
mluis 0:45c4f0364ca4 51
mluis 0:45c4f0364ca4 52 Reset( );
mluis 0:45c4f0364ca4 53
mluis 0:45c4f0364ca4 54 IoInit( );
mluis 0:45c4f0364ca4 55
mluis 0:45c4f0364ca4 56 SetOpMode( RF_OPMODE_SLEEP );
mluis 0:45c4f0364ca4 57
mluis 0:45c4f0364ca4 58 IoIrqInit( dioIrq );
mluis 0:45c4f0364ca4 59
mluis 0:45c4f0364ca4 60 RadioRegistersInit( );
mluis 0:45c4f0364ca4 61
mluis 0:45c4f0364ca4 62 SetModem( MODEM_FSK );
mluis 0:45c4f0364ca4 63
mluis 0:45c4f0364ca4 64 this->settings.State = RF_IDLE ;
mluis 0:45c4f0364ca4 65 }
mluis 0:45c4f0364ca4 66
GregCr 2:cd1093b6676f 67 SX1272MB2xAS::SX1272MB2xAS( RadioEvents_t *events )
mluis 0:45c4f0364ca4 68 #if defined ( TARGET_NUCLEO_L152RE )
mluis 0:45c4f0364ca4 69 : SX1272( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, A3, D9 ), // For NUCLEO L152RE dio4 is on port A3
mluis 0:45c4f0364ca4 70 AntSwitch( A4 ),
mluis 0:45c4f0364ca4 71 Fake( D8 )
mluis 0:45c4f0364ca4 72 #elif defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 73 : SX1272( events, PB_15, PB_14, PB_13, PB_12, PC_2, PC_6, PC_10, PC_11, PC_8, PC_9, PC_12 ),
mluis 0:45c4f0364ca4 74 RfSwitchCntr1( PC_4 ),
mluis 0:45c4f0364ca4 75 RfSwitchCntr2( PC_13 ),
mluis 0:45c4f0364ca4 76 PwrAmpCntr( PD_2 )
dudmuck 1:b0372ef620d0 77 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 78 : SX1272( events, LORA_MOSI, LORA_MISO, LORA_SCK, LORA_NSS, LORA_RESET, LORA_DIO0, LORA_DIO1, LORA_DIO2, LORA_DIO3, LORA_DIO4, LORA_DIO5 ),
dudmuck 1:b0372ef620d0 79 TxCtl( LORA_TXCTL ),
dudmuck 1:b0372ef620d0 80 RxCtl( LORA_RXCTL )
mluis 0:45c4f0364ca4 81 #else
tmulrooney 3:73a1f904eaa5 82 // : SX1272( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
tmulrooney 3:73a1f904eaa5 83 // AntSwitch( A4 ),
tmulrooney 5:e6a3f05e4743 84 // : SX1272( events, PTD6, PTD7, PTD5, PTD4, A0, PTC2, PTB1, PTC3, PTB0, PTC4, PTC1 ),
tmulrooney 5:e6a3f05e4743 85 : SX1272( events, PTC6, PTC7, PTC5, PTC4, A0, PTC8, PTC9, PTC10, PTC11, PTD0, PTD1 ),
tmulrooney 6:af0463c03b8b 86 // AntSwitch( PTC6 ),
tmulrooney 6:af0463c03b8b 87 AntSwitch( PTC0 ),
mluis 0:45c4f0364ca4 88 Fake( A3 )
mluis 0:45c4f0364ca4 89 #endif
mluis 0:45c4f0364ca4 90 {
mluis 0:45c4f0364ca4 91 this->RadioEvents = events;
mluis 0:45c4f0364ca4 92
mluis 0:45c4f0364ca4 93 Reset( );
mluis 0:45c4f0364ca4 94
mluis 0:45c4f0364ca4 95 boardConnected = UNKNOWN;
mluis 0:45c4f0364ca4 96
mluis 0:45c4f0364ca4 97 DetectBoardType( );
mluis 0:45c4f0364ca4 98
mluis 0:45c4f0364ca4 99 IoInit( );
mluis 0:45c4f0364ca4 100
mluis 0:45c4f0364ca4 101 SetOpMode( RF_OPMODE_SLEEP );
mluis 0:45c4f0364ca4 102 IoIrqInit( dioIrq );
mluis 0:45c4f0364ca4 103
mluis 0:45c4f0364ca4 104 RadioRegistersInit( );
mluis 0:45c4f0364ca4 105
mluis 0:45c4f0364ca4 106 SetModem( MODEM_FSK );
mluis 0:45c4f0364ca4 107
mluis 0:45c4f0364ca4 108 this->settings.State = RF_IDLE ;
mluis 0:45c4f0364ca4 109 }
mluis 0:45c4f0364ca4 110
mluis 0:45c4f0364ca4 111 //-------------------------------------------------------------------------
mluis 0:45c4f0364ca4 112 // Board relative functions
mluis 0:45c4f0364ca4 113 //-------------------------------------------------------------------------
GregCr 2:cd1093b6676f 114 uint8_t SX1272MB2xAS::DetectBoardType( void )
mluis 0:45c4f0364ca4 115 {
mluis 0:45c4f0364ca4 116 if( boardConnected == UNKNOWN )
mluis 0:45c4f0364ca4 117 {
mluis 0:45c4f0364ca4 118 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 119 boardConnected = NA_MOTE_72;
dudmuck 1:b0372ef620d0 120 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 121 boardConnected = MDOT_F411RE;
mluis 0:45c4f0364ca4 122 #else
mluis 0:45c4f0364ca4 123 this->AntSwitch.input( );
mluis 0:45c4f0364ca4 124 wait_ms( 1 );
mluis 0:45c4f0364ca4 125 if( this->AntSwitch == 1 )
mluis 0:45c4f0364ca4 126 {
mluis 0:45c4f0364ca4 127 boardConnected = SX1272MB1DCS;
mluis 0:45c4f0364ca4 128 }
mluis 0:45c4f0364ca4 129 else
mluis 0:45c4f0364ca4 130 {
GregCr 2:cd1093b6676f 131 boardConnected = SX1272MB2XAS;
mluis 0:45c4f0364ca4 132 }
mluis 0:45c4f0364ca4 133 this->AntSwitch.output( );
mluis 0:45c4f0364ca4 134 wait_ms( 1 );
mluis 0:45c4f0364ca4 135 #endif
mluis 0:45c4f0364ca4 136 }
mluis 0:45c4f0364ca4 137 return ( boardConnected );
mluis 0:45c4f0364ca4 138 }
mluis 0:45c4f0364ca4 139
GregCr 2:cd1093b6676f 140 void SX1272MB2xAS::IoInit( void )
mluis 0:45c4f0364ca4 141 {
mluis 0:45c4f0364ca4 142 AntSwInit( );
mluis 0:45c4f0364ca4 143 SpiInit( );
mluis 0:45c4f0364ca4 144 }
mluis 0:45c4f0364ca4 145
GregCr 2:cd1093b6676f 146 void SX1272MB2xAS::RadioRegistersInit( )
mluis 0:45c4f0364ca4 147 {
mluis 0:45c4f0364ca4 148 uint8_t i = 0;
mluis 0:45c4f0364ca4 149 for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ )
mluis 0:45c4f0364ca4 150 {
mluis 0:45c4f0364ca4 151 SetModem( RadioRegsInit[i].Modem );
mluis 0:45c4f0364ca4 152 Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
mluis 0:45c4f0364ca4 153 }
mluis 0:45c4f0364ca4 154 }
mluis 0:45c4f0364ca4 155
GregCr 2:cd1093b6676f 156 void SX1272MB2xAS::SpiInit( void )
mluis 0:45c4f0364ca4 157 {
mluis 0:45c4f0364ca4 158 nss = 1;
tmulrooney 4:352d0947f887 159 spi.format( 8,0 );
tmulrooney 5:e6a3f05e4743 160 // uint32_t frequencyToSet = 8000000;
tmulrooney 5:e6a3f05e4743 161 uint32_t frequencyToSet = (8000000 * 2)/3; /* 8 MHz/12 Mhz */
tmulrooney 4:352d0947f887 162 // #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_MOTE_L152RC ) || defined ( TARGET_LPC11U6X ) || defined ( TARGET_MTS_MDOT_F411RE ) )
mluis 0:45c4f0364ca4 163 spi.frequency( frequencyToSet );
tmulrooney 4:352d0947f887 164 // #elif( defined ( TARGET_KL25Z ) ) //busclock frequency is halved -> double the spi frequency to compensate
tmulrooney 4:352d0947f887 165 // spi.frequency( frequencyToSet * 2 );
tmulrooney 4:352d0947f887 166 // #else
tmulrooney 4:352d0947f887 167 // #warning "Check the board's SPI frequency"x
tmulrooney 4:352d0947f887 168 // #endif
mluis 0:45c4f0364ca4 169 wait(0.1);
mluis 0:45c4f0364ca4 170 }
mluis 0:45c4f0364ca4 171
GregCr 2:cd1093b6676f 172 void SX1272MB2xAS::IoIrqInit( DioIrqHandler *irqHandlers )
mluis 0:45c4f0364ca4 173 {
mluis 0:45c4f0364ca4 174 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_MOTE_L152RC ) || defined ( TARGET_LPC11U6X ) )
mluis 0:45c4f0364ca4 175 dio0.mode( PullDown );
mluis 0:45c4f0364ca4 176 dio1.mode( PullDown );
mluis 0:45c4f0364ca4 177 dio2.mode( PullDown );
mluis 0:45c4f0364ca4 178 dio3.mode( PullDown );
mluis 0:45c4f0364ca4 179 dio4.mode( PullDown );
mluis 0:45c4f0364ca4 180 #endif
GregCr 2:cd1093b6676f 181 dio0.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[0] ) );
GregCr 2:cd1093b6676f 182 dio1.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[1] ) );
GregCr 2:cd1093b6676f 183 dio2.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[2] ) );
GregCr 2:cd1093b6676f 184 dio3.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[3] ) );
GregCr 2:cd1093b6676f 185 dio4.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[4] ) );
mluis 0:45c4f0364ca4 186 }
mluis 0:45c4f0364ca4 187
GregCr 2:cd1093b6676f 188 void SX1272MB2xAS::IoDeInit( void )
mluis 0:45c4f0364ca4 189 {
mluis 0:45c4f0364ca4 190 //nothing
mluis 0:45c4f0364ca4 191 }
mluis 0:45c4f0364ca4 192
GregCr 2:cd1093b6676f 193 uint8_t SX1272MB2xAS::GetPaSelect( uint32_t channel )
mluis 0:45c4f0364ca4 194 {
dudmuck 1:b0372ef620d0 195 if( boardConnected == SX1272MB1DCS || boardConnected == MDOT_F411RE )
mluis 0:45c4f0364ca4 196 {
mluis 0:45c4f0364ca4 197 return RF_PACONFIG_PASELECT_PABOOST;
mluis 0:45c4f0364ca4 198 }
mluis 0:45c4f0364ca4 199 else
mluis 0:45c4f0364ca4 200 {
mluis 0:45c4f0364ca4 201 return RF_PACONFIG_PASELECT_RFO;
mluis 0:45c4f0364ca4 202 }
mluis 0:45c4f0364ca4 203 }
mluis 0:45c4f0364ca4 204
GregCr 2:cd1093b6676f 205 void SX1272MB2xAS::SetAntSwLowPower( bool status )
mluis 0:45c4f0364ca4 206 {
mluis 0:45c4f0364ca4 207 if( isRadioActive != status )
mluis 0:45c4f0364ca4 208 {
mluis 0:45c4f0364ca4 209 isRadioActive = status;
mluis 0:45c4f0364ca4 210
mluis 0:45c4f0364ca4 211 if( status == false )
mluis 0:45c4f0364ca4 212 {
mluis 0:45c4f0364ca4 213 AntSwInit( );
mluis 0:45c4f0364ca4 214 }
mluis 0:45c4f0364ca4 215 else
mluis 0:45c4f0364ca4 216 {
mluis 0:45c4f0364ca4 217 AntSwDeInit( );
mluis 0:45c4f0364ca4 218 }
mluis 0:45c4f0364ca4 219 }
mluis 0:45c4f0364ca4 220 }
mluis 0:45c4f0364ca4 221
GregCr 2:cd1093b6676f 222 void SX1272MB2xAS::AntSwInit( void )
mluis 0:45c4f0364ca4 223 {
mluis 0:45c4f0364ca4 224 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 225 this->RfSwitchCntr1 = 0;
mluis 0:45c4f0364ca4 226 this->RfSwitchCntr2 = 0;
mluis 0:45c4f0364ca4 227 this->PwrAmpCntr = 0;
dudmuck 1:b0372ef620d0 228 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 229 this->TxCtl = 0;
dudmuck 1:b0372ef620d0 230 this->RxCtl = 0;
mluis 0:45c4f0364ca4 231 #else
mluis 0:45c4f0364ca4 232 this->AntSwitch = 0;
mluis 0:45c4f0364ca4 233 #endif
mluis 0:45c4f0364ca4 234 }
mluis 0:45c4f0364ca4 235
GregCr 2:cd1093b6676f 236 void SX1272MB2xAS::AntSwDeInit( void )
mluis 0:45c4f0364ca4 237 {
mluis 0:45c4f0364ca4 238 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 239 this->RfSwitchCntr1 = 0;
mluis 0:45c4f0364ca4 240 this->RfSwitchCntr2 = 0;
mluis 0:45c4f0364ca4 241 this->PwrAmpCntr = 0;
dudmuck 1:b0372ef620d0 242 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 243 this->TxCtl = 0;
dudmuck 1:b0372ef620d0 244 this->RxCtl = 0;
mluis 0:45c4f0364ca4 245 #else
mluis 0:45c4f0364ca4 246 this->AntSwitch = 0;
mluis 0:45c4f0364ca4 247 #endif
mluis 0:45c4f0364ca4 248 }
mluis 0:45c4f0364ca4 249
GregCr 2:cd1093b6676f 250 void SX1272MB2xAS::SetAntSw( uint8_t rxTx )
mluis 0:45c4f0364ca4 251 {
mluis 0:45c4f0364ca4 252 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 253 switch( this->currentOpMode )
mluis 0:45c4f0364ca4 254 {
mluis 0:45c4f0364ca4 255 case RFLR_OPMODE_TRANSMITTER:
mluis 0:45c4f0364ca4 256 if( ( Read( REG_PACONFIG ) & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
mluis 0:45c4f0364ca4 257 {
mluis 0:45c4f0364ca4 258 this->RfSwitchCntr1 = 1;
mluis 0:45c4f0364ca4 259 this->RfSwitchCntr2 = 0;
mluis 0:45c4f0364ca4 260 }
mluis 0:45c4f0364ca4 261 else
mluis 0:45c4f0364ca4 262 {
mluis 0:45c4f0364ca4 263 this->RfSwitchCntr1 = 0;
mluis 0:45c4f0364ca4 264 this->RfSwitchCntr2 = 1;
mluis 0:45c4f0364ca4 265 }
mluis 0:45c4f0364ca4 266 break;
mluis 0:45c4f0364ca4 267 case RFLR_OPMODE_RECEIVER:
mluis 0:45c4f0364ca4 268 case RFLR_OPMODE_RECEIVER_SINGLE:
mluis 0:45c4f0364ca4 269 case RFLR_OPMODE_CAD:
mluis 0:45c4f0364ca4 270 this->RfSwitchCntr1 = 1;
mluis 0:45c4f0364ca4 271 this->RfSwitchCntr2 = 1;
mluis 0:45c4f0364ca4 272 break;
mluis 0:45c4f0364ca4 273 default:
mluis 0:45c4f0364ca4 274 this->RfSwitchCntr1 = 0;
mluis 0:45c4f0364ca4 275 this->RfSwitchCntr2 = 0;
mluis 0:45c4f0364ca4 276 this->PwrAmpCntr = 0;
mluis 0:45c4f0364ca4 277 break;
mluis 0:45c4f0364ca4 278 }
dudmuck 1:b0372ef620d0 279 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 280 if( this->rxTx == rxTx )
dudmuck 1:b0372ef620d0 281 {
dudmuck 1:b0372ef620d0 282 //no need to go further
dudmuck 1:b0372ef620d0 283 return;
dudmuck 1:b0372ef620d0 284 }
dudmuck 1:b0372ef620d0 285
dudmuck 1:b0372ef620d0 286 /* SKY13350 */
dudmuck 1:b0372ef620d0 287 this->rxTx = rxTx;
dudmuck 1:b0372ef620d0 288
dudmuck 1:b0372ef620d0 289 // 1: Tx, 0: Rx
dudmuck 1:b0372ef620d0 290 if( rxTx != 0 )
dudmuck 1:b0372ef620d0 291 {
dudmuck 1:b0372ef620d0 292 this->TxCtl = 1;
dudmuck 1:b0372ef620d0 293 this->RxCtl = 0;
dudmuck 1:b0372ef620d0 294 }
dudmuck 1:b0372ef620d0 295 else
dudmuck 1:b0372ef620d0 296 {
dudmuck 1:b0372ef620d0 297 this->TxCtl = 0;
dudmuck 1:b0372ef620d0 298 this->RxCtl = 1;
dudmuck 1:b0372ef620d0 299 }
mluis 0:45c4f0364ca4 300 #else
mluis 0:45c4f0364ca4 301 if( this->rxTx == rxTx )
mluis 0:45c4f0364ca4 302 {
mluis 0:45c4f0364ca4 303 //no need to go further
mluis 0:45c4f0364ca4 304 return;
mluis 0:45c4f0364ca4 305 }
mluis 0:45c4f0364ca4 306
mluis 0:45c4f0364ca4 307 this->rxTx = rxTx;
mluis 0:45c4f0364ca4 308
mluis 0:45c4f0364ca4 309 // 1: Tx, 0: Rx
mluis 0:45c4f0364ca4 310 if( rxTx != 0 )
mluis 0:45c4f0364ca4 311 {
mluis 0:45c4f0364ca4 312 this->AntSwitch = 1;
mluis 0:45c4f0364ca4 313 }
mluis 0:45c4f0364ca4 314 else
mluis 0:45c4f0364ca4 315 {
mluis 0:45c4f0364ca4 316 this->AntSwitch = 0;
mluis 0:45c4f0364ca4 317 }
mluis 0:45c4f0364ca4 318 #endif
mluis 0:45c4f0364ca4 319 }
mluis 0:45c4f0364ca4 320
GregCr 2:cd1093b6676f 321 bool SX1272MB2xAS::CheckRfFrequency( uint32_t frequency )
mluis 0:45c4f0364ca4 322 {
mluis 0:45c4f0364ca4 323 //TODO: Implement check, currently all frequencies are supported
mluis 0:45c4f0364ca4 324 return true;
mluis 0:45c4f0364ca4 325 }
mluis 0:45c4f0364ca4 326
mluis 0:45c4f0364ca4 327
GregCr 2:cd1093b6676f 328 void SX1272MB2xAS::Reset( void )
mluis 0:45c4f0364ca4 329 {
mluis 0:45c4f0364ca4 330 reset.output();
mluis 0:45c4f0364ca4 331 reset = 0;
mluis 0:45c4f0364ca4 332 wait_ms( 1 );
mluis 0:45c4f0364ca4 333 reset.input();
mluis 0:45c4f0364ca4 334 wait_ms( 6 );
mluis 0:45c4f0364ca4 335 }
mluis 0:45c4f0364ca4 336
GregCr 2:cd1093b6676f 337 void SX1272MB2xAS::Write( uint8_t addr, uint8_t data )
mluis 0:45c4f0364ca4 338 {
mluis 0:45c4f0364ca4 339 Write( addr, &data, 1 );
mluis 0:45c4f0364ca4 340 }
mluis 0:45c4f0364ca4 341
GregCr 2:cd1093b6676f 342 uint8_t SX1272MB2xAS::Read( uint8_t addr )
mluis 0:45c4f0364ca4 343 {
mluis 0:45c4f0364ca4 344 uint8_t data;
mluis 0:45c4f0364ca4 345 Read( addr, &data, 1 );
mluis 0:45c4f0364ca4 346 return data;
mluis 0:45c4f0364ca4 347 }
mluis 0:45c4f0364ca4 348
GregCr 2:cd1093b6676f 349 void SX1272MB2xAS::Write( uint8_t addr, uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 350 {
mluis 0:45c4f0364ca4 351 uint8_t i;
mluis 0:45c4f0364ca4 352
mluis 0:45c4f0364ca4 353 nss = 0;
mluis 0:45c4f0364ca4 354 spi.write( addr | 0x80 );
mluis 0:45c4f0364ca4 355 for( i = 0; i < size; i++ )
mluis 0:45c4f0364ca4 356 {
mluis 0:45c4f0364ca4 357 spi.write( buffer[i] );
mluis 0:45c4f0364ca4 358 }
mluis 0:45c4f0364ca4 359 nss = 1;
mluis 0:45c4f0364ca4 360 }
mluis 0:45c4f0364ca4 361
GregCr 2:cd1093b6676f 362 void SX1272MB2xAS::Read( uint8_t addr, uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 363 {
mluis 0:45c4f0364ca4 364 uint8_t i;
mluis 0:45c4f0364ca4 365
mluis 0:45c4f0364ca4 366 nss = 0;
mluis 0:45c4f0364ca4 367 spi.write( addr & 0x7F );
mluis 0:45c4f0364ca4 368 for( i = 0; i < size; i++ )
mluis 0:45c4f0364ca4 369 {
mluis 0:45c4f0364ca4 370 buffer[i] = spi.write( 0 );
mluis 0:45c4f0364ca4 371 }
mluis 0:45c4f0364ca4 372 nss = 1;
mluis 0:45c4f0364ca4 373 }
mluis 0:45c4f0364ca4 374
GregCr 2:cd1093b6676f 375 void SX1272MB2xAS::WriteFifo( uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 376 {
mluis 0:45c4f0364ca4 377 Write( 0, buffer, size );
mluis 0:45c4f0364ca4 378 }
mluis 0:45c4f0364ca4 379
GregCr 2:cd1093b6676f 380 void SX1272MB2xAS::ReadFifo( uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 381 {
mluis 0:45c4f0364ca4 382 Read( 0, buffer, size );
mluis 0:45c4f0364ca4 383 }